2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/callout.h>
35 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
43 #include <sys/sysctl.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/stdarg.h>
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcreg.h>
52 #include <dev/mmc/mmcbrvar.h>
54 #include <dev/sdhci/sdhci.h>
59 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
61 static int sdhci_debug;
62 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
64 u_int sdhci_quirk_clear = 0;
65 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
66 0, "Mask of quirks to clear");
67 u_int sdhci_quirk_set = 0;
68 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
69 "Mask of quirks to set");
71 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
72 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
73 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
74 #define RD_MULTI_4(slot, off, ptr, count) \
75 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
77 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
78 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
79 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
80 #define WR_MULTI_4(slot, off, ptr, count) \
81 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
83 static void sdhci_card_poll(void *arg);
84 static void sdhci_card_task(void *arg, int pending);
85 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
86 static void sdhci_req_wakeup(struct mmc_request *req);
87 static void sdhci_retune(void *arg);
88 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
89 static void sdhci_start(struct sdhci_slot *slot);
90 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
93 static void sdhci_dumpregs(struct sdhci_slot *slot);
94 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
96 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot);
98 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
99 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
100 #define SDHCI_LOCK_INIT(_slot) \
101 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
102 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
103 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
104 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
106 #define SDHCI_DEFAULT_MAX_FREQ 50
108 #define SDHCI_200_MAX_DIVIDER 256
109 #define SDHCI_300_MAX_DIVIDER 2046
111 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
112 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
115 * Broadcom BCM577xx Controller Constants
117 /* Maximum divider supported by the default clock source. */
118 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
119 /* Alternative clock's base frequency. */
120 #define BCM577XX_ALT_CLOCK_BASE 63000000
122 #define BCM577XX_HOST_CONTROL 0x198
123 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
124 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
125 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
126 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
129 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
133 printf("getaddr: error %d\n", error);
136 *(bus_addr_t *)arg = segs[0].ds_addr;
140 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
145 retval = printf("%s-slot%d: ",
146 device_get_nameunit(slot->bus), slot->num);
149 retval += vprintf(fmt, ap);
155 sdhci_dumpregs(struct sdhci_slot *slot)
159 "============== REGISTER DUMP ==============\n");
161 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
162 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
163 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
164 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
165 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
166 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
167 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
168 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
169 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
170 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
171 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
172 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
173 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
174 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
175 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
176 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
177 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
178 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
179 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
180 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
181 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
182 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
183 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
184 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
187 "===========================================\n");
191 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
196 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
197 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
201 /* Some controllers need this kick or reset won't work. */
202 if ((mask & SDHCI_RESET_ALL) == 0 &&
203 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
204 /* This is to force an update */
207 sdhci_set_clock(slot, clock);
210 if (mask & SDHCI_RESET_ALL) {
215 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
217 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
219 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
220 * specification. The reset bit has internal propagation delay,
221 * so a fast read after write returns 0 even if reset process is
222 * in progress. The workaround is to poll for 1 before polling
223 * for 0. In the worst case, if we miss seeing it asserted the
224 * time we spent waiting is enough to ensure the reset finishes.
227 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
235 /* Wait max 100 ms */
237 /* Controller clears the bits when it's done */
238 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
240 slot_printf(slot, "Reset 0x%x never completed.\n",
242 sdhci_dumpregs(slot);
251 sdhci_tuning_intmask(struct sdhci_slot *slot)
256 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
257 intmask |= SDHCI_INT_TUNEERR;
258 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
259 slot->retune_mode == SDHCI_RETUNE_MODE_3)
260 intmask |= SDHCI_INT_RETUNE;
266 sdhci_init(struct sdhci_slot *slot)
269 sdhci_reset(slot, SDHCI_RESET_ALL);
271 /* Enable interrupts. */
272 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
273 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
274 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
275 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
276 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
279 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
280 !(slot->opt & SDHCI_NON_REMOVABLE)) {
281 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
284 WR4(slot, SDHCI_INT_ENABLE, slot->intmask | sdhci_tuning_intmask(slot));
285 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
289 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
298 if (clock == slot->clock)
302 /* Turn off the clock. */
303 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
304 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
305 /* If no clock requested - leave it so. */
309 /* Determine the clock base frequency */
310 clk_base = slot->max_clk;
311 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
312 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
313 BCM577XX_CTRL_CLKSEL_MASK;
316 * Select clock source appropriate for the requested frequency.
318 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
319 clk_base = BCM577XX_ALT_CLOCK_BASE;
320 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
321 BCM577XX_CTRL_CLKSEL_SHIFT);
323 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
324 BCM577XX_CTRL_CLKSEL_SHIFT);
327 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
330 /* Recalculate timeout clock frequency based on the new sd clock. */
331 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
332 slot->timeout_clk = slot->clock / 1000;
334 if (slot->version < SDHCI_SPEC_300) {
335 /* Looking for highest freq <= clock. */
337 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
342 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
345 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
346 if (clock >= clk_base)
349 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
350 if ((clk_base / div) <= clock)
357 if (bootverbose || sdhci_debug)
358 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
359 div, clock, clk_base);
361 /* Now we have got divider, set it. */
362 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
363 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
364 << SDHCI_DIVIDER_HI_SHIFT;
366 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
368 clk |= SDHCI_CLOCK_INT_EN;
369 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
370 /* Wait up to 10 ms until it stabilize. */
372 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
373 & SDHCI_CLOCK_INT_STABLE)) {
376 "Internal clock never stabilised.\n");
377 sdhci_dumpregs(slot);
383 /* Pass clock signal to the bus. */
384 clk |= SDHCI_CLOCK_CARD_EN;
385 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
389 sdhci_set_power(struct sdhci_slot *slot, u_char power)
394 if (slot->power == power)
399 /* Turn off the power. */
401 WR1(slot, SDHCI_POWER_CONTROL, pwr);
402 /* If power down requested - leave it so. */
406 switch (1 << power) {
407 case MMC_OCR_LOW_VOLTAGE:
408 pwr |= SDHCI_POWER_180;
410 case MMC_OCR_290_300:
411 case MMC_OCR_300_310:
412 pwr |= SDHCI_POWER_300;
414 case MMC_OCR_320_330:
415 case MMC_OCR_330_340:
416 pwr |= SDHCI_POWER_330;
419 WR1(slot, SDHCI_POWER_CONTROL, pwr);
421 * Turn on VDD1 power. Note that at least some Intel controllers can
422 * fail to enable bus power on the first try after transiting from D3
423 * to D0, so we give them up to 2 ms.
425 pwr |= SDHCI_POWER_ON;
426 for (i = 0; i < 20; i++) {
427 WR1(slot, SDHCI_POWER_CONTROL, pwr);
428 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
432 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
433 slot_printf(slot, "Bus power failed to enable");
435 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
436 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
438 WR1(slot, SDHCI_POWER_CONTROL, pwr);
444 sdhci_read_block_pio(struct sdhci_slot *slot)
450 buffer = slot->curcmd->data->data;
451 buffer += slot->offset;
452 /* Transfer one block at a time. */
453 left = min(512, slot->curcmd->data->len - slot->offset);
454 slot->offset += left;
456 /* If we are too fast, broken controllers return zeroes. */
457 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
459 /* Handle unaligned and aligned buffer cases. */
460 if ((intptr_t)buffer & 3) {
462 data = RD4(slot, SDHCI_BUFFER);
464 buffer[1] = (data >> 8);
465 buffer[2] = (data >> 16);
466 buffer[3] = (data >> 24);
471 RD_MULTI_4(slot, SDHCI_BUFFER,
472 (uint32_t *)buffer, left >> 2);
475 /* Handle uneven size case. */
477 data = RD4(slot, SDHCI_BUFFER);
487 sdhci_write_block_pio(struct sdhci_slot *slot)
493 buffer = slot->curcmd->data->data;
494 buffer += slot->offset;
495 /* Transfer one block at a time. */
496 left = min(512, slot->curcmd->data->len - slot->offset);
497 slot->offset += left;
499 /* Handle unaligned and aligned buffer cases. */
500 if ((intptr_t)buffer & 3) {
508 WR4(slot, SDHCI_BUFFER, data);
511 WR_MULTI_4(slot, SDHCI_BUFFER,
512 (uint32_t *)buffer, left >> 2);
515 /* Handle uneven size case. */
522 WR4(slot, SDHCI_BUFFER, data);
527 sdhci_transfer_pio(struct sdhci_slot *slot)
530 /* Read as many blocks as possible. */
531 if (slot->curcmd->data->flags & MMC_DATA_READ) {
532 while (RD4(slot, SDHCI_PRESENT_STATE) &
533 SDHCI_DATA_AVAILABLE) {
534 sdhci_read_block_pio(slot);
535 if (slot->offset >= slot->curcmd->data->len)
539 while (RD4(slot, SDHCI_PRESENT_STATE) &
540 SDHCI_SPACE_AVAILABLE) {
541 sdhci_write_block_pio(slot);
542 if (slot->offset >= slot->curcmd->data->len)
549 sdhci_card_task(void *arg, int pending __unused)
551 struct sdhci_slot *slot = arg;
555 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
556 if (slot->dev == NULL) {
557 /* If card is present - attach mmc bus. */
558 if (bootverbose || sdhci_debug)
559 slot_printf(slot, "Card inserted\n");
560 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
563 device_set_ivars(d, slot);
564 (void)device_probe_and_attach(d);
569 if (slot->dev != NULL) {
570 /* If no card present - detach mmc bus. */
571 if (bootverbose || sdhci_debug)
572 slot_printf(slot, "Card removed\n");
575 slot->intmask &= ~sdhci_tuning_intmask(slot);
576 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
577 slot->opt &= ~SDHCI_TUNING_ENABLED;
579 callout_drain(&slot->retune_callout);
580 device_delete_child(slot->bus, d);
587 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
592 * If there was no card and now there is one, schedule the task to
593 * create the child device after a short delay. The delay is to
594 * debounce the card insert (sometimes the card detect pin stabilizes
595 * before the other pins have made good contact).
597 * If there was a card present and now it's gone, immediately schedule
598 * the task to delete the child device. No debouncing -- gone is gone,
599 * because once power is removed, a full card re-init is needed, and
600 * that happens by deleting and recreating the child device.
602 was_present = slot->dev != NULL;
603 if (!was_present && is_present) {
604 taskqueue_enqueue_timeout(taskqueue_swi_giant,
605 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
606 } else if (was_present && !is_present) {
607 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
612 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
616 sdhci_handle_card_present_locked(slot, is_present);
621 sdhci_card_poll(void *arg)
623 struct sdhci_slot *slot = arg;
625 sdhci_handle_card_present(slot,
626 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
627 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
628 sdhci_card_poll, slot);
632 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
634 kobjop_desc_t kobj_desc;
635 kobj_method_t *kobj_method;
636 uint32_t caps, caps2, freq, host_caps;
639 SDHCI_LOCK_INIT(slot);
643 /* Allocate DMA tag. */
644 err = bus_dma_tag_create(bus_get_dma_tag(dev),
645 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
646 BUS_SPACE_MAXADDR, NULL, NULL,
647 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
648 BUS_DMA_ALLOCNOW, NULL, NULL,
651 device_printf(dev, "Can't create DMA tag\n");
652 SDHCI_LOCK_DESTROY(slot);
655 /* Allocate DMA memory. */
656 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
657 BUS_DMA_NOWAIT, &slot->dmamap);
659 device_printf(dev, "Can't alloc DMA memory\n");
660 bus_dma_tag_destroy(slot->dmatag);
661 SDHCI_LOCK_DESTROY(slot);
664 /* Map the memory. */
665 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
666 (void *)slot->dmamem, DMA_BLOCK_SIZE,
667 sdhci_getaddr, &slot->paddr, 0);
668 if (err != 0 || slot->paddr == 0) {
669 device_printf(dev, "Can't load DMA memory\n");
670 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
671 bus_dma_tag_destroy(slot->dmatag);
672 SDHCI_LOCK_DESTROY(slot);
679 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
680 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
681 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
685 caps = RD4(slot, SDHCI_CAPABILITIES);
686 if (slot->version >= SDHCI_SPEC_300)
687 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
691 if (slot->version >= SDHCI_SPEC_300) {
692 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
693 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
695 "Driver doesn't support shared bus slots\n");
696 bus_dmamap_unload(slot->dmatag, slot->dmamap);
697 bus_dmamem_free(slot->dmatag, slot->dmamem,
699 bus_dma_tag_destroy(slot->dmatag);
700 SDHCI_LOCK_DESTROY(slot);
702 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
703 SDHCI_SLOTTYPE_EMBEDDED) {
704 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
707 /* Calculate base clock frequency. */
708 if (slot->version >= SDHCI_SPEC_300)
709 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
710 SDHCI_CLOCK_BASE_SHIFT;
712 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
713 SDHCI_CLOCK_BASE_SHIFT;
715 slot->max_clk = freq * 1000000;
717 * If the frequency wasn't in the capabilities and the hardware driver
718 * hasn't already set max_clk we're probably not going to work right
719 * with an assumption, so complain about it.
721 if (slot->max_clk == 0) {
722 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
723 device_printf(dev, "Hardware doesn't specify base clock "
724 "frequency, using %dMHz as default.\n",
725 SDHCI_DEFAULT_MAX_FREQ);
727 /* Calculate/set timeout clock frequency. */
728 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
729 slot->timeout_clk = slot->max_clk / 1000;
730 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
731 slot->timeout_clk = 1000;
733 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
734 SDHCI_TIMEOUT_CLK_SHIFT;
735 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
736 slot->timeout_clk *= 1000;
739 * If the frequency wasn't in the capabilities and the hardware driver
740 * hasn't already set timeout_clk we'll probably work okay using the
741 * max timeout, but still mention it.
743 if (slot->timeout_clk == 0) {
744 device_printf(dev, "Hardware doesn't specify timeout clock "
745 "frequency, setting BROKEN_TIMEOUT quirk.\n");
746 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
749 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
750 slot->host.f_max = slot->max_clk;
751 slot->host.host_ocr = 0;
752 if (caps & SDHCI_CAN_VDD_330)
753 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
754 if (caps & SDHCI_CAN_VDD_300)
755 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
756 /* 1.8V VDD is not supposed to be used for removable cards. */
757 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
758 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
759 if (slot->host.host_ocr == 0) {
760 device_printf(dev, "Hardware doesn't report any "
761 "support voltages.\n");
764 host_caps = MMC_CAP_4_BIT_DATA;
765 if (caps & SDHCI_CAN_DO_8BITBUS)
766 host_caps |= MMC_CAP_8_BIT_DATA;
767 if (caps & SDHCI_CAN_DO_HISPD)
768 host_caps |= MMC_CAP_HSPEED;
769 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
770 host_caps |= MMC_CAP_BOOT_NOACC;
771 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
772 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
774 /* Determine supported UHS-I and eMMC modes. */
775 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
776 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
777 if (caps2 & SDHCI_CAN_SDR104) {
778 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
779 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
780 host_caps |= MMC_CAP_MMC_HS200;
781 } else if (caps2 & SDHCI_CAN_SDR50)
782 host_caps |= MMC_CAP_UHS_SDR50;
783 if (caps2 & SDHCI_CAN_DDR50 &&
784 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
785 host_caps |= MMC_CAP_UHS_DDR50;
786 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
787 host_caps |= MMC_CAP_MMC_DDR52;
788 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
789 caps2 & SDHCI_CAN_MMC_HS400)
790 host_caps |= MMC_CAP_MMC_HS400;
793 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
794 * default NULL implementation.
796 kobj_desc = &sdhci_set_uhs_timing_desc;
797 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
799 if (kobj_method == &kobj_desc->deflt)
800 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
801 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
802 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
804 #define SDHCI_CAP_MODES_TUNING(caps2) \
805 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
806 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
810 * Disable UHS-I and eMMC modes that require (re-)tuning if either
811 * the tune or re-tune method is the default NULL implementation.
813 kobj_desc = &mmcbr_tune_desc;
814 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
816 if (kobj_method == &kobj_desc->deflt)
818 kobj_desc = &mmcbr_retune_desc;
819 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
821 if (kobj_method == &kobj_desc->deflt) {
823 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
826 /* Allocate tuning structures and determine tuning parameters. */
827 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
828 slot->opt |= SDHCI_TUNING_SUPPORTED;
829 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
831 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
833 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
835 if (caps2 & SDHCI_TUNE_SDR50)
836 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
837 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
838 SDHCI_RETUNE_MODES_SHIFT;
839 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
840 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
841 SDHCI_RETUNE_CNT_SHIFT;
842 if (slot->retune_count > 0xb) {
843 device_printf(dev, "Unknown re-tuning count "
844 "%x, using 1 sec\n", slot->retune_count);
845 slot->retune_count = 1;
846 } else if (slot->retune_count != 0)
848 1 << (slot->retune_count - 1);
852 #undef SDHCI_CAP_MODES_TUNING
854 /* Determine supported VCCQ signaling levels. */
855 host_caps |= MMC_CAP_SIGNALING_330;
856 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
857 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
858 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
859 MMC_CAP_MMC_HS400_180))
860 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
863 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
864 * default NULL implementation. Disable 1.2 V support if it's the
865 * generic SDHCI implementation.
867 kobj_desc = &mmcbr_switch_vccq_desc;
868 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
870 if (kobj_method == &kobj_desc->deflt)
871 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
872 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
873 host_caps &= ~MMC_CAP_SIGNALING_120;
875 /* Determine supported driver types (type B is always mandatory). */
876 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
877 host_caps |= MMC_CAP_DRIVER_TYPE_A;
878 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
879 host_caps |= MMC_CAP_DRIVER_TYPE_C;
880 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
881 host_caps |= MMC_CAP_DRIVER_TYPE_D;
882 slot->host.caps = host_caps;
884 /* Decide if we have usable DMA. */
885 if (caps & SDHCI_CAN_DO_DMA)
886 slot->opt |= SDHCI_HAVE_DMA;
888 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
889 slot->opt &= ~SDHCI_HAVE_DMA;
890 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
891 slot->opt |= SDHCI_HAVE_DMA;
892 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
893 slot->opt |= SDHCI_NON_REMOVABLE;
896 * Use platform-provided transfer backend
897 * with PIO as a fallback mechanism
899 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
900 slot->opt &= ~SDHCI_HAVE_DMA;
902 if (bootverbose || sdhci_debug) {
904 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
905 slot->max_clk / 1000000,
906 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
907 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
908 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
909 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
910 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
911 ((caps & SDHCI_CAN_VDD_180) &&
912 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
913 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
914 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
915 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
916 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
917 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
918 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
919 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
920 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
922 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
923 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
924 slot_printf(slot, "eMMC:%s%s%s%s\n",
925 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
926 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
927 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
929 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
930 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
932 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
933 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
934 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
935 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
936 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
937 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
938 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
939 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
940 if (slot->opt & SDHCI_TUNING_SUPPORTED)
941 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
942 slot->retune_count, slot->retune_mode + 1);
943 sdhci_dumpregs(slot);
947 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
948 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
949 "timeout", CTLFLAG_RW, &slot->timeout, 0,
950 "Maximum timeout for SDHCI transfers (in secs)");
951 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
952 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
953 sdhci_card_task, slot);
954 callout_init(&slot->card_poll_callout, 1);
955 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
956 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
958 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
959 !(slot->opt & SDHCI_NON_REMOVABLE)) {
960 callout_reset(&slot->card_poll_callout,
961 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
970 sdhci_start_slot(struct sdhci_slot *slot)
973 sdhci_card_task(slot, 0);
977 sdhci_cleanup_slot(struct sdhci_slot *slot)
981 callout_drain(&slot->timeout_callout);
982 callout_drain(&slot->card_poll_callout);
983 callout_drain(&slot->retune_callout);
984 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
985 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
992 device_delete_child(slot->bus, d);
995 sdhci_reset(slot, SDHCI_RESET_ALL);
997 bus_dmamap_unload(slot->dmatag, slot->dmamap);
998 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
999 bus_dma_tag_destroy(slot->dmatag);
1000 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1001 free(slot->tune_req, M_DEVBUF);
1002 free(slot->tune_cmd, M_DEVBUF);
1003 free(slot->tune_data, M_DEVBUF);
1006 SDHCI_LOCK_DESTROY(slot);
1012 sdhci_generic_suspend(struct sdhci_slot *slot)
1016 * We expect the MMC layer to issue initial tuning after resume.
1017 * Otherwise, we'd need to indicate re-tuning including circuit reset
1018 * being required at least for re-tuning modes 1 and 2 ourselves.
1020 callout_drain(&slot->retune_callout);
1022 slot->opt &= ~SDHCI_TUNING_ENABLED;
1023 sdhci_reset(slot, SDHCI_RESET_ALL);
1030 sdhci_generic_resume(struct sdhci_slot *slot)
1041 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1044 if (slot->version >= SDHCI_SPEC_300)
1045 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1047 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1051 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1054 if (slot->opt & SDHCI_NON_REMOVABLE)
1057 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1061 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1063 struct mmc_ios *ios;
1066 if (slot->version < SDHCI_SPEC_300)
1069 SDHCI_ASSERT_LOCKED(slot);
1070 ios = &slot->host.ios;
1071 sdhci_set_clock(slot, 0);
1072 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1073 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1074 if (ios->clock > SD_SDR50_MAX) {
1075 if (ios->timing == bus_timing_mmc_hs400 ||
1076 ios->timing == bus_timing_mmc_hs400es)
1077 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1079 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1081 else if (ios->clock > SD_SDR25_MAX)
1082 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1083 else if (ios->clock > SD_SDR12_MAX) {
1084 if (ios->timing == bus_timing_uhs_ddr50 ||
1085 ios->timing == bus_timing_mmc_ddr52)
1086 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1088 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1089 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1090 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1091 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1092 sdhci_set_clock(slot, ios->clock);
1096 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1098 struct sdhci_slot *slot = device_get_ivars(reqdev);
1099 struct mmc_ios *ios = &slot->host.ios;
1102 /* Do full reset on bus power down to clear from any state. */
1103 if (ios->power_mode == power_off) {
1104 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1107 /* Configure the bus. */
1108 sdhci_set_clock(slot, ios->clock);
1109 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1110 if (ios->bus_width == bus_width_8) {
1111 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1112 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1113 } else if (ios->bus_width == bus_width_4) {
1114 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1115 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1116 } else if (ios->bus_width == bus_width_1) {
1117 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1118 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1120 panic("Invalid bus width: %d", ios->bus_width);
1122 if (ios->clock > SD_SDR12_MAX &&
1123 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1124 slot->hostctrl |= SDHCI_CTRL_HISPD;
1126 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1127 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1128 SDHCI_SET_UHS_TIMING(brdev, slot);
1129 /* Some controllers like reset after bus changes. */
1130 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1131 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1138 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1140 struct sdhci_slot *slot = device_get_ivars(reqdev);
1145 if (slot->version < SDHCI_SPEC_300)
1149 vccq = slot->host.ios.vccq;
1151 sdhci_set_clock(slot, 0);
1152 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1155 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1157 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1158 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1160 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1161 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1166 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1170 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1172 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1173 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1175 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1176 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1182 "Attempt to set unsupported signaling voltage\n");
1187 sdhci_set_clock(slot, slot->host.ios.clock);
1193 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1195 struct sdhci_slot *slot = device_get_ivars(reqdev);
1196 struct mmc_ios *ios = &slot->host.ios;
1197 struct mmc_command *tune_cmd;
1198 struct mmc_data *tune_data;
1202 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1205 slot->retune_ticks = slot->retune_count * hz;
1206 opcode = MMC_SEND_TUNING_BLOCK;
1208 switch (ios->timing) {
1209 case bus_timing_mmc_hs400:
1210 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1213 case bus_timing_mmc_hs200:
1215 * In HS400 mode, controllers use the data strobe line to
1216 * latch data from the devices so periodic re-tuning isn't
1217 * expected to be required.
1220 slot->retune_ticks = 0;
1221 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1223 case bus_timing_uhs_ddr50:
1224 case bus_timing_uhs_sdr104:
1226 case bus_timing_uhs_sdr50:
1227 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1235 tune_cmd = slot->tune_cmd;
1236 memset(tune_cmd, 0, sizeof(*tune_cmd));
1237 tune_cmd->opcode = opcode;
1238 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1239 tune_data = tune_cmd->data = slot->tune_data;
1240 memset(tune_data, 0, sizeof(*tune_data));
1241 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1242 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1244 tune_data->flags = MMC_DATA_READ;
1245 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1247 slot->opt &= ~SDHCI_TUNING_ENABLED;
1248 err = sdhci_exec_tuning(slot, true);
1250 slot->opt |= SDHCI_TUNING_ENABLED;
1251 slot->intmask |= sdhci_tuning_intmask(slot);
1252 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1253 if (slot->retune_ticks) {
1254 callout_reset(&slot->retune_callout, slot->retune_ticks,
1255 sdhci_retune, slot);
1263 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1265 struct sdhci_slot *slot = device_get_ivars(reqdev);
1268 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1271 /* HS400 must be tuned in HS200 mode. */
1272 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1276 err = sdhci_exec_tuning(slot, reset);
1278 * There are two ways sdhci_exec_tuning() can fail:
1279 * EBUSY should not actually happen when requests are only issued
1280 * with the host properly acquired, and
1281 * EIO re-tuning failed (but it did work initially).
1283 * In both cases, we should retry at later point if periodic re-tuning
1284 * is enabled. Note that due to slot->retune_req not being cleared in
1285 * these failure cases, the MMC layer should trigger another attempt at
1286 * re-tuning with the next request anyway, though.
1288 if (slot->retune_ticks) {
1289 callout_reset(&slot->retune_callout, slot->retune_ticks,
1290 sdhci_retune, slot);
1297 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1299 struct mmc_request *tune_req;
1300 struct mmc_command *tune_cmd;
1306 SDHCI_ASSERT_LOCKED(slot);
1307 if (slot->req != NULL)
1310 /* Tuning doesn't work with DMA enabled. */
1312 slot->opt = opt & ~SDHCI_HAVE_DMA;
1315 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1316 * kind of interrupt we receive in response to a tuning request.
1318 intmask = slot->intmask;
1319 slot->intmask = SDHCI_INT_DATA_AVAIL;
1320 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1322 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1324 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1326 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1327 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1329 tune_req = slot->tune_req;
1330 tune_cmd = slot->tune_cmd;
1331 for (i = 0; i < MMC_TUNING_MAX; i++) {
1332 memset(tune_req, 0, sizeof(*tune_req));
1333 tune_req->cmd = tune_cmd;
1334 tune_req->done = sdhci_req_wakeup;
1335 tune_req->done_data = slot;
1336 slot->req = tune_req;
1339 while (!(tune_req->flags & MMC_REQ_DONE))
1340 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1341 if (!(tune_req->flags & MMC_TUNE_DONE))
1343 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1344 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1346 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1351 slot->intmask = intmask;
1352 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1354 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1355 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1356 slot->retune_req = 0;
1360 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1361 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1362 SDHCI_CTRL2_SAMPLING_CLOCK));
1363 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1368 sdhci_retune(void *arg)
1370 struct sdhci_slot *slot = arg;
1372 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1376 sdhci_req_done(struct sdhci_slot *slot)
1378 struct mmc_request *req;
1380 if (slot->req != NULL && slot->curcmd != NULL) {
1381 callout_stop(&slot->timeout_callout);
1384 slot->curcmd = NULL;
1390 sdhci_req_wakeup(struct mmc_request *req)
1392 struct sdhci_slot *slot;
1394 slot = req->done_data;
1395 req->flags |= MMC_REQ_DONE;
1400 sdhci_timeout(void *arg)
1402 struct sdhci_slot *slot = arg;
1404 if (slot->curcmd != NULL) {
1405 slot_printf(slot, "Controller timeout\n");
1406 sdhci_dumpregs(slot);
1407 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1408 slot->curcmd->error = MMC_ERR_TIMEOUT;
1409 sdhci_req_done(slot);
1411 slot_printf(slot, "Spurious timeout - no active command\n");
1416 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
1423 mode = SDHCI_TRNS_BLK_CNT_EN;
1424 if (data->len > 512)
1425 mode |= SDHCI_TRNS_MULTI;
1426 if (data->flags & MMC_DATA_READ)
1427 mode |= SDHCI_TRNS_READ;
1428 if (slot->req->stop)
1429 mode |= SDHCI_TRNS_ACMD12;
1430 if (slot->flags & SDHCI_USE_DMA)
1431 mode |= SDHCI_TRNS_DMA;
1433 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1437 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1445 cmd->error = MMC_ERR_NONE;
1447 /* This flags combination is not supported by controller. */
1448 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1449 slot_printf(slot, "Unsupported response type!\n");
1450 cmd->error = MMC_ERR_FAILED;
1451 sdhci_req_done(slot);
1456 * Do not issue command if there is no card, clock or power.
1457 * Controller will not detect timeout without clock active.
1459 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1462 cmd->error = MMC_ERR_FAILED;
1463 sdhci_req_done(slot);
1466 /* Always wait for free CMD bus. */
1467 mask = SDHCI_CMD_INHIBIT;
1468 /* Wait for free DAT if we have data or busy signal. */
1469 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
1470 mask |= SDHCI_DAT_INHIBIT;
1472 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1473 * that these latter are also special in that SDHCI_CMD_DATA should
1474 * be set below but no actual data is ever read from the controller.
1476 if (cmd == slot->req->stop ||
1477 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1478 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1479 mask &= ~SDHCI_DAT_INHIBIT;
1481 * Wait for bus no more then 250 ms. Typically there will be no wait
1482 * here at all, but when writing a crash dump we may be bypassing the
1483 * host platform's interrupt handler, and in some cases that handler
1484 * may be working around hardware quirks such as not respecting r1b
1485 * busy indications. In those cases, this wait-loop serves the purpose
1486 * of waiting for the prior command and data transfers to be done, and
1487 * SD cards are allowed to take up to 250ms for write and erase ops.
1488 * (It's usually more like 20-30ms in the real world.)
1491 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1493 slot_printf(slot, "Controller never released "
1494 "inhibit bit(s).\n");
1495 sdhci_dumpregs(slot);
1496 cmd->error = MMC_ERR_FAILED;
1497 sdhci_req_done(slot);
1504 /* Prepare command flags. */
1505 if (!(cmd->flags & MMC_RSP_PRESENT))
1506 flags = SDHCI_CMD_RESP_NONE;
1507 else if (cmd->flags & MMC_RSP_136)
1508 flags = SDHCI_CMD_RESP_LONG;
1509 else if (cmd->flags & MMC_RSP_BUSY)
1510 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1512 flags = SDHCI_CMD_RESP_SHORT;
1513 if (cmd->flags & MMC_RSP_CRC)
1514 flags |= SDHCI_CMD_CRC;
1515 if (cmd->flags & MMC_RSP_OPCODE)
1516 flags |= SDHCI_CMD_INDEX;
1518 flags |= SDHCI_CMD_DATA;
1519 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1520 flags |= SDHCI_CMD_TYPE_ABORT;
1522 sdhci_start_data(slot, cmd->data);
1524 * Interrupt aggregation: To reduce total number of interrupts
1525 * group response interrupt with data interrupt when possible.
1526 * If there going to be data interrupt, mask response one.
1528 if (slot->data_done == 0) {
1529 WR4(slot, SDHCI_SIGNAL_ENABLE,
1530 slot->intmask &= ~SDHCI_INT_RESPONSE);
1532 /* Set command argument. */
1533 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1534 /* Set data transfer mode. */
1535 sdhci_set_transfer_mode(slot, cmd->data);
1536 /* Start command. */
1537 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1538 /* Start timeout callout. */
1539 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1540 sdhci_timeout, slot);
1544 sdhci_finish_command(struct sdhci_slot *slot)
1552 * Interrupt aggregation: Restore command interrupt.
1553 * Main restore point for the case when command interrupt
1556 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1557 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1558 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1559 SDHCI_INT_RESPONSE);
1560 /* In case of error - reset host and return. */
1561 if (slot->curcmd->error) {
1562 if (slot->curcmd->error == MMC_ERR_BADCRC)
1563 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1564 sdhci_reset(slot, SDHCI_RESET_CMD);
1565 sdhci_reset(slot, SDHCI_RESET_DATA);
1569 /* If command has response - fetch it. */
1570 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1571 if (slot->curcmd->flags & MMC_RSP_136) {
1572 /* CRC is stripped so we need one byte shift. */
1574 for (i = 0; i < 4; i++) {
1575 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1577 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1578 slot->curcmd->resp[3 - i] = val;
1580 slot->curcmd->resp[3 - i] =
1586 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1588 /* If data ready - finish. */
1589 if (slot->data_done)
1594 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1596 uint32_t target_timeout, current_timeout;
1599 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1600 slot->data_done = 1;
1604 slot->data_done = 0;
1606 /* Calculate and set data timeout.*/
1607 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1608 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1611 target_timeout = 1000000;
1613 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1614 while (current_timeout < target_timeout && div < 0xE) {
1616 current_timeout <<= 1;
1618 /* Compensate for an off-by-one error in the CaFe chip.*/
1620 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1624 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1629 /* Use DMA if possible. */
1630 if ((slot->opt & SDHCI_HAVE_DMA))
1631 slot->flags |= SDHCI_USE_DMA;
1632 /* If data is small, broken DMA may return zeroes instead of data, */
1633 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1635 slot->flags &= ~SDHCI_USE_DMA;
1636 /* Some controllers require even block sizes. */
1637 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1638 ((data->len) & 0x3))
1639 slot->flags &= ~SDHCI_USE_DMA;
1640 /* Load DMA buffer. */
1641 if (slot->flags & SDHCI_USE_DMA) {
1642 if (data->flags & MMC_DATA_READ)
1643 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1644 BUS_DMASYNC_PREREAD);
1646 memcpy(slot->dmamem, data->data,
1647 (data->len < DMA_BLOCK_SIZE) ?
1648 data->len : DMA_BLOCK_SIZE);
1649 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1650 BUS_DMASYNC_PREWRITE);
1652 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1653 /* Interrupt aggregation: Mask border interrupt
1654 * for the last page and unmask else. */
1655 if (data->len == DMA_BLOCK_SIZE)
1656 slot->intmask &= ~SDHCI_INT_DMA_END;
1658 slot->intmask |= SDHCI_INT_DMA_END;
1659 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1661 /* Current data offset for both PIO and DMA. */
1663 /* Set block size and request IRQ on 4K border. */
1664 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
1665 (data->len < 512) ? data->len : 512));
1666 /* Set block count. */
1667 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1671 sdhci_finish_data(struct sdhci_slot *slot)
1673 struct mmc_data *data = slot->curcmd->data;
1676 /* Interrupt aggregation: Restore command interrupt.
1677 * Auxiliary restore point for the case when data interrupt
1678 * happened first. */
1679 if (!slot->cmd_done) {
1680 WR4(slot, SDHCI_SIGNAL_ENABLE,
1681 slot->intmask |= SDHCI_INT_RESPONSE);
1683 /* Unload rest of data from DMA buffer. */
1684 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
1685 if (data->flags & MMC_DATA_READ) {
1686 left = data->len - slot->offset;
1687 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1688 BUS_DMASYNC_POSTREAD);
1689 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1690 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1692 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1693 BUS_DMASYNC_POSTWRITE);
1695 slot->data_done = 1;
1696 /* If there was error - reset the host. */
1697 if (slot->curcmd->error) {
1698 if (slot->curcmd->error == MMC_ERR_BADCRC)
1699 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1700 sdhci_reset(slot, SDHCI_RESET_CMD);
1701 sdhci_reset(slot, SDHCI_RESET_DATA);
1705 /* If we already have command response - finish. */
1711 sdhci_start(struct sdhci_slot *slot)
1713 struct mmc_request *req;
1719 if (!(slot->flags & CMD_STARTED)) {
1720 slot->flags |= CMD_STARTED;
1721 sdhci_start_command(slot, req->cmd);
1724 /* We don't need this until using Auto-CMD12 feature
1725 if (!(slot->flags & STOP_STARTED) && req->stop) {
1726 slot->flags |= STOP_STARTED;
1727 sdhci_start_command(slot, req->stop);
1731 if (__predict_false(sdhci_debug > 1))
1732 slot_printf(slot, "result: %d\n", req->cmd->error);
1733 if (!req->cmd->error &&
1734 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1735 sdhci_reset(slot, SDHCI_RESET_CMD);
1736 sdhci_reset(slot, SDHCI_RESET_DATA);
1739 sdhci_req_done(slot);
1743 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1744 struct mmc_request *req)
1746 struct sdhci_slot *slot = device_get_ivars(reqdev);
1749 if (slot->req != NULL) {
1753 if (__predict_false(sdhci_debug > 1)) {
1755 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1756 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1757 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1758 (req->cmd->data)?req->cmd->data->flags:0);
1765 while (slot->req != NULL) {
1766 sdhci_generic_intr(slot);
1774 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1776 struct sdhci_slot *slot = device_get_ivars(reqdev);
1780 val = RD4(slot, SDHCI_PRESENT_STATE);
1782 return (!(val & SDHCI_WRITE_PROTECT));
1786 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1788 struct sdhci_slot *slot = device_get_ivars(reqdev);
1792 while (slot->bus_busy)
1793 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1796 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1802 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1804 struct sdhci_slot *slot = device_get_ivars(reqdev);
1807 /* Deactivate led. */
1808 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1816 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1819 if (!slot->curcmd) {
1820 slot_printf(slot, "Got command interrupt 0x%08x, but "
1821 "there is no active command.\n", intmask);
1822 sdhci_dumpregs(slot);
1825 if (intmask & SDHCI_INT_TIMEOUT)
1826 slot->curcmd->error = MMC_ERR_TIMEOUT;
1827 else if (intmask & SDHCI_INT_CRC)
1828 slot->curcmd->error = MMC_ERR_BADCRC;
1829 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1830 slot->curcmd->error = MMC_ERR_FIFO;
1832 sdhci_finish_command(slot);
1836 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1838 struct mmc_data *data;
1841 if (!slot->curcmd) {
1842 slot_printf(slot, "Got data interrupt 0x%08x, but "
1843 "there is no active command.\n", intmask);
1844 sdhci_dumpregs(slot);
1847 if (slot->curcmd->data == NULL &&
1848 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1849 slot_printf(slot, "Got data interrupt 0x%08x, but "
1850 "there is no active data operation.\n",
1852 sdhci_dumpregs(slot);
1855 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1856 slot->curcmd->error = MMC_ERR_TIMEOUT;
1857 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1858 slot->curcmd->error = MMC_ERR_BADCRC;
1859 if (slot->curcmd->data == NULL &&
1860 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1861 SDHCI_INT_DMA_END))) {
1862 slot_printf(slot, "Got data interrupt 0x%08x, but "
1863 "there is busy-only command.\n", intmask);
1864 sdhci_dumpregs(slot);
1865 slot->curcmd->error = MMC_ERR_INVALID;
1867 if (slot->curcmd->error) {
1868 /* No need to continue after any error. */
1872 /* Handle tuning completion interrupt. */
1873 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
1874 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
1875 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
1876 slot->req->flags |= MMC_TUNE_DONE;
1877 sdhci_finish_command(slot);
1878 sdhci_finish_data(slot);
1881 /* Handle PIO interrupt. */
1882 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1883 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1884 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1885 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
1887 slot->flags |= PLATFORM_DATA_STARTED;
1889 sdhci_transfer_pio(slot);
1891 /* Handle DMA border. */
1892 if (intmask & SDHCI_INT_DMA_END) {
1893 data = slot->curcmd->data;
1895 /* Unload DMA buffer ... */
1896 left = data->len - slot->offset;
1897 if (data->flags & MMC_DATA_READ) {
1898 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1899 BUS_DMASYNC_POSTREAD);
1900 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1901 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1903 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1904 BUS_DMASYNC_POSTWRITE);
1906 /* ... and reload it again. */
1907 slot->offset += DMA_BLOCK_SIZE;
1908 left = data->len - slot->offset;
1909 if (data->flags & MMC_DATA_READ) {
1910 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1911 BUS_DMASYNC_PREREAD);
1913 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1914 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
1915 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1916 BUS_DMASYNC_PREWRITE);
1918 /* Interrupt aggregation: Mask border interrupt
1919 * for the last page. */
1920 if (left == DMA_BLOCK_SIZE) {
1921 slot->intmask &= ~SDHCI_INT_DMA_END;
1922 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1925 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1927 /* We have got all data. */
1928 if (intmask & SDHCI_INT_DATA_END) {
1929 if (slot->flags & PLATFORM_DATA_STARTED) {
1930 slot->flags &= ~PLATFORM_DATA_STARTED;
1931 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1933 sdhci_finish_data(slot);
1936 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1937 if (slot->flags & PLATFORM_DATA_STARTED) {
1938 slot->flags &= ~PLATFORM_DATA_STARTED;
1939 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1941 sdhci_finish_data(slot);
1946 sdhci_acmd_irq(struct sdhci_slot *slot)
1950 err = RD4(slot, SDHCI_ACMD12_ERR);
1951 if (!slot->curcmd) {
1952 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1953 "there is no active command.\n", err);
1954 sdhci_dumpregs(slot);
1957 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1958 sdhci_reset(slot, SDHCI_RESET_CMD);
1962 sdhci_generic_intr(struct sdhci_slot *slot)
1964 uint32_t intmask, present;
1967 /* Read slot interrupt status. */
1968 intmask = RD4(slot, SDHCI_INT_STATUS);
1969 if (intmask == 0 || intmask == 0xffffffff) {
1973 if (__predict_false(sdhci_debug > 2))
1974 slot_printf(slot, "Interrupt %#x\n", intmask);
1976 /* Handle tuning error interrupt. */
1977 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
1978 slot_printf(slot, "Tuning error indicated\n");
1979 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1981 slot->curcmd->error = MMC_ERR_BADCRC;
1982 sdhci_finish_command(slot);
1985 /* Handle re-tuning interrupt. */
1986 if (__predict_false(intmask & SDHCI_INT_RETUNE))
1987 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1988 /* Handle card presence interrupts. */
1989 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1990 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
1992 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1993 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
1994 SDHCI_INT_CARD_INSERT;
1995 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1996 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1997 WR4(slot, SDHCI_INT_STATUS, intmask &
1998 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1999 sdhci_handle_card_present_locked(slot, present);
2001 /* Handle command interrupts. */
2002 if (intmask & SDHCI_INT_CMD_MASK) {
2003 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2004 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2006 /* Handle data interrupts. */
2007 if (intmask & SDHCI_INT_DATA_MASK) {
2008 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2009 /* Don't call data_irq in case of errored command. */
2010 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2011 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2013 /* Handle AutoCMD12 error interrupt. */
2014 if (intmask & SDHCI_INT_ACMD12ERR) {
2015 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2016 sdhci_acmd_irq(slot);
2018 /* Handle bus power interrupt. */
2019 if (intmask & SDHCI_INT_BUS_POWER) {
2020 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2021 slot_printf(slot, "Card is consuming too much power!\n");
2023 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2024 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2025 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2026 /* The rest is unknown. */
2028 WR4(slot, SDHCI_INT_STATUS, intmask);
2029 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2031 sdhci_dumpregs(slot);
2038 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2041 struct sdhci_slot *slot = device_get_ivars(child);
2046 case MMCBR_IVAR_BUS_MODE:
2047 *result = slot->host.ios.bus_mode;
2049 case MMCBR_IVAR_BUS_WIDTH:
2050 *result = slot->host.ios.bus_width;
2052 case MMCBR_IVAR_CHIP_SELECT:
2053 *result = slot->host.ios.chip_select;
2055 case MMCBR_IVAR_CLOCK:
2056 *result = slot->host.ios.clock;
2058 case MMCBR_IVAR_F_MIN:
2059 *result = slot->host.f_min;
2061 case MMCBR_IVAR_F_MAX:
2062 *result = slot->host.f_max;
2064 case MMCBR_IVAR_HOST_OCR:
2065 *result = slot->host.host_ocr;
2067 case MMCBR_IVAR_MODE:
2068 *result = slot->host.mode;
2070 case MMCBR_IVAR_OCR:
2071 *result = slot->host.ocr;
2073 case MMCBR_IVAR_POWER_MODE:
2074 *result = slot->host.ios.power_mode;
2076 case MMCBR_IVAR_VDD:
2077 *result = slot->host.ios.vdd;
2079 case MMCBR_IVAR_RETUNE_REQ:
2080 if (slot->opt & SDHCI_TUNING_ENABLED) {
2081 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2082 *result = retune_req_reset;
2085 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2086 *result = retune_req_normal;
2090 *result = retune_req_none;
2092 case MMCBR_IVAR_VCCQ:
2093 *result = slot->host.ios.vccq;
2095 case MMCBR_IVAR_CAPS:
2096 *result = slot->host.caps;
2098 case MMCBR_IVAR_TIMING:
2099 *result = slot->host.ios.timing;
2101 case MMCBR_IVAR_MAX_DATA:
2103 * Re-tuning modes 1 and 2 restrict the maximum data length
2104 * per read/write command to 4 MiB.
2106 if (slot->opt & SDHCI_TUNING_ENABLED &&
2107 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2108 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2109 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2114 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2116 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2125 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2128 struct sdhci_slot *slot = device_get_ivars(child);
2129 uint32_t clock, max_clock;
2135 case MMCBR_IVAR_BUS_MODE:
2136 slot->host.ios.bus_mode = value;
2138 case MMCBR_IVAR_BUS_WIDTH:
2139 slot->host.ios.bus_width = value;
2141 case MMCBR_IVAR_CHIP_SELECT:
2142 slot->host.ios.chip_select = value;
2144 case MMCBR_IVAR_CLOCK:
2146 max_clock = slot->max_clk;
2149 if (slot->version < SDHCI_SPEC_300) {
2150 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2157 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2161 clock = max_clock / (i + 2);
2165 slot->host.ios.clock = clock;
2167 slot->host.ios.clock = 0;
2169 case MMCBR_IVAR_MODE:
2170 slot->host.mode = value;
2172 case MMCBR_IVAR_OCR:
2173 slot->host.ocr = value;
2175 case MMCBR_IVAR_POWER_MODE:
2176 slot->host.ios.power_mode = value;
2178 case MMCBR_IVAR_VDD:
2179 slot->host.ios.vdd = value;
2181 case MMCBR_IVAR_VCCQ:
2182 slot->host.ios.vccq = value;
2184 case MMCBR_IVAR_TIMING:
2185 slot->host.ios.timing = value;
2187 case MMCBR_IVAR_CAPS:
2188 case MMCBR_IVAR_HOST_OCR:
2189 case MMCBR_IVAR_F_MIN:
2190 case MMCBR_IVAR_F_MAX:
2191 case MMCBR_IVAR_MAX_DATA:
2192 case MMCBR_IVAR_RETUNE_REQ:
2198 MODULE_VERSION(sdhci, 1);