2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/callout.h>
35 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
43 #include <sys/sysctl.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/stdarg.h>
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcreg.h>
52 #include <dev/mmc/mmcbrvar.h>
54 #include <dev/sdhci/sdhci.h>
59 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
61 static int sdhci_debug;
62 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
64 u_int sdhci_quirk_clear = 0;
65 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
66 0, "Mask of quirks to clear");
67 u_int sdhci_quirk_set = 0;
68 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
69 "Mask of quirks to set");
71 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
72 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
73 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
74 #define RD_MULTI_4(slot, off, ptr, count) \
75 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
77 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
78 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
79 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
80 #define WR_MULTI_4(slot, off, ptr, count) \
81 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
83 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
84 static void sdhci_card_poll(void *arg);
85 static void sdhci_card_task(void *arg, int pending);
86 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
87 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
88 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
89 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
91 static void sdhci_finish_command(struct sdhci_slot *slot);
92 static void sdhci_init(struct sdhci_slot *slot);
93 static void sdhci_read_block_pio(struct sdhci_slot *slot);
94 static void sdhci_req_done(struct sdhci_slot *slot);
95 static void sdhci_req_wakeup(struct mmc_request *req);
96 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask);
97 static void sdhci_retune(void *arg);
98 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
99 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
100 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
101 struct mmc_data *data);
102 static void sdhci_start(struct sdhci_slot *slot);
103 static void sdhci_timeout(void *arg);
104 static void sdhci_start_command(struct sdhci_slot *slot,
105 struct mmc_command *cmd);
106 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
107 static void sdhci_write_block_pio(struct sdhci_slot *slot);
108 static void sdhci_transfer_pio(struct sdhci_slot *slot);
110 /* helper routines */
111 static void sdhci_dumpregs(struct sdhci_slot *slot);
112 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
114 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
116 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot);
118 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
119 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
120 #define SDHCI_LOCK_INIT(_slot) \
121 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
122 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
123 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
124 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
126 #define SDHCI_DEFAULT_MAX_FREQ 50
128 #define SDHCI_200_MAX_DIVIDER 256
129 #define SDHCI_300_MAX_DIVIDER 2046
131 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
132 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
135 * Broadcom BCM577xx Controller Constants
137 /* Maximum divider supported by the default clock source. */
138 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
139 /* Alternative clock's base frequency. */
140 #define BCM577XX_ALT_CLOCK_BASE 63000000
142 #define BCM577XX_HOST_CONTROL 0x198
143 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
144 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
145 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
146 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
149 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
153 printf("getaddr: error %d\n", error);
156 *(bus_addr_t *)arg = segs[0].ds_addr;
160 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
165 retval = printf("%s-slot%d: ",
166 device_get_nameunit(slot->bus), slot->num);
169 retval += vprintf(fmt, ap);
175 sdhci_dumpregs(struct sdhci_slot *slot)
179 "============== REGISTER DUMP ==============\n");
181 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
182 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
183 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
184 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
185 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
186 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
187 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
188 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
189 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
190 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
191 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
192 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
193 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
194 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
195 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
196 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
197 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
198 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
199 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
200 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
201 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
202 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
203 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
204 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
207 "===========================================\n");
211 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
216 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
217 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
221 /* Some controllers need this kick or reset won't work. */
222 if ((mask & SDHCI_RESET_ALL) == 0 &&
223 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
224 /* This is to force an update */
227 sdhci_set_clock(slot, clock);
230 if (mask & SDHCI_RESET_ALL) {
235 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
237 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
239 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
240 * specification. The reset bit has internal propagation delay,
241 * so a fast read after write returns 0 even if reset process is
242 * in progress. The workaround is to poll for 1 before polling
243 * for 0. In the worst case, if we miss seeing it asserted the
244 * time we spent waiting is enough to ensure the reset finishes.
247 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
255 /* Wait max 100 ms */
257 /* Controller clears the bits when it's done */
258 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
260 slot_printf(slot, "Reset 0x%x never completed.\n",
262 sdhci_dumpregs(slot);
271 sdhci_tuning_intmask(struct sdhci_slot *slot)
276 if (slot->opt & SDHCI_TUNING_ENABLED) {
277 intmask |= SDHCI_INT_TUNEERR;
278 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
279 slot->retune_mode == SDHCI_RETUNE_MODE_3)
280 intmask |= SDHCI_INT_RETUNE;
286 sdhci_init(struct sdhci_slot *slot)
289 sdhci_reset(slot, SDHCI_RESET_ALL);
291 /* Enable interrupts. */
292 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
293 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
294 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
295 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
296 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
299 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
300 !(slot->opt & SDHCI_NON_REMOVABLE)) {
301 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
304 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
305 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
309 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
318 if (clock == slot->clock)
322 /* Turn off the clock. */
323 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
324 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
325 /* If no clock requested - leave it so. */
329 /* Determine the clock base frequency */
330 clk_base = slot->max_clk;
331 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
332 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
333 BCM577XX_CTRL_CLKSEL_MASK;
336 * Select clock source appropriate for the requested frequency.
338 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
339 clk_base = BCM577XX_ALT_CLOCK_BASE;
340 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
341 BCM577XX_CTRL_CLKSEL_SHIFT);
343 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
344 BCM577XX_CTRL_CLKSEL_SHIFT);
347 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
350 /* Recalculate timeout clock frequency based on the new sd clock. */
351 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
352 slot->timeout_clk = slot->clock / 1000;
354 if (slot->version < SDHCI_SPEC_300) {
355 /* Looking for highest freq <= clock. */
357 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
362 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
365 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
366 if (clock >= clk_base)
369 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
370 if ((clk_base / div) <= clock)
377 if (bootverbose || sdhci_debug)
378 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
379 div, clock, clk_base);
381 /* Now we have got divider, set it. */
382 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
383 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
384 << SDHCI_DIVIDER_HI_SHIFT;
386 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
388 clk |= SDHCI_CLOCK_INT_EN;
389 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
390 /* Wait up to 10 ms until it stabilize. */
392 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
393 & SDHCI_CLOCK_INT_STABLE)) {
396 "Internal clock never stabilised.\n");
397 sdhci_dumpregs(slot);
403 /* Pass clock signal to the bus. */
404 clk |= SDHCI_CLOCK_CARD_EN;
405 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
409 sdhci_set_power(struct sdhci_slot *slot, u_char power)
414 if (slot->power == power)
419 /* Turn off the power. */
421 WR1(slot, SDHCI_POWER_CONTROL, pwr);
422 /* If power down requested - leave it so. */
426 switch (1 << power) {
427 case MMC_OCR_LOW_VOLTAGE:
428 pwr |= SDHCI_POWER_180;
430 case MMC_OCR_290_300:
431 case MMC_OCR_300_310:
432 pwr |= SDHCI_POWER_300;
434 case MMC_OCR_320_330:
435 case MMC_OCR_330_340:
436 pwr |= SDHCI_POWER_330;
439 WR1(slot, SDHCI_POWER_CONTROL, pwr);
441 * Turn on VDD1 power. Note that at least some Intel controllers can
442 * fail to enable bus power on the first try after transiting from D3
443 * to D0, so we give them up to 2 ms.
445 pwr |= SDHCI_POWER_ON;
446 for (i = 0; i < 20; i++) {
447 WR1(slot, SDHCI_POWER_CONTROL, pwr);
448 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
452 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
453 slot_printf(slot, "Bus power failed to enable");
455 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
456 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
458 WR1(slot, SDHCI_POWER_CONTROL, pwr);
464 sdhci_read_block_pio(struct sdhci_slot *slot)
470 buffer = slot->curcmd->data->data;
471 buffer += slot->offset;
472 /* Transfer one block at a time. */
473 left = min(512, slot->curcmd->data->len - slot->offset);
474 slot->offset += left;
476 /* If we are too fast, broken controllers return zeroes. */
477 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
479 /* Handle unaligned and aligned buffer cases. */
480 if ((intptr_t)buffer & 3) {
482 data = RD4(slot, SDHCI_BUFFER);
484 buffer[1] = (data >> 8);
485 buffer[2] = (data >> 16);
486 buffer[3] = (data >> 24);
491 RD_MULTI_4(slot, SDHCI_BUFFER,
492 (uint32_t *)buffer, left >> 2);
495 /* Handle uneven size case. */
497 data = RD4(slot, SDHCI_BUFFER);
507 sdhci_write_block_pio(struct sdhci_slot *slot)
513 buffer = slot->curcmd->data->data;
514 buffer += slot->offset;
515 /* Transfer one block at a time. */
516 left = min(512, slot->curcmd->data->len - slot->offset);
517 slot->offset += left;
519 /* Handle unaligned and aligned buffer cases. */
520 if ((intptr_t)buffer & 3) {
528 WR4(slot, SDHCI_BUFFER, data);
531 WR_MULTI_4(slot, SDHCI_BUFFER,
532 (uint32_t *)buffer, left >> 2);
535 /* Handle uneven size case. */
542 WR4(slot, SDHCI_BUFFER, data);
547 sdhci_transfer_pio(struct sdhci_slot *slot)
550 /* Read as many blocks as possible. */
551 if (slot->curcmd->data->flags & MMC_DATA_READ) {
552 while (RD4(slot, SDHCI_PRESENT_STATE) &
553 SDHCI_DATA_AVAILABLE) {
554 sdhci_read_block_pio(slot);
555 if (slot->offset >= slot->curcmd->data->len)
559 while (RD4(slot, SDHCI_PRESENT_STATE) &
560 SDHCI_SPACE_AVAILABLE) {
561 sdhci_write_block_pio(slot);
562 if (slot->offset >= slot->curcmd->data->len)
569 sdhci_card_task(void *arg, int pending __unused)
571 struct sdhci_slot *slot = arg;
575 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
576 if (slot->dev == NULL) {
577 /* If card is present - attach mmc bus. */
578 if (bootverbose || sdhci_debug)
579 slot_printf(slot, "Card inserted\n");
580 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
583 device_set_ivars(d, slot);
584 (void)device_probe_and_attach(d);
589 if (slot->dev != NULL) {
590 /* If no card present - detach mmc bus. */
591 if (bootverbose || sdhci_debug)
592 slot_printf(slot, "Card removed\n");
595 slot->intmask &= ~sdhci_tuning_intmask(slot);
596 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
597 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
598 slot->opt &= ~SDHCI_TUNING_ENABLED;
600 callout_drain(&slot->retune_callout);
601 device_delete_child(slot->bus, d);
608 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
613 * If there was no card and now there is one, schedule the task to
614 * create the child device after a short delay. The delay is to
615 * debounce the card insert (sometimes the card detect pin stabilizes
616 * before the other pins have made good contact).
618 * If there was a card present and now it's gone, immediately schedule
619 * the task to delete the child device. No debouncing -- gone is gone,
620 * because once power is removed, a full card re-init is needed, and
621 * that happens by deleting and recreating the child device.
623 was_present = slot->dev != NULL;
624 if (!was_present && is_present) {
625 taskqueue_enqueue_timeout(taskqueue_swi_giant,
626 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
627 } else if (was_present && !is_present) {
628 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
633 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
637 sdhci_handle_card_present_locked(slot, is_present);
642 sdhci_card_poll(void *arg)
644 struct sdhci_slot *slot = arg;
646 sdhci_handle_card_present(slot,
647 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
648 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
649 sdhci_card_poll, slot);
653 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
655 kobjop_desc_t kobj_desc;
656 kobj_method_t *kobj_method;
657 uint32_t caps, caps2, freq, host_caps;
660 SDHCI_LOCK_INIT(slot);
664 /* Allocate DMA tag. */
665 err = bus_dma_tag_create(bus_get_dma_tag(dev),
666 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
667 BUS_SPACE_MAXADDR, NULL, NULL,
668 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
669 BUS_DMA_ALLOCNOW, NULL, NULL,
672 device_printf(dev, "Can't create DMA tag\n");
673 SDHCI_LOCK_DESTROY(slot);
676 /* Allocate DMA memory. */
677 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
678 BUS_DMA_NOWAIT, &slot->dmamap);
680 device_printf(dev, "Can't alloc DMA memory\n");
681 bus_dma_tag_destroy(slot->dmatag);
682 SDHCI_LOCK_DESTROY(slot);
685 /* Map the memory. */
686 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
687 (void *)slot->dmamem, DMA_BLOCK_SIZE,
688 sdhci_getaddr, &slot->paddr, 0);
689 if (err != 0 || slot->paddr == 0) {
690 device_printf(dev, "Can't load DMA memory\n");
691 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
692 bus_dma_tag_destroy(slot->dmatag);
693 SDHCI_LOCK_DESTROY(slot);
700 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
701 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
702 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
706 caps = RD4(slot, SDHCI_CAPABILITIES);
707 if (slot->version >= SDHCI_SPEC_300)
708 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
712 if (slot->version >= SDHCI_SPEC_300) {
713 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
714 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
716 "Driver doesn't support shared bus slots\n");
717 bus_dmamap_unload(slot->dmatag, slot->dmamap);
718 bus_dmamem_free(slot->dmatag, slot->dmamem,
720 bus_dma_tag_destroy(slot->dmatag);
721 SDHCI_LOCK_DESTROY(slot);
723 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
724 SDHCI_SLOTTYPE_EMBEDDED) {
725 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
728 /* Calculate base clock frequency. */
729 if (slot->version >= SDHCI_SPEC_300)
730 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
731 SDHCI_CLOCK_BASE_SHIFT;
733 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
734 SDHCI_CLOCK_BASE_SHIFT;
736 slot->max_clk = freq * 1000000;
738 * If the frequency wasn't in the capabilities and the hardware driver
739 * hasn't already set max_clk we're probably not going to work right
740 * with an assumption, so complain about it.
742 if (slot->max_clk == 0) {
743 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
744 device_printf(dev, "Hardware doesn't specify base clock "
745 "frequency, using %dMHz as default.\n",
746 SDHCI_DEFAULT_MAX_FREQ);
748 /* Calculate/set timeout clock frequency. */
749 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
750 slot->timeout_clk = slot->max_clk / 1000;
751 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
752 slot->timeout_clk = 1000;
754 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
755 SDHCI_TIMEOUT_CLK_SHIFT;
756 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
757 slot->timeout_clk *= 1000;
760 * If the frequency wasn't in the capabilities and the hardware driver
761 * hasn't already set timeout_clk we'll probably work okay using the
762 * max timeout, but still mention it.
764 if (slot->timeout_clk == 0) {
765 device_printf(dev, "Hardware doesn't specify timeout clock "
766 "frequency, setting BROKEN_TIMEOUT quirk.\n");
767 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
770 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
771 slot->host.f_max = slot->max_clk;
772 slot->host.host_ocr = 0;
773 if (caps & SDHCI_CAN_VDD_330)
774 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
775 if (caps & SDHCI_CAN_VDD_300)
776 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
777 /* 1.8V VDD is not supposed to be used for removable cards. */
778 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
779 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
780 if (slot->host.host_ocr == 0) {
781 device_printf(dev, "Hardware doesn't report any "
782 "support voltages.\n");
785 host_caps = MMC_CAP_4_BIT_DATA;
786 if (caps & SDHCI_CAN_DO_8BITBUS)
787 host_caps |= MMC_CAP_8_BIT_DATA;
788 if (caps & SDHCI_CAN_DO_HISPD)
789 host_caps |= MMC_CAP_HSPEED;
790 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
791 host_caps |= MMC_CAP_BOOT_NOACC;
792 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
793 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
795 /* Determine supported UHS-I and eMMC modes. */
796 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
797 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
798 if (caps2 & SDHCI_CAN_SDR104) {
799 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
800 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
801 host_caps |= MMC_CAP_MMC_HS200;
802 } else if (caps2 & SDHCI_CAN_SDR50)
803 host_caps |= MMC_CAP_UHS_SDR50;
804 if (caps2 & SDHCI_CAN_DDR50 &&
805 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
806 host_caps |= MMC_CAP_UHS_DDR50;
807 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
808 host_caps |= MMC_CAP_MMC_DDR52;
809 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
810 caps2 & SDHCI_CAN_MMC_HS400)
811 host_caps |= MMC_CAP_MMC_HS400;
814 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
815 * default NULL implementation.
817 kobj_desc = &sdhci_set_uhs_timing_desc;
818 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
820 if (kobj_method == &kobj_desc->deflt)
821 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
822 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
823 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
825 #define SDHCI_CAP_MODES_TUNING(caps2) \
826 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
827 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
831 * Disable UHS-I and eMMC modes that require (re-)tuning if either
832 * the tune or re-tune method is the default NULL implementation.
834 kobj_desc = &mmcbr_tune_desc;
835 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
837 if (kobj_method == &kobj_desc->deflt)
839 kobj_desc = &mmcbr_retune_desc;
840 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
842 if (kobj_method == &kobj_desc->deflt) {
844 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
847 /* Allocate tuning structures and determine tuning parameters. */
848 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
849 slot->opt |= SDHCI_TUNING_SUPPORTED;
850 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
852 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
854 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
856 if (caps2 & SDHCI_TUNE_SDR50)
857 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
858 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
859 SDHCI_RETUNE_MODES_SHIFT;
860 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
861 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
862 SDHCI_RETUNE_CNT_SHIFT;
863 if (slot->retune_count > 0xb) {
864 device_printf(dev, "Unknown re-tuning count "
865 "%x, using 1 sec\n", slot->retune_count);
866 slot->retune_count = 1;
867 } else if (slot->retune_count != 0)
869 1 << (slot->retune_count - 1);
873 #undef SDHCI_CAP_MODES_TUNING
875 /* Determine supported VCCQ signaling levels. */
876 host_caps |= MMC_CAP_SIGNALING_330;
877 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
878 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
879 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
880 MMC_CAP_MMC_HS400_180))
881 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
884 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
885 * default NULL implementation. Disable 1.2 V support if it's the
886 * generic SDHCI implementation.
888 kobj_desc = &mmcbr_switch_vccq_desc;
889 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
891 if (kobj_method == &kobj_desc->deflt)
892 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
893 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
894 host_caps &= ~MMC_CAP_SIGNALING_120;
896 /* Determine supported driver types (type B is always mandatory). */
897 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
898 host_caps |= MMC_CAP_DRIVER_TYPE_A;
899 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
900 host_caps |= MMC_CAP_DRIVER_TYPE_C;
901 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
902 host_caps |= MMC_CAP_DRIVER_TYPE_D;
903 slot->host.caps = host_caps;
905 /* Decide if we have usable DMA. */
906 if (caps & SDHCI_CAN_DO_DMA)
907 slot->opt |= SDHCI_HAVE_DMA;
909 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
910 slot->opt &= ~SDHCI_HAVE_DMA;
911 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
912 slot->opt |= SDHCI_HAVE_DMA;
913 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
914 slot->opt |= SDHCI_NON_REMOVABLE;
917 * Use platform-provided transfer backend
918 * with PIO as a fallback mechanism
920 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
921 slot->opt &= ~SDHCI_HAVE_DMA;
923 if (bootverbose || sdhci_debug) {
925 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
926 slot->max_clk / 1000000,
927 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
928 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
929 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
930 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
931 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
932 ((caps & SDHCI_CAN_VDD_180) &&
933 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
934 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
935 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
936 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
937 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
938 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
939 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
940 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
941 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
943 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
944 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
945 slot_printf(slot, "eMMC:%s%s%s%s\n",
946 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
947 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
948 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
950 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
951 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
953 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
954 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
955 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
956 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
957 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
958 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
959 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
960 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
961 if (slot->opt & SDHCI_TUNING_SUPPORTED)
962 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
963 slot->retune_count, slot->retune_mode + 1);
964 sdhci_dumpregs(slot);
968 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
969 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
970 "timeout", CTLFLAG_RW, &slot->timeout, 0,
971 "Maximum timeout for SDHCI transfers (in secs)");
972 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
973 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
974 sdhci_card_task, slot);
975 callout_init(&slot->card_poll_callout, 1);
976 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
977 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
979 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
980 !(slot->opt & SDHCI_NON_REMOVABLE)) {
981 callout_reset(&slot->card_poll_callout,
982 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
991 sdhci_start_slot(struct sdhci_slot *slot)
994 sdhci_card_task(slot, 0);
998 sdhci_cleanup_slot(struct sdhci_slot *slot)
1002 callout_drain(&slot->timeout_callout);
1003 callout_drain(&slot->card_poll_callout);
1004 callout_drain(&slot->retune_callout);
1005 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1006 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1013 device_delete_child(slot->bus, d);
1016 sdhci_reset(slot, SDHCI_RESET_ALL);
1018 bus_dmamap_unload(slot->dmatag, slot->dmamap);
1019 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
1020 bus_dma_tag_destroy(slot->dmatag);
1021 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1022 free(slot->tune_req, M_DEVBUF);
1023 free(slot->tune_cmd, M_DEVBUF);
1024 free(slot->tune_data, M_DEVBUF);
1027 SDHCI_LOCK_DESTROY(slot);
1033 sdhci_generic_suspend(struct sdhci_slot *slot)
1037 * We expect the MMC layer to issue initial tuning after resume.
1038 * Otherwise, we'd need to indicate re-tuning including circuit reset
1039 * being required at least for re-tuning modes 1 and 2 ourselves.
1041 callout_drain(&slot->retune_callout);
1043 slot->opt &= ~SDHCI_TUNING_ENABLED;
1044 sdhci_reset(slot, SDHCI_RESET_ALL);
1051 sdhci_generic_resume(struct sdhci_slot *slot)
1062 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1065 if (slot->version >= SDHCI_SPEC_300)
1066 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1068 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1072 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1075 if (slot->opt & SDHCI_NON_REMOVABLE)
1078 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1082 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1084 struct mmc_ios *ios;
1087 if (slot->version < SDHCI_SPEC_300)
1090 SDHCI_ASSERT_LOCKED(slot);
1091 ios = &slot->host.ios;
1092 sdhci_set_clock(slot, 0);
1093 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1094 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1095 if (ios->clock > SD_SDR50_MAX) {
1096 if (ios->timing == bus_timing_mmc_hs400 ||
1097 ios->timing == bus_timing_mmc_hs400es)
1098 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1100 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1102 else if (ios->clock > SD_SDR25_MAX)
1103 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1104 else if (ios->clock > SD_SDR12_MAX) {
1105 if (ios->timing == bus_timing_uhs_ddr50 ||
1106 ios->timing == bus_timing_mmc_ddr52)
1107 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1109 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1110 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1111 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1112 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1113 sdhci_set_clock(slot, ios->clock);
1117 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1119 struct sdhci_slot *slot = device_get_ivars(reqdev);
1120 struct mmc_ios *ios = &slot->host.ios;
1123 /* Do full reset on bus power down to clear from any state. */
1124 if (ios->power_mode == power_off) {
1125 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1128 /* Configure the bus. */
1129 sdhci_set_clock(slot, ios->clock);
1130 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1131 if (ios->bus_width == bus_width_8) {
1132 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1133 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1134 } else if (ios->bus_width == bus_width_4) {
1135 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1136 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1137 } else if (ios->bus_width == bus_width_1) {
1138 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1139 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1141 panic("Invalid bus width: %d", ios->bus_width);
1143 if (ios->clock > SD_SDR12_MAX &&
1144 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1145 slot->hostctrl |= SDHCI_CTRL_HISPD;
1147 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1148 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1149 SDHCI_SET_UHS_TIMING(brdev, slot);
1150 /* Some controllers like reset after bus changes. */
1151 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1152 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1159 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1161 struct sdhci_slot *slot = device_get_ivars(reqdev);
1166 if (slot->version < SDHCI_SPEC_300)
1170 vccq = slot->host.ios.vccq;
1172 sdhci_set_clock(slot, 0);
1173 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1176 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1178 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1179 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1181 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1182 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1187 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1191 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1193 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1194 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1196 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1197 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1203 "Attempt to set unsupported signaling voltage\n");
1208 sdhci_set_clock(slot, slot->host.ios.clock);
1214 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1216 struct sdhci_slot *slot = device_get_ivars(reqdev);
1217 struct mmc_ios *ios = &slot->host.ios;
1218 struct mmc_command *tune_cmd;
1219 struct mmc_data *tune_data;
1223 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1226 slot->retune_ticks = slot->retune_count * hz;
1227 opcode = MMC_SEND_TUNING_BLOCK;
1229 switch (ios->timing) {
1230 case bus_timing_mmc_hs400:
1231 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1234 case bus_timing_mmc_hs200:
1236 * In HS400 mode, controllers use the data strobe line to
1237 * latch data from the devices so periodic re-tuning isn't
1238 * expected to be required.
1241 slot->retune_ticks = 0;
1242 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1244 case bus_timing_uhs_ddr50:
1245 case bus_timing_uhs_sdr104:
1247 case bus_timing_uhs_sdr50:
1248 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1256 tune_cmd = slot->tune_cmd;
1257 memset(tune_cmd, 0, sizeof(*tune_cmd));
1258 tune_cmd->opcode = opcode;
1259 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1260 tune_data = tune_cmd->data = slot->tune_data;
1261 memset(tune_data, 0, sizeof(*tune_data));
1262 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1263 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1265 tune_data->flags = MMC_DATA_READ;
1266 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1268 slot->opt &= ~SDHCI_TUNING_ENABLED;
1269 err = sdhci_exec_tuning(slot, true);
1271 slot->opt |= SDHCI_TUNING_ENABLED;
1272 slot->intmask |= sdhci_tuning_intmask(slot);
1273 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1274 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1275 if (slot->retune_ticks) {
1276 callout_reset(&slot->retune_callout, slot->retune_ticks,
1277 sdhci_retune, slot);
1285 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1287 struct sdhci_slot *slot = device_get_ivars(reqdev);
1290 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1293 /* HS400 must be tuned in HS200 mode. */
1294 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1298 err = sdhci_exec_tuning(slot, reset);
1300 * There are two ways sdhci_exec_tuning() can fail:
1301 * EBUSY should not actually happen when requests are only issued
1302 * with the host properly acquired, and
1303 * EIO re-tuning failed (but it did work initially).
1305 * In both cases, we should retry at later point if periodic re-tuning
1306 * is enabled. Note that due to slot->retune_req not being cleared in
1307 * these failure cases, the MMC layer should trigger another attempt at
1308 * re-tuning with the next request anyway, though.
1310 if (slot->retune_ticks) {
1311 callout_reset(&slot->retune_callout, slot->retune_ticks,
1312 sdhci_retune, slot);
1319 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1321 struct mmc_request *tune_req;
1322 struct mmc_command *tune_cmd;
1328 SDHCI_ASSERT_LOCKED(slot);
1329 if (slot->req != NULL)
1332 /* Tuning doesn't work with DMA enabled. */
1334 slot->opt = opt & ~SDHCI_HAVE_DMA;
1337 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1338 * kind of interrupt we receive in response to a tuning request.
1340 intmask = slot->intmask;
1341 slot->intmask = SDHCI_INT_DATA_AVAIL;
1342 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1343 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1345 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1347 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1349 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1350 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1352 tune_req = slot->tune_req;
1353 tune_cmd = slot->tune_cmd;
1354 for (i = 0; i < MMC_TUNING_MAX; i++) {
1355 memset(tune_req, 0, sizeof(*tune_req));
1356 tune_req->cmd = tune_cmd;
1357 tune_req->done = sdhci_req_wakeup;
1358 tune_req->done_data = slot;
1359 slot->req = tune_req;
1362 while (!(tune_req->flags & MMC_REQ_DONE))
1363 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1364 if (!(tune_req->flags & MMC_TUNE_DONE))
1366 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1367 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1369 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1374 * Restore DMA usage and interrupts.
1375 * Note that the interrupt aggregation code might have cleared
1376 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1377 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1378 * doesn't lose these.
1381 slot->intmask = intmask;
1382 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1383 SDHCI_INT_RESPONSE);
1384 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1386 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1387 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1388 slot->retune_req = 0;
1392 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1393 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1394 SDHCI_CTRL2_SAMPLING_CLOCK));
1395 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1400 sdhci_retune(void *arg)
1402 struct sdhci_slot *slot = arg;
1404 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1408 sdhci_req_done(struct sdhci_slot *slot)
1410 struct mmc_request *req;
1412 if (slot->req != NULL && slot->curcmd != NULL) {
1413 callout_stop(&slot->timeout_callout);
1416 slot->curcmd = NULL;
1422 sdhci_req_wakeup(struct mmc_request *req)
1424 struct sdhci_slot *slot;
1426 slot = req->done_data;
1427 req->flags |= MMC_REQ_DONE;
1432 sdhci_timeout(void *arg)
1434 struct sdhci_slot *slot = arg;
1436 if (slot->curcmd != NULL) {
1437 slot_printf(slot, "Controller timeout\n");
1438 sdhci_dumpregs(slot);
1439 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1440 slot->curcmd->error = MMC_ERR_TIMEOUT;
1441 sdhci_req_done(slot);
1443 slot_printf(slot, "Spurious timeout - no active command\n");
1448 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
1455 mode = SDHCI_TRNS_BLK_CNT_EN;
1456 if (data->len > 512) {
1457 mode |= SDHCI_TRNS_MULTI;
1458 if (__predict_true(slot->req->stop &&
1459 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1460 mode |= SDHCI_TRNS_ACMD12;
1462 if (data->flags & MMC_DATA_READ)
1463 mode |= SDHCI_TRNS_READ;
1464 if (slot->flags & SDHCI_USE_DMA)
1465 mode |= SDHCI_TRNS_DMA;
1467 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1471 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1479 cmd->error = MMC_ERR_NONE;
1481 /* This flags combination is not supported by controller. */
1482 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1483 slot_printf(slot, "Unsupported response type!\n");
1484 cmd->error = MMC_ERR_FAILED;
1485 sdhci_req_done(slot);
1490 * Do not issue command if there is no card, clock or power.
1491 * Controller will not detect timeout without clock active.
1493 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1496 cmd->error = MMC_ERR_FAILED;
1497 sdhci_req_done(slot);
1500 /* Always wait for free CMD bus. */
1501 mask = SDHCI_CMD_INHIBIT;
1502 /* Wait for free DAT if we have data or busy signal. */
1503 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
1504 mask |= SDHCI_DAT_INHIBIT;
1506 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1507 * that these latter are also special in that SDHCI_CMD_DATA should
1508 * be set below but no actual data is ever read from the controller.
1510 if (cmd == slot->req->stop ||
1511 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1512 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1513 mask &= ~SDHCI_DAT_INHIBIT;
1515 * Wait for bus no more then 250 ms. Typically there will be no wait
1516 * here at all, but when writing a crash dump we may be bypassing the
1517 * host platform's interrupt handler, and in some cases that handler
1518 * may be working around hardware quirks such as not respecting r1b
1519 * busy indications. In those cases, this wait-loop serves the purpose
1520 * of waiting for the prior command and data transfers to be done, and
1521 * SD cards are allowed to take up to 250ms for write and erase ops.
1522 * (It's usually more like 20-30ms in the real world.)
1525 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1527 slot_printf(slot, "Controller never released "
1528 "inhibit bit(s).\n");
1529 sdhci_dumpregs(slot);
1530 cmd->error = MMC_ERR_FAILED;
1531 sdhci_req_done(slot);
1538 /* Prepare command flags. */
1539 if (!(cmd->flags & MMC_RSP_PRESENT))
1540 flags = SDHCI_CMD_RESP_NONE;
1541 else if (cmd->flags & MMC_RSP_136)
1542 flags = SDHCI_CMD_RESP_LONG;
1543 else if (cmd->flags & MMC_RSP_BUSY)
1544 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1546 flags = SDHCI_CMD_RESP_SHORT;
1547 if (cmd->flags & MMC_RSP_CRC)
1548 flags |= SDHCI_CMD_CRC;
1549 if (cmd->flags & MMC_RSP_OPCODE)
1550 flags |= SDHCI_CMD_INDEX;
1552 flags |= SDHCI_CMD_DATA;
1553 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1554 flags |= SDHCI_CMD_TYPE_ABORT;
1556 sdhci_start_data(slot, cmd->data);
1558 * Interrupt aggregation: To reduce total number of interrupts
1559 * group response interrupt with data interrupt when possible.
1560 * If there going to be data interrupt, mask response one.
1562 if (slot->data_done == 0) {
1563 WR4(slot, SDHCI_SIGNAL_ENABLE,
1564 slot->intmask &= ~SDHCI_INT_RESPONSE);
1566 /* Set command argument. */
1567 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1568 /* Set data transfer mode. */
1569 sdhci_set_transfer_mode(slot, cmd->data);
1570 /* Start command. */
1571 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1572 /* Start timeout callout. */
1573 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1574 sdhci_timeout, slot);
1578 sdhci_finish_command(struct sdhci_slot *slot)
1586 * Interrupt aggregation: Restore command interrupt.
1587 * Main restore point for the case when command interrupt
1590 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1591 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1592 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1593 SDHCI_INT_RESPONSE);
1594 /* In case of error - reset host and return. */
1595 if (slot->curcmd->error) {
1596 if (slot->curcmd->error == MMC_ERR_BADCRC)
1597 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1598 sdhci_reset(slot, SDHCI_RESET_CMD);
1599 sdhci_reset(slot, SDHCI_RESET_DATA);
1603 /* If command has response - fetch it. */
1604 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1605 if (slot->curcmd->flags & MMC_RSP_136) {
1606 /* CRC is stripped so we need one byte shift. */
1608 for (i = 0; i < 4; i++) {
1609 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1611 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1612 slot->curcmd->resp[3 - i] = val;
1614 slot->curcmd->resp[3 - i] =
1620 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1622 /* If data ready - finish. */
1623 if (slot->data_done)
1628 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1630 uint32_t target_timeout, current_timeout;
1633 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1634 slot->data_done = 1;
1638 slot->data_done = 0;
1640 /* Calculate and set data timeout.*/
1641 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1642 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1645 target_timeout = 1000000;
1647 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1648 while (current_timeout < target_timeout && div < 0xE) {
1650 current_timeout <<= 1;
1652 /* Compensate for an off-by-one error in the CaFe chip.*/
1654 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1658 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1663 /* Use DMA if possible. */
1664 if ((slot->opt & SDHCI_HAVE_DMA))
1665 slot->flags |= SDHCI_USE_DMA;
1666 /* If data is small, broken DMA may return zeroes instead of data, */
1667 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1669 slot->flags &= ~SDHCI_USE_DMA;
1670 /* Some controllers require even block sizes. */
1671 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1672 ((data->len) & 0x3))
1673 slot->flags &= ~SDHCI_USE_DMA;
1674 /* Load DMA buffer. */
1675 if (slot->flags & SDHCI_USE_DMA) {
1676 if (data->flags & MMC_DATA_READ)
1677 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1678 BUS_DMASYNC_PREREAD);
1680 memcpy(slot->dmamem, data->data,
1681 (data->len < DMA_BLOCK_SIZE) ?
1682 data->len : DMA_BLOCK_SIZE);
1683 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1684 BUS_DMASYNC_PREWRITE);
1686 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1687 /* Interrupt aggregation: Mask border interrupt
1688 * for the last page and unmask else. */
1689 if (data->len == DMA_BLOCK_SIZE)
1690 slot->intmask &= ~SDHCI_INT_DMA_END;
1692 slot->intmask |= SDHCI_INT_DMA_END;
1693 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1695 /* Current data offset for both PIO and DMA. */
1697 /* Set block size and request IRQ on 4K border. */
1698 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
1699 (data->len < 512) ? data->len : 512));
1700 /* Set block count. */
1701 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1705 sdhci_finish_data(struct sdhci_slot *slot)
1707 struct mmc_data *data = slot->curcmd->data;
1710 /* Interrupt aggregation: Restore command interrupt.
1711 * Auxiliary restore point for the case when data interrupt
1712 * happened first. */
1713 if (!slot->cmd_done) {
1714 WR4(slot, SDHCI_SIGNAL_ENABLE,
1715 slot->intmask |= SDHCI_INT_RESPONSE);
1717 /* Unload rest of data from DMA buffer. */
1718 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
1719 slot->curcmd->data != NULL) {
1720 if (data->flags & MMC_DATA_READ) {
1721 left = data->len - slot->offset;
1722 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1723 BUS_DMASYNC_POSTREAD);
1724 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1725 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1727 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1728 BUS_DMASYNC_POSTWRITE);
1730 slot->data_done = 1;
1731 /* If there was error - reset the host. */
1732 if (slot->curcmd->error) {
1733 if (slot->curcmd->error == MMC_ERR_BADCRC)
1734 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1735 sdhci_reset(slot, SDHCI_RESET_CMD);
1736 sdhci_reset(slot, SDHCI_RESET_DATA);
1740 /* If we already have command response - finish. */
1746 sdhci_start(struct sdhci_slot *slot)
1748 struct mmc_request *req;
1754 if (!(slot->flags & CMD_STARTED)) {
1755 slot->flags |= CMD_STARTED;
1756 sdhci_start_command(slot, req->cmd);
1759 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
1760 !(slot->flags & STOP_STARTED) && req->stop) {
1761 slot->flags |= STOP_STARTED;
1762 sdhci_start_command(slot, req->stop);
1765 if (__predict_false(sdhci_debug > 1))
1766 slot_printf(slot, "result: %d\n", req->cmd->error);
1767 if (!req->cmd->error &&
1768 ((slot->curcmd == req->stop &&
1769 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
1770 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1771 sdhci_reset(slot, SDHCI_RESET_CMD);
1772 sdhci_reset(slot, SDHCI_RESET_DATA);
1775 sdhci_req_done(slot);
1779 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1780 struct mmc_request *req)
1782 struct sdhci_slot *slot = device_get_ivars(reqdev);
1785 if (slot->req != NULL) {
1789 if (__predict_false(sdhci_debug > 1)) {
1791 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1792 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1793 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1794 (req->cmd->data)?req->cmd->data->flags:0);
1801 while (slot->req != NULL) {
1802 sdhci_generic_intr(slot);
1810 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1812 struct sdhci_slot *slot = device_get_ivars(reqdev);
1816 val = RD4(slot, SDHCI_PRESENT_STATE);
1818 return (!(val & SDHCI_WRITE_PROTECT));
1822 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1824 struct sdhci_slot *slot = device_get_ivars(reqdev);
1828 while (slot->bus_busy)
1829 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1832 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1838 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1840 struct sdhci_slot *slot = device_get_ivars(reqdev);
1843 /* Deactivate led. */
1844 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1852 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1855 if (!slot->curcmd) {
1856 slot_printf(slot, "Got command interrupt 0x%08x, but "
1857 "there is no active command.\n", intmask);
1858 sdhci_dumpregs(slot);
1861 if (intmask & SDHCI_INT_TIMEOUT)
1862 slot->curcmd->error = MMC_ERR_TIMEOUT;
1863 else if (intmask & SDHCI_INT_CRC)
1864 slot->curcmd->error = MMC_ERR_BADCRC;
1865 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1866 slot->curcmd->error = MMC_ERR_FIFO;
1868 sdhci_finish_command(slot);
1872 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1874 struct mmc_data *data;
1877 if (!slot->curcmd) {
1878 slot_printf(slot, "Got data interrupt 0x%08x, but "
1879 "there is no active command.\n", intmask);
1880 sdhci_dumpregs(slot);
1883 if (slot->curcmd->data == NULL &&
1884 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1885 slot_printf(slot, "Got data interrupt 0x%08x, but "
1886 "there is no active data operation.\n",
1888 sdhci_dumpregs(slot);
1891 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1892 slot->curcmd->error = MMC_ERR_TIMEOUT;
1893 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1894 slot->curcmd->error = MMC_ERR_BADCRC;
1895 if (slot->curcmd->data == NULL &&
1896 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1897 SDHCI_INT_DMA_END))) {
1898 slot_printf(slot, "Got data interrupt 0x%08x, but "
1899 "there is busy-only command.\n", intmask);
1900 sdhci_dumpregs(slot);
1901 slot->curcmd->error = MMC_ERR_INVALID;
1903 if (slot->curcmd->error) {
1904 /* No need to continue after any error. */
1908 /* Handle tuning completion interrupt. */
1909 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
1910 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
1911 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
1912 slot->req->flags |= MMC_TUNE_DONE;
1913 sdhci_finish_command(slot);
1914 sdhci_finish_data(slot);
1917 /* Handle PIO interrupt. */
1918 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1919 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1920 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1921 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
1923 slot->flags |= PLATFORM_DATA_STARTED;
1925 sdhci_transfer_pio(slot);
1927 /* Handle DMA border. */
1928 if (intmask & SDHCI_INT_DMA_END) {
1929 data = slot->curcmd->data;
1931 /* Unload DMA buffer ... */
1932 left = data->len - slot->offset;
1933 if (data->flags & MMC_DATA_READ) {
1934 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1935 BUS_DMASYNC_POSTREAD);
1936 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1937 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1939 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1940 BUS_DMASYNC_POSTWRITE);
1942 /* ... and reload it again. */
1943 slot->offset += DMA_BLOCK_SIZE;
1944 left = data->len - slot->offset;
1945 if (data->flags & MMC_DATA_READ) {
1946 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1947 BUS_DMASYNC_PREREAD);
1949 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1950 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
1951 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1952 BUS_DMASYNC_PREWRITE);
1954 /* Interrupt aggregation: Mask border interrupt
1955 * for the last page. */
1956 if (left == DMA_BLOCK_SIZE) {
1957 slot->intmask &= ~SDHCI_INT_DMA_END;
1958 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1961 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1963 /* We have got all data. */
1964 if (intmask & SDHCI_INT_DATA_END) {
1965 if (slot->flags & PLATFORM_DATA_STARTED) {
1966 slot->flags &= ~PLATFORM_DATA_STARTED;
1967 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1969 sdhci_finish_data(slot);
1972 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1973 if (slot->flags & PLATFORM_DATA_STARTED) {
1974 slot->flags &= ~PLATFORM_DATA_STARTED;
1975 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1977 sdhci_finish_data(slot);
1982 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
1985 if (!slot->curcmd) {
1986 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1987 "there is no active command.\n", acmd_err);
1988 sdhci_dumpregs(slot);
1991 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
1992 sdhci_reset(slot, SDHCI_RESET_CMD);
1996 sdhci_generic_intr(struct sdhci_slot *slot)
1998 uint32_t intmask, present;
2002 /* Read slot interrupt status. */
2003 intmask = RD4(slot, SDHCI_INT_STATUS);
2004 if (intmask == 0 || intmask == 0xffffffff) {
2008 if (__predict_false(sdhci_debug > 2))
2009 slot_printf(slot, "Interrupt %#x\n", intmask);
2011 /* Handle tuning error interrupt. */
2012 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2013 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2014 slot_printf(slot, "Tuning error indicated\n");
2015 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2017 slot->curcmd->error = MMC_ERR_BADCRC;
2018 sdhci_finish_command(slot);
2021 /* Handle re-tuning interrupt. */
2022 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2023 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2024 /* Handle card presence interrupts. */
2025 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2026 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2028 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2029 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2030 SDHCI_INT_CARD_INSERT;
2031 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2032 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2033 WR4(slot, SDHCI_INT_STATUS, intmask &
2034 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2035 sdhci_handle_card_present_locked(slot, present);
2037 /* Handle command interrupts. */
2038 if (intmask & SDHCI_INT_CMD_MASK) {
2039 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2040 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2042 /* Handle data interrupts. */
2043 if (intmask & SDHCI_INT_DATA_MASK) {
2044 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2045 /* Don't call data_irq in case of errored command. */
2046 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2047 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2049 /* Handle AutoCMD12 error interrupt. */
2050 if (intmask & SDHCI_INT_ACMD12ERR) {
2051 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2052 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2053 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2054 sdhci_acmd_irq(slot, val16);
2056 /* Handle bus power interrupt. */
2057 if (intmask & SDHCI_INT_BUS_POWER) {
2058 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2059 slot_printf(slot, "Card is consuming too much power!\n");
2061 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2062 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2063 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2064 /* The rest is unknown. */
2066 WR4(slot, SDHCI_INT_STATUS, intmask);
2067 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2069 sdhci_dumpregs(slot);
2076 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2079 struct sdhci_slot *slot = device_get_ivars(child);
2084 case MMCBR_IVAR_BUS_MODE:
2085 *result = slot->host.ios.bus_mode;
2087 case MMCBR_IVAR_BUS_WIDTH:
2088 *result = slot->host.ios.bus_width;
2090 case MMCBR_IVAR_CHIP_SELECT:
2091 *result = slot->host.ios.chip_select;
2093 case MMCBR_IVAR_CLOCK:
2094 *result = slot->host.ios.clock;
2096 case MMCBR_IVAR_F_MIN:
2097 *result = slot->host.f_min;
2099 case MMCBR_IVAR_F_MAX:
2100 *result = slot->host.f_max;
2102 case MMCBR_IVAR_HOST_OCR:
2103 *result = slot->host.host_ocr;
2105 case MMCBR_IVAR_MODE:
2106 *result = slot->host.mode;
2108 case MMCBR_IVAR_OCR:
2109 *result = slot->host.ocr;
2111 case MMCBR_IVAR_POWER_MODE:
2112 *result = slot->host.ios.power_mode;
2114 case MMCBR_IVAR_VDD:
2115 *result = slot->host.ios.vdd;
2117 case MMCBR_IVAR_RETUNE_REQ:
2118 if (slot->opt & SDHCI_TUNING_ENABLED) {
2119 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2120 *result = retune_req_reset;
2123 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2124 *result = retune_req_normal;
2128 *result = retune_req_none;
2130 case MMCBR_IVAR_VCCQ:
2131 *result = slot->host.ios.vccq;
2133 case MMCBR_IVAR_CAPS:
2134 *result = slot->host.caps;
2136 case MMCBR_IVAR_TIMING:
2137 *result = slot->host.ios.timing;
2139 case MMCBR_IVAR_MAX_DATA:
2141 * Re-tuning modes 1 and 2 restrict the maximum data length
2142 * per read/write command to 4 MiB.
2144 if (slot->opt & SDHCI_TUNING_ENABLED &&
2145 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2146 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2147 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2152 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2154 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2163 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2166 struct sdhci_slot *slot = device_get_ivars(child);
2167 uint32_t clock, max_clock;
2173 case MMCBR_IVAR_BUS_MODE:
2174 slot->host.ios.bus_mode = value;
2176 case MMCBR_IVAR_BUS_WIDTH:
2177 slot->host.ios.bus_width = value;
2179 case MMCBR_IVAR_CHIP_SELECT:
2180 slot->host.ios.chip_select = value;
2182 case MMCBR_IVAR_CLOCK:
2184 max_clock = slot->max_clk;
2187 if (slot->version < SDHCI_SPEC_300) {
2188 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2195 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2199 clock = max_clock / (i + 2);
2203 slot->host.ios.clock = clock;
2205 slot->host.ios.clock = 0;
2207 case MMCBR_IVAR_MODE:
2208 slot->host.mode = value;
2210 case MMCBR_IVAR_OCR:
2211 slot->host.ocr = value;
2213 case MMCBR_IVAR_POWER_MODE:
2214 slot->host.ios.power_mode = value;
2216 case MMCBR_IVAR_VDD:
2217 slot->host.ios.vdd = value;
2219 case MMCBR_IVAR_VCCQ:
2220 slot->host.ios.vccq = value;
2222 case MMCBR_IVAR_TIMING:
2223 slot->host.ios.timing = value;
2225 case MMCBR_IVAR_CAPS:
2226 case MMCBR_IVAR_HOST_OCR:
2227 case MMCBR_IVAR_F_MIN:
2228 case MMCBR_IVAR_F_MAX:
2229 case MMCBR_IVAR_MAX_DATA:
2230 case MMCBR_IVAR_RETUNE_REQ:
2236 MODULE_VERSION(sdhci, 1);