2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/callout.h>
37 #include <sys/kernel.h>
39 #include <sys/libkern.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/resource.h>
46 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
49 #include <machine/bus.h>
50 #include <machine/resource.h>
51 #include <machine/stdarg.h>
53 #include <dev/mmc/bridge.h>
54 #include <dev/mmc/mmcreg.h>
55 #include <dev/mmc/mmcbrvar.h>
57 #include <dev/sdhci/sdhci.h>
60 #include <cam/cam_ccb.h>
61 #include <cam/cam_debug.h>
62 #include <cam/cam_sim.h>
63 #include <cam/cam_xpt_sim.h>
68 #include "opt_mmccam.h"
70 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
73 static int sdhci_debug = 0;
74 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
76 u_int sdhci_quirk_clear = 0;
77 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
78 0, "Mask of quirks to clear");
79 u_int sdhci_quirk_set = 0;
80 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
81 "Mask of quirks to set");
83 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
84 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
85 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
86 #define RD_MULTI_4(slot, off, ptr, count) \
87 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
89 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
90 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
91 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
92 #define WR_MULTI_4(slot, off, ptr, count) \
93 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
95 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
96 static void sdhci_card_poll(void *arg);
97 static void sdhci_card_task(void *arg, int pending);
98 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
99 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
100 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
101 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
103 static void sdhci_finish_command(struct sdhci_slot *slot);
104 static void sdhci_init(struct sdhci_slot *slot);
105 static void sdhci_read_block_pio(struct sdhci_slot *slot);
106 static void sdhci_req_done(struct sdhci_slot *slot);
107 static void sdhci_req_wakeup(struct mmc_request *req);
108 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask);
109 static void sdhci_retune(void *arg);
110 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
111 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
112 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
113 const struct mmc_data *data);
114 static void sdhci_start(struct sdhci_slot *slot);
115 static void sdhci_timeout(void *arg);
116 static void sdhci_start_command(struct sdhci_slot *slot,
117 struct mmc_command *cmd);
118 static void sdhci_start_data(struct sdhci_slot *slot,
119 const struct mmc_data *data);
120 static void sdhci_write_block_pio(struct sdhci_slot *slot);
121 static void sdhci_transfer_pio(struct sdhci_slot *slot);
125 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb);
126 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
128 static void sdhci_cam_poll(struct cam_sim *sim);
129 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
130 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
131 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
134 /* helper routines */
135 static int sdhci_dma_alloc(struct sdhci_slot *slot);
136 static void sdhci_dma_free(struct sdhci_slot *slot);
137 static void sdhci_dumpregs(struct sdhci_slot *slot);
138 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
140 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
142 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
144 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
145 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
146 #define SDHCI_LOCK_INIT(_slot) \
147 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
148 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
149 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
150 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
152 #define SDHCI_DEFAULT_MAX_FREQ 50
154 #define SDHCI_200_MAX_DIVIDER 256
155 #define SDHCI_300_MAX_DIVIDER 2046
157 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
158 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
161 * Broadcom BCM577xx Controller Constants
163 /* Maximum divider supported by the default clock source. */
164 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
165 /* Alternative clock's base frequency. */
166 #define BCM577XX_ALT_CLOCK_BASE 63000000
168 #define BCM577XX_HOST_CONTROL 0x198
169 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
170 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
171 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
172 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
175 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
179 printf("getaddr: error %d\n", error);
182 *(bus_addr_t *)arg = segs[0].ds_addr;
186 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
193 * Make sure we print a single line all together rather than in two
194 * halves to avoid console gibberish bingo.
197 retval = vsnprintf(buf, sizeof(buf), fmt, ap);
200 retval += printf("%s-slot%d: %s",
201 device_get_nameunit(slot->bus), slot->num, buf);
206 sdhci_dumpregs(struct sdhci_slot *slot)
210 "============== REGISTER DUMP ==============\n");
212 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
213 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
214 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
215 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
216 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
217 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
218 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
219 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
220 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
221 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
222 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
223 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
224 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
225 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
226 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
227 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
228 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
229 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
230 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
231 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
232 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
233 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
234 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
235 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
238 "===========================================\n");
242 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
247 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
248 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
252 /* Some controllers need this kick or reset won't work. */
253 if ((mask & SDHCI_RESET_ALL) == 0 &&
254 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
255 /* This is to force an update */
258 sdhci_set_clock(slot, clock);
261 if (mask & SDHCI_RESET_ALL) {
266 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
268 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
270 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
271 * specification. The reset bit has internal propagation delay,
272 * so a fast read after write returns 0 even if reset process is
273 * in progress. The workaround is to poll for 1 before polling
274 * for 0. In the worst case, if we miss seeing it asserted the
275 * time we spent waiting is enough to ensure the reset finishes.
278 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
286 /* Wait max 100 ms */
288 /* Controller clears the bits when it's done */
289 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
291 slot_printf(slot, "Reset 0x%x never completed.\n",
293 sdhci_dumpregs(slot);
302 sdhci_tuning_intmask(const struct sdhci_slot *slot)
307 if (slot->opt & SDHCI_TUNING_ENABLED) {
308 intmask |= SDHCI_INT_TUNEERR;
309 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
310 slot->retune_mode == SDHCI_RETUNE_MODE_3)
311 intmask |= SDHCI_INT_RETUNE;
317 sdhci_init(struct sdhci_slot *slot)
320 sdhci_reset(slot, SDHCI_RESET_ALL);
322 /* Enable interrupts. */
323 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
324 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
325 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
326 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
327 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
330 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
331 !(slot->opt & SDHCI_NON_REMOVABLE)) {
332 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
335 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
336 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
340 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
349 if (clock == slot->clock)
353 /* Turn off the clock. */
354 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
355 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
356 /* If no clock requested - leave it so. */
360 /* Determine the clock base frequency */
361 clk_base = slot->max_clk;
362 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
363 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
364 BCM577XX_CTRL_CLKSEL_MASK;
367 * Select clock source appropriate for the requested frequency.
369 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
370 clk_base = BCM577XX_ALT_CLOCK_BASE;
371 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
372 BCM577XX_CTRL_CLKSEL_SHIFT);
374 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
375 BCM577XX_CTRL_CLKSEL_SHIFT);
378 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
381 /* Recalculate timeout clock frequency based on the new sd clock. */
382 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
383 slot->timeout_clk = slot->clock / 1000;
385 if (slot->version < SDHCI_SPEC_300) {
386 /* Looking for highest freq <= clock. */
388 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
393 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
396 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
397 if (clock >= clk_base)
400 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
401 if ((clk_base / div) <= clock)
408 if (bootverbose || sdhci_debug)
409 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
410 div, clock, clk_base);
412 /* Now we have got divider, set it. */
413 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
414 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
415 << SDHCI_DIVIDER_HI_SHIFT;
417 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
419 clk |= SDHCI_CLOCK_INT_EN;
420 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
421 /* Wait up to 10 ms until it stabilize. */
423 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
424 & SDHCI_CLOCK_INT_STABLE)) {
427 "Internal clock never stabilised.\n");
428 sdhci_dumpregs(slot);
434 /* Pass clock signal to the bus. */
435 clk |= SDHCI_CLOCK_CARD_EN;
436 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
440 sdhci_set_power(struct sdhci_slot *slot, u_char power)
445 if (slot->power == power)
450 /* Turn off the power. */
452 WR1(slot, SDHCI_POWER_CONTROL, pwr);
453 /* If power down requested - leave it so. */
457 switch (1 << power) {
458 case MMC_OCR_LOW_VOLTAGE:
459 pwr |= SDHCI_POWER_180;
461 case MMC_OCR_290_300:
462 case MMC_OCR_300_310:
463 pwr |= SDHCI_POWER_300;
465 case MMC_OCR_320_330:
466 case MMC_OCR_330_340:
467 pwr |= SDHCI_POWER_330;
470 WR1(slot, SDHCI_POWER_CONTROL, pwr);
472 * Turn on VDD1 power. Note that at least some Intel controllers can
473 * fail to enable bus power on the first try after transiting from D3
474 * to D0, so we give them up to 2 ms.
476 pwr |= SDHCI_POWER_ON;
477 for (i = 0; i < 20; i++) {
478 WR1(slot, SDHCI_POWER_CONTROL, pwr);
479 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
483 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
484 slot_printf(slot, "Bus power failed to enable\n");
486 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
487 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
489 WR1(slot, SDHCI_POWER_CONTROL, pwr);
495 sdhci_read_block_pio(struct sdhci_slot *slot)
501 buffer = slot->curcmd->data->data;
502 buffer += slot->offset;
503 /* Transfer one block at a time. */
505 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE)
506 left = min(slot->curcmd->data->block_size,
507 slot->curcmd->data->len - slot->offset);
510 left = min(512, slot->curcmd->data->len - slot->offset);
511 slot->offset += left;
513 /* If we are too fast, broken controllers return zeroes. */
514 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
516 /* Handle unaligned and aligned buffer cases. */
517 if ((intptr_t)buffer & 3) {
519 data = RD4(slot, SDHCI_BUFFER);
521 buffer[1] = (data >> 8);
522 buffer[2] = (data >> 16);
523 buffer[3] = (data >> 24);
528 RD_MULTI_4(slot, SDHCI_BUFFER,
529 (uint32_t *)buffer, left >> 2);
532 /* Handle uneven size case. */
534 data = RD4(slot, SDHCI_BUFFER);
544 sdhci_write_block_pio(struct sdhci_slot *slot)
550 buffer = slot->curcmd->data->data;
551 buffer += slot->offset;
552 /* Transfer one block at a time. */
554 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) {
555 left = min(slot->curcmd->data->block_size,
556 slot->curcmd->data->len - slot->offset);
559 left = min(512, slot->curcmd->data->len - slot->offset);
560 slot->offset += left;
562 /* Handle unaligned and aligned buffer cases. */
563 if ((intptr_t)buffer & 3) {
571 WR4(slot, SDHCI_BUFFER, data);
574 WR_MULTI_4(slot, SDHCI_BUFFER,
575 (uint32_t *)buffer, left >> 2);
578 /* Handle uneven size case. */
585 WR4(slot, SDHCI_BUFFER, data);
590 sdhci_transfer_pio(struct sdhci_slot *slot)
593 /* Read as many blocks as possible. */
594 if (slot->curcmd->data->flags & MMC_DATA_READ) {
595 while (RD4(slot, SDHCI_PRESENT_STATE) &
596 SDHCI_DATA_AVAILABLE) {
597 sdhci_read_block_pio(slot);
598 if (slot->offset >= slot->curcmd->data->len)
602 while (RD4(slot, SDHCI_PRESENT_STATE) &
603 SDHCI_SPACE_AVAILABLE) {
604 sdhci_write_block_pio(slot);
605 if (slot->offset >= slot->curcmd->data->len)
612 sdhci_card_task(void *arg, int pending __unused)
614 struct sdhci_slot *slot = arg;
618 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
620 if (slot->card_present == 0) {
622 if (slot->dev == NULL) {
624 /* If card is present - attach mmc bus. */
625 if (bootverbose || sdhci_debug)
626 slot_printf(slot, "Card inserted\n");
628 slot->card_present = 1;
631 pathid = cam_sim_path(slot->sim);
632 ccb = xpt_alloc_ccb_nowait();
634 slot_printf(slot, "Unable to alloc CCB for rescan\n");
640 * We create a rescan request for BUS:0:0, since the card
643 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid,
644 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) {
645 slot_printf(slot, "Unable to create path for rescan\n");
653 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
656 device_set_ivars(d, slot);
657 (void)device_probe_and_attach(d);
664 if (slot->card_present == 1) {
666 if (slot->dev != NULL) {
668 /* If no card present - detach mmc bus. */
669 if (bootverbose || sdhci_debug)
670 slot_printf(slot, "Card removed\n");
674 slot->card_present = 0;
677 pathid = cam_sim_path(slot->sim);
678 ccb = xpt_alloc_ccb_nowait();
680 slot_printf(slot, "Unable to alloc CCB for rescan\n");
686 * We create a rescan request for BUS:0:0, since the card
689 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid,
690 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) {
691 slot_printf(slot, "Unable to create path for rescan\n");
699 slot->intmask &= ~sdhci_tuning_intmask(slot);
700 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
701 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
702 slot->opt &= ~SDHCI_TUNING_ENABLED;
704 callout_drain(&slot->retune_callout);
705 device_delete_child(slot->bus, d);
713 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
718 * If there was no card and now there is one, schedule the task to
719 * create the child device after a short delay. The delay is to
720 * debounce the card insert (sometimes the card detect pin stabilizes
721 * before the other pins have made good contact).
723 * If there was a card present and now it's gone, immediately schedule
724 * the task to delete the child device. No debouncing -- gone is gone,
725 * because once power is removed, a full card re-init is needed, and
726 * that happens by deleting and recreating the child device.
729 was_present = slot->card_present;
731 was_present = slot->dev != NULL;
733 if (!was_present && is_present) {
734 taskqueue_enqueue_timeout(taskqueue_swi_giant,
735 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
736 } else if (was_present && !is_present) {
737 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
742 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
746 sdhci_handle_card_present_locked(slot, is_present);
751 sdhci_card_poll(void *arg)
753 struct sdhci_slot *slot = arg;
755 sdhci_handle_card_present(slot,
756 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
757 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
758 sdhci_card_poll, slot);
762 sdhci_dma_alloc(struct sdhci_slot *slot)
766 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
767 if (MAXPHYS <= 1024 * 4)
768 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
769 else if (MAXPHYS <= 1024 * 8)
770 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
771 else if (MAXPHYS <= 1024 * 16)
772 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
773 else if (MAXPHYS <= 1024 * 32)
774 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
775 else if (MAXPHYS <= 1024 * 64)
776 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
777 else if (MAXPHYS <= 1024 * 128)
778 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
779 else if (MAXPHYS <= 1024 * 256)
780 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
782 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
784 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
787 * Allocate the DMA tag for an SDMA bounce buffer.
788 * Note that the SDHCI specification doesn't state any alignment
789 * constraint for the SDMA system address. However, controllers
790 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when
791 * forming the actual address of data, requiring the SDMA buffer to
792 * be aligned to the SDMA boundary.
794 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
795 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
796 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
797 NULL, NULL, &slot->dmatag);
799 slot_printf(slot, "Can't create DMA tag for SDMA\n");
802 /* Allocate DMA memory for the SDMA bounce buffer. */
803 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
804 BUS_DMA_NOWAIT, &slot->dmamap);
806 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
807 bus_dma_tag_destroy(slot->dmatag);
810 /* Map the memory of the SDMA bounce buffer. */
811 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
812 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
814 if (err != 0 || slot->paddr == 0) {
815 slot_printf(slot, "Can't load DMA memory for SDMA\n");
816 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
817 bus_dma_tag_destroy(slot->dmatag);
828 sdhci_dma_free(struct sdhci_slot *slot)
831 bus_dmamap_unload(slot->dmatag, slot->dmamap);
832 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
833 bus_dma_tag_destroy(slot->dmatag);
837 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
839 kobjop_desc_t kobj_desc;
840 kobj_method_t *kobj_method;
841 uint32_t caps, caps2, freq, host_caps;
844 SDHCI_LOCK_INIT(slot);
849 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
850 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
851 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
855 caps = RD4(slot, SDHCI_CAPABILITIES);
856 if (slot->version >= SDHCI_SPEC_300)
857 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
861 if (slot->version >= SDHCI_SPEC_300) {
862 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
863 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
865 "Driver doesn't support shared bus slots\n");
866 SDHCI_LOCK_DESTROY(slot);
868 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
869 SDHCI_SLOTTYPE_EMBEDDED) {
870 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
873 /* Calculate base clock frequency. */
874 if (slot->version >= SDHCI_SPEC_300)
875 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
876 SDHCI_CLOCK_BASE_SHIFT;
878 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
879 SDHCI_CLOCK_BASE_SHIFT;
881 slot->max_clk = freq * 1000000;
883 * If the frequency wasn't in the capabilities and the hardware driver
884 * hasn't already set max_clk we're probably not going to work right
885 * with an assumption, so complain about it.
887 if (slot->max_clk == 0) {
888 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
889 slot_printf(slot, "Hardware doesn't specify base clock "
890 "frequency, using %dMHz as default.\n",
891 SDHCI_DEFAULT_MAX_FREQ);
893 /* Calculate/set timeout clock frequency. */
894 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
895 slot->timeout_clk = slot->max_clk / 1000;
896 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
897 slot->timeout_clk = 1000;
899 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
900 SDHCI_TIMEOUT_CLK_SHIFT;
901 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
902 slot->timeout_clk *= 1000;
905 * If the frequency wasn't in the capabilities and the hardware driver
906 * hasn't already set timeout_clk we'll probably work okay using the
907 * max timeout, but still mention it.
909 if (slot->timeout_clk == 0) {
910 slot_printf(slot, "Hardware doesn't specify timeout clock "
911 "frequency, setting BROKEN_TIMEOUT quirk.\n");
912 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
915 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
916 slot->host.f_max = slot->max_clk;
917 slot->host.host_ocr = 0;
918 if (caps & SDHCI_CAN_VDD_330)
919 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
920 if (caps & SDHCI_CAN_VDD_300)
921 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
923 * 1.8V VDD is not supposed to be used for removable cards. Hardware
924 * prior to v3.0 had no way to indicate embedded slots, but did
925 * sometimes support 1.8v for non-removable devices.
927 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 ||
928 (slot->opt & SDHCI_SLOT_EMBEDDED)))
929 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
930 if (slot->host.host_ocr == 0) {
931 slot_printf(slot, "Hardware doesn't report any "
932 "support voltages.\n");
935 host_caps = MMC_CAP_4_BIT_DATA;
936 if (caps & SDHCI_CAN_DO_8BITBUS)
937 host_caps |= MMC_CAP_8_BIT_DATA;
938 if (caps & SDHCI_CAN_DO_HISPD)
939 host_caps |= MMC_CAP_HSPEED;
940 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
941 host_caps |= MMC_CAP_BOOT_NOACC;
942 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
943 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
945 /* Determine supported UHS-I and eMMC modes. */
946 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
947 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
948 if (caps2 & SDHCI_CAN_SDR104) {
949 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
950 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
951 host_caps |= MMC_CAP_MMC_HS200;
952 } else if (caps2 & SDHCI_CAN_SDR50)
953 host_caps |= MMC_CAP_UHS_SDR50;
954 if (caps2 & SDHCI_CAN_DDR50 &&
955 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
956 host_caps |= MMC_CAP_UHS_DDR50;
957 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
958 host_caps |= MMC_CAP_MMC_DDR52;
959 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
960 caps2 & SDHCI_CAN_MMC_HS400)
961 host_caps |= MMC_CAP_MMC_HS400;
962 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
963 caps2 & SDHCI_CAN_SDR104)
964 host_caps |= MMC_CAP_MMC_HS400;
967 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
968 * default NULL implementation.
970 kobj_desc = &sdhci_set_uhs_timing_desc;
971 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
973 if (kobj_method == &kobj_desc->deflt)
974 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
975 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
976 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
978 #define SDHCI_CAP_MODES_TUNING(caps2) \
979 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
980 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
984 * Disable UHS-I and eMMC modes that require (re-)tuning if either
985 * the tune or re-tune method is the default NULL implementation.
987 kobj_desc = &mmcbr_tune_desc;
988 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
990 if (kobj_method == &kobj_desc->deflt)
992 kobj_desc = &mmcbr_retune_desc;
993 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
995 if (kobj_method == &kobj_desc->deflt) {
997 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
1000 /* Allocate tuning structures and determine tuning parameters. */
1001 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
1002 slot->opt |= SDHCI_TUNING_SUPPORTED;
1003 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
1005 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
1007 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
1009 if (caps2 & SDHCI_TUNE_SDR50)
1010 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
1011 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
1012 SDHCI_RETUNE_MODES_SHIFT;
1013 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
1014 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
1015 SDHCI_RETUNE_CNT_SHIFT;
1016 if (slot->retune_count > 0xb) {
1017 slot_printf(slot, "Unknown re-tuning count "
1018 "%x, using 1 sec\n", slot->retune_count);
1019 slot->retune_count = 1;
1020 } else if (slot->retune_count != 0)
1021 slot->retune_count =
1022 1 << (slot->retune_count - 1);
1026 #undef SDHCI_CAP_MODES_TUNING
1028 /* Determine supported VCCQ signaling levels. */
1029 host_caps |= MMC_CAP_SIGNALING_330;
1030 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1031 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1032 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
1033 MMC_CAP_MMC_HS400_180))
1034 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
1037 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
1038 * default NULL implementation. Disable 1.2 V support if it's the
1039 * generic SDHCI implementation.
1041 kobj_desc = &mmcbr_switch_vccq_desc;
1042 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1044 if (kobj_method == &kobj_desc->deflt)
1045 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
1046 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
1047 host_caps &= ~MMC_CAP_SIGNALING_120;
1049 /* Determine supported driver types (type B is always mandatory). */
1050 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
1051 host_caps |= MMC_CAP_DRIVER_TYPE_A;
1052 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
1053 host_caps |= MMC_CAP_DRIVER_TYPE_C;
1054 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
1055 host_caps |= MMC_CAP_DRIVER_TYPE_D;
1056 slot->host.caps = host_caps;
1058 /* Decide if we have usable DMA. */
1059 if (caps & SDHCI_CAN_DO_DMA)
1060 slot->opt |= SDHCI_HAVE_DMA;
1062 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
1063 slot->opt &= ~SDHCI_HAVE_DMA;
1064 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
1065 slot->opt |= SDHCI_HAVE_DMA;
1066 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
1067 slot->opt |= SDHCI_NON_REMOVABLE;
1070 * Use platform-provided transfer backend
1071 * with PIO as a fallback mechanism
1073 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
1074 slot->opt &= ~SDHCI_HAVE_DMA;
1076 if (slot->opt & SDHCI_HAVE_DMA) {
1077 err = sdhci_dma_alloc(slot);
1079 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1080 free(slot->tune_req, M_DEVBUF);
1081 free(slot->tune_cmd, M_DEVBUF);
1082 free(slot->tune_data, M_DEVBUF);
1084 SDHCI_LOCK_DESTROY(slot);
1089 if (bootverbose || sdhci_debug) {
1091 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
1092 slot->max_clk / 1000000,
1093 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
1094 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
1095 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
1096 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
1097 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
1098 ((caps & SDHCI_CAN_VDD_180) &&
1099 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
1100 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
1101 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
1102 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
1103 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
1104 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
1105 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
1106 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
1107 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
1109 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
1110 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
1111 slot_printf(slot, "eMMC:%s%s%s%s\n",
1112 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
1113 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
1114 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
1116 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
1117 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
1119 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1120 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
1121 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
1122 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
1123 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
1124 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
1125 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
1126 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
1127 if (slot->opt & SDHCI_TUNING_SUPPORTED)
1128 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
1129 slot->retune_count, slot->retune_mode + 1);
1130 sdhci_dumpregs(slot);
1134 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1135 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1136 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0,
1137 "Maximum timeout for SDHCI transfers (in secs)");
1138 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1139 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1140 sdhci_card_task, slot);
1141 callout_init(&slot->card_poll_callout, 1);
1142 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1143 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1145 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1146 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1147 callout_reset(&slot->card_poll_callout,
1148 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1158 sdhci_start_slot(struct sdhci_slot *slot)
1161 sdhci_card_task(slot, 0);
1166 sdhci_cleanup_slot(struct sdhci_slot *slot)
1170 callout_drain(&slot->timeout_callout);
1171 callout_drain(&slot->card_poll_callout);
1172 callout_drain(&slot->retune_callout);
1173 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1174 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1181 device_delete_child(slot->bus, d);
1184 sdhci_reset(slot, SDHCI_RESET_ALL);
1186 if (slot->opt & SDHCI_HAVE_DMA)
1187 sdhci_dma_free(slot);
1188 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1189 free(slot->tune_req, M_DEVBUF);
1190 free(slot->tune_cmd, M_DEVBUF);
1191 free(slot->tune_data, M_DEVBUF);
1194 SDHCI_LOCK_DESTROY(slot);
1200 sdhci_generic_suspend(struct sdhci_slot *slot)
1204 * We expect the MMC layer to issue initial tuning after resume.
1205 * Otherwise, we'd need to indicate re-tuning including circuit reset
1206 * being required at least for re-tuning modes 1 and 2 ourselves.
1208 callout_drain(&slot->retune_callout);
1210 slot->opt &= ~SDHCI_TUNING_ENABLED;
1211 sdhci_reset(slot, SDHCI_RESET_ALL);
1218 sdhci_generic_resume(struct sdhci_slot *slot)
1229 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1232 if (slot->version >= SDHCI_SPEC_300)
1233 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1235 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1239 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1242 if (slot->opt & SDHCI_NON_REMOVABLE)
1245 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1249 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1251 const struct mmc_ios *ios;
1254 if (slot->version < SDHCI_SPEC_300)
1257 SDHCI_ASSERT_LOCKED(slot);
1258 ios = &slot->host.ios;
1259 sdhci_set_clock(slot, 0);
1260 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1261 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1262 if (ios->clock > SD_SDR50_MAX) {
1263 if (ios->timing == bus_timing_mmc_hs400 ||
1264 ios->timing == bus_timing_mmc_hs400es)
1265 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1267 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1269 else if (ios->clock > SD_SDR25_MAX)
1270 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1271 else if (ios->clock > SD_SDR12_MAX) {
1272 if (ios->timing == bus_timing_uhs_ddr50 ||
1273 ios->timing == bus_timing_mmc_ddr52)
1274 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1276 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1277 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1278 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1279 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1280 sdhci_set_clock(slot, ios->clock);
1284 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1286 struct sdhci_slot *slot = device_get_ivars(reqdev);
1287 struct mmc_ios *ios = &slot->host.ios;
1290 /* Do full reset on bus power down to clear from any state. */
1291 if (ios->power_mode == power_off) {
1292 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1295 /* Configure the bus. */
1296 sdhci_set_clock(slot, ios->clock);
1297 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1298 if (ios->bus_width == bus_width_8) {
1299 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1300 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1301 } else if (ios->bus_width == bus_width_4) {
1302 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1303 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1304 } else if (ios->bus_width == bus_width_1) {
1305 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1306 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1308 panic("Invalid bus width: %d", ios->bus_width);
1310 if (ios->clock > SD_SDR12_MAX &&
1311 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1312 slot->hostctrl |= SDHCI_CTRL_HISPD;
1314 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1315 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1316 SDHCI_SET_UHS_TIMING(brdev, slot);
1317 /* Some controllers like reset after bus changes. */
1318 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1319 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1326 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1328 struct sdhci_slot *slot = device_get_ivars(reqdev);
1333 if (slot->version < SDHCI_SPEC_300)
1337 vccq = slot->host.ios.vccq;
1339 sdhci_set_clock(slot, 0);
1340 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1343 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1345 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1346 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1348 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1349 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1354 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1358 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1360 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1361 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1363 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1364 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1370 "Attempt to set unsupported signaling voltage\n");
1375 sdhci_set_clock(slot, slot->host.ios.clock);
1381 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1383 struct sdhci_slot *slot = device_get_ivars(reqdev);
1384 const struct mmc_ios *ios = &slot->host.ios;
1385 struct mmc_command *tune_cmd;
1386 struct mmc_data *tune_data;
1390 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1393 slot->retune_ticks = slot->retune_count * hz;
1394 opcode = MMC_SEND_TUNING_BLOCK;
1396 switch (ios->timing) {
1397 case bus_timing_mmc_hs400:
1398 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1401 case bus_timing_mmc_hs200:
1403 * In HS400 mode, controllers use the data strobe line to
1404 * latch data from the devices so periodic re-tuning isn't
1405 * expected to be required.
1408 slot->retune_ticks = 0;
1409 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1411 case bus_timing_uhs_ddr50:
1412 case bus_timing_uhs_sdr104:
1414 case bus_timing_uhs_sdr50:
1415 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1423 tune_cmd = slot->tune_cmd;
1424 memset(tune_cmd, 0, sizeof(*tune_cmd));
1425 tune_cmd->opcode = opcode;
1426 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1427 tune_data = tune_cmd->data = slot->tune_data;
1428 memset(tune_data, 0, sizeof(*tune_data));
1429 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1430 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1432 tune_data->flags = MMC_DATA_READ;
1433 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1435 slot->opt &= ~SDHCI_TUNING_ENABLED;
1436 err = sdhci_exec_tuning(slot, true);
1438 slot->opt |= SDHCI_TUNING_ENABLED;
1439 slot->intmask |= sdhci_tuning_intmask(slot);
1440 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1441 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1442 if (slot->retune_ticks) {
1443 callout_reset(&slot->retune_callout, slot->retune_ticks,
1444 sdhci_retune, slot);
1452 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1454 struct sdhci_slot *slot = device_get_ivars(reqdev);
1457 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1460 /* HS400 must be tuned in HS200 mode. */
1461 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1465 err = sdhci_exec_tuning(slot, reset);
1467 * There are two ways sdhci_exec_tuning() can fail:
1468 * EBUSY should not actually happen when requests are only issued
1469 * with the host properly acquired, and
1470 * EIO re-tuning failed (but it did work initially).
1472 * In both cases, we should retry at later point if periodic re-tuning
1473 * is enabled. Note that due to slot->retune_req not being cleared in
1474 * these failure cases, the MMC layer should trigger another attempt at
1475 * re-tuning with the next request anyway, though.
1477 if (slot->retune_ticks) {
1478 callout_reset(&slot->retune_callout, slot->retune_ticks,
1479 sdhci_retune, slot);
1486 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1488 struct mmc_request *tune_req;
1489 struct mmc_command *tune_cmd;
1495 SDHCI_ASSERT_LOCKED(slot);
1496 if (slot->req != NULL)
1499 /* Tuning doesn't work with DMA enabled. */
1501 slot->opt = opt & ~SDHCI_HAVE_DMA;
1504 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1505 * kind of interrupt we receive in response to a tuning request.
1507 intmask = slot->intmask;
1508 slot->intmask = SDHCI_INT_DATA_AVAIL;
1509 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1510 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1512 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1514 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1516 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1517 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1519 tune_req = slot->tune_req;
1520 tune_cmd = slot->tune_cmd;
1521 for (i = 0; i < MMC_TUNING_MAX; i++) {
1522 memset(tune_req, 0, sizeof(*tune_req));
1523 tune_req->cmd = tune_cmd;
1524 tune_req->done = sdhci_req_wakeup;
1525 tune_req->done_data = slot;
1526 slot->req = tune_req;
1529 while (!(tune_req->flags & MMC_REQ_DONE))
1530 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1531 if (!(tune_req->flags & MMC_TUNE_DONE))
1533 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1534 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1536 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1541 * Restore DMA usage and interrupts.
1542 * Note that the interrupt aggregation code might have cleared
1543 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1544 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1545 * doesn't lose these.
1548 slot->intmask = intmask;
1549 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1550 SDHCI_INT_RESPONSE);
1551 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1553 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1554 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1555 slot->retune_req = 0;
1559 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1560 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1561 SDHCI_CTRL2_SAMPLING_CLOCK));
1562 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1567 sdhci_retune(void *arg)
1569 struct sdhci_slot *slot = arg;
1571 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1576 sdhci_req_done(struct sdhci_slot *slot)
1580 if (__predict_false(sdhci_debug > 1))
1581 slot_printf(slot, "%s\n", __func__);
1582 if (slot->ccb != NULL && slot->curcmd != NULL) {
1583 callout_stop(&slot->timeout_callout);
1586 slot->curcmd = NULL;
1588 /* Tell CAM the request is finished */
1589 struct ccb_mmcio *mmcio;
1590 mmcio = &ccb->mmcio;
1593 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1599 sdhci_req_done(struct sdhci_slot *slot)
1601 struct mmc_request *req;
1603 if (slot->req != NULL && slot->curcmd != NULL) {
1604 callout_stop(&slot->timeout_callout);
1607 slot->curcmd = NULL;
1614 sdhci_req_wakeup(struct mmc_request *req)
1616 struct sdhci_slot *slot;
1618 slot = req->done_data;
1619 req->flags |= MMC_REQ_DONE;
1624 sdhci_timeout(void *arg)
1626 struct sdhci_slot *slot = arg;
1628 if (slot->curcmd != NULL) {
1629 slot_printf(slot, "Controller timeout\n");
1630 sdhci_dumpregs(slot);
1631 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1632 slot->curcmd->error = MMC_ERR_TIMEOUT;
1633 sdhci_req_done(slot);
1635 slot_printf(slot, "Spurious timeout - no active command\n");
1640 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data)
1647 mode = SDHCI_TRNS_BLK_CNT_EN;
1648 if (data->len > 512 || data->block_count > 1) {
1649 mode |= SDHCI_TRNS_MULTI;
1650 if (data->block_count == 0 && __predict_true(
1652 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION &&
1654 slot->req->stop != NULL &&
1656 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1657 mode |= SDHCI_TRNS_ACMD12;
1659 if (data->flags & MMC_DATA_READ)
1660 mode |= SDHCI_TRNS_READ;
1661 if (slot->flags & SDHCI_USE_DMA)
1662 mode |= SDHCI_TRNS_DMA;
1664 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1668 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1676 cmd->error = MMC_ERR_NONE;
1678 /* This flags combination is not supported by controller. */
1679 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1680 slot_printf(slot, "Unsupported response type!\n");
1681 cmd->error = MMC_ERR_FAILED;
1682 sdhci_req_done(slot);
1687 * Do not issue command if there is no card, clock or power.
1688 * Controller will not detect timeout without clock active.
1690 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1694 "Cannot issue a command (power=%d clock=%d)",
1695 slot->power, slot->clock);
1696 cmd->error = MMC_ERR_FAILED;
1697 sdhci_req_done(slot);
1700 /* Always wait for free CMD bus. */
1701 mask = SDHCI_CMD_INHIBIT;
1702 /* Wait for free DAT if we have data or busy signal. */
1703 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1704 mask |= SDHCI_DAT_INHIBIT;
1706 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1707 * that these latter are also special in that SDHCI_CMD_DATA should
1708 * be set below but no actual data is ever read from the controller.
1711 if (cmd == &slot->ccb->mmcio.stop ||
1713 if (cmd == slot->req->stop ||
1715 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1716 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1717 mask &= ~SDHCI_DAT_INHIBIT;
1719 * Wait for bus no more then 250 ms. Typically there will be no wait
1720 * here at all, but when writing a crash dump we may be bypassing the
1721 * host platform's interrupt handler, and in some cases that handler
1722 * may be working around hardware quirks such as not respecting r1b
1723 * busy indications. In those cases, this wait-loop serves the purpose
1724 * of waiting for the prior command and data transfers to be done, and
1725 * SD cards are allowed to take up to 250ms for write and erase ops.
1726 * (It's usually more like 20-30ms in the real world.)
1729 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1731 slot_printf(slot, "Controller never released "
1732 "inhibit bit(s).\n");
1733 sdhci_dumpregs(slot);
1734 cmd->error = MMC_ERR_FAILED;
1735 sdhci_req_done(slot);
1742 /* Prepare command flags. */
1743 if (!(cmd->flags & MMC_RSP_PRESENT))
1744 flags = SDHCI_CMD_RESP_NONE;
1745 else if (cmd->flags & MMC_RSP_136)
1746 flags = SDHCI_CMD_RESP_LONG;
1747 else if (cmd->flags & MMC_RSP_BUSY)
1748 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1750 flags = SDHCI_CMD_RESP_SHORT;
1751 if (cmd->flags & MMC_RSP_CRC)
1752 flags |= SDHCI_CMD_CRC;
1753 if (cmd->flags & MMC_RSP_OPCODE)
1754 flags |= SDHCI_CMD_INDEX;
1755 if (cmd->data != NULL)
1756 flags |= SDHCI_CMD_DATA;
1757 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1758 flags |= SDHCI_CMD_TYPE_ABORT;
1760 sdhci_start_data(slot, cmd->data);
1762 * Interrupt aggregation: To reduce total number of interrupts
1763 * group response interrupt with data interrupt when possible.
1764 * If there going to be data interrupt, mask response one.
1766 if (slot->data_done == 0) {
1767 WR4(slot, SDHCI_SIGNAL_ENABLE,
1768 slot->intmask &= ~SDHCI_INT_RESPONSE);
1770 /* Set command argument. */
1771 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1772 /* Set data transfer mode. */
1773 sdhci_set_transfer_mode(slot, cmd->data);
1774 if (__predict_false(sdhci_debug > 1))
1775 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n",
1776 cmd->opcode, flags);
1778 /* Start command. */
1779 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1780 /* Start timeout callout. */
1781 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1782 sdhci_timeout, slot);
1786 sdhci_finish_command(struct sdhci_slot *slot)
1792 if (__predict_false(sdhci_debug > 1))
1793 slot_printf(slot, "%s: called, err %d flags %#04x\n",
1794 __func__, slot->curcmd->error, slot->curcmd->flags);
1797 * Interrupt aggregation: Restore command interrupt.
1798 * Main restore point for the case when command interrupt
1801 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1802 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1803 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1804 SDHCI_INT_RESPONSE);
1805 /* In case of error - reset host and return. */
1806 if (slot->curcmd->error) {
1807 if (slot->curcmd->error == MMC_ERR_BADCRC)
1808 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1809 sdhci_reset(slot, SDHCI_RESET_CMD);
1810 sdhci_reset(slot, SDHCI_RESET_DATA);
1814 /* If command has response - fetch it. */
1815 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1816 if (slot->curcmd->flags & MMC_RSP_136) {
1817 /* CRC is stripped so we need one byte shift. */
1819 for (i = 0; i < 4; i++) {
1820 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1822 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1823 slot->curcmd->resp[3 - i] = val;
1825 slot->curcmd->resp[3 - i] =
1831 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1833 if (__predict_false(sdhci_debug > 1))
1834 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n",
1835 slot->curcmd->resp[0], slot->curcmd->resp[1],
1836 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1838 /* If data ready - finish. */
1839 if (slot->data_done)
1844 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data)
1846 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout;
1849 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1850 slot->data_done = 1;
1854 slot->data_done = 0;
1856 /* Calculate and set data timeout.*/
1857 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1858 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1861 target_timeout = 1000000;
1863 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1864 while (current_timeout < target_timeout && div < 0xE) {
1866 current_timeout <<= 1;
1868 /* Compensate for an off-by-one error in the CaFe chip.*/
1870 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1874 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1879 /* Use DMA if possible. */
1880 if ((slot->opt & SDHCI_HAVE_DMA))
1881 slot->flags |= SDHCI_USE_DMA;
1882 /* If data is small, broken DMA may return zeroes instead of data. */
1883 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1885 slot->flags &= ~SDHCI_USE_DMA;
1886 /* Some controllers require even block sizes. */
1887 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1888 ((data->len) & 0x3))
1889 slot->flags &= ~SDHCI_USE_DMA;
1890 /* Load DMA buffer. */
1891 if (slot->flags & SDHCI_USE_DMA) {
1892 sdma_bbufsz = slot->sdma_bbufsz;
1893 if (data->flags & MMC_DATA_READ)
1894 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1895 BUS_DMASYNC_PREREAD);
1897 memcpy(slot->dmamem, data->data, ulmin(data->len,
1899 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1900 BUS_DMASYNC_PREWRITE);
1902 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1904 * Interrupt aggregation: Mask border interrupt for the last
1905 * bounce buffer and unmask otherwise.
1907 if (data->len == sdma_bbufsz)
1908 slot->intmask &= ~SDHCI_INT_DMA_END;
1910 slot->intmask |= SDHCI_INT_DMA_END;
1911 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1913 /* Current data offset for both PIO and DMA. */
1916 if (data->flags & MMC_DATA_BLOCK_SIZE) {
1917 /* Set block size and request border interrupts on the SDMA boundary. */
1918 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size);
1919 blkcnt = data->block_count;
1920 if (__predict_false(sdhci_debug > 0))
1921 slot_printf(slot, "SDIO Custom block params: blksz: "
1922 "%#10x, blk cnt: %#10x\n", blksz, blkcnt);
1926 /* Set block size and request border interrupts on the SDMA boundary. */
1927 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
1928 blkcnt = howmany(data->len, 512);
1931 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
1932 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
1933 if (__predict_false(sdhci_debug > 1))
1934 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
1939 sdhci_finish_data(struct sdhci_slot *slot)
1941 struct mmc_data *data = slot->curcmd->data;
1944 /* Interrupt aggregation: Restore command interrupt.
1945 * Auxiliary restore point for the case when data interrupt
1946 * happened first. */
1947 if (!slot->cmd_done) {
1948 WR4(slot, SDHCI_SIGNAL_ENABLE,
1949 slot->intmask |= SDHCI_INT_RESPONSE);
1951 /* Unload rest of data from DMA buffer. */
1952 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
1953 slot->curcmd->data != NULL) {
1954 if (data->flags & MMC_DATA_READ) {
1955 left = data->len - slot->offset;
1956 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1957 BUS_DMASYNC_POSTREAD);
1958 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1959 ulmin(left, slot->sdma_bbufsz));
1961 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1962 BUS_DMASYNC_POSTWRITE);
1964 slot->data_done = 1;
1965 /* If there was error - reset the host. */
1966 if (slot->curcmd->error) {
1967 if (slot->curcmd->error == MMC_ERR_BADCRC)
1968 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1969 sdhci_reset(slot, SDHCI_RESET_CMD);
1970 sdhci_reset(slot, SDHCI_RESET_DATA);
1974 /* If we already have command response - finish. */
1981 sdhci_start(struct sdhci_slot *slot)
1984 struct ccb_mmcio *mmcio;
1990 mmcio = &ccb->mmcio;
1991 if (!(slot->flags & CMD_STARTED)) {
1992 slot->flags |= CMD_STARTED;
1993 sdhci_start_command(slot, &mmcio->cmd);
1998 * Old stack doesn't use this!
1999 * Enabling this code causes significant performance degradation
2000 * and IRQ storms on BBB, Wandboard behaves fine.
2001 * Not using this code does no harm...
2002 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
2003 slot->flags |= STOP_STARTED;
2004 sdhci_start_command(slot, &mmcio->stop);
2008 if (__predict_false(sdhci_debug > 1))
2009 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
2010 if (mmcio->cmd.error == 0 &&
2011 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
2012 sdhci_reset(slot, SDHCI_RESET_CMD);
2013 sdhci_reset(slot, SDHCI_RESET_DATA);
2016 sdhci_req_done(slot);
2020 sdhci_start(struct sdhci_slot *slot)
2022 const struct mmc_request *req;
2028 if (!(slot->flags & CMD_STARTED)) {
2029 slot->flags |= CMD_STARTED;
2030 sdhci_start_command(slot, req->cmd);
2033 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
2034 !(slot->flags & STOP_STARTED) && req->stop) {
2035 slot->flags |= STOP_STARTED;
2036 sdhci_start_command(slot, req->stop);
2039 if (__predict_false(sdhci_debug > 1))
2040 slot_printf(slot, "result: %d\n", req->cmd->error);
2041 if (!req->cmd->error &&
2042 ((slot->curcmd == req->stop &&
2043 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
2044 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2045 sdhci_reset(slot, SDHCI_RESET_CMD);
2046 sdhci_reset(slot, SDHCI_RESET_DATA);
2049 sdhci_req_done(slot);
2054 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
2055 struct mmc_request *req)
2057 struct sdhci_slot *slot = device_get_ivars(reqdev);
2060 if (slot->req != NULL) {
2064 if (__predict_false(sdhci_debug > 1)) {
2066 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
2067 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
2068 (req->cmd->data)?(u_int)req->cmd->data->len:0,
2069 (req->cmd->data)?req->cmd->data->flags:0);
2076 while (slot->req != NULL) {
2077 sdhci_generic_intr(slot);
2085 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
2087 struct sdhci_slot *slot = device_get_ivars(reqdev);
2091 val = RD4(slot, SDHCI_PRESENT_STATE);
2093 return (!(val & SDHCI_WRITE_PROTECT));
2097 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
2099 struct sdhci_slot *slot = device_get_ivars(reqdev);
2103 while (slot->bus_busy)
2104 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
2107 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2113 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
2115 struct sdhci_slot *slot = device_get_ivars(reqdev);
2118 /* Deactivate led. */
2119 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2127 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
2130 if (!slot->curcmd) {
2131 slot_printf(slot, "Got command interrupt 0x%08x, but "
2132 "there is no active command.\n", intmask);
2133 sdhci_dumpregs(slot);
2136 if (intmask & SDHCI_INT_TIMEOUT)
2137 slot->curcmd->error = MMC_ERR_TIMEOUT;
2138 else if (intmask & SDHCI_INT_CRC)
2139 slot->curcmd->error = MMC_ERR_BADCRC;
2140 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
2141 slot->curcmd->error = MMC_ERR_FIFO;
2143 sdhci_finish_command(slot);
2147 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
2149 struct mmc_data *data;
2151 uint32_t sdma_bbufsz;
2153 if (!slot->curcmd) {
2154 slot_printf(slot, "Got data interrupt 0x%08x, but "
2155 "there is no active command.\n", intmask);
2156 sdhci_dumpregs(slot);
2159 if (slot->curcmd->data == NULL &&
2160 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2161 slot_printf(slot, "Got data interrupt 0x%08x, but "
2162 "there is no active data operation.\n",
2164 sdhci_dumpregs(slot);
2167 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2168 slot->curcmd->error = MMC_ERR_TIMEOUT;
2169 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
2170 slot->curcmd->error = MMC_ERR_BADCRC;
2171 if (slot->curcmd->data == NULL &&
2172 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2173 SDHCI_INT_DMA_END))) {
2174 slot_printf(slot, "Got data interrupt 0x%08x, but "
2175 "there is busy-only command.\n", intmask);
2176 sdhci_dumpregs(slot);
2177 slot->curcmd->error = MMC_ERR_INVALID;
2179 if (slot->curcmd->error) {
2180 /* No need to continue after any error. */
2184 /* Handle tuning completion interrupt. */
2185 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
2186 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2187 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2188 slot->req->flags |= MMC_TUNE_DONE;
2189 sdhci_finish_command(slot);
2190 sdhci_finish_data(slot);
2193 /* Handle PIO interrupt. */
2194 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
2195 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2196 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2197 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2199 slot->flags |= PLATFORM_DATA_STARTED;
2201 sdhci_transfer_pio(slot);
2203 /* Handle DMA border. */
2204 if (intmask & SDHCI_INT_DMA_END) {
2205 data = slot->curcmd->data;
2206 sdma_bbufsz = slot->sdma_bbufsz;
2208 /* Unload DMA buffer ... */
2209 left = data->len - slot->offset;
2210 if (data->flags & MMC_DATA_READ) {
2211 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2212 BUS_DMASYNC_POSTREAD);
2213 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2214 ulmin(left, sdma_bbufsz));
2216 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2217 BUS_DMASYNC_POSTWRITE);
2219 /* ... and reload it again. */
2220 slot->offset += sdma_bbufsz;
2221 left = data->len - slot->offset;
2222 if (data->flags & MMC_DATA_READ) {
2223 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2224 BUS_DMASYNC_PREREAD);
2226 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2227 ulmin(left, sdma_bbufsz));
2228 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2229 BUS_DMASYNC_PREWRITE);
2232 * Interrupt aggregation: Mask border interrupt for the last
2235 if (left == sdma_bbufsz) {
2236 slot->intmask &= ~SDHCI_INT_DMA_END;
2237 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2240 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2242 /* We have got all data. */
2243 if (intmask & SDHCI_INT_DATA_END) {
2244 if (slot->flags & PLATFORM_DATA_STARTED) {
2245 slot->flags &= ~PLATFORM_DATA_STARTED;
2246 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2248 sdhci_finish_data(slot);
2251 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2252 if (slot->flags & PLATFORM_DATA_STARTED) {
2253 slot->flags &= ~PLATFORM_DATA_STARTED;
2254 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2256 sdhci_finish_data(slot);
2261 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
2264 if (!slot->curcmd) {
2265 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2266 "there is no active command.\n", acmd_err);
2267 sdhci_dumpregs(slot);
2270 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2271 sdhci_reset(slot, SDHCI_RESET_CMD);
2275 sdhci_generic_intr(struct sdhci_slot *slot)
2277 uint32_t intmask, present;
2281 /* Read slot interrupt status. */
2282 intmask = RD4(slot, SDHCI_INT_STATUS);
2283 if (intmask == 0 || intmask == 0xffffffff) {
2287 if (__predict_false(sdhci_debug > 2))
2288 slot_printf(slot, "Interrupt %#x\n", intmask);
2290 /* Handle tuning error interrupt. */
2291 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2292 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2293 slot_printf(slot, "Tuning error indicated\n");
2294 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2296 slot->curcmd->error = MMC_ERR_BADCRC;
2297 sdhci_finish_command(slot);
2300 /* Handle re-tuning interrupt. */
2301 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2302 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2303 /* Handle card presence interrupts. */
2304 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2305 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2307 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2308 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2309 SDHCI_INT_CARD_INSERT;
2310 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2311 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2312 WR4(slot, SDHCI_INT_STATUS, intmask &
2313 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2314 sdhci_handle_card_present_locked(slot, present);
2316 /* Handle command interrupts. */
2317 if (intmask & SDHCI_INT_CMD_MASK) {
2318 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2319 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2321 /* Handle data interrupts. */
2322 if (intmask & SDHCI_INT_DATA_MASK) {
2323 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2324 /* Don't call data_irq in case of errored command. */
2325 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2326 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2328 /* Handle AutoCMD12 error interrupt. */
2329 if (intmask & SDHCI_INT_ACMD12ERR) {
2330 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2331 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2332 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2333 sdhci_acmd_irq(slot, val16);
2335 /* Handle bus power interrupt. */
2336 if (intmask & SDHCI_INT_BUS_POWER) {
2337 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2338 slot_printf(slot, "Card is consuming too much power!\n");
2340 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2341 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2342 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2343 /* The rest is unknown. */
2345 WR4(slot, SDHCI_INT_STATUS, intmask);
2346 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2348 sdhci_dumpregs(slot);
2355 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2358 const struct sdhci_slot *slot = device_get_ivars(child);
2363 case MMCBR_IVAR_BUS_MODE:
2364 *result = slot->host.ios.bus_mode;
2366 case MMCBR_IVAR_BUS_WIDTH:
2367 *result = slot->host.ios.bus_width;
2369 case MMCBR_IVAR_CHIP_SELECT:
2370 *result = slot->host.ios.chip_select;
2372 case MMCBR_IVAR_CLOCK:
2373 *result = slot->host.ios.clock;
2375 case MMCBR_IVAR_F_MIN:
2376 *result = slot->host.f_min;
2378 case MMCBR_IVAR_F_MAX:
2379 *result = slot->host.f_max;
2381 case MMCBR_IVAR_HOST_OCR:
2382 *result = slot->host.host_ocr;
2384 case MMCBR_IVAR_MODE:
2385 *result = slot->host.mode;
2387 case MMCBR_IVAR_OCR:
2388 *result = slot->host.ocr;
2390 case MMCBR_IVAR_POWER_MODE:
2391 *result = slot->host.ios.power_mode;
2393 case MMCBR_IVAR_VDD:
2394 *result = slot->host.ios.vdd;
2396 case MMCBR_IVAR_RETUNE_REQ:
2397 if (slot->opt & SDHCI_TUNING_ENABLED) {
2398 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2399 *result = retune_req_reset;
2402 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2403 *result = retune_req_normal;
2407 *result = retune_req_none;
2409 case MMCBR_IVAR_VCCQ:
2410 *result = slot->host.ios.vccq;
2412 case MMCBR_IVAR_CAPS:
2413 *result = slot->host.caps;
2415 case MMCBR_IVAR_TIMING:
2416 *result = slot->host.ios.timing;
2418 case MMCBR_IVAR_MAX_DATA:
2420 * Re-tuning modes 1 and 2 restrict the maximum data length
2421 * per read/write command to 4 MiB.
2423 if (slot->opt & SDHCI_TUNING_ENABLED &&
2424 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2425 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2426 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2431 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2433 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2442 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2445 struct sdhci_slot *slot = device_get_ivars(child);
2446 uint32_t clock, max_clock;
2449 if (sdhci_debug > 1)
2450 slot_printf(slot, "%s: var=%d\n", __func__, which);
2454 case MMCBR_IVAR_BUS_MODE:
2455 slot->host.ios.bus_mode = value;
2457 case MMCBR_IVAR_BUS_WIDTH:
2458 slot->host.ios.bus_width = value;
2460 case MMCBR_IVAR_CHIP_SELECT:
2461 slot->host.ios.chip_select = value;
2463 case MMCBR_IVAR_CLOCK:
2465 max_clock = slot->max_clk;
2468 if (slot->version < SDHCI_SPEC_300) {
2469 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2476 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2480 clock = max_clock / (i + 2);
2484 slot->host.ios.clock = clock;
2486 slot->host.ios.clock = 0;
2488 case MMCBR_IVAR_MODE:
2489 slot->host.mode = value;
2491 case MMCBR_IVAR_OCR:
2492 slot->host.ocr = value;
2494 case MMCBR_IVAR_POWER_MODE:
2495 slot->host.ios.power_mode = value;
2497 case MMCBR_IVAR_VDD:
2498 slot->host.ios.vdd = value;
2500 case MMCBR_IVAR_VCCQ:
2501 slot->host.ios.vccq = value;
2503 case MMCBR_IVAR_TIMING:
2504 slot->host.ios.timing = value;
2506 case MMCBR_IVAR_CAPS:
2507 case MMCBR_IVAR_HOST_OCR:
2508 case MMCBR_IVAR_F_MIN:
2509 case MMCBR_IVAR_F_MAX:
2510 case MMCBR_IVAR_MAX_DATA:
2511 case MMCBR_IVAR_RETUNE_REQ:
2519 sdhci_start_slot(struct sdhci_slot *slot)
2522 if ((slot->devq = cam_simq_alloc(1)) == NULL)
2525 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2526 slot->sim = cam_sim_alloc_dev(sdhci_cam_action, sdhci_cam_poll,
2527 "sdhci_slot", slot, slot->bus,
2528 &slot->sim_mtx, 1, 1, slot->devq);
2530 if (slot->sim == NULL) {
2531 cam_simq_free(slot->devq);
2532 slot_printf(slot, "cannot allocate CAM SIM\n");
2536 mtx_lock(&slot->sim_mtx);
2537 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2538 slot_printf(slot, "cannot register SCSI pass-through bus\n");
2539 cam_sim_free(slot->sim, FALSE);
2540 cam_simq_free(slot->devq);
2541 mtx_unlock(&slot->sim_mtx);
2544 mtx_unlock(&slot->sim_mtx);
2546 /* End CAM-specific init */
2547 slot->card_present = 0;
2548 sdhci_card_task(slot, 0);
2552 if (slot->sim != NULL) {
2553 mtx_lock(&slot->sim_mtx);
2554 xpt_bus_deregister(cam_sim_path(slot->sim));
2555 cam_sim_free(slot->sim, FALSE);
2556 mtx_unlock(&slot->sim_mtx);
2559 if (slot->devq != NULL)
2560 cam_simq_free(slot->devq);
2564 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb)
2566 struct sdhci_slot *slot;
2568 slot = cam_sim_softc(sim);
2570 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2575 mtx_assert(&slot->sim_mtx, MA_OWNED);
2577 switch (ccb->ccb_h.func_code) {
2579 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, MAXPHYS);
2582 case XPT_GET_TRAN_SETTINGS:
2584 struct ccb_trans_settings *cts = &ccb->cts;
2587 if (sdhci_debug > 1)
2588 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2590 cts->protocol = PROTO_MMCSD;
2591 cts->protocol_version = 1;
2592 cts->transport = XPORT_MMCSD;
2593 cts->transport_version = 1;
2594 cts->xport_specific.valid = 0;
2595 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2596 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2597 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2598 cts->proto_specific.mmc.host_caps = slot->host.caps;
2600 * Re-tuning modes 1 and 2 restrict the maximum data length
2601 * per read/write command to 4 MiB.
2603 if (slot->opt & SDHCI_TUNING_ENABLED &&
2604 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2605 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2606 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2610 cts->proto_specific.mmc.host_max_data = max_data;
2612 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2613 ccb->ccb_h.status = CAM_REQ_CMP;
2616 case XPT_SET_TRAN_SETTINGS:
2617 if (sdhci_debug > 1)
2618 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2619 sdhci_cam_settran_settings(slot, ccb);
2620 ccb->ccb_h.status = CAM_REQ_CMP;
2623 if (sdhci_debug > 1)
2624 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2625 ccb->ccb_h.status = CAM_REQ_CMP;
2629 * Here is the HW-dependent part of
2630 * sending the command to the underlying h/w
2631 * At some point in the future an interrupt comes.
2632 * Then the request will be marked as completed.
2634 if (__predict_false(sdhci_debug > 1))
2635 slot_printf(slot, "Got XPT_MMC_IO\n");
2636 ccb->ccb_h.status = CAM_REQ_INPROG;
2638 sdhci_cam_request(cam_sim_softc(sim), ccb);
2641 ccb->ccb_h.status = CAM_REQ_INVALID;
2649 sdhci_cam_poll(struct cam_sim *sim)
2655 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
2658 int max_clock, clock, i;
2660 if (proposed_clock == 0)
2662 max_clock = slot->max_clk;
2665 if (slot->version < SDHCI_SPEC_300) {
2666 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) {
2667 if (clock <= proposed_clock)
2672 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) {
2673 if (clock <= proposed_clock)
2675 clock = max_clock / (i + 2);
2682 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb)
2684 struct mmc_ios *ios;
2685 const struct mmc_ios *new_ios;
2686 const struct ccb_trans_settings_mmc *cts;
2688 ios = &slot->host.ios;
2689 cts = &ccb->cts.proto_specific.mmc;
2690 new_ios = &cts->ios;
2692 /* Update only requested fields */
2693 if (cts->ios_valid & MMC_CLK) {
2694 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2695 slot_printf(slot, "Clock => %d\n", ios->clock);
2697 if (cts->ios_valid & MMC_VDD) {
2698 ios->vdd = new_ios->vdd;
2699 slot_printf(slot, "VDD => %d\n", ios->vdd);
2701 if (cts->ios_valid & MMC_CS) {
2702 ios->chip_select = new_ios->chip_select;
2703 slot_printf(slot, "CS => %d\n", ios->chip_select);
2705 if (cts->ios_valid & MMC_BW) {
2706 ios->bus_width = new_ios->bus_width;
2707 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2709 if (cts->ios_valid & MMC_PM) {
2710 ios->power_mode = new_ios->power_mode;
2711 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2713 if (cts->ios_valid & MMC_BT) {
2714 ios->timing = new_ios->timing;
2715 slot_printf(slot, "Timing => %d\n", ios->timing);
2717 if (cts->ios_valid & MMC_BM) {
2718 ios->bus_mode = new_ios->bus_mode;
2719 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2722 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2723 return (sdhci_cam_update_ios(slot));
2727 sdhci_cam_update_ios(struct sdhci_slot *slot)
2729 struct mmc_ios *ios = &slot->host.ios;
2731 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2732 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2734 /* Do full reset on bus power down to clear from any state. */
2735 if (ios->power_mode == power_off) {
2736 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2739 /* Configure the bus. */
2740 sdhci_set_clock(slot, ios->clock);
2741 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2742 if (ios->bus_width == bus_width_8) {
2743 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2744 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2745 } else if (ios->bus_width == bus_width_4) {
2746 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2747 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2748 } else if (ios->bus_width == bus_width_1) {
2749 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2750 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2752 panic("Invalid bus width: %d", ios->bus_width);
2754 if (ios->timing == bus_timing_hs &&
2755 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2756 slot->hostctrl |= SDHCI_CTRL_HISPD;
2758 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2759 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2760 /* Some controllers like reset after bus changes. */
2761 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2762 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2769 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb)
2771 const struct ccb_mmcio *mmcio;
2773 mmcio = &ccb->mmcio;
2776 /* if (slot->req != NULL) {
2781 if (__predict_false(sdhci_debug > 1)) {
2782 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x "
2783 "blksz=%zu blkcnt=%zu\n",
2784 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2785 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2786 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0,
2787 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0,
2788 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0);
2790 if (mmcio->cmd.data != NULL) {
2791 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2792 panic("data->len = %d, data->flags = %d -- something is b0rked",
2793 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2800 while (slot->ccb != NULL) {
2801 sdhci_generic_intr(slot);
2809 MODULE_VERSION(sdhci, SDHCI_VERSION);