2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/callout.h>
37 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/resource.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <machine/stdarg.h>
52 #include <dev/mmc/bridge.h>
53 #include <dev/mmc/mmcreg.h>
54 #include <dev/mmc/mmcbrvar.h>
56 #include <dev/sdhci/sdhci.h>
59 #include <cam/cam_ccb.h>
60 #include <cam/cam_debug.h>
61 #include <cam/cam_sim.h>
62 #include <cam/cam_xpt_sim.h>
67 #include "opt_mmccam.h"
69 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
71 static int sdhci_debug = 0;
72 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
74 u_int sdhci_quirk_clear = 0;
75 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
76 0, "Mask of quirks to clear");
77 u_int sdhci_quirk_set = 0;
78 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
79 "Mask of quirks to set");
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
84 #define RD_MULTI_4(slot, off, ptr, count) \
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
90 #define WR_MULTI_4(slot, off, ptr, count) \
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
93 static void sdhci_card_poll(void *arg);
94 static void sdhci_card_task(void *arg, int pending);
95 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
96 static void sdhci_req_wakeup(struct mmc_request *req);
97 static void sdhci_retune(void *arg);
98 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
99 static void sdhci_start(struct sdhci_slot *slot);
100 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
104 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock);
105 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
106 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
107 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb);
108 static void sdhci_cam_poll(struct cam_sim *sim);
109 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
112 /* helper routines */
113 static void sdhci_dumpregs(struct sdhci_slot *slot);
114 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
116 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot);
118 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
119 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
120 #define SDHCI_LOCK_INIT(_slot) \
121 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
122 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
123 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
124 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
126 #define SDHCI_DEFAULT_MAX_FREQ 50
128 #define SDHCI_200_MAX_DIVIDER 256
129 #define SDHCI_300_MAX_DIVIDER 2046
131 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
132 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
135 * Broadcom BCM577xx Controller Constants
137 /* Maximum divider supported by the default clock source. */
138 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
139 /* Alternative clock's base frequency. */
140 #define BCM577XX_ALT_CLOCK_BASE 63000000
142 #define BCM577XX_HOST_CONTROL 0x198
143 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
144 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
145 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
146 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
149 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
153 printf("getaddr: error %d\n", error);
156 *(bus_addr_t *)arg = segs[0].ds_addr;
160 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
165 retval = printf("%s-slot%d: ",
166 device_get_nameunit(slot->bus), slot->num);
169 retval += vprintf(fmt, ap);
175 sdhci_dumpregs(struct sdhci_slot *slot)
179 "============== REGISTER DUMP ==============\n");
181 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
182 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
183 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
184 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
185 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
186 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
187 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
188 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
189 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
190 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
191 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
192 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
193 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
194 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
195 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
196 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
197 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
198 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
199 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
200 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
201 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
202 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
203 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
204 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
207 "===========================================\n");
211 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
216 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
217 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
221 /* Some controllers need this kick or reset won't work. */
222 if ((mask & SDHCI_RESET_ALL) == 0 &&
223 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
224 /* This is to force an update */
227 sdhci_set_clock(slot, clock);
230 if (mask & SDHCI_RESET_ALL) {
235 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
237 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
239 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
240 * specification. The reset bit has internal propagation delay,
241 * so a fast read after write returns 0 even if reset process is
242 * in progress. The workaround is to poll for 1 before polling
243 * for 0. In the worst case, if we miss seeing it asserted the
244 * time we spent waiting is enough to ensure the reset finishes.
247 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
255 /* Wait max 100 ms */
257 /* Controller clears the bits when it's done */
258 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
260 slot_printf(slot, "Reset 0x%x never completed.\n",
262 sdhci_dumpregs(slot);
271 sdhci_tuning_intmask(struct sdhci_slot *slot)
276 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
277 intmask |= SDHCI_INT_TUNEERR;
278 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
279 slot->retune_mode == SDHCI_RETUNE_MODE_3)
280 intmask |= SDHCI_INT_RETUNE;
286 sdhci_init(struct sdhci_slot *slot)
289 sdhci_reset(slot, SDHCI_RESET_ALL);
291 /* Enable interrupts. */
292 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
293 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
294 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
295 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
296 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
299 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
300 !(slot->opt & SDHCI_NON_REMOVABLE)) {
301 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
304 WR4(slot, SDHCI_INT_ENABLE, slot->intmask | sdhci_tuning_intmask(slot));
305 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
309 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
318 if (clock == slot->clock)
322 /* Turn off the clock. */
323 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
324 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
325 /* If no clock requested - leave it so. */
329 /* Determine the clock base frequency */
330 clk_base = slot->max_clk;
331 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
332 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
333 BCM577XX_CTRL_CLKSEL_MASK;
336 * Select clock source appropriate for the requested frequency.
338 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
339 clk_base = BCM577XX_ALT_CLOCK_BASE;
340 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
341 BCM577XX_CTRL_CLKSEL_SHIFT);
343 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
344 BCM577XX_CTRL_CLKSEL_SHIFT);
347 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
350 /* Recalculate timeout clock frequency based on the new sd clock. */
351 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
352 slot->timeout_clk = slot->clock / 1000;
354 if (slot->version < SDHCI_SPEC_300) {
355 /* Looking for highest freq <= clock. */
357 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
362 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
365 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
366 if (clock >= clk_base)
369 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
370 if ((clk_base / div) <= clock)
377 if (bootverbose || sdhci_debug)
378 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
379 div, clock, clk_base);
381 /* Now we have got divider, set it. */
382 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
383 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
384 << SDHCI_DIVIDER_HI_SHIFT;
386 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
388 clk |= SDHCI_CLOCK_INT_EN;
389 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
390 /* Wait up to 10 ms until it stabilize. */
392 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
393 & SDHCI_CLOCK_INT_STABLE)) {
396 "Internal clock never stabilised.\n");
397 sdhci_dumpregs(slot);
403 /* Pass clock signal to the bus. */
404 clk |= SDHCI_CLOCK_CARD_EN;
405 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
409 sdhci_set_power(struct sdhci_slot *slot, u_char power)
414 if (slot->power == power)
419 /* Turn off the power. */
421 WR1(slot, SDHCI_POWER_CONTROL, pwr);
422 /* If power down requested - leave it so. */
426 switch (1 << power) {
427 case MMC_OCR_LOW_VOLTAGE:
428 pwr |= SDHCI_POWER_180;
430 case MMC_OCR_290_300:
431 case MMC_OCR_300_310:
432 pwr |= SDHCI_POWER_300;
434 case MMC_OCR_320_330:
435 case MMC_OCR_330_340:
436 pwr |= SDHCI_POWER_330;
439 WR1(slot, SDHCI_POWER_CONTROL, pwr);
441 * Turn on VDD1 power. Note that at least some Intel controllers can
442 * fail to enable bus power on the first try after transiting from D3
443 * to D0, so we give them up to 2 ms.
445 pwr |= SDHCI_POWER_ON;
446 for (i = 0; i < 20; i++) {
447 WR1(slot, SDHCI_POWER_CONTROL, pwr);
448 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
452 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
453 slot_printf(slot, "Bus power failed to enable");
455 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
456 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
458 WR1(slot, SDHCI_POWER_CONTROL, pwr);
464 sdhci_read_block_pio(struct sdhci_slot *slot)
470 buffer = slot->curcmd->data->data;
471 buffer += slot->offset;
472 /* Transfer one block at a time. */
473 left = min(512, slot->curcmd->data->len - slot->offset);
474 slot->offset += left;
476 /* If we are too fast, broken controllers return zeroes. */
477 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
479 /* Handle unaligned and aligned buffer cases. */
480 if ((intptr_t)buffer & 3) {
482 data = RD4(slot, SDHCI_BUFFER);
484 buffer[1] = (data >> 8);
485 buffer[2] = (data >> 16);
486 buffer[3] = (data >> 24);
491 RD_MULTI_4(slot, SDHCI_BUFFER,
492 (uint32_t *)buffer, left >> 2);
495 /* Handle uneven size case. */
497 data = RD4(slot, SDHCI_BUFFER);
507 sdhci_write_block_pio(struct sdhci_slot *slot)
513 buffer = slot->curcmd->data->data;
514 buffer += slot->offset;
515 /* Transfer one block at a time. */
516 left = min(512, slot->curcmd->data->len - slot->offset);
517 slot->offset += left;
519 /* Handle unaligned and aligned buffer cases. */
520 if ((intptr_t)buffer & 3) {
528 WR4(slot, SDHCI_BUFFER, data);
531 WR_MULTI_4(slot, SDHCI_BUFFER,
532 (uint32_t *)buffer, left >> 2);
535 /* Handle uneven size case. */
542 WR4(slot, SDHCI_BUFFER, data);
547 sdhci_transfer_pio(struct sdhci_slot *slot)
550 /* Read as many blocks as possible. */
551 if (slot->curcmd->data->flags & MMC_DATA_READ) {
552 while (RD4(slot, SDHCI_PRESENT_STATE) &
553 SDHCI_DATA_AVAILABLE) {
554 sdhci_read_block_pio(slot);
555 if (slot->offset >= slot->curcmd->data->len)
559 while (RD4(slot, SDHCI_PRESENT_STATE) &
560 SDHCI_SPACE_AVAILABLE) {
561 sdhci_write_block_pio(slot);
562 if (slot->offset >= slot->curcmd->data->len)
569 sdhci_card_task(void *arg, int pending __unused)
571 struct sdhci_slot *slot = arg;
575 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
577 if (slot->card_present == 0) {
579 if (slot->dev == NULL) {
581 /* If card is present - attach mmc bus. */
582 if (bootverbose || sdhci_debug)
583 slot_printf(slot, "Card inserted\n");
585 slot->card_present = 1;
588 pathid = cam_sim_path(slot->sim);
589 ccb = xpt_alloc_ccb_nowait();
591 slot_printf(slot, "Unable to alloc CCB for rescan\n");
597 * We create a rescan request for BUS:0:0, since the card
600 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid,
601 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) {
602 slot_printf(slot, "Unable to create path for rescan\n");
610 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
613 device_set_ivars(d, slot);
614 (void)device_probe_and_attach(d);
621 if (slot->card_present == 1) {
623 if (slot->dev != NULL) {
625 /* If no card present - detach mmc bus. */
626 if (bootverbose || sdhci_debug)
627 slot_printf(slot, "Card removed\n");
631 slot->card_present = 0;
634 pathid = cam_sim_path(slot->sim);
635 ccb = xpt_alloc_ccb_nowait();
637 slot_printf(slot, "Unable to alloc CCB for rescan\n");
643 * We create a rescan request for BUS:0:0, since the card
646 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid,
647 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) {
648 slot_printf(slot, "Unable to create path for rescan\n");
656 slot->intmask &= ~sdhci_tuning_intmask(slot);
657 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
658 slot->opt &= ~SDHCI_TUNING_ENABLED;
660 callout_drain(&slot->retune_callout);
661 device_delete_child(slot->bus, d);
669 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
674 * If there was no card and now there is one, schedule the task to
675 * create the child device after a short delay. The delay is to
676 * debounce the card insert (sometimes the card detect pin stabilizes
677 * before the other pins have made good contact).
679 * If there was a card present and now it's gone, immediately schedule
680 * the task to delete the child device. No debouncing -- gone is gone,
681 * because once power is removed, a full card re-init is needed, and
682 * that happens by deleting and recreating the child device.
685 was_present = slot->card_present;
687 was_present = slot->dev != NULL;
689 if (!was_present && is_present) {
690 taskqueue_enqueue_timeout(taskqueue_swi_giant,
691 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
692 } else if (was_present && !is_present) {
693 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
698 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
702 sdhci_handle_card_present_locked(slot, is_present);
707 sdhci_card_poll(void *arg)
709 struct sdhci_slot *slot = arg;
711 sdhci_handle_card_present(slot,
712 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
713 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
714 sdhci_card_poll, slot);
718 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
720 kobjop_desc_t kobj_desc;
721 kobj_method_t *kobj_method;
722 uint32_t caps, caps2, freq, host_caps;
725 SDHCI_LOCK_INIT(slot);
730 /* Allocate DMA tag. */
731 err = bus_dma_tag_create(bus_get_dma_tag(dev),
732 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
733 BUS_SPACE_MAXADDR, NULL, NULL,
734 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
735 BUS_DMA_ALLOCNOW, NULL, NULL,
738 device_printf(dev, "Can't create DMA tag\n");
739 SDHCI_LOCK_DESTROY(slot);
742 /* Allocate DMA memory. */
743 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
744 BUS_DMA_NOWAIT, &slot->dmamap);
746 device_printf(dev, "Can't alloc DMA memory\n");
747 bus_dma_tag_destroy(slot->dmatag);
748 SDHCI_LOCK_DESTROY(slot);
751 /* Map the memory. */
752 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
753 (void *)slot->dmamem, DMA_BLOCK_SIZE,
754 sdhci_getaddr, &slot->paddr, 0);
755 if (err != 0 || slot->paddr == 0) {
756 device_printf(dev, "Can't load DMA memory\n");
757 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
758 bus_dma_tag_destroy(slot->dmatag);
759 SDHCI_LOCK_DESTROY(slot);
766 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
767 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
768 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
772 caps = RD4(slot, SDHCI_CAPABILITIES);
773 if (slot->version >= SDHCI_SPEC_300)
774 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
778 if (slot->version >= SDHCI_SPEC_300) {
779 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
780 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
782 "Driver doesn't support shared bus slots\n");
783 bus_dmamap_unload(slot->dmatag, slot->dmamap);
784 bus_dmamem_free(slot->dmatag, slot->dmamem,
786 bus_dma_tag_destroy(slot->dmatag);
787 SDHCI_LOCK_DESTROY(slot);
789 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
790 SDHCI_SLOTTYPE_EMBEDDED) {
791 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
794 /* Calculate base clock frequency. */
795 if (slot->version >= SDHCI_SPEC_300)
796 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
797 SDHCI_CLOCK_BASE_SHIFT;
799 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
800 SDHCI_CLOCK_BASE_SHIFT;
802 slot->max_clk = freq * 1000000;
804 * If the frequency wasn't in the capabilities and the hardware driver
805 * hasn't already set max_clk we're probably not going to work right
806 * with an assumption, so complain about it.
808 if (slot->max_clk == 0) {
809 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
810 device_printf(dev, "Hardware doesn't specify base clock "
811 "frequency, using %dMHz as default.\n",
812 SDHCI_DEFAULT_MAX_FREQ);
814 /* Calculate/set timeout clock frequency. */
815 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
816 slot->timeout_clk = slot->max_clk / 1000;
817 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
818 slot->timeout_clk = 1000;
820 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
821 SDHCI_TIMEOUT_CLK_SHIFT;
822 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
823 slot->timeout_clk *= 1000;
826 * If the frequency wasn't in the capabilities and the hardware driver
827 * hasn't already set timeout_clk we'll probably work okay using the
828 * max timeout, but still mention it.
830 if (slot->timeout_clk == 0) {
831 device_printf(dev, "Hardware doesn't specify timeout clock "
832 "frequency, setting BROKEN_TIMEOUT quirk.\n");
833 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
836 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
837 slot->host.f_max = slot->max_clk;
838 slot->host.host_ocr = 0;
839 if (caps & SDHCI_CAN_VDD_330)
840 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
841 if (caps & SDHCI_CAN_VDD_300)
842 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
843 /* 1.8V VDD is not supposed to be used for removable cards. */
844 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
845 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
846 if (slot->host.host_ocr == 0) {
847 device_printf(dev, "Hardware doesn't report any "
848 "support voltages.\n");
851 host_caps = MMC_CAP_4_BIT_DATA;
852 if (caps & SDHCI_CAN_DO_8BITBUS)
853 host_caps |= MMC_CAP_8_BIT_DATA;
854 if (caps & SDHCI_CAN_DO_HISPD)
855 host_caps |= MMC_CAP_HSPEED;
856 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
857 host_caps |= MMC_CAP_BOOT_NOACC;
858 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
859 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
861 /* Determine supported UHS-I and eMMC modes. */
862 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
863 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
864 if (caps2 & SDHCI_CAN_SDR104) {
865 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
866 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
867 host_caps |= MMC_CAP_MMC_HS200;
868 } else if (caps2 & SDHCI_CAN_SDR50)
869 host_caps |= MMC_CAP_UHS_SDR50;
870 if (caps2 & SDHCI_CAN_DDR50 &&
871 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
872 host_caps |= MMC_CAP_UHS_DDR50;
873 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
874 host_caps |= MMC_CAP_MMC_DDR52;
875 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
876 caps2 & SDHCI_CAN_MMC_HS400)
877 host_caps |= MMC_CAP_MMC_HS400;
880 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
881 * default NULL implementation.
883 kobj_desc = &sdhci_set_uhs_timing_desc;
884 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
886 if (kobj_method == &kobj_desc->deflt)
887 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
888 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
889 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
891 #define SDHCI_CAP_MODES_TUNING(caps2) \
892 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
893 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
897 * Disable UHS-I and eMMC modes that require (re-)tuning if either
898 * the tune or re-tune method is the default NULL implementation.
900 kobj_desc = &mmcbr_tune_desc;
901 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
903 if (kobj_method == &kobj_desc->deflt)
905 kobj_desc = &mmcbr_retune_desc;
906 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
908 if (kobj_method == &kobj_desc->deflt) {
910 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
913 /* Allocate tuning structures and determine tuning parameters. */
914 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
915 slot->opt |= SDHCI_TUNING_SUPPORTED;
916 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
918 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
920 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
922 if (caps2 & SDHCI_TUNE_SDR50)
923 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
924 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
925 SDHCI_RETUNE_MODES_SHIFT;
926 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
927 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
928 SDHCI_RETUNE_CNT_SHIFT;
929 if (slot->retune_count > 0xb) {
930 device_printf(dev, "Unknown re-tuning count "
931 "%x, using 1 sec\n", slot->retune_count);
932 slot->retune_count = 1;
933 } else if (slot->retune_count != 0)
935 1 << (slot->retune_count - 1);
939 #undef SDHCI_CAP_MODES_TUNING
941 /* Determine supported VCCQ signaling levels. */
942 host_caps |= MMC_CAP_SIGNALING_330;
943 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
944 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
945 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
946 MMC_CAP_MMC_HS400_180))
947 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
950 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
951 * default NULL implementation. Disable 1.2 V support if it's the
952 * generic SDHCI implementation.
954 kobj_desc = &mmcbr_switch_vccq_desc;
955 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
957 if (kobj_method == &kobj_desc->deflt)
958 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
959 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
960 host_caps &= ~MMC_CAP_SIGNALING_120;
962 /* Determine supported driver types (type B is always mandatory). */
963 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
964 host_caps |= MMC_CAP_DRIVER_TYPE_A;
965 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
966 host_caps |= MMC_CAP_DRIVER_TYPE_C;
967 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
968 host_caps |= MMC_CAP_DRIVER_TYPE_D;
969 slot->host.caps = host_caps;
971 /* Decide if we have usable DMA. */
972 if (caps & SDHCI_CAN_DO_DMA)
973 slot->opt |= SDHCI_HAVE_DMA;
975 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
976 slot->opt &= ~SDHCI_HAVE_DMA;
977 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
978 slot->opt |= SDHCI_HAVE_DMA;
979 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
980 slot->opt |= SDHCI_NON_REMOVABLE;
983 * Use platform-provided transfer backend
984 * with PIO as a fallback mechanism
986 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
987 slot->opt &= ~SDHCI_HAVE_DMA;
989 if (bootverbose || sdhci_debug) {
991 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
992 slot->max_clk / 1000000,
993 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
994 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
995 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
996 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
997 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
998 ((caps & SDHCI_CAN_VDD_180) &&
999 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
1000 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
1001 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
1002 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
1003 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
1004 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
1005 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
1006 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
1007 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
1009 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
1010 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
1011 slot_printf(slot, "eMMC:%s%s%s%s\n",
1012 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
1013 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
1014 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
1016 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
1017 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
1019 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1020 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
1021 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
1022 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
1023 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
1024 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
1025 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
1026 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
1027 if (slot->opt & SDHCI_TUNING_SUPPORTED)
1028 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
1029 slot->retune_count, slot->retune_mode + 1);
1030 sdhci_dumpregs(slot);
1034 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1035 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1036 "timeout", CTLFLAG_RW, &slot->timeout, 0,
1037 "Maximum timeout for SDHCI transfers (in secs)");
1038 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1039 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1040 sdhci_card_task, slot);
1041 callout_init(&slot->card_poll_callout, 1);
1042 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1043 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1045 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1046 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1047 callout_reset(&slot->card_poll_callout,
1048 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1058 sdhci_start_slot(struct sdhci_slot *slot)
1061 sdhci_card_task(slot, 0);
1066 sdhci_cleanup_slot(struct sdhci_slot *slot)
1070 callout_drain(&slot->timeout_callout);
1071 callout_drain(&slot->card_poll_callout);
1072 callout_drain(&slot->retune_callout);
1073 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1074 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1081 device_delete_child(slot->bus, d);
1084 sdhci_reset(slot, SDHCI_RESET_ALL);
1086 bus_dmamap_unload(slot->dmatag, slot->dmamap);
1087 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
1088 bus_dma_tag_destroy(slot->dmatag);
1089 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1090 free(slot->tune_req, M_DEVBUF);
1091 free(slot->tune_cmd, M_DEVBUF);
1092 free(slot->tune_data, M_DEVBUF);
1095 SDHCI_LOCK_DESTROY(slot);
1101 sdhci_generic_suspend(struct sdhci_slot *slot)
1105 * We expect the MMC layer to issue initial tuning after resume.
1106 * Otherwise, we'd need to indicate re-tuning including circuit reset
1107 * being required at least for re-tuning modes 1 and 2 ourselves.
1109 callout_drain(&slot->retune_callout);
1111 slot->opt &= ~SDHCI_TUNING_ENABLED;
1112 sdhci_reset(slot, SDHCI_RESET_ALL);
1119 sdhci_generic_resume(struct sdhci_slot *slot)
1130 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1133 if (slot->version >= SDHCI_SPEC_300)
1134 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1136 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1140 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1143 if (slot->opt & SDHCI_NON_REMOVABLE)
1146 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1150 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1152 struct mmc_ios *ios;
1155 if (slot->version < SDHCI_SPEC_300)
1158 SDHCI_ASSERT_LOCKED(slot);
1159 ios = &slot->host.ios;
1160 sdhci_set_clock(slot, 0);
1161 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1162 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1163 if (ios->clock > SD_SDR50_MAX) {
1164 if (ios->timing == bus_timing_mmc_hs400 ||
1165 ios->timing == bus_timing_mmc_hs400es)
1166 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1168 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1170 else if (ios->clock > SD_SDR25_MAX)
1171 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1172 else if (ios->clock > SD_SDR12_MAX) {
1173 if (ios->timing == bus_timing_uhs_ddr50 ||
1174 ios->timing == bus_timing_mmc_ddr52)
1175 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1177 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1178 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1179 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1180 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1181 sdhci_set_clock(slot, ios->clock);
1185 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1187 struct sdhci_slot *slot = device_get_ivars(reqdev);
1188 struct mmc_ios *ios = &slot->host.ios;
1191 /* Do full reset on bus power down to clear from any state. */
1192 if (ios->power_mode == power_off) {
1193 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1196 /* Configure the bus. */
1197 sdhci_set_clock(slot, ios->clock);
1198 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1199 if (ios->bus_width == bus_width_8) {
1200 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1201 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1202 } else if (ios->bus_width == bus_width_4) {
1203 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1204 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1205 } else if (ios->bus_width == bus_width_1) {
1206 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1207 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1209 panic("Invalid bus width: %d", ios->bus_width);
1211 if (ios->clock > SD_SDR12_MAX &&
1212 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1213 slot->hostctrl |= SDHCI_CTRL_HISPD;
1215 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1216 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1217 SDHCI_SET_UHS_TIMING(brdev, slot);
1218 /* Some controllers like reset after bus changes. */
1219 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1220 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1227 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1229 struct sdhci_slot *slot = device_get_ivars(reqdev);
1234 if (slot->version < SDHCI_SPEC_300)
1238 vccq = slot->host.ios.vccq;
1240 sdhci_set_clock(slot, 0);
1241 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1244 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1246 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1247 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1249 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1250 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1255 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1259 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1261 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1262 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1264 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1265 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1271 "Attempt to set unsupported signaling voltage\n");
1276 sdhci_set_clock(slot, slot->host.ios.clock);
1282 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1284 struct sdhci_slot *slot = device_get_ivars(reqdev);
1285 struct mmc_ios *ios = &slot->host.ios;
1286 struct mmc_command *tune_cmd;
1287 struct mmc_data *tune_data;
1291 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1294 slot->retune_ticks = slot->retune_count * hz;
1295 opcode = MMC_SEND_TUNING_BLOCK;
1297 switch (ios->timing) {
1298 case bus_timing_mmc_hs400:
1299 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1302 case bus_timing_mmc_hs200:
1304 * In HS400 mode, controllers use the data strobe line to
1305 * latch data from the devices so periodic re-tuning isn't
1306 * expected to be required.
1309 slot->retune_ticks = 0;
1310 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1312 case bus_timing_uhs_ddr50:
1313 case bus_timing_uhs_sdr104:
1315 case bus_timing_uhs_sdr50:
1316 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1324 tune_cmd = slot->tune_cmd;
1325 memset(tune_cmd, 0, sizeof(*tune_cmd));
1326 tune_cmd->opcode = opcode;
1327 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1328 tune_data = tune_cmd->data = slot->tune_data;
1329 memset(tune_data, 0, sizeof(*tune_data));
1330 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1331 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1333 tune_data->flags = MMC_DATA_READ;
1334 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1336 slot->opt &= ~SDHCI_TUNING_ENABLED;
1337 err = sdhci_exec_tuning(slot, true);
1339 slot->opt |= SDHCI_TUNING_ENABLED;
1340 slot->intmask |= sdhci_tuning_intmask(slot);
1341 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1342 if (slot->retune_ticks) {
1343 callout_reset(&slot->retune_callout, slot->retune_ticks,
1344 sdhci_retune, slot);
1352 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1354 struct sdhci_slot *slot = device_get_ivars(reqdev);
1357 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1360 /* HS400 must be tuned in HS200 mode. */
1361 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1365 err = sdhci_exec_tuning(slot, reset);
1367 * There are two ways sdhci_exec_tuning() can fail:
1368 * EBUSY should not actually happen when requests are only issued
1369 * with the host properly acquired, and
1370 * EIO re-tuning failed (but it did work initially).
1372 * In both cases, we should retry at later point if periodic re-tuning
1373 * is enabled. Note that due to slot->retune_req not being cleared in
1374 * these failure cases, the MMC layer should trigger another attempt at
1375 * re-tuning with the next request anyway, though.
1377 if (slot->retune_ticks) {
1378 callout_reset(&slot->retune_callout, slot->retune_ticks,
1379 sdhci_retune, slot);
1386 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1388 struct mmc_request *tune_req;
1389 struct mmc_command *tune_cmd;
1395 SDHCI_ASSERT_LOCKED(slot);
1396 if (slot->req != NULL)
1399 /* Tuning doesn't work with DMA enabled. */
1401 slot->opt = opt & ~SDHCI_HAVE_DMA;
1404 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1405 * kind of interrupt we receive in response to a tuning request.
1407 intmask = slot->intmask;
1408 slot->intmask = SDHCI_INT_DATA_AVAIL;
1409 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1411 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1413 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1415 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1416 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1418 tune_req = slot->tune_req;
1419 tune_cmd = slot->tune_cmd;
1420 for (i = 0; i < MMC_TUNING_MAX; i++) {
1421 memset(tune_req, 0, sizeof(*tune_req));
1422 tune_req->cmd = tune_cmd;
1423 tune_req->done = sdhci_req_wakeup;
1424 tune_req->done_data = slot;
1425 slot->req = tune_req;
1428 while (!(tune_req->flags & MMC_REQ_DONE))
1429 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1430 if (!(tune_req->flags & MMC_TUNE_DONE))
1432 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1433 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1435 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1440 slot->intmask = intmask;
1441 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1443 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1444 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1445 slot->retune_req = 0;
1449 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1450 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1451 SDHCI_CTRL2_SAMPLING_CLOCK));
1452 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1457 sdhci_retune(void *arg)
1459 struct sdhci_slot *slot = arg;
1461 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1466 sdhci_req_done(struct sdhci_slot *slot)
1470 if (__predict_false(sdhci_debug > 1))
1471 slot_printf(slot, "%s\n", __func__);
1472 if (slot->ccb != NULL && slot->curcmd != NULL) {
1473 callout_stop(&slot->timeout_callout);
1476 slot->curcmd = NULL;
1478 /* Tell CAM the request is finished */
1479 struct ccb_mmcio *mmcio;
1480 mmcio = &ccb->mmcio;
1483 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1489 sdhci_req_done(struct sdhci_slot *slot)
1491 struct mmc_request *req;
1493 if (slot->req != NULL && slot->curcmd != NULL) {
1494 callout_stop(&slot->timeout_callout);
1497 slot->curcmd = NULL;
1504 sdhci_req_wakeup(struct mmc_request *req)
1506 struct sdhci_slot *slot;
1508 slot = req->done_data;
1509 req->flags |= MMC_REQ_DONE;
1514 sdhci_timeout(void *arg)
1516 struct sdhci_slot *slot = arg;
1518 if (slot->curcmd != NULL) {
1519 slot_printf(slot, "Controller timeout\n");
1520 sdhci_dumpregs(slot);
1521 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1522 slot->curcmd->error = MMC_ERR_TIMEOUT;
1523 sdhci_req_done(slot);
1525 slot_printf(slot, "Spurious timeout - no active command\n");
1530 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
1537 mode = SDHCI_TRNS_BLK_CNT_EN;
1538 if (data->len > 512)
1539 mode |= SDHCI_TRNS_MULTI;
1540 if (data->flags & MMC_DATA_READ)
1541 mode |= SDHCI_TRNS_READ;
1543 struct ccb_mmcio *mmcio;
1544 mmcio = &slot->ccb->mmcio;
1545 if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION
1546 && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))
1547 mode |= SDHCI_TRNS_ACMD12;
1549 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))
1550 mode |= SDHCI_TRNS_ACMD12;
1552 if (slot->flags & SDHCI_USE_DMA)
1553 mode |= SDHCI_TRNS_DMA;
1555 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1559 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1567 cmd->error = MMC_ERR_NONE;
1569 /* This flags combination is not supported by controller. */
1570 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1571 slot_printf(slot, "Unsupported response type!\n");
1572 cmd->error = MMC_ERR_FAILED;
1573 sdhci_req_done(slot);
1578 * Do not issue command if there is no card, clock or power.
1579 * Controller will not detect timeout without clock active.
1581 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1585 "Cannot issue a command (power=%d clock=%d)",
1586 slot->power, slot->clock);
1587 cmd->error = MMC_ERR_FAILED;
1588 sdhci_req_done(slot);
1591 /* Always wait for free CMD bus. */
1592 mask = SDHCI_CMD_INHIBIT;
1593 /* Wait for free DAT if we have data or busy signal. */
1594 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1595 mask |= SDHCI_DAT_INHIBIT;
1597 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1598 * that these latter are also special in that SDHCI_CMD_DATA should
1599 * be set below but no actual data is ever read from the controller.
1602 if (cmd == &slot->ccb->mmcio.stop ||
1604 if (cmd == slot->req->stop ||
1606 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1607 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1608 mask &= ~SDHCI_DAT_INHIBIT;
1610 * Wait for bus no more then 250 ms. Typically there will be no wait
1611 * here at all, but when writing a crash dump we may be bypassing the
1612 * host platform's interrupt handler, and in some cases that handler
1613 * may be working around hardware quirks such as not respecting r1b
1614 * busy indications. In those cases, this wait-loop serves the purpose
1615 * of waiting for the prior command and data transfers to be done, and
1616 * SD cards are allowed to take up to 250ms for write and erase ops.
1617 * (It's usually more like 20-30ms in the real world.)
1620 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1622 slot_printf(slot, "Controller never released "
1623 "inhibit bit(s).\n");
1624 sdhci_dumpregs(slot);
1625 cmd->error = MMC_ERR_FAILED;
1626 sdhci_req_done(slot);
1633 /* Prepare command flags. */
1634 if (!(cmd->flags & MMC_RSP_PRESENT))
1635 flags = SDHCI_CMD_RESP_NONE;
1636 else if (cmd->flags & MMC_RSP_136)
1637 flags = SDHCI_CMD_RESP_LONG;
1638 else if (cmd->flags & MMC_RSP_BUSY)
1639 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1641 flags = SDHCI_CMD_RESP_SHORT;
1642 if (cmd->flags & MMC_RSP_CRC)
1643 flags |= SDHCI_CMD_CRC;
1644 if (cmd->flags & MMC_RSP_OPCODE)
1645 flags |= SDHCI_CMD_INDEX;
1646 if (cmd->data != NULL)
1647 flags |= SDHCI_CMD_DATA;
1648 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1649 flags |= SDHCI_CMD_TYPE_ABORT;
1651 sdhci_start_data(slot, cmd->data);
1653 * Interrupt aggregation: To reduce total number of interrupts
1654 * group response interrupt with data interrupt when possible.
1655 * If there going to be data interrupt, mask response one.
1657 if (slot->data_done == 0) {
1658 WR4(slot, SDHCI_SIGNAL_ENABLE,
1659 slot->intmask &= ~SDHCI_INT_RESPONSE);
1661 /* Set command argument. */
1662 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1663 /* Set data transfer mode. */
1664 sdhci_set_transfer_mode(slot, cmd->data);
1665 if (__predict_false(sdhci_debug > 1))
1666 slot_printf(slot, "Starting command!\n");
1667 /* Start command. */
1668 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1669 /* Start timeout callout. */
1670 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1671 sdhci_timeout, slot);
1675 sdhci_finish_command(struct sdhci_slot *slot)
1681 if (__predict_false(sdhci_debug > 1))
1682 slot_printf(slot, "%s: called, err %d flags %d\n",
1683 __func__, slot->curcmd->error, slot->curcmd->flags);
1686 * Interrupt aggregation: Restore command interrupt.
1687 * Main restore point for the case when command interrupt
1690 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1691 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1692 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1693 SDHCI_INT_RESPONSE);
1694 /* In case of error - reset host and return. */
1695 if (slot->curcmd->error) {
1696 if (slot->curcmd->error == MMC_ERR_BADCRC)
1697 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1698 sdhci_reset(slot, SDHCI_RESET_CMD);
1699 sdhci_reset(slot, SDHCI_RESET_DATA);
1703 /* If command has response - fetch it. */
1704 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1705 if (slot->curcmd->flags & MMC_RSP_136) {
1706 /* CRC is stripped so we need one byte shift. */
1708 for (i = 0; i < 4; i++) {
1709 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1711 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1712 slot->curcmd->resp[3 - i] = val;
1714 slot->curcmd->resp[3 - i] =
1720 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1722 if (__predict_false(sdhci_debug > 1))
1723 printf("Resp: %02x %02x %02x %02x\n",
1724 slot->curcmd->resp[0], slot->curcmd->resp[1],
1725 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1727 /* If data ready - finish. */
1728 if (slot->data_done)
1733 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1735 uint32_t target_timeout, current_timeout;
1738 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1739 slot->data_done = 1;
1743 slot->data_done = 0;
1745 /* Calculate and set data timeout.*/
1746 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1747 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1750 target_timeout = 1000000;
1752 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1753 while (current_timeout < target_timeout && div < 0xE) {
1755 current_timeout <<= 1;
1757 /* Compensate for an off-by-one error in the CaFe chip.*/
1759 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1763 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1768 /* Use DMA if possible. */
1769 if ((slot->opt & SDHCI_HAVE_DMA))
1770 slot->flags |= SDHCI_USE_DMA;
1771 /* If data is small, broken DMA may return zeroes instead of data, */
1772 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1774 slot->flags &= ~SDHCI_USE_DMA;
1775 /* Some controllers require even block sizes. */
1776 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1777 ((data->len) & 0x3))
1778 slot->flags &= ~SDHCI_USE_DMA;
1779 /* Load DMA buffer. */
1780 if (slot->flags & SDHCI_USE_DMA) {
1781 if (data->flags & MMC_DATA_READ)
1782 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1783 BUS_DMASYNC_PREREAD);
1785 memcpy(slot->dmamem, data->data,
1786 (data->len < DMA_BLOCK_SIZE) ?
1787 data->len : DMA_BLOCK_SIZE);
1788 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1789 BUS_DMASYNC_PREWRITE);
1791 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1792 /* Interrupt aggregation: Mask border interrupt
1793 * for the last page and unmask else. */
1794 if (data->len == DMA_BLOCK_SIZE)
1795 slot->intmask &= ~SDHCI_INT_DMA_END;
1797 slot->intmask |= SDHCI_INT_DMA_END;
1798 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1800 /* Current data offset for both PIO and DMA. */
1802 /* Set block size and request IRQ on 4K border. */
1803 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
1804 (data->len < 512) ? data->len : 512));
1805 /* Set block count. */
1806 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1808 if (__predict_false(sdhci_debug > 1))
1809 slot_printf(slot, "Block size: %02x, count %lu\n",
1810 (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512),
1811 (unsigned long)(data->len + 511) / 512);
1815 sdhci_finish_data(struct sdhci_slot *slot)
1817 struct mmc_data *data = slot->curcmd->data;
1820 /* Interrupt aggregation: Restore command interrupt.
1821 * Auxiliary restore point for the case when data interrupt
1822 * happened first. */
1823 if (!slot->cmd_done) {
1824 WR4(slot, SDHCI_SIGNAL_ENABLE,
1825 slot->intmask |= SDHCI_INT_RESPONSE);
1827 /* Unload rest of data from DMA buffer. */
1828 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
1829 slot->curcmd->data != NULL) {
1830 if (data->flags & MMC_DATA_READ) {
1831 left = data->len - slot->offset;
1832 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1833 BUS_DMASYNC_POSTREAD);
1834 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1835 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1837 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1838 BUS_DMASYNC_POSTWRITE);
1840 slot->data_done = 1;
1841 /* If there was error - reset the host. */
1842 if (slot->curcmd->error) {
1843 if (slot->curcmd->error == MMC_ERR_BADCRC)
1844 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1845 sdhci_reset(slot, SDHCI_RESET_CMD);
1846 sdhci_reset(slot, SDHCI_RESET_DATA);
1850 /* If we already have command response - finish. */
1857 sdhci_start(struct sdhci_slot *slot)
1865 struct ccb_mmcio *mmcio;
1866 mmcio = &ccb->mmcio;
1868 if (!(slot->flags & CMD_STARTED)) {
1869 slot->flags |= CMD_STARTED;
1870 sdhci_start_command(slot, &mmcio->cmd);
1875 * Old stack doesn't use this!
1876 * Enabling this code causes significant performance degradation
1877 * and IRQ storms on BBB, Wandboard behaves fine.
1878 * Not using this code does no harm...
1879 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
1880 slot->flags |= STOP_STARTED;
1881 sdhci_start_command(slot, &mmcio->stop);
1885 if (__predict_false(sdhci_debug > 1))
1886 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
1887 if (mmcio->cmd.error == 0 &&
1888 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1889 sdhci_reset(slot, SDHCI_RESET_CMD);
1890 sdhci_reset(slot, SDHCI_RESET_DATA);
1893 sdhci_req_done(slot);
1897 sdhci_start(struct sdhci_slot *slot)
1899 struct mmc_request *req;
1905 if (!(slot->flags & CMD_STARTED)) {
1906 slot->flags |= CMD_STARTED;
1907 sdhci_start_command(slot, req->cmd);
1910 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
1911 !(slot->flags & STOP_STARTED) && req->stop) {
1912 slot->flags |= STOP_STARTED;
1913 sdhci_start_command(slot, req->stop);
1916 if (__predict_false(sdhci_debug > 1))
1917 slot_printf(slot, "result: %d\n", req->cmd->error);
1918 if (!req->cmd->error &&
1919 ((slot->curcmd == req->stop &&
1920 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
1921 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1922 sdhci_reset(slot, SDHCI_RESET_CMD);
1923 sdhci_reset(slot, SDHCI_RESET_DATA);
1926 sdhci_req_done(slot);
1931 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1932 struct mmc_request *req)
1934 struct sdhci_slot *slot = device_get_ivars(reqdev);
1937 if (slot->req != NULL) {
1941 if (__predict_false(sdhci_debug > 1)) {
1943 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1944 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1945 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1946 (req->cmd->data)?req->cmd->data->flags:0);
1953 while (slot->req != NULL) {
1954 sdhci_generic_intr(slot);
1962 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1964 struct sdhci_slot *slot = device_get_ivars(reqdev);
1968 val = RD4(slot, SDHCI_PRESENT_STATE);
1970 return (!(val & SDHCI_WRITE_PROTECT));
1974 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1976 struct sdhci_slot *slot = device_get_ivars(reqdev);
1980 while (slot->bus_busy)
1981 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1984 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1990 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1992 struct sdhci_slot *slot = device_get_ivars(reqdev);
1995 /* Deactivate led. */
1996 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2004 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
2007 if (!slot->curcmd) {
2008 slot_printf(slot, "Got command interrupt 0x%08x, but "
2009 "there is no active command.\n", intmask);
2010 sdhci_dumpregs(slot);
2013 if (intmask & SDHCI_INT_TIMEOUT)
2014 slot->curcmd->error = MMC_ERR_TIMEOUT;
2015 else if (intmask & SDHCI_INT_CRC)
2016 slot->curcmd->error = MMC_ERR_BADCRC;
2017 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
2018 slot->curcmd->error = MMC_ERR_FIFO;
2020 sdhci_finish_command(slot);
2024 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
2026 struct mmc_data *data;
2029 if (!slot->curcmd) {
2030 slot_printf(slot, "Got data interrupt 0x%08x, but "
2031 "there is no active command.\n", intmask);
2032 sdhci_dumpregs(slot);
2035 if (slot->curcmd->data == NULL &&
2036 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2037 slot_printf(slot, "Got data interrupt 0x%08x, but "
2038 "there is no active data operation.\n",
2040 sdhci_dumpregs(slot);
2043 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2044 slot->curcmd->error = MMC_ERR_TIMEOUT;
2045 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
2046 slot->curcmd->error = MMC_ERR_BADCRC;
2047 if (slot->curcmd->data == NULL &&
2048 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2049 SDHCI_INT_DMA_END))) {
2050 slot_printf(slot, "Got data interrupt 0x%08x, but "
2051 "there is busy-only command.\n", intmask);
2052 sdhci_dumpregs(slot);
2053 slot->curcmd->error = MMC_ERR_INVALID;
2055 if (slot->curcmd->error) {
2056 /* No need to continue after any error. */
2060 /* Handle tuning completion interrupt. */
2061 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
2062 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2063 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2064 slot->req->flags |= MMC_TUNE_DONE;
2065 sdhci_finish_command(slot);
2066 sdhci_finish_data(slot);
2069 /* Handle PIO interrupt. */
2070 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
2071 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2072 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2073 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2075 slot->flags |= PLATFORM_DATA_STARTED;
2077 sdhci_transfer_pio(slot);
2079 /* Handle DMA border. */
2080 if (intmask & SDHCI_INT_DMA_END) {
2081 data = slot->curcmd->data;
2083 /* Unload DMA buffer ... */
2084 left = data->len - slot->offset;
2085 if (data->flags & MMC_DATA_READ) {
2086 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2087 BUS_DMASYNC_POSTREAD);
2088 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2089 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
2091 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2092 BUS_DMASYNC_POSTWRITE);
2094 /* ... and reload it again. */
2095 slot->offset += DMA_BLOCK_SIZE;
2096 left = data->len - slot->offset;
2097 if (data->flags & MMC_DATA_READ) {
2098 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2099 BUS_DMASYNC_PREREAD);
2101 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2102 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
2103 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2104 BUS_DMASYNC_PREWRITE);
2106 /* Interrupt aggregation: Mask border interrupt
2107 * for the last page. */
2108 if (left == DMA_BLOCK_SIZE) {
2109 slot->intmask &= ~SDHCI_INT_DMA_END;
2110 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2113 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2115 /* We have got all data. */
2116 if (intmask & SDHCI_INT_DATA_END) {
2117 if (slot->flags & PLATFORM_DATA_STARTED) {
2118 slot->flags &= ~PLATFORM_DATA_STARTED;
2119 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2121 sdhci_finish_data(slot);
2124 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2125 if (slot->flags & PLATFORM_DATA_STARTED) {
2126 slot->flags &= ~PLATFORM_DATA_STARTED;
2127 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2129 sdhci_finish_data(slot);
2134 sdhci_acmd_irq(struct sdhci_slot *slot)
2138 err = RD4(slot, SDHCI_ACMD12_ERR);
2139 if (!slot->curcmd) {
2140 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2141 "there is no active command.\n", err);
2142 sdhci_dumpregs(slot);
2145 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
2146 sdhci_reset(slot, SDHCI_RESET_CMD);
2150 sdhci_generic_intr(struct sdhci_slot *slot)
2152 uint32_t intmask, present;
2155 /* Read slot interrupt status. */
2156 intmask = RD4(slot, SDHCI_INT_STATUS);
2157 if (intmask == 0 || intmask == 0xffffffff) {
2161 if (__predict_false(sdhci_debug > 2))
2162 slot_printf(slot, "Interrupt %#x\n", intmask);
2164 /* Handle tuning error interrupt. */
2165 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2166 slot_printf(slot, "Tuning error indicated\n");
2167 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2169 slot->curcmd->error = MMC_ERR_BADCRC;
2170 sdhci_finish_command(slot);
2173 /* Handle re-tuning interrupt. */
2174 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2175 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2176 /* Handle card presence interrupts. */
2177 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2178 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2180 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2181 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2182 SDHCI_INT_CARD_INSERT;
2183 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2184 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2185 WR4(slot, SDHCI_INT_STATUS, intmask &
2186 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2187 sdhci_handle_card_present_locked(slot, present);
2189 /* Handle command interrupts. */
2190 if (intmask & SDHCI_INT_CMD_MASK) {
2191 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2192 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2194 /* Handle data interrupts. */
2195 if (intmask & SDHCI_INT_DATA_MASK) {
2196 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2197 /* Don't call data_irq in case of errored command. */
2198 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2199 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2201 /* Handle AutoCMD12 error interrupt. */
2202 if (intmask & SDHCI_INT_ACMD12ERR) {
2203 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2204 sdhci_acmd_irq(slot);
2206 /* Handle bus power interrupt. */
2207 if (intmask & SDHCI_INT_BUS_POWER) {
2208 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2209 slot_printf(slot, "Card is consuming too much power!\n");
2211 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2212 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2213 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2214 /* The rest is unknown. */
2216 WR4(slot, SDHCI_INT_STATUS, intmask);
2217 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2219 sdhci_dumpregs(slot);
2226 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2229 struct sdhci_slot *slot = device_get_ivars(child);
2234 case MMCBR_IVAR_BUS_MODE:
2235 *result = slot->host.ios.bus_mode;
2237 case MMCBR_IVAR_BUS_WIDTH:
2238 *result = slot->host.ios.bus_width;
2240 case MMCBR_IVAR_CHIP_SELECT:
2241 *result = slot->host.ios.chip_select;
2243 case MMCBR_IVAR_CLOCK:
2244 *result = slot->host.ios.clock;
2246 case MMCBR_IVAR_F_MIN:
2247 *result = slot->host.f_min;
2249 case MMCBR_IVAR_F_MAX:
2250 *result = slot->host.f_max;
2252 case MMCBR_IVAR_HOST_OCR:
2253 *result = slot->host.host_ocr;
2255 case MMCBR_IVAR_MODE:
2256 *result = slot->host.mode;
2258 case MMCBR_IVAR_OCR:
2259 *result = slot->host.ocr;
2261 case MMCBR_IVAR_POWER_MODE:
2262 *result = slot->host.ios.power_mode;
2264 case MMCBR_IVAR_VDD:
2265 *result = slot->host.ios.vdd;
2267 case MMCBR_IVAR_RETUNE_REQ:
2268 if (slot->opt & SDHCI_TUNING_ENABLED) {
2269 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2270 *result = retune_req_reset;
2273 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2274 *result = retune_req_normal;
2278 *result = retune_req_none;
2280 case MMCBR_IVAR_VCCQ:
2281 *result = slot->host.ios.vccq;
2283 case MMCBR_IVAR_CAPS:
2284 *result = slot->host.caps;
2286 case MMCBR_IVAR_TIMING:
2287 *result = slot->host.ios.timing;
2289 case MMCBR_IVAR_MAX_DATA:
2291 * Re-tuning modes 1 and 2 restrict the maximum data length
2292 * per read/write command to 4 MiB.
2294 if (slot->opt & SDHCI_TUNING_ENABLED &&
2295 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2296 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2297 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2302 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2304 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2313 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2316 struct sdhci_slot *slot = device_get_ivars(child);
2317 uint32_t clock, max_clock;
2320 if (sdhci_debug > 1)
2321 slot_printf(slot, "%s: var=%d\n", __func__, which);
2325 case MMCBR_IVAR_BUS_MODE:
2326 slot->host.ios.bus_mode = value;
2328 case MMCBR_IVAR_BUS_WIDTH:
2329 slot->host.ios.bus_width = value;
2331 case MMCBR_IVAR_CHIP_SELECT:
2332 slot->host.ios.chip_select = value;
2334 case MMCBR_IVAR_CLOCK:
2336 max_clock = slot->max_clk;
2339 if (slot->version < SDHCI_SPEC_300) {
2340 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2347 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2351 clock = max_clock / (i + 2);
2355 slot->host.ios.clock = clock;
2357 slot->host.ios.clock = 0;
2359 case MMCBR_IVAR_MODE:
2360 slot->host.mode = value;
2362 case MMCBR_IVAR_OCR:
2363 slot->host.ocr = value;
2365 case MMCBR_IVAR_POWER_MODE:
2366 slot->host.ios.power_mode = value;
2368 case MMCBR_IVAR_VDD:
2369 slot->host.ios.vdd = value;
2371 case MMCBR_IVAR_VCCQ:
2372 slot->host.ios.vccq = value;
2374 case MMCBR_IVAR_TIMING:
2375 slot->host.ios.timing = value;
2377 case MMCBR_IVAR_CAPS:
2378 case MMCBR_IVAR_HOST_OCR:
2379 case MMCBR_IVAR_F_MIN:
2380 case MMCBR_IVAR_F_MAX:
2381 case MMCBR_IVAR_MAX_DATA:
2382 case MMCBR_IVAR_RETUNE_REQ:
2390 sdhci_start_slot(struct sdhci_slot *slot)
2392 if ((slot->devq = cam_simq_alloc(1)) == NULL) {
2396 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2397 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2398 "sdhci_slot", slot, device_get_unit(slot->bus),
2399 &slot->sim_mtx, 1, 1, slot->devq);
2401 if (slot->sim == NULL) {
2402 cam_simq_free(slot->devq);
2403 slot_printf(slot, "cannot allocate CAM SIM\n");
2407 mtx_lock(&slot->sim_mtx);
2408 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2410 "cannot register SCSI pass-through bus\n");
2411 cam_sim_free(slot->sim, FALSE);
2412 cam_simq_free(slot->devq);
2413 mtx_unlock(&slot->sim_mtx);
2417 mtx_unlock(&slot->sim_mtx);
2418 /* End CAM-specific init */
2419 slot->card_present = 0;
2420 sdhci_card_task(slot, 0);
2424 if (slot->sim != NULL) {
2425 mtx_lock(&slot->sim_mtx);
2426 xpt_bus_deregister(cam_sim_path(slot->sim));
2427 cam_sim_free(slot->sim, FALSE);
2428 mtx_unlock(&slot->sim_mtx);
2431 if (slot->devq != NULL)
2432 cam_simq_free(slot->devq);
2436 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb)
2438 struct sdhci_slot *slot;
2440 slot = cam_sim_softc(sim);
2442 sdhci_cam_request(slot, ccb);
2446 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb)
2448 struct sdhci_slot *slot;
2450 slot = cam_sim_softc(sim);
2452 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2457 mtx_assert(&slot->sim_mtx, MA_OWNED);
2459 switch (ccb->ccb_h.func_code) {
2462 struct ccb_pathinq *cpi;
2465 cpi->version_num = 1;
2466 cpi->hba_inquiry = 0;
2467 cpi->target_sprt = 0;
2468 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN;
2469 cpi->hba_eng_cnt = 0;
2470 cpi->max_target = 0;
2472 cpi->initiator_id = 1;
2473 cpi->maxio = MAXPHYS;
2474 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2475 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN);
2476 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2477 cpi->unit_number = cam_sim_unit(sim);
2478 cpi->bus_id = cam_sim_bus(sim);
2479 cpi->base_transfer_speed = 100; /* XXX WTF? */
2480 cpi->protocol = PROTO_MMCSD;
2481 cpi->protocol_version = SCSI_REV_0;
2482 cpi->transport = XPORT_MMCSD;
2483 cpi->transport_version = 0;
2485 cpi->ccb_h.status = CAM_REQ_CMP;
2488 case XPT_GET_TRAN_SETTINGS:
2490 struct ccb_trans_settings *cts = &ccb->cts;
2492 if (sdhci_debug > 1)
2493 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2495 cts->protocol = PROTO_MMCSD;
2496 cts->protocol_version = 1;
2497 cts->transport = XPORT_MMCSD;
2498 cts->transport_version = 1;
2499 cts->xport_specific.valid = 0;
2500 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2501 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2502 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2503 cts->proto_specific.mmc.host_caps = slot->host.caps;
2504 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2505 ccb->ccb_h.status = CAM_REQ_CMP;
2508 case XPT_SET_TRAN_SETTINGS:
2510 if (sdhci_debug > 1)
2511 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2512 sdhci_cam_settran_settings(slot, ccb);
2513 ccb->ccb_h.status = CAM_REQ_CMP;
2517 if (sdhci_debug > 1)
2518 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2519 ccb->ccb_h.status = CAM_REQ_CMP;
2523 * Here is the HW-dependent part of
2524 * sending the command to the underlying h/w
2525 * At some point in the future an interrupt comes.
2526 * Then the request will be marked as completed.
2528 if (__predict_false(sdhci_debug > 1))
2529 slot_printf(slot, "Got XPT_MMC_IO\n");
2530 ccb->ccb_h.status = CAM_REQ_INPROG;
2532 sdhci_cam_handle_mmcio(sim, ccb);
2537 ccb->ccb_h.status = CAM_REQ_INVALID;
2545 sdhci_cam_poll(struct cam_sim *sim)
2550 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) {
2551 int max_clock, clock, i;
2553 if (proposed_clock == 0)
2555 max_clock = slot->max_clk;
2558 if (slot->version < SDHCI_SPEC_300) {
2559 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2561 if (clock <= proposed_clock)
2566 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2568 if (clock <= proposed_clock)
2570 clock = max_clock / (i + 2);
2577 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb)
2579 struct mmc_ios *ios;
2580 struct mmc_ios *new_ios;
2581 struct ccb_trans_settings_mmc *cts;
2583 ios = &slot->host.ios;
2585 cts = &ccb->cts.proto_specific.mmc;
2586 new_ios = &cts->ios;
2588 /* Update only requested fields */
2589 if (cts->ios_valid & MMC_CLK) {
2590 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2591 slot_printf(slot, "Clock => %d\n", ios->clock);
2593 if (cts->ios_valid & MMC_VDD) {
2594 ios->vdd = new_ios->vdd;
2595 slot_printf(slot, "VDD => %d\n", ios->vdd);
2597 if (cts->ios_valid & MMC_CS) {
2598 ios->chip_select = new_ios->chip_select;
2599 slot_printf(slot, "CS => %d\n", ios->chip_select);
2601 if (cts->ios_valid & MMC_BW) {
2602 ios->bus_width = new_ios->bus_width;
2603 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2605 if (cts->ios_valid & MMC_PM) {
2606 ios->power_mode = new_ios->power_mode;
2607 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2609 if (cts->ios_valid & MMC_BT) {
2610 ios->timing = new_ios->timing;
2611 slot_printf(slot, "Timing => %d\n", ios->timing);
2613 if (cts->ios_valid & MMC_BM) {
2614 ios->bus_mode = new_ios->bus_mode;
2615 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2618 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2619 return (sdhci_cam_update_ios(slot));
2623 sdhci_cam_update_ios(struct sdhci_slot *slot)
2625 struct mmc_ios *ios = &slot->host.ios;
2627 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2628 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2630 /* Do full reset on bus power down to clear from any state. */
2631 if (ios->power_mode == power_off) {
2632 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2635 /* Configure the bus. */
2636 sdhci_set_clock(slot, ios->clock);
2637 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2638 if (ios->bus_width == bus_width_8) {
2639 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2640 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2641 } else if (ios->bus_width == bus_width_4) {
2642 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2643 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2644 } else if (ios->bus_width == bus_width_1) {
2645 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2646 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2648 panic("Invalid bus width: %d", ios->bus_width);
2650 if (ios->timing == bus_timing_hs &&
2651 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2652 slot->hostctrl |= SDHCI_CTRL_HISPD;
2654 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2655 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2656 /* Some controllers like reset after bus changes. */
2657 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2658 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2665 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb)
2667 struct ccb_mmcio *mmcio;
2669 mmcio = &ccb->mmcio;
2672 /* if (slot->req != NULL) {
2677 if (__predict_false(sdhci_debug > 1)) {
2678 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
2679 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2680 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2681 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
2683 if (mmcio->cmd.data != NULL) {
2684 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2685 panic("data->len = %d, data->flags = %d -- something is b0rked",
2686 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2693 while (slot->ccb != NULL) {
2694 sdhci_generic_intr(slot);
2702 MODULE_VERSION(sdhci, 1);