2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/callout.h>
35 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
43 #include <sys/sysctl.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/stdarg.h>
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcreg.h>
52 #include <dev/mmc/mmcbrvar.h>
54 #include <dev/sdhci/sdhci.h>
59 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
61 static int sdhci_debug;
62 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
63 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
65 u_int sdhci_quirk_clear = 0;
66 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
67 0, "Mask of quirks to clear");
68 u_int sdhci_quirk_set = 0;
69 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
70 "Mask of quirks to set");
72 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
73 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
74 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
75 #define RD_MULTI_4(slot, off, ptr, count) \
76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
78 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
79 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
80 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
81 #define WR_MULTI_4(slot, off, ptr, count) \
82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
84 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
85 static void sdhci_card_poll(void *arg);
86 static void sdhci_card_task(void *arg, int pending);
87 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
88 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
89 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
90 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
92 static void sdhci_finish_command(struct sdhci_slot *slot);
93 static void sdhci_init(struct sdhci_slot *slot);
94 static void sdhci_read_block_pio(struct sdhci_slot *slot);
95 static void sdhci_req_done(struct sdhci_slot *slot);
96 static void sdhci_req_wakeup(struct mmc_request *req);
97 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask);
98 static void sdhci_retune(void *arg);
99 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
100 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
101 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
102 struct mmc_data *data);
103 static void sdhci_start(struct sdhci_slot *slot);
104 static void sdhci_timeout(void *arg);
105 static void sdhci_start_command(struct sdhci_slot *slot,
106 struct mmc_command *cmd);
107 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
108 static void sdhci_write_block_pio(struct sdhci_slot *slot);
109 static void sdhci_transfer_pio(struct sdhci_slot *slot);
111 /* helper routines */
112 static void sdhci_dumpregs(struct sdhci_slot *slot);
113 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
115 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
117 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot);
119 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
120 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
121 #define SDHCI_LOCK_INIT(_slot) \
122 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
123 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
124 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
125 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
127 #define SDHCI_DEFAULT_MAX_FREQ 50
129 #define SDHCI_200_MAX_DIVIDER 256
130 #define SDHCI_300_MAX_DIVIDER 2046
132 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
133 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
136 * Broadcom BCM577xx Controller Constants
138 /* Maximum divider supported by the default clock source. */
139 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
140 /* Alternative clock's base frequency. */
141 #define BCM577XX_ALT_CLOCK_BASE 63000000
143 #define BCM577XX_HOST_CONTROL 0x198
144 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
145 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
146 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
147 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
150 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
154 printf("getaddr: error %d\n", error);
157 *(bus_addr_t *)arg = segs[0].ds_addr;
161 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
166 retval = printf("%s-slot%d: ",
167 device_get_nameunit(slot->bus), slot->num);
170 retval += vprintf(fmt, ap);
176 sdhci_dumpregs(struct sdhci_slot *slot)
180 "============== REGISTER DUMP ==============\n");
182 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
183 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
184 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
185 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
186 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
187 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
188 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
189 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
190 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
191 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
192 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
193 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
194 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
195 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
196 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
197 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
198 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
199 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
200 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
201 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
202 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
203 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
204 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
205 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
208 "===========================================\n");
212 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
217 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
218 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
222 /* Some controllers need this kick or reset won't work. */
223 if ((mask & SDHCI_RESET_ALL) == 0 &&
224 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
225 /* This is to force an update */
228 sdhci_set_clock(slot, clock);
231 if (mask & SDHCI_RESET_ALL) {
236 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
238 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
240 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
241 * specification. The reset bit has internal propagation delay,
242 * so a fast read after write returns 0 even if reset process is
243 * in progress. The workaround is to poll for 1 before polling
244 * for 0. In the worst case, if we miss seeing it asserted the
245 * time we spent waiting is enough to ensure the reset finishes.
248 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
256 /* Wait max 100 ms */
258 /* Controller clears the bits when it's done */
259 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
261 slot_printf(slot, "Reset 0x%x never completed.\n",
263 sdhci_dumpregs(slot);
272 sdhci_tuning_intmask(struct sdhci_slot *slot)
277 if (slot->opt & SDHCI_TUNING_ENABLED) {
278 intmask |= SDHCI_INT_TUNEERR;
279 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
280 slot->retune_mode == SDHCI_RETUNE_MODE_3)
281 intmask |= SDHCI_INT_RETUNE;
287 sdhci_init(struct sdhci_slot *slot)
290 sdhci_reset(slot, SDHCI_RESET_ALL);
292 /* Enable interrupts. */
293 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
294 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
295 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
296 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
297 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
300 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
301 !(slot->opt & SDHCI_NON_REMOVABLE)) {
302 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
305 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
306 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
310 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
319 if (clock == slot->clock)
323 /* Turn off the clock. */
324 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
325 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
326 /* If no clock requested - leave it so. */
330 /* Determine the clock base frequency */
331 clk_base = slot->max_clk;
332 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
333 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
334 BCM577XX_CTRL_CLKSEL_MASK;
337 * Select clock source appropriate for the requested frequency.
339 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
340 clk_base = BCM577XX_ALT_CLOCK_BASE;
341 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
342 BCM577XX_CTRL_CLKSEL_SHIFT);
344 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
345 BCM577XX_CTRL_CLKSEL_SHIFT);
348 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
351 /* Recalculate timeout clock frequency based on the new sd clock. */
352 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
353 slot->timeout_clk = slot->clock / 1000;
355 if (slot->version < SDHCI_SPEC_300) {
356 /* Looking for highest freq <= clock. */
358 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
363 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
366 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
367 if (clock >= clk_base)
370 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
371 if ((clk_base / div) <= clock)
378 if (bootverbose || sdhci_debug)
379 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
380 div, clock, clk_base);
382 /* Now we have got divider, set it. */
383 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
384 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
385 << SDHCI_DIVIDER_HI_SHIFT;
387 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
389 clk |= SDHCI_CLOCK_INT_EN;
390 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
391 /* Wait up to 10 ms until it stabilize. */
393 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
394 & SDHCI_CLOCK_INT_STABLE)) {
397 "Internal clock never stabilised.\n");
398 sdhci_dumpregs(slot);
404 /* Pass clock signal to the bus. */
405 clk |= SDHCI_CLOCK_CARD_EN;
406 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
410 sdhci_set_power(struct sdhci_slot *slot, u_char power)
415 if (slot->power == power)
420 /* Turn off the power. */
422 WR1(slot, SDHCI_POWER_CONTROL, pwr);
423 /* If power down requested - leave it so. */
427 switch (1 << power) {
428 case MMC_OCR_LOW_VOLTAGE:
429 pwr |= SDHCI_POWER_180;
431 case MMC_OCR_290_300:
432 case MMC_OCR_300_310:
433 pwr |= SDHCI_POWER_300;
435 case MMC_OCR_320_330:
436 case MMC_OCR_330_340:
437 pwr |= SDHCI_POWER_330;
440 WR1(slot, SDHCI_POWER_CONTROL, pwr);
442 * Turn on VDD1 power. Note that at least some Intel controllers can
443 * fail to enable bus power on the first try after transiting from D3
444 * to D0, so we give them up to 2 ms.
446 pwr |= SDHCI_POWER_ON;
447 for (i = 0; i < 20; i++) {
448 WR1(slot, SDHCI_POWER_CONTROL, pwr);
449 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
453 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
454 slot_printf(slot, "Bus power failed to enable");
456 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
457 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
459 WR1(slot, SDHCI_POWER_CONTROL, pwr);
465 sdhci_read_block_pio(struct sdhci_slot *slot)
471 buffer = slot->curcmd->data->data;
472 buffer += slot->offset;
473 /* Transfer one block at a time. */
474 left = min(512, slot->curcmd->data->len - slot->offset);
475 slot->offset += left;
477 /* If we are too fast, broken controllers return zeroes. */
478 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
480 /* Handle unaligned and aligned buffer cases. */
481 if ((intptr_t)buffer & 3) {
483 data = RD4(slot, SDHCI_BUFFER);
485 buffer[1] = (data >> 8);
486 buffer[2] = (data >> 16);
487 buffer[3] = (data >> 24);
492 RD_MULTI_4(slot, SDHCI_BUFFER,
493 (uint32_t *)buffer, left >> 2);
496 /* Handle uneven size case. */
498 data = RD4(slot, SDHCI_BUFFER);
508 sdhci_write_block_pio(struct sdhci_slot *slot)
514 buffer = slot->curcmd->data->data;
515 buffer += slot->offset;
516 /* Transfer one block at a time. */
517 left = min(512, slot->curcmd->data->len - slot->offset);
518 slot->offset += left;
520 /* Handle unaligned and aligned buffer cases. */
521 if ((intptr_t)buffer & 3) {
529 WR4(slot, SDHCI_BUFFER, data);
532 WR_MULTI_4(slot, SDHCI_BUFFER,
533 (uint32_t *)buffer, left >> 2);
536 /* Handle uneven size case. */
543 WR4(slot, SDHCI_BUFFER, data);
548 sdhci_transfer_pio(struct sdhci_slot *slot)
551 /* Read as many blocks as possible. */
552 if (slot->curcmd->data->flags & MMC_DATA_READ) {
553 while (RD4(slot, SDHCI_PRESENT_STATE) &
554 SDHCI_DATA_AVAILABLE) {
555 sdhci_read_block_pio(slot);
556 if (slot->offset >= slot->curcmd->data->len)
560 while (RD4(slot, SDHCI_PRESENT_STATE) &
561 SDHCI_SPACE_AVAILABLE) {
562 sdhci_write_block_pio(slot);
563 if (slot->offset >= slot->curcmd->data->len)
570 sdhci_card_task(void *arg, int pending __unused)
572 struct sdhci_slot *slot = arg;
576 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
577 if (slot->dev == NULL) {
578 /* If card is present - attach mmc bus. */
579 if (bootverbose || sdhci_debug)
580 slot_printf(slot, "Card inserted\n");
581 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
584 device_set_ivars(d, slot);
585 (void)device_probe_and_attach(d);
590 if (slot->dev != NULL) {
591 /* If no card present - detach mmc bus. */
592 if (bootverbose || sdhci_debug)
593 slot_printf(slot, "Card removed\n");
596 slot->intmask &= ~sdhci_tuning_intmask(slot);
597 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
598 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
599 slot->opt &= ~SDHCI_TUNING_ENABLED;
601 callout_drain(&slot->retune_callout);
602 device_delete_child(slot->bus, d);
609 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
614 * If there was no card and now there is one, schedule the task to
615 * create the child device after a short delay. The delay is to
616 * debounce the card insert (sometimes the card detect pin stabilizes
617 * before the other pins have made good contact).
619 * If there was a card present and now it's gone, immediately schedule
620 * the task to delete the child device. No debouncing -- gone is gone,
621 * because once power is removed, a full card re-init is needed, and
622 * that happens by deleting and recreating the child device.
624 was_present = slot->dev != NULL;
625 if (!was_present && is_present) {
626 taskqueue_enqueue_timeout(taskqueue_swi_giant,
627 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
628 } else if (was_present && !is_present) {
629 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
634 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
638 sdhci_handle_card_present_locked(slot, is_present);
643 sdhci_card_poll(void *arg)
645 struct sdhci_slot *slot = arg;
647 sdhci_handle_card_present(slot,
648 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
649 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
650 sdhci_card_poll, slot);
654 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
656 kobjop_desc_t kobj_desc;
657 kobj_method_t *kobj_method;
658 uint32_t caps, caps2, freq, host_caps;
661 SDHCI_LOCK_INIT(slot);
665 /* Allocate DMA tag. */
666 err = bus_dma_tag_create(bus_get_dma_tag(dev),
667 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
668 BUS_SPACE_MAXADDR, NULL, NULL,
669 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
670 BUS_DMA_ALLOCNOW, NULL, NULL,
673 device_printf(dev, "Can't create DMA tag\n");
674 SDHCI_LOCK_DESTROY(slot);
677 /* Allocate DMA memory. */
678 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
679 BUS_DMA_NOWAIT, &slot->dmamap);
681 device_printf(dev, "Can't alloc DMA memory\n");
682 bus_dma_tag_destroy(slot->dmatag);
683 SDHCI_LOCK_DESTROY(slot);
686 /* Map the memory. */
687 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
688 (void *)slot->dmamem, DMA_BLOCK_SIZE,
689 sdhci_getaddr, &slot->paddr, 0);
690 if (err != 0 || slot->paddr == 0) {
691 device_printf(dev, "Can't load DMA memory\n");
692 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
693 bus_dma_tag_destroy(slot->dmatag);
694 SDHCI_LOCK_DESTROY(slot);
701 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
702 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
703 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
707 caps = RD4(slot, SDHCI_CAPABILITIES);
708 if (slot->version >= SDHCI_SPEC_300)
709 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
713 if (slot->version >= SDHCI_SPEC_300) {
714 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
715 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
717 "Driver doesn't support shared bus slots\n");
718 bus_dmamap_unload(slot->dmatag, slot->dmamap);
719 bus_dmamem_free(slot->dmatag, slot->dmamem,
721 bus_dma_tag_destroy(slot->dmatag);
722 SDHCI_LOCK_DESTROY(slot);
724 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
725 SDHCI_SLOTTYPE_EMBEDDED) {
726 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
729 /* Calculate base clock frequency. */
730 if (slot->version >= SDHCI_SPEC_300)
731 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
732 SDHCI_CLOCK_BASE_SHIFT;
734 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
735 SDHCI_CLOCK_BASE_SHIFT;
737 slot->max_clk = freq * 1000000;
739 * If the frequency wasn't in the capabilities and the hardware driver
740 * hasn't already set max_clk we're probably not going to work right
741 * with an assumption, so complain about it.
743 if (slot->max_clk == 0) {
744 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
745 device_printf(dev, "Hardware doesn't specify base clock "
746 "frequency, using %dMHz as default.\n",
747 SDHCI_DEFAULT_MAX_FREQ);
749 /* Calculate/set timeout clock frequency. */
750 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
751 slot->timeout_clk = slot->max_clk / 1000;
752 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
753 slot->timeout_clk = 1000;
755 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
756 SDHCI_TIMEOUT_CLK_SHIFT;
757 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
758 slot->timeout_clk *= 1000;
761 * If the frequency wasn't in the capabilities and the hardware driver
762 * hasn't already set timeout_clk we'll probably work okay using the
763 * max timeout, but still mention it.
765 if (slot->timeout_clk == 0) {
766 device_printf(dev, "Hardware doesn't specify timeout clock "
767 "frequency, setting BROKEN_TIMEOUT quirk.\n");
768 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
771 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
772 slot->host.f_max = slot->max_clk;
773 slot->host.host_ocr = 0;
774 if (caps & SDHCI_CAN_VDD_330)
775 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
776 if (caps & SDHCI_CAN_VDD_300)
777 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
778 /* 1.8V VDD is not supposed to be used for removable cards. */
779 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
780 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
781 if (slot->host.host_ocr == 0) {
782 device_printf(dev, "Hardware doesn't report any "
783 "support voltages.\n");
786 host_caps = MMC_CAP_4_BIT_DATA;
787 if (caps & SDHCI_CAN_DO_8BITBUS)
788 host_caps |= MMC_CAP_8_BIT_DATA;
789 if (caps & SDHCI_CAN_DO_HISPD)
790 host_caps |= MMC_CAP_HSPEED;
791 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
792 host_caps |= MMC_CAP_BOOT_NOACC;
793 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
794 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
796 /* Determine supported UHS-I and eMMC modes. */
797 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
798 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
799 if (caps2 & SDHCI_CAN_SDR104) {
800 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
801 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
802 host_caps |= MMC_CAP_MMC_HS200;
803 } else if (caps2 & SDHCI_CAN_SDR50)
804 host_caps |= MMC_CAP_UHS_SDR50;
805 if (caps2 & SDHCI_CAN_DDR50 &&
806 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
807 host_caps |= MMC_CAP_UHS_DDR50;
808 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
809 host_caps |= MMC_CAP_MMC_DDR52;
810 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
811 caps2 & SDHCI_CAN_MMC_HS400)
812 host_caps |= MMC_CAP_MMC_HS400;
815 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
816 * default NULL implementation.
818 kobj_desc = &sdhci_set_uhs_timing_desc;
819 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
821 if (kobj_method == &kobj_desc->deflt)
822 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
823 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
824 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
826 #define SDHCI_CAP_MODES_TUNING(caps2) \
827 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
828 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
832 * Disable UHS-I and eMMC modes that require (re-)tuning if either
833 * the tune or re-tune method is the default NULL implementation.
835 kobj_desc = &mmcbr_tune_desc;
836 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
838 if (kobj_method == &kobj_desc->deflt)
840 kobj_desc = &mmcbr_retune_desc;
841 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
843 if (kobj_method == &kobj_desc->deflt) {
845 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
848 /* Allocate tuning structures and determine tuning parameters. */
849 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
850 slot->opt |= SDHCI_TUNING_SUPPORTED;
851 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
853 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
855 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
857 if (caps2 & SDHCI_TUNE_SDR50)
858 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
859 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
860 SDHCI_RETUNE_MODES_SHIFT;
861 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
862 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
863 SDHCI_RETUNE_CNT_SHIFT;
864 if (slot->retune_count > 0xb) {
865 device_printf(dev, "Unknown re-tuning count "
866 "%x, using 1 sec\n", slot->retune_count);
867 slot->retune_count = 1;
868 } else if (slot->retune_count != 0)
870 1 << (slot->retune_count - 1);
874 #undef SDHCI_CAP_MODES_TUNING
876 /* Determine supported VCCQ signaling levels. */
877 host_caps |= MMC_CAP_SIGNALING_330;
878 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
879 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
880 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
881 MMC_CAP_MMC_HS400_180))
882 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
885 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
886 * default NULL implementation. Disable 1.2 V support if it's the
887 * generic SDHCI implementation.
889 kobj_desc = &mmcbr_switch_vccq_desc;
890 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
892 if (kobj_method == &kobj_desc->deflt)
893 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
894 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
895 host_caps &= ~MMC_CAP_SIGNALING_120;
897 /* Determine supported driver types (type B is always mandatory). */
898 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
899 host_caps |= MMC_CAP_DRIVER_TYPE_A;
900 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
901 host_caps |= MMC_CAP_DRIVER_TYPE_C;
902 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
903 host_caps |= MMC_CAP_DRIVER_TYPE_D;
904 slot->host.caps = host_caps;
906 /* Decide if we have usable DMA. */
907 if (caps & SDHCI_CAN_DO_DMA)
908 slot->opt |= SDHCI_HAVE_DMA;
910 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
911 slot->opt &= ~SDHCI_HAVE_DMA;
912 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
913 slot->opt |= SDHCI_HAVE_DMA;
914 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
915 slot->opt |= SDHCI_NON_REMOVABLE;
918 * Use platform-provided transfer backend
919 * with PIO as a fallback mechanism
921 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
922 slot->opt &= ~SDHCI_HAVE_DMA;
924 if (bootverbose || sdhci_debug) {
926 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
927 slot->max_clk / 1000000,
928 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
929 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
930 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
931 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
932 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
933 ((caps & SDHCI_CAN_VDD_180) &&
934 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
935 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
936 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
937 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
938 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
939 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
940 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
941 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
942 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
944 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
945 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
946 slot_printf(slot, "eMMC:%s%s%s%s\n",
947 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
948 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
949 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
951 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
952 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
954 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
955 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
956 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
957 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
958 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
959 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
960 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
961 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
962 if (slot->opt & SDHCI_TUNING_SUPPORTED)
963 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
964 slot->retune_count, slot->retune_mode + 1);
965 sdhci_dumpregs(slot);
969 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
970 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
971 "timeout", CTLFLAG_RW, &slot->timeout, 0,
972 "Maximum timeout for SDHCI transfers (in secs)");
973 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
974 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
975 sdhci_card_task, slot);
976 callout_init(&slot->card_poll_callout, 1);
977 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
978 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
980 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
981 !(slot->opt & SDHCI_NON_REMOVABLE)) {
982 callout_reset(&slot->card_poll_callout,
983 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
992 sdhci_start_slot(struct sdhci_slot *slot)
995 sdhci_card_task(slot, 0);
999 sdhci_cleanup_slot(struct sdhci_slot *slot)
1003 callout_drain(&slot->timeout_callout);
1004 callout_drain(&slot->card_poll_callout);
1005 callout_drain(&slot->retune_callout);
1006 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1007 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1014 device_delete_child(slot->bus, d);
1017 sdhci_reset(slot, SDHCI_RESET_ALL);
1019 bus_dmamap_unload(slot->dmatag, slot->dmamap);
1020 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
1021 bus_dma_tag_destroy(slot->dmatag);
1022 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1023 free(slot->tune_req, M_DEVBUF);
1024 free(slot->tune_cmd, M_DEVBUF);
1025 free(slot->tune_data, M_DEVBUF);
1028 SDHCI_LOCK_DESTROY(slot);
1034 sdhci_generic_suspend(struct sdhci_slot *slot)
1038 * We expect the MMC layer to issue initial tuning after resume.
1039 * Otherwise, we'd need to indicate re-tuning including circuit reset
1040 * being required at least for re-tuning modes 1 and 2 ourselves.
1042 callout_drain(&slot->retune_callout);
1044 slot->opt &= ~SDHCI_TUNING_ENABLED;
1045 sdhci_reset(slot, SDHCI_RESET_ALL);
1052 sdhci_generic_resume(struct sdhci_slot *slot)
1063 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1066 if (slot->version >= SDHCI_SPEC_300)
1067 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1069 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1073 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1076 if (slot->opt & SDHCI_NON_REMOVABLE)
1079 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1083 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1085 struct mmc_ios *ios;
1088 if (slot->version < SDHCI_SPEC_300)
1091 SDHCI_ASSERT_LOCKED(slot);
1092 ios = &slot->host.ios;
1093 sdhci_set_clock(slot, 0);
1094 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1095 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1096 if (ios->clock > SD_SDR50_MAX) {
1097 if (ios->timing == bus_timing_mmc_hs400 ||
1098 ios->timing == bus_timing_mmc_hs400es)
1099 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1101 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1103 else if (ios->clock > SD_SDR25_MAX)
1104 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1105 else if (ios->clock > SD_SDR12_MAX) {
1106 if (ios->timing == bus_timing_uhs_ddr50 ||
1107 ios->timing == bus_timing_mmc_ddr52)
1108 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1110 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1111 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1112 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1113 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1114 sdhci_set_clock(slot, ios->clock);
1118 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1120 struct sdhci_slot *slot = device_get_ivars(reqdev);
1121 struct mmc_ios *ios = &slot->host.ios;
1124 /* Do full reset on bus power down to clear from any state. */
1125 if (ios->power_mode == power_off) {
1126 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1129 /* Configure the bus. */
1130 sdhci_set_clock(slot, ios->clock);
1131 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1132 if (ios->bus_width == bus_width_8) {
1133 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1134 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1135 } else if (ios->bus_width == bus_width_4) {
1136 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1137 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1138 } else if (ios->bus_width == bus_width_1) {
1139 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1140 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1142 panic("Invalid bus width: %d", ios->bus_width);
1144 if (ios->clock > SD_SDR12_MAX &&
1145 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1146 slot->hostctrl |= SDHCI_CTRL_HISPD;
1148 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1149 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1150 SDHCI_SET_UHS_TIMING(brdev, slot);
1151 /* Some controllers like reset after bus changes. */
1152 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1153 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1160 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1162 struct sdhci_slot *slot = device_get_ivars(reqdev);
1167 if (slot->version < SDHCI_SPEC_300)
1171 vccq = slot->host.ios.vccq;
1173 sdhci_set_clock(slot, 0);
1174 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1177 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1179 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1180 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1182 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1183 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1188 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1192 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1194 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1195 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1197 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1198 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1204 "Attempt to set unsupported signaling voltage\n");
1209 sdhci_set_clock(slot, slot->host.ios.clock);
1215 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1217 struct sdhci_slot *slot = device_get_ivars(reqdev);
1218 struct mmc_ios *ios = &slot->host.ios;
1219 struct mmc_command *tune_cmd;
1220 struct mmc_data *tune_data;
1224 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1227 slot->retune_ticks = slot->retune_count * hz;
1228 opcode = MMC_SEND_TUNING_BLOCK;
1230 switch (ios->timing) {
1231 case bus_timing_mmc_hs400:
1232 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1235 case bus_timing_mmc_hs200:
1237 * In HS400 mode, controllers use the data strobe line to
1238 * latch data from the devices so periodic re-tuning isn't
1239 * expected to be required.
1242 slot->retune_ticks = 0;
1243 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1245 case bus_timing_uhs_ddr50:
1246 case bus_timing_uhs_sdr104:
1248 case bus_timing_uhs_sdr50:
1249 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1257 tune_cmd = slot->tune_cmd;
1258 memset(tune_cmd, 0, sizeof(*tune_cmd));
1259 tune_cmd->opcode = opcode;
1260 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1261 tune_data = tune_cmd->data = slot->tune_data;
1262 memset(tune_data, 0, sizeof(*tune_data));
1263 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1264 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1266 tune_data->flags = MMC_DATA_READ;
1267 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1269 slot->opt &= ~SDHCI_TUNING_ENABLED;
1270 err = sdhci_exec_tuning(slot, true);
1272 slot->opt |= SDHCI_TUNING_ENABLED;
1273 slot->intmask |= sdhci_tuning_intmask(slot);
1274 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1275 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1276 if (slot->retune_ticks) {
1277 callout_reset(&slot->retune_callout, slot->retune_ticks,
1278 sdhci_retune, slot);
1286 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1288 struct sdhci_slot *slot = device_get_ivars(reqdev);
1291 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1294 /* HS400 must be tuned in HS200 mode. */
1295 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1299 err = sdhci_exec_tuning(slot, reset);
1301 * There are two ways sdhci_exec_tuning() can fail:
1302 * EBUSY should not actually happen when requests are only issued
1303 * with the host properly acquired, and
1304 * EIO re-tuning failed (but it did work initially).
1306 * In both cases, we should retry at later point if periodic re-tuning
1307 * is enabled. Note that due to slot->retune_req not being cleared in
1308 * these failure cases, the MMC layer should trigger another attempt at
1309 * re-tuning with the next request anyway, though.
1311 if (slot->retune_ticks) {
1312 callout_reset(&slot->retune_callout, slot->retune_ticks,
1313 sdhci_retune, slot);
1320 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1322 struct mmc_request *tune_req;
1323 struct mmc_command *tune_cmd;
1329 SDHCI_ASSERT_LOCKED(slot);
1330 if (slot->req != NULL)
1333 /* Tuning doesn't work with DMA enabled. */
1335 slot->opt = opt & ~SDHCI_HAVE_DMA;
1338 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1339 * kind of interrupt we receive in response to a tuning request.
1341 intmask = slot->intmask;
1342 slot->intmask = SDHCI_INT_DATA_AVAIL;
1343 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1344 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1346 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1348 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1350 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1351 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1353 tune_req = slot->tune_req;
1354 tune_cmd = slot->tune_cmd;
1355 for (i = 0; i < MMC_TUNING_MAX; i++) {
1356 memset(tune_req, 0, sizeof(*tune_req));
1357 tune_req->cmd = tune_cmd;
1358 tune_req->done = sdhci_req_wakeup;
1359 tune_req->done_data = slot;
1360 slot->req = tune_req;
1363 while (!(tune_req->flags & MMC_REQ_DONE))
1364 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1365 if (!(tune_req->flags & MMC_TUNE_DONE))
1367 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1368 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1370 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1375 * Restore DMA usage and interrupts.
1376 * Note that the interrupt aggregation code might have cleared
1377 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1378 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1379 * doesn't lose these.
1382 slot->intmask = intmask;
1383 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1384 SDHCI_INT_RESPONSE);
1385 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1387 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1388 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1389 slot->retune_req = 0;
1393 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1394 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1395 SDHCI_CTRL2_SAMPLING_CLOCK));
1396 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1401 sdhci_retune(void *arg)
1403 struct sdhci_slot *slot = arg;
1405 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1409 sdhci_req_done(struct sdhci_slot *slot)
1411 struct mmc_request *req;
1413 if (slot->req != NULL && slot->curcmd != NULL) {
1414 callout_stop(&slot->timeout_callout);
1417 slot->curcmd = NULL;
1423 sdhci_req_wakeup(struct mmc_request *req)
1425 struct sdhci_slot *slot;
1427 slot = req->done_data;
1428 req->flags |= MMC_REQ_DONE;
1433 sdhci_timeout(void *arg)
1435 struct sdhci_slot *slot = arg;
1437 if (slot->curcmd != NULL) {
1438 slot_printf(slot, "Controller timeout\n");
1439 sdhci_dumpregs(slot);
1440 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1441 slot->curcmd->error = MMC_ERR_TIMEOUT;
1442 sdhci_req_done(slot);
1444 slot_printf(slot, "Spurious timeout - no active command\n");
1449 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
1456 mode = SDHCI_TRNS_BLK_CNT_EN;
1457 if (data->len > 512) {
1458 mode |= SDHCI_TRNS_MULTI;
1459 if (__predict_true(slot->req->stop != NULL))
1460 mode |= SDHCI_TRNS_ACMD12;
1462 if (data->flags & MMC_DATA_READ)
1463 mode |= SDHCI_TRNS_READ;
1464 if (slot->flags & SDHCI_USE_DMA)
1465 mode |= SDHCI_TRNS_DMA;
1467 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1471 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1479 cmd->error = MMC_ERR_NONE;
1481 /* This flags combination is not supported by controller. */
1482 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1483 slot_printf(slot, "Unsupported response type!\n");
1484 cmd->error = MMC_ERR_FAILED;
1485 sdhci_req_done(slot);
1490 * Do not issue command if there is no card, clock or power.
1491 * Controller will not detect timeout without clock active.
1493 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1496 cmd->error = MMC_ERR_FAILED;
1497 sdhci_req_done(slot);
1500 /* Always wait for free CMD bus. */
1501 mask = SDHCI_CMD_INHIBIT;
1502 /* Wait for free DAT if we have data or busy signal. */
1503 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
1504 mask |= SDHCI_DAT_INHIBIT;
1506 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1507 * that these latter are also special in that SDHCI_CMD_DATA should
1508 * be set below but no actual data is ever read from the controller.
1510 if (cmd == slot->req->stop ||
1511 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1512 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1513 mask &= ~SDHCI_DAT_INHIBIT;
1515 * Wait for bus no more then 250 ms. Typically there will be no wait
1516 * here at all, but when writing a crash dump we may be bypassing the
1517 * host platform's interrupt handler, and in some cases that handler
1518 * may be working around hardware quirks such as not respecting r1b
1519 * busy indications. In those cases, this wait-loop serves the purpose
1520 * of waiting for the prior command and data transfers to be done, and
1521 * SD cards are allowed to take up to 250ms for write and erase ops.
1522 * (It's usually more like 20-30ms in the real world.)
1525 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1527 slot_printf(slot, "Controller never released "
1528 "inhibit bit(s).\n");
1529 sdhci_dumpregs(slot);
1530 cmd->error = MMC_ERR_FAILED;
1531 sdhci_req_done(slot);
1538 /* Prepare command flags. */
1539 if (!(cmd->flags & MMC_RSP_PRESENT))
1540 flags = SDHCI_CMD_RESP_NONE;
1541 else if (cmd->flags & MMC_RSP_136)
1542 flags = SDHCI_CMD_RESP_LONG;
1543 else if (cmd->flags & MMC_RSP_BUSY)
1544 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1546 flags = SDHCI_CMD_RESP_SHORT;
1547 if (cmd->flags & MMC_RSP_CRC)
1548 flags |= SDHCI_CMD_CRC;
1549 if (cmd->flags & MMC_RSP_OPCODE)
1550 flags |= SDHCI_CMD_INDEX;
1552 flags |= SDHCI_CMD_DATA;
1553 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1554 flags |= SDHCI_CMD_TYPE_ABORT;
1556 sdhci_start_data(slot, cmd->data);
1558 * Interrupt aggregation: To reduce total number of interrupts
1559 * group response interrupt with data interrupt when possible.
1560 * If there going to be data interrupt, mask response one.
1562 if (slot->data_done == 0) {
1563 WR4(slot, SDHCI_SIGNAL_ENABLE,
1564 slot->intmask &= ~SDHCI_INT_RESPONSE);
1566 /* Set command argument. */
1567 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1568 /* Set data transfer mode. */
1569 sdhci_set_transfer_mode(slot, cmd->data);
1570 /* Start command. */
1571 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1572 /* Start timeout callout. */
1573 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1574 sdhci_timeout, slot);
1578 sdhci_finish_command(struct sdhci_slot *slot)
1586 * Interrupt aggregation: Restore command interrupt.
1587 * Main restore point for the case when command interrupt
1590 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1591 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1592 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1593 SDHCI_INT_RESPONSE);
1594 /* In case of error - reset host and return. */
1595 if (slot->curcmd->error) {
1596 if (slot->curcmd->error == MMC_ERR_BADCRC)
1597 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1598 sdhci_reset(slot, SDHCI_RESET_CMD);
1599 sdhci_reset(slot, SDHCI_RESET_DATA);
1603 /* If command has response - fetch it. */
1604 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1605 if (slot->curcmd->flags & MMC_RSP_136) {
1606 /* CRC is stripped so we need one byte shift. */
1608 for (i = 0; i < 4; i++) {
1609 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1611 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1612 slot->curcmd->resp[3 - i] = val;
1614 slot->curcmd->resp[3 - i] =
1620 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1622 /* If data ready - finish. */
1623 if (slot->data_done)
1628 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1630 uint32_t target_timeout, current_timeout;
1633 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1634 slot->data_done = 1;
1638 slot->data_done = 0;
1640 /* Calculate and set data timeout.*/
1641 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1642 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1645 target_timeout = 1000000;
1647 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1648 while (current_timeout < target_timeout && div < 0xE) {
1650 current_timeout <<= 1;
1652 /* Compensate for an off-by-one error in the CaFe chip.*/
1654 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1658 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1663 /* Use DMA if possible. */
1664 if ((slot->opt & SDHCI_HAVE_DMA))
1665 slot->flags |= SDHCI_USE_DMA;
1666 /* If data is small, broken DMA may return zeroes instead of data, */
1667 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1669 slot->flags &= ~SDHCI_USE_DMA;
1670 /* Some controllers require even block sizes. */
1671 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1672 ((data->len) & 0x3))
1673 slot->flags &= ~SDHCI_USE_DMA;
1674 /* Load DMA buffer. */
1675 if (slot->flags & SDHCI_USE_DMA) {
1676 if (data->flags & MMC_DATA_READ)
1677 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1678 BUS_DMASYNC_PREREAD);
1680 memcpy(slot->dmamem, data->data,
1681 (data->len < DMA_BLOCK_SIZE) ?
1682 data->len : DMA_BLOCK_SIZE);
1683 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1684 BUS_DMASYNC_PREWRITE);
1686 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1687 /* Interrupt aggregation: Mask border interrupt
1688 * for the last page and unmask else. */
1689 if (data->len == DMA_BLOCK_SIZE)
1690 slot->intmask &= ~SDHCI_INT_DMA_END;
1692 slot->intmask |= SDHCI_INT_DMA_END;
1693 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1695 /* Current data offset for both PIO and DMA. */
1697 /* Set block size and request IRQ on 4K border. */
1698 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
1699 (data->len < 512) ? data->len : 512));
1700 /* Set block count. */
1701 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1705 sdhci_finish_data(struct sdhci_slot *slot)
1707 struct mmc_data *data = slot->curcmd->data;
1710 /* Interrupt aggregation: Restore command interrupt.
1711 * Auxiliary restore point for the case when data interrupt
1712 * happened first. */
1713 if (!slot->cmd_done) {
1714 WR4(slot, SDHCI_SIGNAL_ENABLE,
1715 slot->intmask |= SDHCI_INT_RESPONSE);
1717 /* Unload rest of data from DMA buffer. */
1718 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
1719 if (data->flags & MMC_DATA_READ) {
1720 left = data->len - slot->offset;
1721 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1722 BUS_DMASYNC_POSTREAD);
1723 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1724 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1726 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1727 BUS_DMASYNC_POSTWRITE);
1729 slot->data_done = 1;
1730 /* If there was error - reset the host. */
1731 if (slot->curcmd->error) {
1732 if (slot->curcmd->error == MMC_ERR_BADCRC)
1733 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1734 sdhci_reset(slot, SDHCI_RESET_CMD);
1735 sdhci_reset(slot, SDHCI_RESET_DATA);
1739 /* If we already have command response - finish. */
1745 sdhci_start(struct sdhci_slot *slot)
1747 struct mmc_request *req;
1753 if (!(slot->flags & CMD_STARTED)) {
1754 slot->flags |= CMD_STARTED;
1755 sdhci_start_command(slot, req->cmd);
1758 /* We don't need this until using Auto-CMD12 feature
1759 if (!(slot->flags & STOP_STARTED) && req->stop) {
1760 slot->flags |= STOP_STARTED;
1761 sdhci_start_command(slot, req->stop);
1765 if (__predict_false(sdhci_debug > 1))
1766 slot_printf(slot, "result: %d\n", req->cmd->error);
1767 if (!req->cmd->error &&
1768 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1769 sdhci_reset(slot, SDHCI_RESET_CMD);
1770 sdhci_reset(slot, SDHCI_RESET_DATA);
1773 sdhci_req_done(slot);
1777 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1778 struct mmc_request *req)
1780 struct sdhci_slot *slot = device_get_ivars(reqdev);
1783 if (slot->req != NULL) {
1787 if (__predict_false(sdhci_debug > 1)) {
1789 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1790 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1791 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1792 (req->cmd->data)?req->cmd->data->flags:0);
1799 while (slot->req != NULL) {
1800 sdhci_generic_intr(slot);
1808 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1810 struct sdhci_slot *slot = device_get_ivars(reqdev);
1814 val = RD4(slot, SDHCI_PRESENT_STATE);
1816 return (!(val & SDHCI_WRITE_PROTECT));
1820 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1822 struct sdhci_slot *slot = device_get_ivars(reqdev);
1826 while (slot->bus_busy)
1827 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1830 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1836 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1838 struct sdhci_slot *slot = device_get_ivars(reqdev);
1841 /* Deactivate led. */
1842 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1850 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1853 if (!slot->curcmd) {
1854 slot_printf(slot, "Got command interrupt 0x%08x, but "
1855 "there is no active command.\n", intmask);
1856 sdhci_dumpregs(slot);
1859 if (intmask & SDHCI_INT_TIMEOUT)
1860 slot->curcmd->error = MMC_ERR_TIMEOUT;
1861 else if (intmask & SDHCI_INT_CRC)
1862 slot->curcmd->error = MMC_ERR_BADCRC;
1863 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1864 slot->curcmd->error = MMC_ERR_FIFO;
1866 sdhci_finish_command(slot);
1870 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1872 struct mmc_data *data;
1875 if (!slot->curcmd) {
1876 slot_printf(slot, "Got data interrupt 0x%08x, but "
1877 "there is no active command.\n", intmask);
1878 sdhci_dumpregs(slot);
1881 if (slot->curcmd->data == NULL &&
1882 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1883 slot_printf(slot, "Got data interrupt 0x%08x, but "
1884 "there is no active data operation.\n",
1886 sdhci_dumpregs(slot);
1889 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1890 slot->curcmd->error = MMC_ERR_TIMEOUT;
1891 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1892 slot->curcmd->error = MMC_ERR_BADCRC;
1893 if (slot->curcmd->data == NULL &&
1894 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1895 SDHCI_INT_DMA_END))) {
1896 slot_printf(slot, "Got data interrupt 0x%08x, but "
1897 "there is busy-only command.\n", intmask);
1898 sdhci_dumpregs(slot);
1899 slot->curcmd->error = MMC_ERR_INVALID;
1901 if (slot->curcmd->error) {
1902 /* No need to continue after any error. */
1906 /* Handle tuning completion interrupt. */
1907 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
1908 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
1909 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
1910 slot->req->flags |= MMC_TUNE_DONE;
1911 sdhci_finish_command(slot);
1912 sdhci_finish_data(slot);
1915 /* Handle PIO interrupt. */
1916 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1917 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1918 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1919 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
1921 slot->flags |= PLATFORM_DATA_STARTED;
1923 sdhci_transfer_pio(slot);
1925 /* Handle DMA border. */
1926 if (intmask & SDHCI_INT_DMA_END) {
1927 data = slot->curcmd->data;
1929 /* Unload DMA buffer ... */
1930 left = data->len - slot->offset;
1931 if (data->flags & MMC_DATA_READ) {
1932 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1933 BUS_DMASYNC_POSTREAD);
1934 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1935 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1937 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1938 BUS_DMASYNC_POSTWRITE);
1940 /* ... and reload it again. */
1941 slot->offset += DMA_BLOCK_SIZE;
1942 left = data->len - slot->offset;
1943 if (data->flags & MMC_DATA_READ) {
1944 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1945 BUS_DMASYNC_PREREAD);
1947 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1948 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
1949 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1950 BUS_DMASYNC_PREWRITE);
1952 /* Interrupt aggregation: Mask border interrupt
1953 * for the last page. */
1954 if (left == DMA_BLOCK_SIZE) {
1955 slot->intmask &= ~SDHCI_INT_DMA_END;
1956 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1959 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1961 /* We have got all data. */
1962 if (intmask & SDHCI_INT_DATA_END) {
1963 if (slot->flags & PLATFORM_DATA_STARTED) {
1964 slot->flags &= ~PLATFORM_DATA_STARTED;
1965 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1967 sdhci_finish_data(slot);
1970 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1971 if (slot->flags & PLATFORM_DATA_STARTED) {
1972 slot->flags &= ~PLATFORM_DATA_STARTED;
1973 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1975 sdhci_finish_data(slot);
1980 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
1983 if (!slot->curcmd) {
1984 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1985 "there is no active command.\n", acmd_err);
1986 sdhci_dumpregs(slot);
1989 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
1990 sdhci_reset(slot, SDHCI_RESET_CMD);
1994 sdhci_generic_intr(struct sdhci_slot *slot)
1996 uint32_t intmask, present;
2000 /* Read slot interrupt status. */
2001 intmask = RD4(slot, SDHCI_INT_STATUS);
2002 if (intmask == 0 || intmask == 0xffffffff) {
2006 if (__predict_false(sdhci_debug > 2))
2007 slot_printf(slot, "Interrupt %#x\n", intmask);
2009 /* Handle tuning error interrupt. */
2010 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2011 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2012 slot_printf(slot, "Tuning error indicated\n");
2013 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2015 slot->curcmd->error = MMC_ERR_BADCRC;
2016 sdhci_finish_command(slot);
2019 /* Handle re-tuning interrupt. */
2020 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2021 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2022 /* Handle card presence interrupts. */
2023 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2024 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2026 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2027 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2028 SDHCI_INT_CARD_INSERT;
2029 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2030 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2031 WR4(slot, SDHCI_INT_STATUS, intmask &
2032 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2033 sdhci_handle_card_present_locked(slot, present);
2035 /* Handle command interrupts. */
2036 if (intmask & SDHCI_INT_CMD_MASK) {
2037 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2038 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2040 /* Handle data interrupts. */
2041 if (intmask & SDHCI_INT_DATA_MASK) {
2042 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2043 /* Don't call data_irq in case of errored command. */
2044 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2045 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2047 /* Handle AutoCMD12 error interrupt. */
2048 if (intmask & SDHCI_INT_ACMD12ERR) {
2049 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2050 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2051 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2052 sdhci_acmd_irq(slot, val16);
2054 /* Handle bus power interrupt. */
2055 if (intmask & SDHCI_INT_BUS_POWER) {
2056 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2057 slot_printf(slot, "Card is consuming too much power!\n");
2059 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2060 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2061 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2062 /* The rest is unknown. */
2064 WR4(slot, SDHCI_INT_STATUS, intmask);
2065 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2067 sdhci_dumpregs(slot);
2074 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2077 struct sdhci_slot *slot = device_get_ivars(child);
2082 case MMCBR_IVAR_BUS_MODE:
2083 *result = slot->host.ios.bus_mode;
2085 case MMCBR_IVAR_BUS_WIDTH:
2086 *result = slot->host.ios.bus_width;
2088 case MMCBR_IVAR_CHIP_SELECT:
2089 *result = slot->host.ios.chip_select;
2091 case MMCBR_IVAR_CLOCK:
2092 *result = slot->host.ios.clock;
2094 case MMCBR_IVAR_F_MIN:
2095 *result = slot->host.f_min;
2097 case MMCBR_IVAR_F_MAX:
2098 *result = slot->host.f_max;
2100 case MMCBR_IVAR_HOST_OCR:
2101 *result = slot->host.host_ocr;
2103 case MMCBR_IVAR_MODE:
2104 *result = slot->host.mode;
2106 case MMCBR_IVAR_OCR:
2107 *result = slot->host.ocr;
2109 case MMCBR_IVAR_POWER_MODE:
2110 *result = slot->host.ios.power_mode;
2112 case MMCBR_IVAR_VDD:
2113 *result = slot->host.ios.vdd;
2115 case MMCBR_IVAR_RETUNE_REQ:
2116 if (slot->opt & SDHCI_TUNING_ENABLED) {
2117 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2118 *result = retune_req_reset;
2121 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2122 *result = retune_req_normal;
2126 *result = retune_req_none;
2128 case MMCBR_IVAR_VCCQ:
2129 *result = slot->host.ios.vccq;
2131 case MMCBR_IVAR_CAPS:
2132 *result = slot->host.caps;
2134 case MMCBR_IVAR_TIMING:
2135 *result = slot->host.ios.timing;
2137 case MMCBR_IVAR_MAX_DATA:
2139 * Re-tuning modes 1 and 2 restrict the maximum data length
2140 * per read/write command to 4 MiB.
2142 if (slot->opt & SDHCI_TUNING_ENABLED &&
2143 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2144 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2145 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2150 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2152 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2161 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2164 struct sdhci_slot *slot = device_get_ivars(child);
2165 uint32_t clock, max_clock;
2171 case MMCBR_IVAR_BUS_MODE:
2172 slot->host.ios.bus_mode = value;
2174 case MMCBR_IVAR_BUS_WIDTH:
2175 slot->host.ios.bus_width = value;
2177 case MMCBR_IVAR_CHIP_SELECT:
2178 slot->host.ios.chip_select = value;
2180 case MMCBR_IVAR_CLOCK:
2182 max_clock = slot->max_clk;
2185 if (slot->version < SDHCI_SPEC_300) {
2186 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2193 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2197 clock = max_clock / (i + 2);
2201 slot->host.ios.clock = clock;
2203 slot->host.ios.clock = 0;
2205 case MMCBR_IVAR_MODE:
2206 slot->host.mode = value;
2208 case MMCBR_IVAR_OCR:
2209 slot->host.ocr = value;
2211 case MMCBR_IVAR_POWER_MODE:
2212 slot->host.ios.power_mode = value;
2214 case MMCBR_IVAR_VDD:
2215 slot->host.ios.vdd = value;
2217 case MMCBR_IVAR_VCCQ:
2218 slot->host.ios.vccq = value;
2220 case MMCBR_IVAR_TIMING:
2221 slot->host.ios.timing = value;
2223 case MMCBR_IVAR_CAPS:
2224 case MMCBR_IVAR_HOST_OCR:
2225 case MMCBR_IVAR_F_MIN:
2226 case MMCBR_IVAR_F_MAX:
2227 case MMCBR_IVAR_MAX_DATA:
2228 case MMCBR_IVAR_RETUNE_REQ:
2234 MODULE_VERSION(sdhci, 1);