2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/callout.h>
35 #include <sys/kernel.h>
37 #include <sys/libkern.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49 #include <machine/stdarg.h>
51 #include <dev/mmc/bridge.h>
52 #include <dev/mmc/mmcreg.h>
53 #include <dev/mmc/mmcbrvar.h>
55 #include <dev/sdhci/sdhci.h>
60 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
62 static int sdhci_debug;
63 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
64 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
66 u_int sdhci_quirk_clear = 0;
67 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
68 0, "Mask of quirks to clear");
69 u_int sdhci_quirk_set = 0;
70 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
71 "Mask of quirks to set");
73 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
74 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
75 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
76 #define RD_MULTI_4(slot, off, ptr, count) \
77 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
79 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
80 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
81 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
82 #define WR_MULTI_4(slot, off, ptr, count) \
83 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
85 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
86 static void sdhci_card_poll(void *arg);
87 static void sdhci_card_task(void *arg, int pending);
88 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
89 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
90 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
91 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
93 static void sdhci_finish_command(struct sdhci_slot *slot);
94 static void sdhci_init(struct sdhci_slot *slot);
95 static void sdhci_read_block_pio(struct sdhci_slot *slot);
96 static void sdhci_req_done(struct sdhci_slot *slot);
97 static void sdhci_req_wakeup(struct mmc_request *req);
98 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask);
99 static void sdhci_retune(void *arg);
100 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
101 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
102 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
103 const struct mmc_data *data);
104 static void sdhci_start(struct sdhci_slot *slot);
105 static void sdhci_timeout(void *arg);
106 static void sdhci_start_command(struct sdhci_slot *slot,
107 struct mmc_command *cmd);
108 static void sdhci_start_data(struct sdhci_slot *slot,
109 const struct mmc_data *data);
110 static void sdhci_write_block_pio(struct sdhci_slot *slot);
111 static void sdhci_transfer_pio(struct sdhci_slot *slot);
113 /* helper routines */
114 static int sdhci_dma_alloc(struct sdhci_slot *slot);
115 static void sdhci_dma_free(struct sdhci_slot *slot);
116 static void sdhci_dumpregs(struct sdhci_slot *slot);
117 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
119 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
121 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
123 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
124 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
125 #define SDHCI_LOCK_INIT(_slot) \
126 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
127 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
128 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
129 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
131 #define SDHCI_DEFAULT_MAX_FREQ 50
133 #define SDHCI_200_MAX_DIVIDER 256
134 #define SDHCI_300_MAX_DIVIDER 2046
136 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
137 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
140 * Broadcom BCM577xx Controller Constants
142 /* Maximum divider supported by the default clock source. */
143 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
144 /* Alternative clock's base frequency. */
145 #define BCM577XX_ALT_CLOCK_BASE 63000000
147 #define BCM577XX_HOST_CONTROL 0x198
148 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
149 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
150 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
151 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
154 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
158 printf("getaddr: error %d\n", error);
161 *(bus_addr_t *)arg = segs[0].ds_addr;
165 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
170 retval = printf("%s-slot%d: ",
171 device_get_nameunit(slot->bus), slot->num);
174 retval += vprintf(fmt, ap);
180 sdhci_dumpregs(struct sdhci_slot *slot)
184 "============== REGISTER DUMP ==============\n");
186 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
187 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
188 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
189 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
190 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
191 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
192 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
193 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
194 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
195 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
196 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
197 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
198 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
199 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
200 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
201 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
202 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
203 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
204 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
205 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
206 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
207 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
208 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
209 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
212 "===========================================\n");
216 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
221 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
222 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
226 /* Some controllers need this kick or reset won't work. */
227 if ((mask & SDHCI_RESET_ALL) == 0 &&
228 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
229 /* This is to force an update */
232 sdhci_set_clock(slot, clock);
235 if (mask & SDHCI_RESET_ALL) {
240 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
242 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
244 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
245 * specification. The reset bit has internal propagation delay,
246 * so a fast read after write returns 0 even if reset process is
247 * in progress. The workaround is to poll for 1 before polling
248 * for 0. In the worst case, if we miss seeing it asserted the
249 * time we spent waiting is enough to ensure the reset finishes.
252 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
260 /* Wait max 100 ms */
262 /* Controller clears the bits when it's done */
263 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
265 slot_printf(slot, "Reset 0x%x never completed.\n",
267 sdhci_dumpregs(slot);
276 sdhci_tuning_intmask(const struct sdhci_slot *slot)
281 if (slot->opt & SDHCI_TUNING_ENABLED) {
282 intmask |= SDHCI_INT_TUNEERR;
283 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
284 slot->retune_mode == SDHCI_RETUNE_MODE_3)
285 intmask |= SDHCI_INT_RETUNE;
291 sdhci_init(struct sdhci_slot *slot)
294 sdhci_reset(slot, SDHCI_RESET_ALL);
296 /* Enable interrupts. */
297 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
298 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
299 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
300 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
301 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
304 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
305 !(slot->opt & SDHCI_NON_REMOVABLE)) {
306 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
309 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
310 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
314 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
323 if (clock == slot->clock)
327 /* Turn off the clock. */
328 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
329 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
330 /* If no clock requested - leave it so. */
334 /* Determine the clock base frequency */
335 clk_base = slot->max_clk;
336 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
337 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
338 BCM577XX_CTRL_CLKSEL_MASK;
341 * Select clock source appropriate for the requested frequency.
343 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
344 clk_base = BCM577XX_ALT_CLOCK_BASE;
345 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
346 BCM577XX_CTRL_CLKSEL_SHIFT);
348 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
349 BCM577XX_CTRL_CLKSEL_SHIFT);
352 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
355 /* Recalculate timeout clock frequency based on the new sd clock. */
356 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
357 slot->timeout_clk = slot->clock / 1000;
359 if (slot->version < SDHCI_SPEC_300) {
360 /* Looking for highest freq <= clock. */
362 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
367 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
370 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
371 if (clock >= clk_base)
374 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
375 if ((clk_base / div) <= clock)
382 if (bootverbose || sdhci_debug)
383 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
384 div, clock, clk_base);
386 /* Now we have got divider, set it. */
387 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
388 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
389 << SDHCI_DIVIDER_HI_SHIFT;
391 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
393 clk |= SDHCI_CLOCK_INT_EN;
394 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
395 /* Wait up to 10 ms until it stabilize. */
397 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
398 & SDHCI_CLOCK_INT_STABLE)) {
401 "Internal clock never stabilised.\n");
402 sdhci_dumpregs(slot);
408 /* Pass clock signal to the bus. */
409 clk |= SDHCI_CLOCK_CARD_EN;
410 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
414 sdhci_set_power(struct sdhci_slot *slot, u_char power)
419 if (slot->power == power)
424 /* Turn off the power. */
426 WR1(slot, SDHCI_POWER_CONTROL, pwr);
427 /* If power down requested - leave it so. */
431 switch (1 << power) {
432 case MMC_OCR_LOW_VOLTAGE:
433 pwr |= SDHCI_POWER_180;
435 case MMC_OCR_290_300:
436 case MMC_OCR_300_310:
437 pwr |= SDHCI_POWER_300;
439 case MMC_OCR_320_330:
440 case MMC_OCR_330_340:
441 pwr |= SDHCI_POWER_330;
444 WR1(slot, SDHCI_POWER_CONTROL, pwr);
446 * Turn on VDD1 power. Note that at least some Intel controllers can
447 * fail to enable bus power on the first try after transiting from D3
448 * to D0, so we give them up to 2 ms.
450 pwr |= SDHCI_POWER_ON;
451 for (i = 0; i < 20; i++) {
452 WR1(slot, SDHCI_POWER_CONTROL, pwr);
453 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
457 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
458 slot_printf(slot, "Bus power failed to enable");
460 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
461 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
463 WR1(slot, SDHCI_POWER_CONTROL, pwr);
469 sdhci_read_block_pio(struct sdhci_slot *slot)
475 buffer = slot->curcmd->data->data;
476 buffer += slot->offset;
477 /* Transfer one block at a time. */
478 left = min(512, slot->curcmd->data->len - slot->offset);
479 slot->offset += left;
481 /* If we are too fast, broken controllers return zeroes. */
482 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
484 /* Handle unaligned and aligned buffer cases. */
485 if ((intptr_t)buffer & 3) {
487 data = RD4(slot, SDHCI_BUFFER);
489 buffer[1] = (data >> 8);
490 buffer[2] = (data >> 16);
491 buffer[3] = (data >> 24);
496 RD_MULTI_4(slot, SDHCI_BUFFER,
497 (uint32_t *)buffer, left >> 2);
500 /* Handle uneven size case. */
502 data = RD4(slot, SDHCI_BUFFER);
512 sdhci_write_block_pio(struct sdhci_slot *slot)
518 buffer = slot->curcmd->data->data;
519 buffer += slot->offset;
520 /* Transfer one block at a time. */
521 left = min(512, slot->curcmd->data->len - slot->offset);
522 slot->offset += left;
524 /* Handle unaligned and aligned buffer cases. */
525 if ((intptr_t)buffer & 3) {
533 WR4(slot, SDHCI_BUFFER, data);
536 WR_MULTI_4(slot, SDHCI_BUFFER,
537 (uint32_t *)buffer, left >> 2);
540 /* Handle uneven size case. */
547 WR4(slot, SDHCI_BUFFER, data);
552 sdhci_transfer_pio(struct sdhci_slot *slot)
555 /* Read as many blocks as possible. */
556 if (slot->curcmd->data->flags & MMC_DATA_READ) {
557 while (RD4(slot, SDHCI_PRESENT_STATE) &
558 SDHCI_DATA_AVAILABLE) {
559 sdhci_read_block_pio(slot);
560 if (slot->offset >= slot->curcmd->data->len)
564 while (RD4(slot, SDHCI_PRESENT_STATE) &
565 SDHCI_SPACE_AVAILABLE) {
566 sdhci_write_block_pio(slot);
567 if (slot->offset >= slot->curcmd->data->len)
574 sdhci_card_task(void *arg, int pending __unused)
576 struct sdhci_slot *slot = arg;
580 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
581 if (slot->dev == NULL) {
582 /* If card is present - attach mmc bus. */
583 if (bootverbose || sdhci_debug)
584 slot_printf(slot, "Card inserted\n");
585 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
588 device_set_ivars(d, slot);
589 (void)device_probe_and_attach(d);
594 if (slot->dev != NULL) {
595 /* If no card present - detach mmc bus. */
596 if (bootverbose || sdhci_debug)
597 slot_printf(slot, "Card removed\n");
600 slot->intmask &= ~sdhci_tuning_intmask(slot);
601 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
602 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
603 slot->opt &= ~SDHCI_TUNING_ENABLED;
605 callout_drain(&slot->retune_callout);
606 device_delete_child(slot->bus, d);
613 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
618 * If there was no card and now there is one, schedule the task to
619 * create the child device after a short delay. The delay is to
620 * debounce the card insert (sometimes the card detect pin stabilizes
621 * before the other pins have made good contact).
623 * If there was a card present and now it's gone, immediately schedule
624 * the task to delete the child device. No debouncing -- gone is gone,
625 * because once power is removed, a full card re-init is needed, and
626 * that happens by deleting and recreating the child device.
628 was_present = slot->dev != NULL;
629 if (!was_present && is_present) {
630 taskqueue_enqueue_timeout(taskqueue_swi_giant,
631 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
632 } else if (was_present && !is_present) {
633 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
638 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
642 sdhci_handle_card_present_locked(slot, is_present);
647 sdhci_card_poll(void *arg)
649 struct sdhci_slot *slot = arg;
651 sdhci_handle_card_present(slot,
652 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
653 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
654 sdhci_card_poll, slot);
658 sdhci_dma_alloc(struct sdhci_slot *slot)
662 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
663 if (MAXPHYS <= 1024 * 4)
664 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
665 else if (MAXPHYS <= 1024 * 8)
666 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
667 else if (MAXPHYS <= 1024 * 16)
668 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
669 else if (MAXPHYS <= 1024 * 32)
670 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
671 else if (MAXPHYS <= 1024 * 64)
672 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
673 else if (MAXPHYS <= 1024 * 128)
674 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
675 else if (MAXPHYS <= 1024 * 256)
676 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
678 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
680 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
682 * Allocate the DMA tag for an SDMA bounce buffer.
683 * Note that the SDHCI specification doesn't state any alignment
684 * constraint for the SDMA system address. However, controllers
685 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when
686 * forming the actual address of data, requiring the SDMA buffer to
687 * be aligned to the SDMA boundary.
689 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
690 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
691 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
692 NULL, NULL, &slot->dmatag);
694 slot_printf(slot, "Can't create DMA tag for SDMA\n");
697 /* Allocate DMA memory for the SDMA bounce buffer. */
698 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
699 BUS_DMA_NOWAIT, &slot->dmamap);
701 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
702 bus_dma_tag_destroy(slot->dmatag);
705 /* Map the memory of the SDMA bounce buffer. */
706 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
707 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
709 if (err != 0 || slot->paddr == 0) {
710 slot_printf(slot, "Can't load DMA memory for SDMA\n");
711 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
712 bus_dma_tag_destroy(slot->dmatag);
723 sdhci_dma_free(struct sdhci_slot *slot)
726 bus_dmamap_unload(slot->dmatag, slot->dmamap);
727 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
728 bus_dma_tag_destroy(slot->dmatag);
732 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
734 kobjop_desc_t kobj_desc;
735 kobj_method_t *kobj_method;
736 uint32_t caps, caps2, freq, host_caps;
739 SDHCI_LOCK_INIT(slot);
744 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
745 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
746 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
750 caps = RD4(slot, SDHCI_CAPABILITIES);
751 if (slot->version >= SDHCI_SPEC_300)
752 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
756 if (slot->version >= SDHCI_SPEC_300) {
757 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
758 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
760 "Driver doesn't support shared bus slots\n");
761 SDHCI_LOCK_DESTROY(slot);
763 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
764 SDHCI_SLOTTYPE_EMBEDDED) {
765 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
768 /* Calculate base clock frequency. */
769 if (slot->version >= SDHCI_SPEC_300)
770 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
771 SDHCI_CLOCK_BASE_SHIFT;
773 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
774 SDHCI_CLOCK_BASE_SHIFT;
776 slot->max_clk = freq * 1000000;
778 * If the frequency wasn't in the capabilities and the hardware driver
779 * hasn't already set max_clk we're probably not going to work right
780 * with an assumption, so complain about it.
782 if (slot->max_clk == 0) {
783 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
784 slot_printf(slot, "Hardware doesn't specify base clock "
785 "frequency, using %dMHz as default.\n",
786 SDHCI_DEFAULT_MAX_FREQ);
788 /* Calculate/set timeout clock frequency. */
789 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
790 slot->timeout_clk = slot->max_clk / 1000;
791 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
792 slot->timeout_clk = 1000;
794 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
795 SDHCI_TIMEOUT_CLK_SHIFT;
796 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
797 slot->timeout_clk *= 1000;
800 * If the frequency wasn't in the capabilities and the hardware driver
801 * hasn't already set timeout_clk we'll probably work okay using the
802 * max timeout, but still mention it.
804 if (slot->timeout_clk == 0) {
805 slot_printf(slot, "Hardware doesn't specify timeout clock "
806 "frequency, setting BROKEN_TIMEOUT quirk.\n");
807 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
810 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
811 slot->host.f_max = slot->max_clk;
812 slot->host.host_ocr = 0;
813 if (caps & SDHCI_CAN_VDD_330)
814 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
815 if (caps & SDHCI_CAN_VDD_300)
816 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
817 /* 1.8V VDD is not supposed to be used for removable cards. */
818 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
819 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
820 if (slot->host.host_ocr == 0) {
821 slot_printf(slot, "Hardware doesn't report any "
822 "support voltages.\n");
825 host_caps = MMC_CAP_4_BIT_DATA;
826 if (caps & SDHCI_CAN_DO_8BITBUS)
827 host_caps |= MMC_CAP_8_BIT_DATA;
828 if (caps & SDHCI_CAN_DO_HISPD)
829 host_caps |= MMC_CAP_HSPEED;
830 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
831 host_caps |= MMC_CAP_BOOT_NOACC;
832 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
833 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
835 /* Determine supported UHS-I and eMMC modes. */
836 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
837 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
838 if (caps2 & SDHCI_CAN_SDR104) {
839 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
840 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
841 host_caps |= MMC_CAP_MMC_HS200;
842 } else if (caps2 & SDHCI_CAN_SDR50)
843 host_caps |= MMC_CAP_UHS_SDR50;
844 if (caps2 & SDHCI_CAN_DDR50 &&
845 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
846 host_caps |= MMC_CAP_UHS_DDR50;
847 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
848 host_caps |= MMC_CAP_MMC_DDR52;
849 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
850 caps2 & SDHCI_CAN_MMC_HS400)
851 host_caps |= MMC_CAP_MMC_HS400;
852 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
853 caps2 & SDHCI_CAN_SDR104)
854 host_caps |= MMC_CAP_MMC_HS400;
857 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
858 * default NULL implementation.
860 kobj_desc = &sdhci_set_uhs_timing_desc;
861 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
863 if (kobj_method == &kobj_desc->deflt)
864 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
865 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
866 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
868 #define SDHCI_CAP_MODES_TUNING(caps2) \
869 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
870 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
874 * Disable UHS-I and eMMC modes that require (re-)tuning if either
875 * the tune or re-tune method is the default NULL implementation.
877 kobj_desc = &mmcbr_tune_desc;
878 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
880 if (kobj_method == &kobj_desc->deflt)
882 kobj_desc = &mmcbr_retune_desc;
883 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
885 if (kobj_method == &kobj_desc->deflt) {
887 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
890 /* Allocate tuning structures and determine tuning parameters. */
891 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
892 slot->opt |= SDHCI_TUNING_SUPPORTED;
893 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
895 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
897 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
899 if (caps2 & SDHCI_TUNE_SDR50)
900 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
901 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
902 SDHCI_RETUNE_MODES_SHIFT;
903 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
904 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
905 SDHCI_RETUNE_CNT_SHIFT;
906 if (slot->retune_count > 0xb) {
907 slot_printf(slot, "Unknown re-tuning count "
908 "%x, using 1 sec\n", slot->retune_count);
909 slot->retune_count = 1;
910 } else if (slot->retune_count != 0)
912 1 << (slot->retune_count - 1);
916 #undef SDHCI_CAP_MODES_TUNING
918 /* Determine supported VCCQ signaling levels. */
919 host_caps |= MMC_CAP_SIGNALING_330;
920 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
921 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
922 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
923 MMC_CAP_MMC_HS400_180))
924 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
927 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
928 * default NULL implementation. Disable 1.2 V support if it's the
929 * generic SDHCI implementation.
931 kobj_desc = &mmcbr_switch_vccq_desc;
932 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
934 if (kobj_method == &kobj_desc->deflt)
935 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
936 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
937 host_caps &= ~MMC_CAP_SIGNALING_120;
939 /* Determine supported driver types (type B is always mandatory). */
940 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
941 host_caps |= MMC_CAP_DRIVER_TYPE_A;
942 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
943 host_caps |= MMC_CAP_DRIVER_TYPE_C;
944 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
945 host_caps |= MMC_CAP_DRIVER_TYPE_D;
946 slot->host.caps = host_caps;
948 /* Decide if we have usable DMA. */
949 if (caps & SDHCI_CAN_DO_DMA)
950 slot->opt |= SDHCI_HAVE_DMA;
952 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
953 slot->opt &= ~SDHCI_HAVE_DMA;
954 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
955 slot->opt |= SDHCI_HAVE_DMA;
956 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
957 slot->opt |= SDHCI_NON_REMOVABLE;
960 * Use platform-provided transfer backend
961 * with PIO as a fallback mechanism
963 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
964 slot->opt &= ~SDHCI_HAVE_DMA;
966 if (slot->opt & SDHCI_HAVE_DMA) {
967 err = sdhci_dma_alloc(slot);
969 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
970 free(slot->tune_req, M_DEVBUF);
971 free(slot->tune_cmd, M_DEVBUF);
972 free(slot->tune_data, M_DEVBUF);
974 SDHCI_LOCK_DESTROY(slot);
979 if (bootverbose || sdhci_debug) {
981 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
982 slot->max_clk / 1000000,
983 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
984 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
985 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
986 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
987 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
988 ((caps & SDHCI_CAN_VDD_180) &&
989 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
990 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
991 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
992 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
993 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
994 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
995 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
996 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
997 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
999 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
1000 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
1001 slot_printf(slot, "eMMC:%s%s%s%s\n",
1002 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
1003 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
1004 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
1006 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
1007 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
1009 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1010 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
1011 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
1012 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
1013 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
1014 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
1015 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
1016 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
1017 if (slot->opt & SDHCI_TUNING_SUPPORTED)
1018 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
1019 slot->retune_count, slot->retune_mode + 1);
1020 sdhci_dumpregs(slot);
1024 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1025 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1026 "timeout", CTLFLAG_RW, &slot->timeout, 0,
1027 "Maximum timeout for SDHCI transfers (in secs)");
1028 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1029 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1030 sdhci_card_task, slot);
1031 callout_init(&slot->card_poll_callout, 1);
1032 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1033 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1035 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1036 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1037 callout_reset(&slot->card_poll_callout,
1038 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1047 sdhci_start_slot(struct sdhci_slot *slot)
1050 sdhci_card_task(slot, 0);
1054 sdhci_cleanup_slot(struct sdhci_slot *slot)
1058 callout_drain(&slot->timeout_callout);
1059 callout_drain(&slot->card_poll_callout);
1060 callout_drain(&slot->retune_callout);
1061 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1062 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1069 device_delete_child(slot->bus, d);
1072 sdhci_reset(slot, SDHCI_RESET_ALL);
1074 if (slot->opt & SDHCI_HAVE_DMA)
1075 sdhci_dma_free(slot);
1076 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1077 free(slot->tune_req, M_DEVBUF);
1078 free(slot->tune_cmd, M_DEVBUF);
1079 free(slot->tune_data, M_DEVBUF);
1082 SDHCI_LOCK_DESTROY(slot);
1088 sdhci_generic_suspend(struct sdhci_slot *slot)
1092 * We expect the MMC layer to issue initial tuning after resume.
1093 * Otherwise, we'd need to indicate re-tuning including circuit reset
1094 * being required at least for re-tuning modes 1 and 2 ourselves.
1096 callout_drain(&slot->retune_callout);
1098 slot->opt &= ~SDHCI_TUNING_ENABLED;
1099 sdhci_reset(slot, SDHCI_RESET_ALL);
1106 sdhci_generic_resume(struct sdhci_slot *slot)
1117 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1120 if (slot->version >= SDHCI_SPEC_300)
1121 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1123 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1127 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1130 if (slot->opt & SDHCI_NON_REMOVABLE)
1133 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1137 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1139 const struct mmc_ios *ios;
1142 if (slot->version < SDHCI_SPEC_300)
1145 SDHCI_ASSERT_LOCKED(slot);
1146 ios = &slot->host.ios;
1147 sdhci_set_clock(slot, 0);
1148 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1149 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1150 if (ios->clock > SD_SDR50_MAX) {
1151 if (ios->timing == bus_timing_mmc_hs400 ||
1152 ios->timing == bus_timing_mmc_hs400es)
1153 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1155 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1157 else if (ios->clock > SD_SDR25_MAX)
1158 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1159 else if (ios->clock > SD_SDR12_MAX) {
1160 if (ios->timing == bus_timing_uhs_ddr50 ||
1161 ios->timing == bus_timing_mmc_ddr52)
1162 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1164 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1165 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1166 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1167 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1168 sdhci_set_clock(slot, ios->clock);
1172 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1174 struct sdhci_slot *slot = device_get_ivars(reqdev);
1175 struct mmc_ios *ios = &slot->host.ios;
1178 /* Do full reset on bus power down to clear from any state. */
1179 if (ios->power_mode == power_off) {
1180 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1183 /* Configure the bus. */
1184 sdhci_set_clock(slot, ios->clock);
1185 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1186 if (ios->bus_width == bus_width_8) {
1187 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1188 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1189 } else if (ios->bus_width == bus_width_4) {
1190 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1191 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1192 } else if (ios->bus_width == bus_width_1) {
1193 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1194 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1196 panic("Invalid bus width: %d", ios->bus_width);
1198 if (ios->clock > SD_SDR12_MAX &&
1199 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1200 slot->hostctrl |= SDHCI_CTRL_HISPD;
1202 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1203 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1204 SDHCI_SET_UHS_TIMING(brdev, slot);
1205 /* Some controllers like reset after bus changes. */
1206 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1207 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1214 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1216 struct sdhci_slot *slot = device_get_ivars(reqdev);
1221 if (slot->version < SDHCI_SPEC_300)
1225 vccq = slot->host.ios.vccq;
1227 sdhci_set_clock(slot, 0);
1228 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1231 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1233 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1234 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1236 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1237 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1242 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1246 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1248 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1249 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1251 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1252 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1258 "Attempt to set unsupported signaling voltage\n");
1263 sdhci_set_clock(slot, slot->host.ios.clock);
1269 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1271 struct sdhci_slot *slot = device_get_ivars(reqdev);
1272 const struct mmc_ios *ios = &slot->host.ios;
1273 struct mmc_command *tune_cmd;
1274 struct mmc_data *tune_data;
1278 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1281 slot->retune_ticks = slot->retune_count * hz;
1282 opcode = MMC_SEND_TUNING_BLOCK;
1284 switch (ios->timing) {
1285 case bus_timing_mmc_hs400:
1286 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1289 case bus_timing_mmc_hs200:
1291 * In HS400 mode, controllers use the data strobe line to
1292 * latch data from the devices so periodic re-tuning isn't
1293 * expected to be required.
1296 slot->retune_ticks = 0;
1297 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1299 case bus_timing_uhs_ddr50:
1300 case bus_timing_uhs_sdr104:
1302 case bus_timing_uhs_sdr50:
1303 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1311 tune_cmd = slot->tune_cmd;
1312 memset(tune_cmd, 0, sizeof(*tune_cmd));
1313 tune_cmd->opcode = opcode;
1314 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1315 tune_data = tune_cmd->data = slot->tune_data;
1316 memset(tune_data, 0, sizeof(*tune_data));
1317 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1318 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1320 tune_data->flags = MMC_DATA_READ;
1321 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1323 slot->opt &= ~SDHCI_TUNING_ENABLED;
1324 err = sdhci_exec_tuning(slot, true);
1326 slot->opt |= SDHCI_TUNING_ENABLED;
1327 slot->intmask |= sdhci_tuning_intmask(slot);
1328 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1329 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1330 if (slot->retune_ticks) {
1331 callout_reset(&slot->retune_callout, slot->retune_ticks,
1332 sdhci_retune, slot);
1340 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1342 struct sdhci_slot *slot = device_get_ivars(reqdev);
1345 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1348 /* HS400 must be tuned in HS200 mode. */
1349 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1353 err = sdhci_exec_tuning(slot, reset);
1355 * There are two ways sdhci_exec_tuning() can fail:
1356 * EBUSY should not actually happen when requests are only issued
1357 * with the host properly acquired, and
1358 * EIO re-tuning failed (but it did work initially).
1360 * In both cases, we should retry at later point if periodic re-tuning
1361 * is enabled. Note that due to slot->retune_req not being cleared in
1362 * these failure cases, the MMC layer should trigger another attempt at
1363 * re-tuning with the next request anyway, though.
1365 if (slot->retune_ticks) {
1366 callout_reset(&slot->retune_callout, slot->retune_ticks,
1367 sdhci_retune, slot);
1374 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1376 struct mmc_request *tune_req;
1377 struct mmc_command *tune_cmd;
1383 SDHCI_ASSERT_LOCKED(slot);
1384 if (slot->req != NULL)
1387 /* Tuning doesn't work with DMA enabled. */
1389 slot->opt = opt & ~SDHCI_HAVE_DMA;
1392 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1393 * kind of interrupt we receive in response to a tuning request.
1395 intmask = slot->intmask;
1396 slot->intmask = SDHCI_INT_DATA_AVAIL;
1397 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1398 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1400 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1402 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1404 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1405 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1407 tune_req = slot->tune_req;
1408 tune_cmd = slot->tune_cmd;
1409 for (i = 0; i < MMC_TUNING_MAX; i++) {
1410 memset(tune_req, 0, sizeof(*tune_req));
1411 tune_req->cmd = tune_cmd;
1412 tune_req->done = sdhci_req_wakeup;
1413 tune_req->done_data = slot;
1414 slot->req = tune_req;
1417 while (!(tune_req->flags & MMC_REQ_DONE))
1418 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1419 if (!(tune_req->flags & MMC_TUNE_DONE))
1421 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1422 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1424 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1429 * Restore DMA usage and interrupts.
1430 * Note that the interrupt aggregation code might have cleared
1431 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1432 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1433 * doesn't lose these.
1436 slot->intmask = intmask;
1437 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1438 SDHCI_INT_RESPONSE);
1439 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1441 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1442 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1443 slot->retune_req = 0;
1447 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1448 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1449 SDHCI_CTRL2_SAMPLING_CLOCK));
1450 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1455 sdhci_retune(void *arg)
1457 struct sdhci_slot *slot = arg;
1459 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1463 sdhci_req_done(struct sdhci_slot *slot)
1465 struct mmc_request *req;
1467 if (slot->req != NULL && slot->curcmd != NULL) {
1468 callout_stop(&slot->timeout_callout);
1471 slot->curcmd = NULL;
1477 sdhci_req_wakeup(struct mmc_request *req)
1479 struct sdhci_slot *slot;
1481 slot = req->done_data;
1482 req->flags |= MMC_REQ_DONE;
1487 sdhci_timeout(void *arg)
1489 struct sdhci_slot *slot = arg;
1491 if (slot->curcmd != NULL) {
1492 slot_printf(slot, "Controller timeout\n");
1493 sdhci_dumpregs(slot);
1494 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1495 slot->curcmd->error = MMC_ERR_TIMEOUT;
1496 sdhci_req_done(slot);
1498 slot_printf(slot, "Spurious timeout - no active command\n");
1503 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data)
1510 mode = SDHCI_TRNS_BLK_CNT_EN;
1511 if (data->len > 512) {
1512 mode |= SDHCI_TRNS_MULTI;
1513 if (__predict_true(slot->req->stop != NULL))
1514 mode |= SDHCI_TRNS_ACMD12;
1516 if (data->flags & MMC_DATA_READ)
1517 mode |= SDHCI_TRNS_READ;
1518 if (slot->flags & SDHCI_USE_DMA)
1519 mode |= SDHCI_TRNS_DMA;
1521 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1525 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1533 cmd->error = MMC_ERR_NONE;
1535 /* This flags combination is not supported by controller. */
1536 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1537 slot_printf(slot, "Unsupported response type!\n");
1538 cmd->error = MMC_ERR_FAILED;
1539 sdhci_req_done(slot);
1544 * Do not issue command if there is no card, clock or power.
1545 * Controller will not detect timeout without clock active.
1547 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1550 cmd->error = MMC_ERR_FAILED;
1551 sdhci_req_done(slot);
1554 /* Always wait for free CMD bus. */
1555 mask = SDHCI_CMD_INHIBIT;
1556 /* Wait for free DAT if we have data or busy signal. */
1557 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
1558 mask |= SDHCI_DAT_INHIBIT;
1560 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1561 * that these latter are also special in that SDHCI_CMD_DATA should
1562 * be set below but no actual data is ever read from the controller.
1564 if (cmd == slot->req->stop ||
1565 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1566 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1567 mask &= ~SDHCI_DAT_INHIBIT;
1569 * Wait for bus no more then 250 ms. Typically there will be no wait
1570 * here at all, but when writing a crash dump we may be bypassing the
1571 * host platform's interrupt handler, and in some cases that handler
1572 * may be working around hardware quirks such as not respecting r1b
1573 * busy indications. In those cases, this wait-loop serves the purpose
1574 * of waiting for the prior command and data transfers to be done, and
1575 * SD cards are allowed to take up to 250ms for write and erase ops.
1576 * (It's usually more like 20-30ms in the real world.)
1579 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1581 slot_printf(slot, "Controller never released "
1582 "inhibit bit(s).\n");
1583 sdhci_dumpregs(slot);
1584 cmd->error = MMC_ERR_FAILED;
1585 sdhci_req_done(slot);
1592 /* Prepare command flags. */
1593 if (!(cmd->flags & MMC_RSP_PRESENT))
1594 flags = SDHCI_CMD_RESP_NONE;
1595 else if (cmd->flags & MMC_RSP_136)
1596 flags = SDHCI_CMD_RESP_LONG;
1597 else if (cmd->flags & MMC_RSP_BUSY)
1598 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1600 flags = SDHCI_CMD_RESP_SHORT;
1601 if (cmd->flags & MMC_RSP_CRC)
1602 flags |= SDHCI_CMD_CRC;
1603 if (cmd->flags & MMC_RSP_OPCODE)
1604 flags |= SDHCI_CMD_INDEX;
1606 flags |= SDHCI_CMD_DATA;
1607 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1608 flags |= SDHCI_CMD_TYPE_ABORT;
1610 sdhci_start_data(slot, cmd->data);
1612 * Interrupt aggregation: To reduce total number of interrupts
1613 * group response interrupt with data interrupt when possible.
1614 * If there going to be data interrupt, mask response one.
1616 if (slot->data_done == 0) {
1617 WR4(slot, SDHCI_SIGNAL_ENABLE,
1618 slot->intmask &= ~SDHCI_INT_RESPONSE);
1620 /* Set command argument. */
1621 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1622 /* Set data transfer mode. */
1623 sdhci_set_transfer_mode(slot, cmd->data);
1624 /* Start command. */
1625 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1626 /* Start timeout callout. */
1627 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1628 sdhci_timeout, slot);
1632 sdhci_finish_command(struct sdhci_slot *slot)
1640 * Interrupt aggregation: Restore command interrupt.
1641 * Main restore point for the case when command interrupt
1644 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1645 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1646 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1647 SDHCI_INT_RESPONSE);
1648 /* In case of error - reset host and return. */
1649 if (slot->curcmd->error) {
1650 if (slot->curcmd->error == MMC_ERR_BADCRC)
1651 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1652 sdhci_reset(slot, SDHCI_RESET_CMD);
1653 sdhci_reset(slot, SDHCI_RESET_DATA);
1657 /* If command has response - fetch it. */
1658 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1659 if (slot->curcmd->flags & MMC_RSP_136) {
1660 /* CRC is stripped so we need one byte shift. */
1662 for (i = 0; i < 4; i++) {
1663 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1665 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1666 slot->curcmd->resp[3 - i] = val;
1668 slot->curcmd->resp[3 - i] =
1674 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1676 /* If data ready - finish. */
1677 if (slot->data_done)
1682 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data)
1684 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout;
1687 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1688 slot->data_done = 1;
1692 slot->data_done = 0;
1694 /* Calculate and set data timeout.*/
1695 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1696 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1699 target_timeout = 1000000;
1701 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1702 while (current_timeout < target_timeout && div < 0xE) {
1704 current_timeout <<= 1;
1706 /* Compensate for an off-by-one error in the CaFe chip.*/
1708 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1712 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1717 /* Use DMA if possible. */
1718 if ((slot->opt & SDHCI_HAVE_DMA))
1719 slot->flags |= SDHCI_USE_DMA;
1720 /* If data is small, broken DMA may return zeroes instead of data. */
1721 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1723 slot->flags &= ~SDHCI_USE_DMA;
1724 /* Some controllers require even block sizes. */
1725 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1726 ((data->len) & 0x3))
1727 slot->flags &= ~SDHCI_USE_DMA;
1728 /* Load DMA buffer. */
1729 if (slot->flags & SDHCI_USE_DMA) {
1730 sdma_bbufsz = slot->sdma_bbufsz;
1731 if (data->flags & MMC_DATA_READ)
1732 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1733 BUS_DMASYNC_PREREAD);
1735 memcpy(slot->dmamem, data->data, ulmin(data->len,
1737 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1738 BUS_DMASYNC_PREWRITE);
1740 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1742 * Interrupt aggregation: Mask border interrupt for the last
1743 * bounce buffer and unmask otherwise.
1745 if (data->len == sdma_bbufsz)
1746 slot->intmask &= ~SDHCI_INT_DMA_END;
1748 slot->intmask |= SDHCI_INT_DMA_END;
1749 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1751 /* Current data offset for both PIO and DMA. */
1753 /* Set block size and request border interrupts on the SDMA boundary. */
1754 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
1755 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
1756 /* Set block count. */
1757 blkcnt = howmany(data->len, 512);
1758 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
1762 sdhci_finish_data(struct sdhci_slot *slot)
1764 struct mmc_data *data = slot->curcmd->data;
1767 /* Interrupt aggregation: Restore command interrupt.
1768 * Auxiliary restore point for the case when data interrupt
1769 * happened first. */
1770 if (!slot->cmd_done) {
1771 WR4(slot, SDHCI_SIGNAL_ENABLE,
1772 slot->intmask |= SDHCI_INT_RESPONSE);
1774 /* Unload rest of data from DMA buffer. */
1775 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
1776 if (data->flags & MMC_DATA_READ) {
1777 left = data->len - slot->offset;
1778 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1779 BUS_DMASYNC_POSTREAD);
1780 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1781 ulmin(left, slot->sdma_bbufsz));
1783 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1784 BUS_DMASYNC_POSTWRITE);
1786 slot->data_done = 1;
1787 /* If there was error - reset the host. */
1788 if (slot->curcmd->error) {
1789 if (slot->curcmd->error == MMC_ERR_BADCRC)
1790 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1791 sdhci_reset(slot, SDHCI_RESET_CMD);
1792 sdhci_reset(slot, SDHCI_RESET_DATA);
1796 /* If we already have command response - finish. */
1802 sdhci_start(struct sdhci_slot *slot)
1804 const struct mmc_request *req;
1810 if (!(slot->flags & CMD_STARTED)) {
1811 slot->flags |= CMD_STARTED;
1812 sdhci_start_command(slot, req->cmd);
1815 /* We don't need this until using Auto-CMD12 feature
1816 if (!(slot->flags & STOP_STARTED) && req->stop) {
1817 slot->flags |= STOP_STARTED;
1818 sdhci_start_command(slot, req->stop);
1822 if (__predict_false(sdhci_debug > 1))
1823 slot_printf(slot, "result: %d\n", req->cmd->error);
1824 if (!req->cmd->error &&
1825 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1826 sdhci_reset(slot, SDHCI_RESET_CMD);
1827 sdhci_reset(slot, SDHCI_RESET_DATA);
1830 sdhci_req_done(slot);
1834 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1835 struct mmc_request *req)
1837 struct sdhci_slot *slot = device_get_ivars(reqdev);
1840 if (slot->req != NULL) {
1844 if (__predict_false(sdhci_debug > 1)) {
1846 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1847 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1848 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1849 (req->cmd->data)?req->cmd->data->flags:0);
1856 while (slot->req != NULL) {
1857 sdhci_generic_intr(slot);
1865 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1867 struct sdhci_slot *slot = device_get_ivars(reqdev);
1871 val = RD4(slot, SDHCI_PRESENT_STATE);
1873 return (!(val & SDHCI_WRITE_PROTECT));
1877 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1879 struct sdhci_slot *slot = device_get_ivars(reqdev);
1883 while (slot->bus_busy)
1884 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1887 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1893 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1895 struct sdhci_slot *slot = device_get_ivars(reqdev);
1898 /* Deactivate led. */
1899 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1907 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1910 if (!slot->curcmd) {
1911 slot_printf(slot, "Got command interrupt 0x%08x, but "
1912 "there is no active command.\n", intmask);
1913 sdhci_dumpregs(slot);
1916 if (intmask & SDHCI_INT_TIMEOUT)
1917 slot->curcmd->error = MMC_ERR_TIMEOUT;
1918 else if (intmask & SDHCI_INT_CRC)
1919 slot->curcmd->error = MMC_ERR_BADCRC;
1920 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1921 slot->curcmd->error = MMC_ERR_FIFO;
1923 sdhci_finish_command(slot);
1927 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1929 struct mmc_data *data;
1931 uint32_t sdma_bbufsz;
1933 if (!slot->curcmd) {
1934 slot_printf(slot, "Got data interrupt 0x%08x, but "
1935 "there is no active command.\n", intmask);
1936 sdhci_dumpregs(slot);
1939 if (slot->curcmd->data == NULL &&
1940 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1941 slot_printf(slot, "Got data interrupt 0x%08x, but "
1942 "there is no active data operation.\n",
1944 sdhci_dumpregs(slot);
1947 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1948 slot->curcmd->error = MMC_ERR_TIMEOUT;
1949 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1950 slot->curcmd->error = MMC_ERR_BADCRC;
1951 if (slot->curcmd->data == NULL &&
1952 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1953 SDHCI_INT_DMA_END))) {
1954 slot_printf(slot, "Got data interrupt 0x%08x, but "
1955 "there is busy-only command.\n", intmask);
1956 sdhci_dumpregs(slot);
1957 slot->curcmd->error = MMC_ERR_INVALID;
1959 if (slot->curcmd->error) {
1960 /* No need to continue after any error. */
1964 /* Handle tuning completion interrupt. */
1965 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
1966 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
1967 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
1968 slot->req->flags |= MMC_TUNE_DONE;
1969 sdhci_finish_command(slot);
1970 sdhci_finish_data(slot);
1973 /* Handle PIO interrupt. */
1974 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1975 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1976 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1977 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
1979 slot->flags |= PLATFORM_DATA_STARTED;
1981 sdhci_transfer_pio(slot);
1983 /* Handle DMA border. */
1984 if (intmask & SDHCI_INT_DMA_END) {
1985 data = slot->curcmd->data;
1986 sdma_bbufsz = slot->sdma_bbufsz;
1988 /* Unload DMA buffer ... */
1989 left = data->len - slot->offset;
1990 if (data->flags & MMC_DATA_READ) {
1991 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1992 BUS_DMASYNC_POSTREAD);
1993 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1994 ulmin(left, sdma_bbufsz));
1996 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1997 BUS_DMASYNC_POSTWRITE);
1999 /* ... and reload it again. */
2000 slot->offset += sdma_bbufsz;
2001 left = data->len - slot->offset;
2002 if (data->flags & MMC_DATA_READ) {
2003 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2004 BUS_DMASYNC_PREREAD);
2006 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2007 ulmin(left, sdma_bbufsz));
2008 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2009 BUS_DMASYNC_PREWRITE);
2012 * Interrupt aggregation: Mask border interrupt for the last
2015 if (left == sdma_bbufsz) {
2016 slot->intmask &= ~SDHCI_INT_DMA_END;
2017 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2020 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2022 /* We have got all data. */
2023 if (intmask & SDHCI_INT_DATA_END) {
2024 if (slot->flags & PLATFORM_DATA_STARTED) {
2025 slot->flags &= ~PLATFORM_DATA_STARTED;
2026 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2028 sdhci_finish_data(slot);
2031 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2032 if (slot->flags & PLATFORM_DATA_STARTED) {
2033 slot->flags &= ~PLATFORM_DATA_STARTED;
2034 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2036 sdhci_finish_data(slot);
2041 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
2044 if (!slot->curcmd) {
2045 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2046 "there is no active command.\n", acmd_err);
2047 sdhci_dumpregs(slot);
2050 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2051 sdhci_reset(slot, SDHCI_RESET_CMD);
2055 sdhci_generic_intr(struct sdhci_slot *slot)
2057 uint32_t intmask, present;
2061 /* Read slot interrupt status. */
2062 intmask = RD4(slot, SDHCI_INT_STATUS);
2063 if (intmask == 0 || intmask == 0xffffffff) {
2067 if (__predict_false(sdhci_debug > 2))
2068 slot_printf(slot, "Interrupt %#x\n", intmask);
2070 /* Handle tuning error interrupt. */
2071 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2072 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2073 slot_printf(slot, "Tuning error indicated\n");
2074 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2076 slot->curcmd->error = MMC_ERR_BADCRC;
2077 sdhci_finish_command(slot);
2080 /* Handle re-tuning interrupt. */
2081 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2082 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2083 /* Handle card presence interrupts. */
2084 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2085 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2087 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2088 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2089 SDHCI_INT_CARD_INSERT;
2090 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2091 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2092 WR4(slot, SDHCI_INT_STATUS, intmask &
2093 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2094 sdhci_handle_card_present_locked(slot, present);
2096 /* Handle command interrupts. */
2097 if (intmask & SDHCI_INT_CMD_MASK) {
2098 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2099 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2101 /* Handle data interrupts. */
2102 if (intmask & SDHCI_INT_DATA_MASK) {
2103 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2104 /* Don't call data_irq in case of errored command. */
2105 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2106 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2108 /* Handle AutoCMD12 error interrupt. */
2109 if (intmask & SDHCI_INT_ACMD12ERR) {
2110 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2111 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2112 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2113 sdhci_acmd_irq(slot, val16);
2115 /* Handle bus power interrupt. */
2116 if (intmask & SDHCI_INT_BUS_POWER) {
2117 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2118 slot_printf(slot, "Card is consuming too much power!\n");
2120 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2121 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2122 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2123 /* The rest is unknown. */
2125 WR4(slot, SDHCI_INT_STATUS, intmask);
2126 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2128 sdhci_dumpregs(slot);
2135 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2138 const struct sdhci_slot *slot = device_get_ivars(child);
2143 case MMCBR_IVAR_BUS_MODE:
2144 *result = slot->host.ios.bus_mode;
2146 case MMCBR_IVAR_BUS_WIDTH:
2147 *result = slot->host.ios.bus_width;
2149 case MMCBR_IVAR_CHIP_SELECT:
2150 *result = slot->host.ios.chip_select;
2152 case MMCBR_IVAR_CLOCK:
2153 *result = slot->host.ios.clock;
2155 case MMCBR_IVAR_F_MIN:
2156 *result = slot->host.f_min;
2158 case MMCBR_IVAR_F_MAX:
2159 *result = slot->host.f_max;
2161 case MMCBR_IVAR_HOST_OCR:
2162 *result = slot->host.host_ocr;
2164 case MMCBR_IVAR_MODE:
2165 *result = slot->host.mode;
2167 case MMCBR_IVAR_OCR:
2168 *result = slot->host.ocr;
2170 case MMCBR_IVAR_POWER_MODE:
2171 *result = slot->host.ios.power_mode;
2173 case MMCBR_IVAR_VDD:
2174 *result = slot->host.ios.vdd;
2176 case MMCBR_IVAR_RETUNE_REQ:
2177 if (slot->opt & SDHCI_TUNING_ENABLED) {
2178 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2179 *result = retune_req_reset;
2182 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2183 *result = retune_req_normal;
2187 *result = retune_req_none;
2189 case MMCBR_IVAR_VCCQ:
2190 *result = slot->host.ios.vccq;
2192 case MMCBR_IVAR_CAPS:
2193 *result = slot->host.caps;
2195 case MMCBR_IVAR_TIMING:
2196 *result = slot->host.ios.timing;
2198 case MMCBR_IVAR_MAX_DATA:
2200 * Re-tuning modes 1 and 2 restrict the maximum data length
2201 * per read/write command to 4 MiB.
2203 if (slot->opt & SDHCI_TUNING_ENABLED &&
2204 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2205 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2206 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2211 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2213 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2222 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2225 struct sdhci_slot *slot = device_get_ivars(child);
2226 uint32_t clock, max_clock;
2232 case MMCBR_IVAR_BUS_MODE:
2233 slot->host.ios.bus_mode = value;
2235 case MMCBR_IVAR_BUS_WIDTH:
2236 slot->host.ios.bus_width = value;
2238 case MMCBR_IVAR_CHIP_SELECT:
2239 slot->host.ios.chip_select = value;
2241 case MMCBR_IVAR_CLOCK:
2243 max_clock = slot->max_clk;
2246 if (slot->version < SDHCI_SPEC_300) {
2247 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2254 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2258 clock = max_clock / (i + 2);
2262 slot->host.ios.clock = clock;
2264 slot->host.ios.clock = 0;
2266 case MMCBR_IVAR_MODE:
2267 slot->host.mode = value;
2269 case MMCBR_IVAR_OCR:
2270 slot->host.ocr = value;
2272 case MMCBR_IVAR_POWER_MODE:
2273 slot->host.ios.power_mode = value;
2275 case MMCBR_IVAR_VDD:
2276 slot->host.ios.vdd = value;
2278 case MMCBR_IVAR_VCCQ:
2279 slot->host.ios.vccq = value;
2281 case MMCBR_IVAR_TIMING:
2282 slot->host.ios.timing = value;
2284 case MMCBR_IVAR_CAPS:
2285 case MMCBR_IVAR_HOST_OCR:
2286 case MMCBR_IVAR_F_MIN:
2287 case MMCBR_IVAR_F_MAX:
2288 case MMCBR_IVAR_MAX_DATA:
2289 case MMCBR_IVAR_RETUNE_REQ:
2295 MODULE_VERSION(sdhci, SDHCI_VERSION);