2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/callout.h>
35 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
43 #include <sys/sysctl.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/stdarg.h>
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcreg.h>
52 #include <dev/mmc/mmcbrvar.h>
54 #include <dev/sdhci/sdhci.h>
57 #include <cam/cam_ccb.h>
58 #include <cam/cam_debug.h>
59 #include <cam/cam_sim.h>
60 #include <cam/cam_xpt_sim.h>
65 #include "opt_mmccam.h"
67 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
69 static int sdhci_debug = 0;
70 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
72 u_int sdhci_quirk_clear = 0;
73 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
74 0, "Mask of quirks to clear");
75 u_int sdhci_quirk_set = 0;
76 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
77 "Mask of quirks to set");
79 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
80 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
81 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
82 #define RD_MULTI_4(slot, off, ptr, count) \
83 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
85 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
86 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
87 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
88 #define WR_MULTI_4(slot, off, ptr, count) \
89 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
91 static void sdhci_card_poll(void *arg);
92 static void sdhci_card_task(void *arg, int pending);
93 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
94 static void sdhci_req_wakeup(struct mmc_request *req);
95 static void sdhci_retune(void *arg);
96 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
97 static void sdhci_start(struct sdhci_slot *slot);
98 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
102 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock);
103 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
104 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
105 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb);
106 static void sdhci_cam_poll(struct cam_sim *sim);
107 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
110 /* helper routines */
111 static void sdhci_dumpregs(struct sdhci_slot *slot);
112 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
114 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot);
116 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
117 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
118 #define SDHCI_LOCK_INIT(_slot) \
119 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
120 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
121 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
122 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
124 #define SDHCI_DEFAULT_MAX_FREQ 50
126 #define SDHCI_200_MAX_DIVIDER 256
127 #define SDHCI_300_MAX_DIVIDER 2046
129 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
130 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
133 * Broadcom BCM577xx Controller Constants
135 /* Maximum divider supported by the default clock source. */
136 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
137 /* Alternative clock's base frequency. */
138 #define BCM577XX_ALT_CLOCK_BASE 63000000
140 #define BCM577XX_HOST_CONTROL 0x198
141 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
142 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
143 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
144 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
147 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
151 printf("getaddr: error %d\n", error);
154 *(bus_addr_t *)arg = segs[0].ds_addr;
158 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
163 retval = printf("%s-slot%d: ",
164 device_get_nameunit(slot->bus), slot->num);
167 retval += vprintf(fmt, ap);
173 sdhci_dumpregs(struct sdhci_slot *slot)
177 "============== REGISTER DUMP ==============\n");
179 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
180 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
181 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
182 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
183 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
184 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
185 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
186 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
187 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
188 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
189 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
190 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
191 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
192 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
193 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
194 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
195 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
196 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
197 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
198 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
199 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
200 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
201 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
202 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
205 "===========================================\n");
209 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
214 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
215 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
219 /* Some controllers need this kick or reset won't work. */
220 if ((mask & SDHCI_RESET_ALL) == 0 &&
221 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
222 /* This is to force an update */
225 sdhci_set_clock(slot, clock);
228 if (mask & SDHCI_RESET_ALL) {
233 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
235 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
237 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
238 * specification. The reset bit has internal propagation delay,
239 * so a fast read after write returns 0 even if reset process is
240 * in progress. The workaround is to poll for 1 before polling
241 * for 0. In the worst case, if we miss seeing it asserted the
242 * time we spent waiting is enough to ensure the reset finishes.
245 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
253 /* Wait max 100 ms */
255 /* Controller clears the bits when it's done */
256 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
258 slot_printf(slot, "Reset 0x%x never completed.\n",
260 sdhci_dumpregs(slot);
269 sdhci_tuning_intmask(struct sdhci_slot *slot)
274 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
275 intmask |= SDHCI_INT_TUNEERR;
276 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
277 slot->retune_mode == SDHCI_RETUNE_MODE_3)
278 intmask |= SDHCI_INT_RETUNE;
284 sdhci_init(struct sdhci_slot *slot)
287 sdhci_reset(slot, SDHCI_RESET_ALL);
289 /* Enable interrupts. */
290 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
291 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
292 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
293 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
294 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
297 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
298 !(slot->opt & SDHCI_NON_REMOVABLE)) {
299 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
302 WR4(slot, SDHCI_INT_ENABLE, slot->intmask | sdhci_tuning_intmask(slot));
303 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
307 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
316 if (clock == slot->clock)
320 /* Turn off the clock. */
321 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
322 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
323 /* If no clock requested - leave it so. */
327 /* Determine the clock base frequency */
328 clk_base = slot->max_clk;
329 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
330 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
331 BCM577XX_CTRL_CLKSEL_MASK;
334 * Select clock source appropriate for the requested frequency.
336 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
337 clk_base = BCM577XX_ALT_CLOCK_BASE;
338 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
339 BCM577XX_CTRL_CLKSEL_SHIFT);
341 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
342 BCM577XX_CTRL_CLKSEL_SHIFT);
345 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
348 /* Recalculate timeout clock frequency based on the new sd clock. */
349 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
350 slot->timeout_clk = slot->clock / 1000;
352 if (slot->version < SDHCI_SPEC_300) {
353 /* Looking for highest freq <= clock. */
355 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
360 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
363 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
364 if (clock >= clk_base)
367 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
368 if ((clk_base / div) <= clock)
375 if (bootverbose || sdhci_debug)
376 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
377 div, clock, clk_base);
379 /* Now we have got divider, set it. */
380 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
381 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
382 << SDHCI_DIVIDER_HI_SHIFT;
384 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
386 clk |= SDHCI_CLOCK_INT_EN;
387 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
388 /* Wait up to 10 ms until it stabilize. */
390 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
391 & SDHCI_CLOCK_INT_STABLE)) {
394 "Internal clock never stabilised.\n");
395 sdhci_dumpregs(slot);
401 /* Pass clock signal to the bus. */
402 clk |= SDHCI_CLOCK_CARD_EN;
403 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
407 sdhci_set_power(struct sdhci_slot *slot, u_char power)
412 if (slot->power == power)
417 /* Turn off the power. */
419 WR1(slot, SDHCI_POWER_CONTROL, pwr);
420 /* If power down requested - leave it so. */
424 switch (1 << power) {
425 case MMC_OCR_LOW_VOLTAGE:
426 pwr |= SDHCI_POWER_180;
428 case MMC_OCR_290_300:
429 case MMC_OCR_300_310:
430 pwr |= SDHCI_POWER_300;
432 case MMC_OCR_320_330:
433 case MMC_OCR_330_340:
434 pwr |= SDHCI_POWER_330;
437 WR1(slot, SDHCI_POWER_CONTROL, pwr);
439 * Turn on VDD1 power. Note that at least some Intel controllers can
440 * fail to enable bus power on the first try after transiting from D3
441 * to D0, so we give them up to 2 ms.
443 pwr |= SDHCI_POWER_ON;
444 for (i = 0; i < 20; i++) {
445 WR1(slot, SDHCI_POWER_CONTROL, pwr);
446 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
450 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
451 slot_printf(slot, "Bus power failed to enable");
453 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
454 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
456 WR1(slot, SDHCI_POWER_CONTROL, pwr);
462 sdhci_read_block_pio(struct sdhci_slot *slot)
468 buffer = slot->curcmd->data->data;
469 buffer += slot->offset;
470 /* Transfer one block at a time. */
471 left = min(512, slot->curcmd->data->len - slot->offset);
472 slot->offset += left;
474 /* If we are too fast, broken controllers return zeroes. */
475 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
477 /* Handle unaligned and aligned buffer cases. */
478 if ((intptr_t)buffer & 3) {
480 data = RD4(slot, SDHCI_BUFFER);
482 buffer[1] = (data >> 8);
483 buffer[2] = (data >> 16);
484 buffer[3] = (data >> 24);
489 RD_MULTI_4(slot, SDHCI_BUFFER,
490 (uint32_t *)buffer, left >> 2);
493 /* Handle uneven size case. */
495 data = RD4(slot, SDHCI_BUFFER);
505 sdhci_write_block_pio(struct sdhci_slot *slot)
511 buffer = slot->curcmd->data->data;
512 buffer += slot->offset;
513 /* Transfer one block at a time. */
514 left = min(512, slot->curcmd->data->len - slot->offset);
515 slot->offset += left;
517 /* Handle unaligned and aligned buffer cases. */
518 if ((intptr_t)buffer & 3) {
526 WR4(slot, SDHCI_BUFFER, data);
529 WR_MULTI_4(slot, SDHCI_BUFFER,
530 (uint32_t *)buffer, left >> 2);
533 /* Handle uneven size case. */
540 WR4(slot, SDHCI_BUFFER, data);
545 sdhci_transfer_pio(struct sdhci_slot *slot)
548 /* Read as many blocks as possible. */
549 if (slot->curcmd->data->flags & MMC_DATA_READ) {
550 while (RD4(slot, SDHCI_PRESENT_STATE) &
551 SDHCI_DATA_AVAILABLE) {
552 sdhci_read_block_pio(slot);
553 if (slot->offset >= slot->curcmd->data->len)
557 while (RD4(slot, SDHCI_PRESENT_STATE) &
558 SDHCI_SPACE_AVAILABLE) {
559 sdhci_write_block_pio(slot);
560 if (slot->offset >= slot->curcmd->data->len)
567 sdhci_card_task(void *arg, int pending __unused)
569 struct sdhci_slot *slot = arg;
573 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
575 if (slot->card_present == 0) {
577 if (slot->dev == NULL) {
579 /* If card is present - attach mmc bus. */
580 if (bootverbose || sdhci_debug)
581 slot_printf(slot, "Card inserted\n");
583 slot->card_present = 1;
586 pathid = cam_sim_path(slot->sim);
587 ccb = xpt_alloc_ccb_nowait();
589 slot_printf(slot, "Unable to alloc CCB for rescan\n");
595 * We create a rescan request for BUS:0:0, since the card
598 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid,
599 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) {
600 slot_printf(slot, "Unable to create path for rescan\n");
608 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
611 device_set_ivars(d, slot);
612 (void)device_probe_and_attach(d);
619 if (slot->card_present == 1) {
621 if (slot->dev != NULL) {
623 /* If no card present - detach mmc bus. */
624 if (bootverbose || sdhci_debug)
625 slot_printf(slot, "Card removed\n");
629 slot->card_present = 0;
632 pathid = cam_sim_path(slot->sim);
633 ccb = xpt_alloc_ccb_nowait();
635 slot_printf(slot, "Unable to alloc CCB for rescan\n");
641 * We create a rescan request for BUS:0:0, since the card
644 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid,
645 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) {
646 slot_printf(slot, "Unable to create path for rescan\n");
654 slot->intmask &= ~sdhci_tuning_intmask(slot);
655 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
656 slot->opt &= ~SDHCI_TUNING_ENABLED;
658 callout_drain(&slot->retune_callout);
659 device_delete_child(slot->bus, d);
667 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
672 * If there was no card and now there is one, schedule the task to
673 * create the child device after a short delay. The delay is to
674 * debounce the card insert (sometimes the card detect pin stabilizes
675 * before the other pins have made good contact).
677 * If there was a card present and now it's gone, immediately schedule
678 * the task to delete the child device. No debouncing -- gone is gone,
679 * because once power is removed, a full card re-init is needed, and
680 * that happens by deleting and recreating the child device.
683 was_present = slot->card_present;
685 was_present = slot->dev != NULL;
687 if (!was_present && is_present) {
688 taskqueue_enqueue_timeout(taskqueue_swi_giant,
689 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
690 } else if (was_present && !is_present) {
691 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
696 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
700 sdhci_handle_card_present_locked(slot, is_present);
705 sdhci_card_poll(void *arg)
707 struct sdhci_slot *slot = arg;
709 sdhci_handle_card_present(slot,
710 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
711 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
712 sdhci_card_poll, slot);
716 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
718 kobjop_desc_t kobj_desc;
719 kobj_method_t *kobj_method;
720 uint32_t caps, caps2, freq, host_caps;
723 SDHCI_LOCK_INIT(slot);
728 /* Allocate DMA tag. */
729 err = bus_dma_tag_create(bus_get_dma_tag(dev),
730 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
731 BUS_SPACE_MAXADDR, NULL, NULL,
732 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
733 BUS_DMA_ALLOCNOW, NULL, NULL,
736 device_printf(dev, "Can't create DMA tag\n");
737 SDHCI_LOCK_DESTROY(slot);
740 /* Allocate DMA memory. */
741 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
742 BUS_DMA_NOWAIT, &slot->dmamap);
744 device_printf(dev, "Can't alloc DMA memory\n");
745 bus_dma_tag_destroy(slot->dmatag);
746 SDHCI_LOCK_DESTROY(slot);
749 /* Map the memory. */
750 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
751 (void *)slot->dmamem, DMA_BLOCK_SIZE,
752 sdhci_getaddr, &slot->paddr, 0);
753 if (err != 0 || slot->paddr == 0) {
754 device_printf(dev, "Can't load DMA memory\n");
755 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
756 bus_dma_tag_destroy(slot->dmatag);
757 SDHCI_LOCK_DESTROY(slot);
764 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
765 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
766 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
770 caps = RD4(slot, SDHCI_CAPABILITIES);
771 if (slot->version >= SDHCI_SPEC_300)
772 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
776 if (slot->version >= SDHCI_SPEC_300) {
777 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
778 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
780 "Driver doesn't support shared bus slots\n");
781 bus_dmamap_unload(slot->dmatag, slot->dmamap);
782 bus_dmamem_free(slot->dmatag, slot->dmamem,
784 bus_dma_tag_destroy(slot->dmatag);
785 SDHCI_LOCK_DESTROY(slot);
787 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
788 SDHCI_SLOTTYPE_EMBEDDED) {
789 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
792 /* Calculate base clock frequency. */
793 if (slot->version >= SDHCI_SPEC_300)
794 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
795 SDHCI_CLOCK_BASE_SHIFT;
797 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
798 SDHCI_CLOCK_BASE_SHIFT;
800 slot->max_clk = freq * 1000000;
802 * If the frequency wasn't in the capabilities and the hardware driver
803 * hasn't already set max_clk we're probably not going to work right
804 * with an assumption, so complain about it.
806 if (slot->max_clk == 0) {
807 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
808 device_printf(dev, "Hardware doesn't specify base clock "
809 "frequency, using %dMHz as default.\n",
810 SDHCI_DEFAULT_MAX_FREQ);
812 /* Calculate/set timeout clock frequency. */
813 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
814 slot->timeout_clk = slot->max_clk / 1000;
815 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
816 slot->timeout_clk = 1000;
818 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
819 SDHCI_TIMEOUT_CLK_SHIFT;
820 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
821 slot->timeout_clk *= 1000;
824 * If the frequency wasn't in the capabilities and the hardware driver
825 * hasn't already set timeout_clk we'll probably work okay using the
826 * max timeout, but still mention it.
828 if (slot->timeout_clk == 0) {
829 device_printf(dev, "Hardware doesn't specify timeout clock "
830 "frequency, setting BROKEN_TIMEOUT quirk.\n");
831 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
834 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
835 slot->host.f_max = slot->max_clk;
836 slot->host.host_ocr = 0;
837 if (caps & SDHCI_CAN_VDD_330)
838 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
839 if (caps & SDHCI_CAN_VDD_300)
840 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
841 /* 1.8V VDD is not supposed to be used for removable cards. */
842 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
843 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
844 if (slot->host.host_ocr == 0) {
845 device_printf(dev, "Hardware doesn't report any "
846 "support voltages.\n");
849 host_caps = MMC_CAP_4_BIT_DATA;
850 if (caps & SDHCI_CAN_DO_8BITBUS)
851 host_caps |= MMC_CAP_8_BIT_DATA;
852 if (caps & SDHCI_CAN_DO_HISPD)
853 host_caps |= MMC_CAP_HSPEED;
854 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
855 host_caps |= MMC_CAP_BOOT_NOACC;
856 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
857 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
859 /* Determine supported UHS-I and eMMC modes. */
860 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
861 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
862 if (caps2 & SDHCI_CAN_SDR104) {
863 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
864 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
865 host_caps |= MMC_CAP_MMC_HS200;
866 } else if (caps2 & SDHCI_CAN_SDR50)
867 host_caps |= MMC_CAP_UHS_SDR50;
868 if (caps2 & SDHCI_CAN_DDR50 &&
869 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
870 host_caps |= MMC_CAP_UHS_DDR50;
871 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
872 host_caps |= MMC_CAP_MMC_DDR52;
873 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
874 caps2 & SDHCI_CAN_MMC_HS400)
875 host_caps |= MMC_CAP_MMC_HS400;
878 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
879 * default NULL implementation.
881 kobj_desc = &sdhci_set_uhs_timing_desc;
882 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
884 if (kobj_method == &kobj_desc->deflt)
885 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
886 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
887 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
889 #define SDHCI_CAP_MODES_TUNING(caps2) \
890 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
891 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
895 * Disable UHS-I and eMMC modes that require (re-)tuning if either
896 * the tune or re-tune method is the default NULL implementation.
898 kobj_desc = &mmcbr_tune_desc;
899 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
901 if (kobj_method == &kobj_desc->deflt)
903 kobj_desc = &mmcbr_retune_desc;
904 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
906 if (kobj_method == &kobj_desc->deflt) {
908 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
911 /* Allocate tuning structures and determine tuning parameters. */
912 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
913 slot->opt |= SDHCI_TUNING_SUPPORTED;
914 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
916 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
918 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
920 if (caps2 & SDHCI_TUNE_SDR50)
921 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
922 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
923 SDHCI_RETUNE_MODES_SHIFT;
924 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
925 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
926 SDHCI_RETUNE_CNT_SHIFT;
927 if (slot->retune_count > 0xb) {
928 device_printf(dev, "Unknown re-tuning count "
929 "%x, using 1 sec\n", slot->retune_count);
930 slot->retune_count = 1;
931 } else if (slot->retune_count != 0)
933 1 << (slot->retune_count - 1);
937 #undef SDHCI_CAP_MODES_TUNING
939 /* Determine supported VCCQ signaling levels. */
940 host_caps |= MMC_CAP_SIGNALING_330;
941 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
942 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
943 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
944 MMC_CAP_MMC_HS400_180))
945 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
948 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
949 * default NULL implementation. Disable 1.2 V support if it's the
950 * generic SDHCI implementation.
952 kobj_desc = &mmcbr_switch_vccq_desc;
953 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
955 if (kobj_method == &kobj_desc->deflt)
956 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
957 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
958 host_caps &= ~MMC_CAP_SIGNALING_120;
960 /* Determine supported driver types (type B is always mandatory). */
961 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
962 host_caps |= MMC_CAP_DRIVER_TYPE_A;
963 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
964 host_caps |= MMC_CAP_DRIVER_TYPE_C;
965 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
966 host_caps |= MMC_CAP_DRIVER_TYPE_D;
967 slot->host.caps = host_caps;
969 /* Decide if we have usable DMA. */
970 if (caps & SDHCI_CAN_DO_DMA)
971 slot->opt |= SDHCI_HAVE_DMA;
973 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
974 slot->opt &= ~SDHCI_HAVE_DMA;
975 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
976 slot->opt |= SDHCI_HAVE_DMA;
977 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
978 slot->opt |= SDHCI_NON_REMOVABLE;
981 * Use platform-provided transfer backend
982 * with PIO as a fallback mechanism
984 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
985 slot->opt &= ~SDHCI_HAVE_DMA;
987 if (bootverbose || sdhci_debug) {
989 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
990 slot->max_clk / 1000000,
991 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
992 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
993 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
994 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
995 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
996 ((caps & SDHCI_CAN_VDD_180) &&
997 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
998 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
999 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
1000 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
1001 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
1002 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
1003 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
1004 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
1005 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
1007 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
1008 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
1009 slot_printf(slot, "eMMC:%s%s%s%s\n",
1010 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
1011 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
1012 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
1014 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
1015 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
1017 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1018 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
1019 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
1020 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
1021 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
1022 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
1023 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
1024 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
1025 if (slot->opt & SDHCI_TUNING_SUPPORTED)
1026 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
1027 slot->retune_count, slot->retune_mode + 1);
1028 sdhci_dumpregs(slot);
1032 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1033 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1034 "timeout", CTLFLAG_RW, &slot->timeout, 0,
1035 "Maximum timeout for SDHCI transfers (in secs)");
1036 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1037 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1038 sdhci_card_task, slot);
1039 callout_init(&slot->card_poll_callout, 1);
1040 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1041 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1043 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1044 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1045 callout_reset(&slot->card_poll_callout,
1046 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1056 sdhci_start_slot(struct sdhci_slot *slot)
1059 sdhci_card_task(slot, 0);
1064 sdhci_cleanup_slot(struct sdhci_slot *slot)
1068 callout_drain(&slot->timeout_callout);
1069 callout_drain(&slot->card_poll_callout);
1070 callout_drain(&slot->retune_callout);
1071 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1072 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1079 device_delete_child(slot->bus, d);
1082 sdhci_reset(slot, SDHCI_RESET_ALL);
1084 bus_dmamap_unload(slot->dmatag, slot->dmamap);
1085 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
1086 bus_dma_tag_destroy(slot->dmatag);
1087 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1088 free(slot->tune_req, M_DEVBUF);
1089 free(slot->tune_cmd, M_DEVBUF);
1090 free(slot->tune_data, M_DEVBUF);
1093 SDHCI_LOCK_DESTROY(slot);
1099 sdhci_generic_suspend(struct sdhci_slot *slot)
1103 * We expect the MMC layer to issue initial tuning after resume.
1104 * Otherwise, we'd need to indicate re-tuning including circuit reset
1105 * being required at least for re-tuning modes 1 and 2 ourselves.
1107 callout_drain(&slot->retune_callout);
1109 slot->opt &= ~SDHCI_TUNING_ENABLED;
1110 sdhci_reset(slot, SDHCI_RESET_ALL);
1117 sdhci_generic_resume(struct sdhci_slot *slot)
1128 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1131 if (slot->version >= SDHCI_SPEC_300)
1132 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1134 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1138 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1141 if (slot->opt & SDHCI_NON_REMOVABLE)
1144 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1148 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1150 struct mmc_ios *ios;
1153 if (slot->version < SDHCI_SPEC_300)
1156 SDHCI_ASSERT_LOCKED(slot);
1157 ios = &slot->host.ios;
1158 sdhci_set_clock(slot, 0);
1159 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1160 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1161 if (ios->clock > SD_SDR50_MAX) {
1162 if (ios->timing == bus_timing_mmc_hs400 ||
1163 ios->timing == bus_timing_mmc_hs400es)
1164 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1166 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1168 else if (ios->clock > SD_SDR25_MAX)
1169 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1170 else if (ios->clock > SD_SDR12_MAX) {
1171 if (ios->timing == bus_timing_uhs_ddr50 ||
1172 ios->timing == bus_timing_mmc_ddr52)
1173 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1175 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1176 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1177 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1178 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1179 sdhci_set_clock(slot, ios->clock);
1183 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1185 struct sdhci_slot *slot = device_get_ivars(reqdev);
1186 struct mmc_ios *ios = &slot->host.ios;
1189 /* Do full reset on bus power down to clear from any state. */
1190 if (ios->power_mode == power_off) {
1191 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1194 /* Configure the bus. */
1195 sdhci_set_clock(slot, ios->clock);
1196 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1197 if (ios->bus_width == bus_width_8) {
1198 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1199 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1200 } else if (ios->bus_width == bus_width_4) {
1201 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1202 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1203 } else if (ios->bus_width == bus_width_1) {
1204 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1205 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1207 panic("Invalid bus width: %d", ios->bus_width);
1209 if (ios->clock > SD_SDR12_MAX &&
1210 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1211 slot->hostctrl |= SDHCI_CTRL_HISPD;
1213 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1214 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1215 SDHCI_SET_UHS_TIMING(brdev, slot);
1216 /* Some controllers like reset after bus changes. */
1217 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1218 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1225 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1227 struct sdhci_slot *slot = device_get_ivars(reqdev);
1232 if (slot->version < SDHCI_SPEC_300)
1236 vccq = slot->host.ios.vccq;
1238 sdhci_set_clock(slot, 0);
1239 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1242 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1244 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1245 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1247 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1248 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1253 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1257 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1259 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1260 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1262 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1263 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1269 "Attempt to set unsupported signaling voltage\n");
1274 sdhci_set_clock(slot, slot->host.ios.clock);
1280 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1282 struct sdhci_slot *slot = device_get_ivars(reqdev);
1283 struct mmc_ios *ios = &slot->host.ios;
1284 struct mmc_command *tune_cmd;
1285 struct mmc_data *tune_data;
1289 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1292 slot->retune_ticks = slot->retune_count * hz;
1293 opcode = MMC_SEND_TUNING_BLOCK;
1295 switch (ios->timing) {
1296 case bus_timing_mmc_hs400:
1297 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1300 case bus_timing_mmc_hs200:
1302 * In HS400 mode, controllers use the data strobe line to
1303 * latch data from the devices so periodic re-tuning isn't
1304 * expected to be required.
1307 slot->retune_ticks = 0;
1308 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1310 case bus_timing_uhs_ddr50:
1311 case bus_timing_uhs_sdr104:
1313 case bus_timing_uhs_sdr50:
1314 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1322 tune_cmd = slot->tune_cmd;
1323 memset(tune_cmd, 0, sizeof(*tune_cmd));
1324 tune_cmd->opcode = opcode;
1325 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1326 tune_data = tune_cmd->data = slot->tune_data;
1327 memset(tune_data, 0, sizeof(*tune_data));
1328 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1329 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1331 tune_data->flags = MMC_DATA_READ;
1332 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1334 slot->opt &= ~SDHCI_TUNING_ENABLED;
1335 err = sdhci_exec_tuning(slot, true);
1337 slot->opt |= SDHCI_TUNING_ENABLED;
1338 slot->intmask |= sdhci_tuning_intmask(slot);
1339 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1340 if (slot->retune_ticks) {
1341 callout_reset(&slot->retune_callout, slot->retune_ticks,
1342 sdhci_retune, slot);
1350 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1352 struct sdhci_slot *slot = device_get_ivars(reqdev);
1355 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1358 /* HS400 must be tuned in HS200 mode. */
1359 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1363 err = sdhci_exec_tuning(slot, reset);
1365 * There are two ways sdhci_exec_tuning() can fail:
1366 * EBUSY should not actually happen when requests are only issued
1367 * with the host properly acquired, and
1368 * EIO re-tuning failed (but it did work initially).
1370 * In both cases, we should retry at later point if periodic re-tuning
1371 * is enabled. Note that due to slot->retune_req not being cleared in
1372 * these failure cases, the MMC layer should trigger another attempt at
1373 * re-tuning with the next request anyway, though.
1375 if (slot->retune_ticks) {
1376 callout_reset(&slot->retune_callout, slot->retune_ticks,
1377 sdhci_retune, slot);
1384 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1386 struct mmc_request *tune_req;
1387 struct mmc_command *tune_cmd;
1393 SDHCI_ASSERT_LOCKED(slot);
1394 if (slot->req != NULL)
1397 /* Tuning doesn't work with DMA enabled. */
1399 slot->opt = opt & ~SDHCI_HAVE_DMA;
1402 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1403 * kind of interrupt we receive in response to a tuning request.
1405 intmask = slot->intmask;
1406 slot->intmask = SDHCI_INT_DATA_AVAIL;
1407 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1409 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1411 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1413 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1414 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1416 tune_req = slot->tune_req;
1417 tune_cmd = slot->tune_cmd;
1418 for (i = 0; i < MMC_TUNING_MAX; i++) {
1419 memset(tune_req, 0, sizeof(*tune_req));
1420 tune_req->cmd = tune_cmd;
1421 tune_req->done = sdhci_req_wakeup;
1422 tune_req->done_data = slot;
1423 slot->req = tune_req;
1426 while (!(tune_req->flags & MMC_REQ_DONE))
1427 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1428 if (!(tune_req->flags & MMC_TUNE_DONE))
1430 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1431 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1433 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1438 slot->intmask = intmask;
1439 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1441 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1442 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1443 slot->retune_req = 0;
1447 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1448 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1449 SDHCI_CTRL2_SAMPLING_CLOCK));
1450 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1455 sdhci_retune(void *arg)
1457 struct sdhci_slot *slot = arg;
1459 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1464 sdhci_req_done(struct sdhci_slot *slot)
1468 if (__predict_false(sdhci_debug > 1))
1469 slot_printf(slot, "%s\n", __func__);
1470 if (slot->ccb != NULL && slot->curcmd != NULL) {
1471 callout_stop(&slot->timeout_callout);
1474 slot->curcmd = NULL;
1476 /* Tell CAM the request is finished */
1477 struct ccb_mmcio *mmcio;
1478 mmcio = &ccb->mmcio;
1481 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1487 sdhci_req_done(struct sdhci_slot *slot)
1489 struct mmc_request *req;
1491 if (slot->req != NULL && slot->curcmd != NULL) {
1492 callout_stop(&slot->timeout_callout);
1495 slot->curcmd = NULL;
1502 sdhci_req_wakeup(struct mmc_request *req)
1504 struct sdhci_slot *slot;
1506 slot = req->done_data;
1507 req->flags |= MMC_REQ_DONE;
1512 sdhci_timeout(void *arg)
1514 struct sdhci_slot *slot = arg;
1516 if (slot->curcmd != NULL) {
1517 slot_printf(slot, "Controller timeout\n");
1518 sdhci_dumpregs(slot);
1519 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1520 slot->curcmd->error = MMC_ERR_TIMEOUT;
1521 sdhci_req_done(slot);
1523 slot_printf(slot, "Spurious timeout - no active command\n");
1528 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
1535 mode = SDHCI_TRNS_BLK_CNT_EN;
1536 if (data->len > 512)
1537 mode |= SDHCI_TRNS_MULTI;
1538 if (data->flags & MMC_DATA_READ)
1539 mode |= SDHCI_TRNS_READ;
1541 struct ccb_mmcio *mmcio;
1542 mmcio = &slot->ccb->mmcio;
1543 if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION
1544 && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))
1545 mode |= SDHCI_TRNS_ACMD12;
1547 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))
1548 mode |= SDHCI_TRNS_ACMD12;
1550 if (slot->flags & SDHCI_USE_DMA)
1551 mode |= SDHCI_TRNS_DMA;
1553 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1557 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1565 cmd->error = MMC_ERR_NONE;
1567 /* This flags combination is not supported by controller. */
1568 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1569 slot_printf(slot, "Unsupported response type!\n");
1570 cmd->error = MMC_ERR_FAILED;
1571 sdhci_req_done(slot);
1576 * Do not issue command if there is no card, clock or power.
1577 * Controller will not detect timeout without clock active.
1579 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1583 "Cannot issue a command (power=%d clock=%d)",
1584 slot->power, slot->clock);
1585 cmd->error = MMC_ERR_FAILED;
1586 sdhci_req_done(slot);
1589 /* Always wait for free CMD bus. */
1590 mask = SDHCI_CMD_INHIBIT;
1591 /* Wait for free DAT if we have data or busy signal. */
1592 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1593 mask |= SDHCI_DAT_INHIBIT;
1595 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1596 * that these latter are also special in that SDHCI_CMD_DATA should
1597 * be set below but no actual data is ever read from the controller.
1600 if (cmd == &slot->ccb->mmcio.stop ||
1602 if (cmd == slot->req->stop ||
1604 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1605 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1606 mask &= ~SDHCI_DAT_INHIBIT;
1608 * Wait for bus no more then 250 ms. Typically there will be no wait
1609 * here at all, but when writing a crash dump we may be bypassing the
1610 * host platform's interrupt handler, and in some cases that handler
1611 * may be working around hardware quirks such as not respecting r1b
1612 * busy indications. In those cases, this wait-loop serves the purpose
1613 * of waiting for the prior command and data transfers to be done, and
1614 * SD cards are allowed to take up to 250ms for write and erase ops.
1615 * (It's usually more like 20-30ms in the real world.)
1618 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1620 slot_printf(slot, "Controller never released "
1621 "inhibit bit(s).\n");
1622 sdhci_dumpregs(slot);
1623 cmd->error = MMC_ERR_FAILED;
1624 sdhci_req_done(slot);
1631 /* Prepare command flags. */
1632 if (!(cmd->flags & MMC_RSP_PRESENT))
1633 flags = SDHCI_CMD_RESP_NONE;
1634 else if (cmd->flags & MMC_RSP_136)
1635 flags = SDHCI_CMD_RESP_LONG;
1636 else if (cmd->flags & MMC_RSP_BUSY)
1637 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1639 flags = SDHCI_CMD_RESP_SHORT;
1640 if (cmd->flags & MMC_RSP_CRC)
1641 flags |= SDHCI_CMD_CRC;
1642 if (cmd->flags & MMC_RSP_OPCODE)
1643 flags |= SDHCI_CMD_INDEX;
1644 if (cmd->data != NULL)
1645 flags |= SDHCI_CMD_DATA;
1646 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1647 flags |= SDHCI_CMD_TYPE_ABORT;
1649 sdhci_start_data(slot, cmd->data);
1651 * Interrupt aggregation: To reduce total number of interrupts
1652 * group response interrupt with data interrupt when possible.
1653 * If there going to be data interrupt, mask response one.
1655 if (slot->data_done == 0) {
1656 WR4(slot, SDHCI_SIGNAL_ENABLE,
1657 slot->intmask &= ~SDHCI_INT_RESPONSE);
1659 /* Set command argument. */
1660 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1661 /* Set data transfer mode. */
1662 sdhci_set_transfer_mode(slot, cmd->data);
1663 if (__predict_false(sdhci_debug > 1))
1664 slot_printf(slot, "Starting command!\n");
1665 /* Start command. */
1666 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1667 /* Start timeout callout. */
1668 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1669 sdhci_timeout, slot);
1673 sdhci_finish_command(struct sdhci_slot *slot)
1679 if (__predict_false(sdhci_debug > 1))
1680 slot_printf(slot, "%s: called, err %d flags %d\n",
1681 __func__, slot->curcmd->error, slot->curcmd->flags);
1684 * Interrupt aggregation: Restore command interrupt.
1685 * Main restore point for the case when command interrupt
1688 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1689 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1690 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1691 SDHCI_INT_RESPONSE);
1692 /* In case of error - reset host and return. */
1693 if (slot->curcmd->error) {
1694 if (slot->curcmd->error == MMC_ERR_BADCRC)
1695 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1696 sdhci_reset(slot, SDHCI_RESET_CMD);
1697 sdhci_reset(slot, SDHCI_RESET_DATA);
1701 /* If command has response - fetch it. */
1702 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1703 if (slot->curcmd->flags & MMC_RSP_136) {
1704 /* CRC is stripped so we need one byte shift. */
1706 for (i = 0; i < 4; i++) {
1707 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1709 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1710 slot->curcmd->resp[3 - i] = val;
1712 slot->curcmd->resp[3 - i] =
1718 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1720 if (__predict_false(sdhci_debug > 1))
1721 printf("Resp: %02x %02x %02x %02x\n",
1722 slot->curcmd->resp[0], slot->curcmd->resp[1],
1723 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1725 /* If data ready - finish. */
1726 if (slot->data_done)
1731 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1733 uint32_t target_timeout, current_timeout;
1736 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1737 slot->data_done = 1;
1741 slot->data_done = 0;
1743 /* Calculate and set data timeout.*/
1744 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1745 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1748 target_timeout = 1000000;
1750 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1751 while (current_timeout < target_timeout && div < 0xE) {
1753 current_timeout <<= 1;
1755 /* Compensate for an off-by-one error in the CaFe chip.*/
1757 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1761 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1766 /* Use DMA if possible. */
1767 if ((slot->opt & SDHCI_HAVE_DMA))
1768 slot->flags |= SDHCI_USE_DMA;
1769 /* If data is small, broken DMA may return zeroes instead of data, */
1770 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1772 slot->flags &= ~SDHCI_USE_DMA;
1773 /* Some controllers require even block sizes. */
1774 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1775 ((data->len) & 0x3))
1776 slot->flags &= ~SDHCI_USE_DMA;
1777 /* Load DMA buffer. */
1778 if (slot->flags & SDHCI_USE_DMA) {
1779 if (data->flags & MMC_DATA_READ)
1780 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1781 BUS_DMASYNC_PREREAD);
1783 memcpy(slot->dmamem, data->data,
1784 (data->len < DMA_BLOCK_SIZE) ?
1785 data->len : DMA_BLOCK_SIZE);
1786 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1787 BUS_DMASYNC_PREWRITE);
1789 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1790 /* Interrupt aggregation: Mask border interrupt
1791 * for the last page and unmask else. */
1792 if (data->len == DMA_BLOCK_SIZE)
1793 slot->intmask &= ~SDHCI_INT_DMA_END;
1795 slot->intmask |= SDHCI_INT_DMA_END;
1796 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1798 /* Current data offset for both PIO and DMA. */
1800 /* Set block size and request IRQ on 4K border. */
1801 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
1802 (data->len < 512) ? data->len : 512));
1803 /* Set block count. */
1804 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1806 if (__predict_false(sdhci_debug > 1))
1807 slot_printf(slot, "Block size: %02x, count %lu\n",
1808 (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512),
1809 (unsigned long)(data->len + 511) / 512);
1813 sdhci_finish_data(struct sdhci_slot *slot)
1815 struct mmc_data *data = slot->curcmd->data;
1818 /* Interrupt aggregation: Restore command interrupt.
1819 * Auxiliary restore point for the case when data interrupt
1820 * happened first. */
1821 if (!slot->cmd_done) {
1822 WR4(slot, SDHCI_SIGNAL_ENABLE,
1823 slot->intmask |= SDHCI_INT_RESPONSE);
1825 /* Unload rest of data from DMA buffer. */
1826 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
1827 slot->curcmd->data != NULL) {
1828 if (data->flags & MMC_DATA_READ) {
1829 left = data->len - slot->offset;
1830 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1831 BUS_DMASYNC_POSTREAD);
1832 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1833 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1835 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1836 BUS_DMASYNC_POSTWRITE);
1838 slot->data_done = 1;
1839 /* If there was error - reset the host. */
1840 if (slot->curcmd->error) {
1841 if (slot->curcmd->error == MMC_ERR_BADCRC)
1842 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1843 sdhci_reset(slot, SDHCI_RESET_CMD);
1844 sdhci_reset(slot, SDHCI_RESET_DATA);
1848 /* If we already have command response - finish. */
1855 sdhci_start(struct sdhci_slot *slot)
1863 struct ccb_mmcio *mmcio;
1864 mmcio = &ccb->mmcio;
1866 if (!(slot->flags & CMD_STARTED)) {
1867 slot->flags |= CMD_STARTED;
1868 sdhci_start_command(slot, &mmcio->cmd);
1873 * Old stack doesn't use this!
1874 * Enabling this code causes significant performance degradation
1875 * and IRQ storms on BBB, Wandboard behaves fine.
1876 * Not using this code does no harm...
1877 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
1878 slot->flags |= STOP_STARTED;
1879 sdhci_start_command(slot, &mmcio->stop);
1883 if (__predict_false(sdhci_debug > 1))
1884 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
1885 if (mmcio->cmd.error == 0 &&
1886 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1887 sdhci_reset(slot, SDHCI_RESET_CMD);
1888 sdhci_reset(slot, SDHCI_RESET_DATA);
1891 sdhci_req_done(slot);
1895 sdhci_start(struct sdhci_slot *slot)
1897 struct mmc_request *req;
1903 if (!(slot->flags & CMD_STARTED)) {
1904 slot->flags |= CMD_STARTED;
1905 sdhci_start_command(slot, req->cmd);
1908 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
1909 !(slot->flags & STOP_STARTED) && req->stop) {
1910 slot->flags |= STOP_STARTED;
1911 sdhci_start_command(slot, req->stop);
1914 if (__predict_false(sdhci_debug > 1))
1915 slot_printf(slot, "result: %d\n", req->cmd->error);
1916 if (!req->cmd->error &&
1917 ((slot->curcmd == req->stop &&
1918 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
1919 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1920 sdhci_reset(slot, SDHCI_RESET_CMD);
1921 sdhci_reset(slot, SDHCI_RESET_DATA);
1924 sdhci_req_done(slot);
1929 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1930 struct mmc_request *req)
1932 struct sdhci_slot *slot = device_get_ivars(reqdev);
1935 if (slot->req != NULL) {
1939 if (__predict_false(sdhci_debug > 1)) {
1941 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1942 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1943 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1944 (req->cmd->data)?req->cmd->data->flags:0);
1951 while (slot->req != NULL) {
1952 sdhci_generic_intr(slot);
1960 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1962 struct sdhci_slot *slot = device_get_ivars(reqdev);
1966 val = RD4(slot, SDHCI_PRESENT_STATE);
1968 return (!(val & SDHCI_WRITE_PROTECT));
1972 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1974 struct sdhci_slot *slot = device_get_ivars(reqdev);
1978 while (slot->bus_busy)
1979 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1982 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1988 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1990 struct sdhci_slot *slot = device_get_ivars(reqdev);
1993 /* Deactivate led. */
1994 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2002 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
2005 if (!slot->curcmd) {
2006 slot_printf(slot, "Got command interrupt 0x%08x, but "
2007 "there is no active command.\n", intmask);
2008 sdhci_dumpregs(slot);
2011 if (intmask & SDHCI_INT_TIMEOUT)
2012 slot->curcmd->error = MMC_ERR_TIMEOUT;
2013 else if (intmask & SDHCI_INT_CRC)
2014 slot->curcmd->error = MMC_ERR_BADCRC;
2015 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
2016 slot->curcmd->error = MMC_ERR_FIFO;
2018 sdhci_finish_command(slot);
2022 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
2024 struct mmc_data *data;
2027 if (!slot->curcmd) {
2028 slot_printf(slot, "Got data interrupt 0x%08x, but "
2029 "there is no active command.\n", intmask);
2030 sdhci_dumpregs(slot);
2033 if (slot->curcmd->data == NULL &&
2034 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2035 slot_printf(slot, "Got data interrupt 0x%08x, but "
2036 "there is no active data operation.\n",
2038 sdhci_dumpregs(slot);
2041 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2042 slot->curcmd->error = MMC_ERR_TIMEOUT;
2043 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
2044 slot->curcmd->error = MMC_ERR_BADCRC;
2045 if (slot->curcmd->data == NULL &&
2046 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2047 SDHCI_INT_DMA_END))) {
2048 slot_printf(slot, "Got data interrupt 0x%08x, but "
2049 "there is busy-only command.\n", intmask);
2050 sdhci_dumpregs(slot);
2051 slot->curcmd->error = MMC_ERR_INVALID;
2053 if (slot->curcmd->error) {
2054 /* No need to continue after any error. */
2058 /* Handle tuning completion interrupt. */
2059 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
2060 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2061 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2062 slot->req->flags |= MMC_TUNE_DONE;
2063 sdhci_finish_command(slot);
2064 sdhci_finish_data(slot);
2067 /* Handle PIO interrupt. */
2068 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
2069 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2070 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2071 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2073 slot->flags |= PLATFORM_DATA_STARTED;
2075 sdhci_transfer_pio(slot);
2077 /* Handle DMA border. */
2078 if (intmask & SDHCI_INT_DMA_END) {
2079 data = slot->curcmd->data;
2081 /* Unload DMA buffer ... */
2082 left = data->len - slot->offset;
2083 if (data->flags & MMC_DATA_READ) {
2084 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2085 BUS_DMASYNC_POSTREAD);
2086 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2087 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
2089 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2090 BUS_DMASYNC_POSTWRITE);
2092 /* ... and reload it again. */
2093 slot->offset += DMA_BLOCK_SIZE;
2094 left = data->len - slot->offset;
2095 if (data->flags & MMC_DATA_READ) {
2096 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2097 BUS_DMASYNC_PREREAD);
2099 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2100 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
2101 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2102 BUS_DMASYNC_PREWRITE);
2104 /* Interrupt aggregation: Mask border interrupt
2105 * for the last page. */
2106 if (left == DMA_BLOCK_SIZE) {
2107 slot->intmask &= ~SDHCI_INT_DMA_END;
2108 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2111 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2113 /* We have got all data. */
2114 if (intmask & SDHCI_INT_DATA_END) {
2115 if (slot->flags & PLATFORM_DATA_STARTED) {
2116 slot->flags &= ~PLATFORM_DATA_STARTED;
2117 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2119 sdhci_finish_data(slot);
2122 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2123 if (slot->flags & PLATFORM_DATA_STARTED) {
2124 slot->flags &= ~PLATFORM_DATA_STARTED;
2125 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2127 sdhci_finish_data(slot);
2132 sdhci_acmd_irq(struct sdhci_slot *slot)
2136 err = RD4(slot, SDHCI_ACMD12_ERR);
2137 if (!slot->curcmd) {
2138 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2139 "there is no active command.\n", err);
2140 sdhci_dumpregs(slot);
2143 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
2144 sdhci_reset(slot, SDHCI_RESET_CMD);
2148 sdhci_generic_intr(struct sdhci_slot *slot)
2150 uint32_t intmask, present;
2153 /* Read slot interrupt status. */
2154 intmask = RD4(slot, SDHCI_INT_STATUS);
2155 if (intmask == 0 || intmask == 0xffffffff) {
2159 if (__predict_false(sdhci_debug > 2))
2160 slot_printf(slot, "Interrupt %#x\n", intmask);
2162 /* Handle tuning error interrupt. */
2163 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2164 slot_printf(slot, "Tuning error indicated\n");
2165 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2167 slot->curcmd->error = MMC_ERR_BADCRC;
2168 sdhci_finish_command(slot);
2171 /* Handle re-tuning interrupt. */
2172 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2173 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2174 /* Handle card presence interrupts. */
2175 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2176 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2178 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2179 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2180 SDHCI_INT_CARD_INSERT;
2181 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2182 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2183 WR4(slot, SDHCI_INT_STATUS, intmask &
2184 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2185 sdhci_handle_card_present_locked(slot, present);
2187 /* Handle command interrupts. */
2188 if (intmask & SDHCI_INT_CMD_MASK) {
2189 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2190 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2192 /* Handle data interrupts. */
2193 if (intmask & SDHCI_INT_DATA_MASK) {
2194 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2195 /* Don't call data_irq in case of errored command. */
2196 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2197 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2199 /* Handle AutoCMD12 error interrupt. */
2200 if (intmask & SDHCI_INT_ACMD12ERR) {
2201 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2202 sdhci_acmd_irq(slot);
2204 /* Handle bus power interrupt. */
2205 if (intmask & SDHCI_INT_BUS_POWER) {
2206 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2207 slot_printf(slot, "Card is consuming too much power!\n");
2209 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2210 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2211 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2212 /* The rest is unknown. */
2214 WR4(slot, SDHCI_INT_STATUS, intmask);
2215 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2217 sdhci_dumpregs(slot);
2224 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2227 struct sdhci_slot *slot = device_get_ivars(child);
2232 case MMCBR_IVAR_BUS_MODE:
2233 *result = slot->host.ios.bus_mode;
2235 case MMCBR_IVAR_BUS_WIDTH:
2236 *result = slot->host.ios.bus_width;
2238 case MMCBR_IVAR_CHIP_SELECT:
2239 *result = slot->host.ios.chip_select;
2241 case MMCBR_IVAR_CLOCK:
2242 *result = slot->host.ios.clock;
2244 case MMCBR_IVAR_F_MIN:
2245 *result = slot->host.f_min;
2247 case MMCBR_IVAR_F_MAX:
2248 *result = slot->host.f_max;
2250 case MMCBR_IVAR_HOST_OCR:
2251 *result = slot->host.host_ocr;
2253 case MMCBR_IVAR_MODE:
2254 *result = slot->host.mode;
2256 case MMCBR_IVAR_OCR:
2257 *result = slot->host.ocr;
2259 case MMCBR_IVAR_POWER_MODE:
2260 *result = slot->host.ios.power_mode;
2262 case MMCBR_IVAR_VDD:
2263 *result = slot->host.ios.vdd;
2265 case MMCBR_IVAR_RETUNE_REQ:
2266 if (slot->opt & SDHCI_TUNING_ENABLED) {
2267 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2268 *result = retune_req_reset;
2271 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2272 *result = retune_req_normal;
2276 *result = retune_req_none;
2278 case MMCBR_IVAR_VCCQ:
2279 *result = slot->host.ios.vccq;
2281 case MMCBR_IVAR_CAPS:
2282 *result = slot->host.caps;
2284 case MMCBR_IVAR_TIMING:
2285 *result = slot->host.ios.timing;
2287 case MMCBR_IVAR_MAX_DATA:
2289 * Re-tuning modes 1 and 2 restrict the maximum data length
2290 * per read/write command to 4 MiB.
2292 if (slot->opt & SDHCI_TUNING_ENABLED &&
2293 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2294 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2295 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2300 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2302 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2311 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2314 struct sdhci_slot *slot = device_get_ivars(child);
2315 uint32_t clock, max_clock;
2318 if (sdhci_debug > 1)
2319 slot_printf(slot, "%s: var=%d\n", __func__, which);
2323 case MMCBR_IVAR_BUS_MODE:
2324 slot->host.ios.bus_mode = value;
2326 case MMCBR_IVAR_BUS_WIDTH:
2327 slot->host.ios.bus_width = value;
2329 case MMCBR_IVAR_CHIP_SELECT:
2330 slot->host.ios.chip_select = value;
2332 case MMCBR_IVAR_CLOCK:
2334 max_clock = slot->max_clk;
2337 if (slot->version < SDHCI_SPEC_300) {
2338 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2345 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2349 clock = max_clock / (i + 2);
2353 slot->host.ios.clock = clock;
2355 slot->host.ios.clock = 0;
2357 case MMCBR_IVAR_MODE:
2358 slot->host.mode = value;
2360 case MMCBR_IVAR_OCR:
2361 slot->host.ocr = value;
2363 case MMCBR_IVAR_POWER_MODE:
2364 slot->host.ios.power_mode = value;
2366 case MMCBR_IVAR_VDD:
2367 slot->host.ios.vdd = value;
2369 case MMCBR_IVAR_VCCQ:
2370 slot->host.ios.vccq = value;
2372 case MMCBR_IVAR_TIMING:
2373 slot->host.ios.timing = value;
2375 case MMCBR_IVAR_CAPS:
2376 case MMCBR_IVAR_HOST_OCR:
2377 case MMCBR_IVAR_F_MIN:
2378 case MMCBR_IVAR_F_MAX:
2379 case MMCBR_IVAR_MAX_DATA:
2380 case MMCBR_IVAR_RETUNE_REQ:
2388 sdhci_start_slot(struct sdhci_slot *slot)
2390 if ((slot->devq = cam_simq_alloc(1)) == NULL) {
2394 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2395 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2396 "sdhci_slot", slot, device_get_unit(slot->bus),
2397 &slot->sim_mtx, 1, 1, slot->devq);
2399 if (slot->sim == NULL) {
2400 cam_simq_free(slot->devq);
2401 slot_printf(slot, "cannot allocate CAM SIM\n");
2405 mtx_lock(&slot->sim_mtx);
2406 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2408 "cannot register SCSI pass-through bus\n");
2409 cam_sim_free(slot->sim, FALSE);
2410 cam_simq_free(slot->devq);
2411 mtx_unlock(&slot->sim_mtx);
2415 mtx_unlock(&slot->sim_mtx);
2416 /* End CAM-specific init */
2417 slot->card_present = 0;
2418 sdhci_card_task(slot, 0);
2422 if (slot->sim != NULL) {
2423 mtx_lock(&slot->sim_mtx);
2424 xpt_bus_deregister(cam_sim_path(slot->sim));
2425 cam_sim_free(slot->sim, FALSE);
2426 mtx_unlock(&slot->sim_mtx);
2429 if (slot->devq != NULL)
2430 cam_simq_free(slot->devq);
2434 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb)
2436 struct sdhci_slot *slot;
2438 slot = cam_sim_softc(sim);
2440 sdhci_cam_request(slot, ccb);
2444 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb)
2446 struct sdhci_slot *slot;
2448 slot = cam_sim_softc(sim);
2450 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2455 mtx_assert(&slot->sim_mtx, MA_OWNED);
2457 switch (ccb->ccb_h.func_code) {
2460 struct ccb_pathinq *cpi;
2463 cpi->version_num = 1;
2464 cpi->hba_inquiry = 0;
2465 cpi->target_sprt = 0;
2466 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN;
2467 cpi->hba_eng_cnt = 0;
2468 cpi->max_target = 0;
2470 cpi->initiator_id = 1;
2471 cpi->maxio = MAXPHYS;
2472 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2473 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN);
2474 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2475 cpi->unit_number = cam_sim_unit(sim);
2476 cpi->bus_id = cam_sim_bus(sim);
2477 cpi->base_transfer_speed = 100; /* XXX WTF? */
2478 cpi->protocol = PROTO_MMCSD;
2479 cpi->protocol_version = SCSI_REV_0;
2480 cpi->transport = XPORT_MMCSD;
2481 cpi->transport_version = 0;
2483 cpi->ccb_h.status = CAM_REQ_CMP;
2486 case XPT_GET_TRAN_SETTINGS:
2488 struct ccb_trans_settings *cts = &ccb->cts;
2490 if (sdhci_debug > 1)
2491 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2493 cts->protocol = PROTO_MMCSD;
2494 cts->protocol_version = 1;
2495 cts->transport = XPORT_MMCSD;
2496 cts->transport_version = 1;
2497 cts->xport_specific.valid = 0;
2498 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2499 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2500 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2501 cts->proto_specific.mmc.host_caps = slot->host.caps;
2502 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2503 ccb->ccb_h.status = CAM_REQ_CMP;
2506 case XPT_SET_TRAN_SETTINGS:
2508 if (sdhci_debug > 1)
2509 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2510 sdhci_cam_settran_settings(slot, ccb);
2511 ccb->ccb_h.status = CAM_REQ_CMP;
2515 if (sdhci_debug > 1)
2516 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2517 ccb->ccb_h.status = CAM_REQ_CMP;
2521 * Here is the HW-dependent part of
2522 * sending the command to the underlying h/w
2523 * At some point in the future an interrupt comes.
2524 * Then the request will be marked as completed.
2526 if (__predict_false(sdhci_debug > 1))
2527 slot_printf(slot, "Got XPT_MMC_IO\n");
2528 ccb->ccb_h.status = CAM_REQ_INPROG;
2530 sdhci_cam_handle_mmcio(sim, ccb);
2535 ccb->ccb_h.status = CAM_REQ_INVALID;
2543 sdhci_cam_poll(struct cam_sim *sim)
2548 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) {
2549 int max_clock, clock, i;
2551 if (proposed_clock == 0)
2553 max_clock = slot->max_clk;
2556 if (slot->version < SDHCI_SPEC_300) {
2557 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2559 if (clock <= proposed_clock)
2564 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2566 if (clock <= proposed_clock)
2568 clock = max_clock / (i + 2);
2575 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb)
2577 struct mmc_ios *ios;
2578 struct mmc_ios *new_ios;
2579 struct ccb_trans_settings_mmc *cts;
2581 ios = &slot->host.ios;
2583 cts = &ccb->cts.proto_specific.mmc;
2584 new_ios = &cts->ios;
2586 /* Update only requested fields */
2587 if (cts->ios_valid & MMC_CLK) {
2588 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2589 slot_printf(slot, "Clock => %d\n", ios->clock);
2591 if (cts->ios_valid & MMC_VDD) {
2592 ios->vdd = new_ios->vdd;
2593 slot_printf(slot, "VDD => %d\n", ios->vdd);
2595 if (cts->ios_valid & MMC_CS) {
2596 ios->chip_select = new_ios->chip_select;
2597 slot_printf(slot, "CS => %d\n", ios->chip_select);
2599 if (cts->ios_valid & MMC_BW) {
2600 ios->bus_width = new_ios->bus_width;
2601 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2603 if (cts->ios_valid & MMC_PM) {
2604 ios->power_mode = new_ios->power_mode;
2605 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2607 if (cts->ios_valid & MMC_BT) {
2608 ios->timing = new_ios->timing;
2609 slot_printf(slot, "Timing => %d\n", ios->timing);
2611 if (cts->ios_valid & MMC_BM) {
2612 ios->bus_mode = new_ios->bus_mode;
2613 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2616 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2617 return (sdhci_cam_update_ios(slot));
2621 sdhci_cam_update_ios(struct sdhci_slot *slot)
2623 struct mmc_ios *ios = &slot->host.ios;
2625 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2626 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2628 /* Do full reset on bus power down to clear from any state. */
2629 if (ios->power_mode == power_off) {
2630 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2633 /* Configure the bus. */
2634 sdhci_set_clock(slot, ios->clock);
2635 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2636 if (ios->bus_width == bus_width_8) {
2637 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2638 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2639 } else if (ios->bus_width == bus_width_4) {
2640 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2641 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2642 } else if (ios->bus_width == bus_width_1) {
2643 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2644 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2646 panic("Invalid bus width: %d", ios->bus_width);
2648 if (ios->timing == bus_timing_hs &&
2649 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2650 slot->hostctrl |= SDHCI_CTRL_HISPD;
2652 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2653 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2654 /* Some controllers like reset after bus changes. */
2655 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2656 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2663 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb)
2665 struct ccb_mmcio *mmcio;
2667 mmcio = &ccb->mmcio;
2670 /* if (slot->req != NULL) {
2675 if (__predict_false(sdhci_debug > 1)) {
2676 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
2677 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2678 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2679 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
2681 if (mmcio->cmd.data != NULL) {
2682 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2683 panic("data->len = %d, data->flags = %d -- something is b0rked",
2684 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2691 while (slot->ccb != NULL) {
2692 sdhci_generic_intr(slot);
2700 MODULE_VERSION(sdhci, 1);