2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/callout.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
57 static int sdhci_debug;
58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level");
60 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
61 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
62 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
63 #define RD_MULTI_4(slot, off, ptr, count) \
64 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
66 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
67 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
68 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
69 #define WR_MULTI_4(slot, off, ptr, count) \
70 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
72 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
73 static void sdhci_start(struct sdhci_slot *slot);
74 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
76 static void sdhci_card_poll(void *);
77 static void sdhci_card_task(void *, int);
80 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
81 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
82 #define SDHCI_LOCK_INIT(_slot) \
83 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
84 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
85 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
86 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
88 #define SDHCI_DEFAULT_MAX_FREQ 50
90 #define SDHCI_200_MAX_DIVIDER 256
91 #define SDHCI_300_MAX_DIVIDER 2046
93 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
94 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
97 * Broadcom BCM577xx Controller Constants
99 /* Maximum divider supported by the default clock source. */
100 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
101 /* Alternative clock's base frequency. */
102 #define BCM577XX_ALT_CLOCK_BASE 63000000
104 #define BCM577XX_HOST_CONTROL 0x198
105 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
106 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
107 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
108 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
112 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
115 printf("getaddr: error %d\n", error);
118 *(bus_addr_t *)arg = segs[0].ds_addr;
122 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
127 retval = printf("%s-slot%d: ",
128 device_get_nameunit(slot->bus), slot->num);
131 retval += vprintf(fmt, ap);
137 sdhci_dumpregs(struct sdhci_slot *slot)
140 "============== REGISTER DUMP ==============\n");
142 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
143 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
144 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
145 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
146 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
147 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
148 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
149 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
150 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
151 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
152 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
153 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
154 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
155 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
156 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
157 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
158 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
159 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
160 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
161 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
164 "===========================================\n");
168 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
172 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
173 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
177 /* Some controllers need this kick or reset won't work. */
178 if ((mask & SDHCI_RESET_ALL) == 0 &&
179 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
182 /* This is to force an update */
185 sdhci_set_clock(slot, clock);
188 if (mask & SDHCI_RESET_ALL) {
193 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
195 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
197 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
198 * specification. The reset bit has internal propagation delay,
199 * so a fast read after write returns 0 even if reset process is
200 * in progress. The workaround is to poll for 1 before polling
201 * for 0. In the worst case, if we miss seeing it asserted the
202 * time we spent waiting is enough to ensure the reset finishes.
205 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
213 /* Wait max 100 ms */
215 /* Controller clears the bits when it's done */
216 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
218 slot_printf(slot, "Reset 0x%x never completed.\n",
220 sdhci_dumpregs(slot);
229 sdhci_init(struct sdhci_slot *slot)
232 sdhci_reset(slot, SDHCI_RESET_ALL);
234 /* Enable interrupts. */
235 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
237 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
238 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
239 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
242 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
243 !(slot->opt & SDHCI_NON_REMOVABLE)) {
244 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
247 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
248 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
252 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
261 if (clock == slot->clock)
265 /* Turn off the clock. */
266 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
267 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
268 /* If no clock requested - left it so. */
272 /* Determine the clock base frequency */
273 clk_base = slot->max_clk;
274 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
275 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
276 BCM577XX_CTRL_CLKSEL_MASK;
279 * Select clock source appropriate for the requested frequency.
281 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
282 clk_base = BCM577XX_ALT_CLOCK_BASE;
283 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
284 BCM577XX_CTRL_CLKSEL_SHIFT);
286 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
287 BCM577XX_CTRL_CLKSEL_SHIFT);
290 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
293 /* Recalculate timeout clock frequency based on the new sd clock. */
294 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
295 slot->timeout_clk = slot->clock / 1000;
297 if (slot->version < SDHCI_SPEC_300) {
298 /* Looking for highest freq <= clock. */
300 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
305 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
309 /* Version 3.0 divisors are multiples of two up to 1023*2 */
310 if (clock >= clk_base)
313 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
314 if ((clk_base / div) <= clock)
321 if (bootverbose || sdhci_debug)
322 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
323 div, clock, clk_base);
325 /* Now we have got divider, set it. */
326 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
327 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
328 << SDHCI_DIVIDER_HI_SHIFT;
330 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
332 clk |= SDHCI_CLOCK_INT_EN;
333 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
334 /* Wait up to 10 ms until it stabilize. */
336 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
337 & SDHCI_CLOCK_INT_STABLE)) {
340 "Internal clock never stabilised.\n");
341 sdhci_dumpregs(slot);
347 /* Pass clock signal to the bus. */
348 clk |= SDHCI_CLOCK_CARD_EN;
349 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
353 sdhci_set_power(struct sdhci_slot *slot, u_char power)
357 if (slot->power == power)
362 /* Turn off the power. */
364 WR1(slot, SDHCI_POWER_CONTROL, pwr);
365 /* If power down requested - left it so. */
369 switch (1 << power) {
370 case MMC_OCR_LOW_VOLTAGE:
371 pwr |= SDHCI_POWER_180;
373 case MMC_OCR_290_300:
374 case MMC_OCR_300_310:
375 pwr |= SDHCI_POWER_300;
377 case MMC_OCR_320_330:
378 case MMC_OCR_330_340:
379 pwr |= SDHCI_POWER_330;
382 WR1(slot, SDHCI_POWER_CONTROL, pwr);
383 /* Turn on the power. */
384 pwr |= SDHCI_POWER_ON;
385 WR1(slot, SDHCI_POWER_CONTROL, pwr);
387 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
388 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
390 WR1(slot, SDHCI_POWER_CONTROL, pwr);
396 sdhci_read_block_pio(struct sdhci_slot *slot)
402 buffer = slot->curcmd->data->data;
403 buffer += slot->offset;
404 /* Transfer one block at a time. */
405 left = min(512, slot->curcmd->data->len - slot->offset);
406 slot->offset += left;
408 /* If we are too fast, broken controllers return zeroes. */
409 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
411 /* Handle unaligned and aligned buffer cases. */
412 if ((intptr_t)buffer & 3) {
414 data = RD4(slot, SDHCI_BUFFER);
416 buffer[1] = (data >> 8);
417 buffer[2] = (data >> 16);
418 buffer[3] = (data >> 24);
423 RD_MULTI_4(slot, SDHCI_BUFFER,
424 (uint32_t *)buffer, left >> 2);
427 /* Handle uneven size case. */
429 data = RD4(slot, SDHCI_BUFFER);
439 sdhci_write_block_pio(struct sdhci_slot *slot)
445 buffer = slot->curcmd->data->data;
446 buffer += slot->offset;
447 /* Transfer one block at a time. */
448 left = min(512, slot->curcmd->data->len - slot->offset);
449 slot->offset += left;
451 /* Handle unaligned and aligned buffer cases. */
452 if ((intptr_t)buffer & 3) {
460 WR4(slot, SDHCI_BUFFER, data);
463 WR_MULTI_4(slot, SDHCI_BUFFER,
464 (uint32_t *)buffer, left >> 2);
467 /* Handle uneven size case. */
474 WR4(slot, SDHCI_BUFFER, data);
479 sdhci_transfer_pio(struct sdhci_slot *slot)
482 /* Read as many blocks as possible. */
483 if (slot->curcmd->data->flags & MMC_DATA_READ) {
484 while (RD4(slot, SDHCI_PRESENT_STATE) &
485 SDHCI_DATA_AVAILABLE) {
486 sdhci_read_block_pio(slot);
487 if (slot->offset >= slot->curcmd->data->len)
491 while (RD4(slot, SDHCI_PRESENT_STATE) &
492 SDHCI_SPACE_AVAILABLE) {
493 sdhci_write_block_pio(slot);
494 if (slot->offset >= slot->curcmd->data->len)
501 sdhci_card_task(void *arg, int pending)
503 struct sdhci_slot *slot = arg;
506 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
507 if (slot->dev == NULL) {
508 /* If card is present - attach mmc bus. */
509 if (bootverbose || sdhci_debug)
510 slot_printf(slot, "Card inserted\n");
511 slot->dev = device_add_child(slot->bus, "mmc", -1);
512 device_set_ivars(slot->dev, slot);
514 device_probe_and_attach(slot->dev);
518 if (slot->dev != NULL) {
519 /* If no card present - detach mmc bus. */
520 if (bootverbose || sdhci_debug)
521 slot_printf(slot, "Card removed\n");
522 device_t d = slot->dev;
525 device_delete_child(slot->bus, d);
532 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
537 * If there was no card and now there is one, schedule the task to
538 * create the child device after a short delay. The delay is to
539 * debounce the card insert (sometimes the card detect pin stabilizes
540 * before the other pins have made good contact).
542 * If there was a card present and now it's gone, immediately schedule
543 * the task to delete the child device. No debouncing -- gone is gone,
544 * because once power is removed, a full card re-init is needed, and
545 * that happens by deleting and recreating the child device.
547 was_present = slot->dev != NULL;
548 if (!was_present && is_present) {
549 taskqueue_enqueue_timeout(taskqueue_swi_giant,
550 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
551 } else if (was_present && !is_present) {
552 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
557 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
561 sdhci_handle_card_present_locked(slot, is_present);
566 sdhci_card_poll(void *arg)
568 struct sdhci_slot *slot = arg;
570 sdhci_handle_card_present(slot,
571 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
572 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
573 sdhci_card_poll, slot);
577 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
582 SDHCI_LOCK_INIT(slot);
586 /* Allocate DMA tag. */
587 err = bus_dma_tag_create(bus_get_dma_tag(dev),
588 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
589 BUS_SPACE_MAXADDR, NULL, NULL,
590 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
591 BUS_DMA_ALLOCNOW, NULL, NULL,
594 device_printf(dev, "Can't create DMA tag\n");
595 SDHCI_LOCK_DESTROY(slot);
598 /* Allocate DMA memory. */
599 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
600 BUS_DMA_NOWAIT, &slot->dmamap);
602 device_printf(dev, "Can't alloc DMA memory\n");
603 SDHCI_LOCK_DESTROY(slot);
606 /* Map the memory. */
607 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
608 (void *)slot->dmamem, DMA_BLOCK_SIZE,
609 sdhci_getaddr, &slot->paddr, 0);
610 if (err != 0 || slot->paddr == 0) {
611 device_printf(dev, "Can't load DMA memory\n");
612 SDHCI_LOCK_DESTROY(slot);
619 /* Initialize slot. */
621 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
622 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
623 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
626 caps = RD4(slot, SDHCI_CAPABILITIES);
627 /* Calculate base clock frequency. */
628 if (slot->version >= SDHCI_SPEC_300)
629 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
630 SDHCI_CLOCK_BASE_SHIFT;
632 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
633 SDHCI_CLOCK_BASE_SHIFT;
635 slot->max_clk = freq * 1000000;
637 * If the frequency wasn't in the capabilities and the hardware driver
638 * hasn't already set max_clk we're probably not going to work right
639 * with an assumption, so complain about it.
641 if (slot->max_clk == 0) {
642 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
643 device_printf(dev, "Hardware doesn't specify base clock "
644 "frequency, using %dMHz as default.\n",
645 SDHCI_DEFAULT_MAX_FREQ);
647 /* Calculate/set timeout clock frequency. */
648 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
649 slot->timeout_clk = slot->max_clk / 1000;
650 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
651 slot->timeout_clk = 1000;
653 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
654 SDHCI_TIMEOUT_CLK_SHIFT;
655 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
656 slot->timeout_clk *= 1000;
659 * If the frequency wasn't in the capabilities and the hardware driver
660 * hasn't already set timeout_clk we'll probably work okay using the
661 * max timeout, but still mention it.
663 if (slot->timeout_clk == 0) {
664 device_printf(dev, "Hardware doesn't specify timeout clock "
665 "frequency, setting BROKEN_TIMEOUT quirk.\n");
666 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
669 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
670 slot->host.f_max = slot->max_clk;
671 slot->host.host_ocr = 0;
672 if (caps & SDHCI_CAN_VDD_330)
673 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
674 if (caps & SDHCI_CAN_VDD_300)
675 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
676 if (caps & SDHCI_CAN_VDD_180)
677 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
678 if (slot->host.host_ocr == 0) {
679 device_printf(dev, "Hardware doesn't report any "
680 "support voltages.\n");
682 slot->host.caps = MMC_CAP_4_BIT_DATA;
683 if (caps & SDHCI_CAN_DO_8BITBUS)
684 slot->host.caps |= MMC_CAP_8_BIT_DATA;
685 if (caps & SDHCI_CAN_DO_HISPD)
686 slot->host.caps |= MMC_CAP_HSPEED;
687 /* Decide if we have usable DMA. */
688 if (caps & SDHCI_CAN_DO_DMA)
689 slot->opt |= SDHCI_HAVE_DMA;
691 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
692 slot->opt &= ~SDHCI_HAVE_DMA;
693 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
694 slot->opt |= SDHCI_HAVE_DMA;
695 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
696 slot->opt |= SDHCI_NON_REMOVABLE;
699 * Use platform-provided transfer backend
700 * with PIO as a fallback mechanism
702 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
703 slot->opt &= ~SDHCI_HAVE_DMA;
705 if (bootverbose || sdhci_debug) {
706 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n",
707 slot->max_clk / 1000000,
708 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
709 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
710 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" :
712 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
713 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
714 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
715 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
716 sdhci_dumpregs(slot);
720 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
721 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
722 "timeout", CTLFLAG_RW, &slot->timeout, 0,
723 "Maximum timeout for SDHCI transfers (in secs)");
724 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
725 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
726 sdhci_card_task, slot);
727 callout_init(&slot->card_poll_callout, 1);
728 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
730 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
731 !(slot->opt & SDHCI_NON_REMOVABLE)) {
732 callout_reset(&slot->card_poll_callout,
733 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
740 sdhci_start_slot(struct sdhci_slot *slot)
742 sdhci_card_task(slot, 0);
746 sdhci_cleanup_slot(struct sdhci_slot *slot)
750 callout_drain(&slot->timeout_callout);
751 callout_drain(&slot->card_poll_callout);
752 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
753 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
760 device_delete_child(slot->bus, d);
763 sdhci_reset(slot, SDHCI_RESET_ALL);
765 bus_dmamap_unload(slot->dmatag, slot->dmamap);
766 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
767 bus_dma_tag_destroy(slot->dmatag);
769 SDHCI_LOCK_DESTROY(slot);
775 sdhci_generic_suspend(struct sdhci_slot *slot)
777 sdhci_reset(slot, SDHCI_RESET_ALL);
783 sdhci_generic_resume(struct sdhci_slot *slot)
791 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
793 if (slot->version >= SDHCI_SPEC_300)
794 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
796 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
800 sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot)
803 if (slot->opt & SDHCI_NON_REMOVABLE)
806 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
810 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
812 struct sdhci_slot *slot = device_get_ivars(reqdev);
813 struct mmc_ios *ios = &slot->host.ios;
816 /* Do full reset on bus power down to clear from any state. */
817 if (ios->power_mode == power_off) {
818 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
821 /* Configure the bus. */
822 sdhci_set_clock(slot, ios->clock);
823 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
824 if (ios->bus_width == bus_width_8) {
825 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
826 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
827 } else if (ios->bus_width == bus_width_4) {
828 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
829 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
830 } else if (ios->bus_width == bus_width_1) {
831 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
832 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
834 panic("Invalid bus width: %d", ios->bus_width);
836 if (ios->timing == bus_timing_hs &&
837 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
838 slot->hostctrl |= SDHCI_CTRL_HISPD;
840 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
841 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
842 /* Some controllers like reset after bus changes. */
843 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
844 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
851 sdhci_req_done(struct sdhci_slot *slot)
853 struct mmc_request *req;
855 if (slot->req != NULL && slot->curcmd != NULL) {
856 callout_stop(&slot->timeout_callout);
865 sdhci_timeout(void *arg)
867 struct sdhci_slot *slot = arg;
869 if (slot->curcmd != NULL) {
870 slot_printf(slot, " Controller timeout\n");
871 sdhci_dumpregs(slot);
872 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
873 slot->curcmd->error = MMC_ERR_TIMEOUT;
874 sdhci_req_done(slot);
876 slot_printf(slot, " Spurious timeout - no active command\n");
881 sdhci_set_transfer_mode(struct sdhci_slot *slot,
882 struct mmc_data *data)
889 mode = SDHCI_TRNS_BLK_CNT_EN;
891 mode |= SDHCI_TRNS_MULTI;
892 if (data->flags & MMC_DATA_READ)
893 mode |= SDHCI_TRNS_READ;
895 mode |= SDHCI_TRNS_ACMD12;
896 if (slot->flags & SDHCI_USE_DMA)
897 mode |= SDHCI_TRNS_DMA;
899 WR2(slot, SDHCI_TRANSFER_MODE, mode);
903 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
911 cmd->error = MMC_ERR_NONE;
913 /* This flags combination is not supported by controller. */
914 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
915 slot_printf(slot, "Unsupported response type!\n");
916 cmd->error = MMC_ERR_FAILED;
917 sdhci_req_done(slot);
921 /* Do not issue command if there is no card, clock or power.
922 * Controller will not detect timeout without clock active. */
923 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
926 cmd->error = MMC_ERR_FAILED;
927 sdhci_req_done(slot);
930 /* Always wait for free CMD bus. */
931 mask = SDHCI_CMD_INHIBIT;
932 /* Wait for free DAT if we have data or busy signal. */
933 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
934 mask |= SDHCI_DAT_INHIBIT;
935 /* We shouldn't wait for DAT for stop commands. */
936 if (cmd == slot->req->stop)
937 mask &= ~SDHCI_DAT_INHIBIT;
939 * Wait for bus no more then 250 ms. Typically there will be no wait
940 * here at all, but when writing a crash dump we may be bypassing the
941 * host platform's interrupt handler, and in some cases that handler
942 * may be working around hardware quirks such as not respecting r1b
943 * busy indications. In those cases, this wait-loop serves the purpose
944 * of waiting for the prior command and data transfers to be done, and
945 * SD cards are allowed to take up to 250ms for write and erase ops.
946 * (It's usually more like 20-30ms in the real world.)
949 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
951 slot_printf(slot, "Controller never released "
952 "inhibit bit(s).\n");
953 sdhci_dumpregs(slot);
954 cmd->error = MMC_ERR_FAILED;
955 sdhci_req_done(slot);
962 /* Prepare command flags. */
963 if (!(cmd->flags & MMC_RSP_PRESENT))
964 flags = SDHCI_CMD_RESP_NONE;
965 else if (cmd->flags & MMC_RSP_136)
966 flags = SDHCI_CMD_RESP_LONG;
967 else if (cmd->flags & MMC_RSP_BUSY)
968 flags = SDHCI_CMD_RESP_SHORT_BUSY;
970 flags = SDHCI_CMD_RESP_SHORT;
971 if (cmd->flags & MMC_RSP_CRC)
972 flags |= SDHCI_CMD_CRC;
973 if (cmd->flags & MMC_RSP_OPCODE)
974 flags |= SDHCI_CMD_INDEX;
976 flags |= SDHCI_CMD_DATA;
977 if (cmd->opcode == MMC_STOP_TRANSMISSION)
978 flags |= SDHCI_CMD_TYPE_ABORT;
980 sdhci_start_data(slot, cmd->data);
982 * Interrupt aggregation: To reduce total number of interrupts
983 * group response interrupt with data interrupt when possible.
984 * If there going to be data interrupt, mask response one.
986 if (slot->data_done == 0) {
987 WR4(slot, SDHCI_SIGNAL_ENABLE,
988 slot->intmask &= ~SDHCI_INT_RESPONSE);
990 /* Set command argument. */
991 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
992 /* Set data transfer mode. */
993 sdhci_set_transfer_mode(slot, cmd->data);
995 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
996 /* Start timeout callout. */
997 callout_reset(&slot->timeout_callout, slot->timeout * hz,
998 sdhci_timeout, slot);
1002 sdhci_finish_command(struct sdhci_slot *slot)
1009 /* Interrupt aggregation: Restore command interrupt.
1010 * Main restore point for the case when command interrupt
1011 * happened first. */
1012 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
1013 /* In case of error - reset host and return. */
1014 if (slot->curcmd->error) {
1015 sdhci_reset(slot, SDHCI_RESET_CMD);
1016 sdhci_reset(slot, SDHCI_RESET_DATA);
1020 /* If command has response - fetch it. */
1021 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1022 if (slot->curcmd->flags & MMC_RSP_136) {
1023 /* CRC is stripped so we need one byte shift. */
1025 for (i = 0; i < 4; i++) {
1026 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1028 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1029 slot->curcmd->resp[3 - i] = val;
1031 slot->curcmd->resp[3 - i] =
1037 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1039 /* If data ready - finish. */
1040 if (slot->data_done)
1045 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1047 uint32_t target_timeout, current_timeout;
1050 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1051 slot->data_done = 1;
1055 slot->data_done = 0;
1057 /* Calculate and set data timeout.*/
1058 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1059 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1062 target_timeout = 1000000;
1064 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1065 while (current_timeout < target_timeout && div < 0xE) {
1067 current_timeout <<= 1;
1069 /* Compensate for an off-by-one error in the CaFe chip.*/
1071 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1075 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1080 /* Use DMA if possible. */
1081 if ((slot->opt & SDHCI_HAVE_DMA))
1082 slot->flags |= SDHCI_USE_DMA;
1083 /* If data is small, broken DMA may return zeroes instead of data, */
1084 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1086 slot->flags &= ~SDHCI_USE_DMA;
1087 /* Some controllers require even block sizes. */
1088 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1089 ((data->len) & 0x3))
1090 slot->flags &= ~SDHCI_USE_DMA;
1091 /* Load DMA buffer. */
1092 if (slot->flags & SDHCI_USE_DMA) {
1093 if (data->flags & MMC_DATA_READ)
1094 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1095 BUS_DMASYNC_PREREAD);
1097 memcpy(slot->dmamem, data->data,
1098 (data->len < DMA_BLOCK_SIZE) ?
1099 data->len : DMA_BLOCK_SIZE);
1100 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1101 BUS_DMASYNC_PREWRITE);
1103 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1104 /* Interrupt aggregation: Mask border interrupt
1105 * for the last page and unmask else. */
1106 if (data->len == DMA_BLOCK_SIZE)
1107 slot->intmask &= ~SDHCI_INT_DMA_END;
1109 slot->intmask |= SDHCI_INT_DMA_END;
1110 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1112 /* Current data offset for both PIO and DMA. */
1114 /* Set block size and request IRQ on 4K border. */
1115 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
1116 (data->len < 512) ? data->len : 512));
1117 /* Set block count. */
1118 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1122 sdhci_finish_data(struct sdhci_slot *slot)
1124 struct mmc_data *data = slot->curcmd->data;
1126 /* Interrupt aggregation: Restore command interrupt.
1127 * Auxiliary restore point for the case when data interrupt
1128 * happened first. */
1129 if (!slot->cmd_done) {
1130 WR4(slot, SDHCI_SIGNAL_ENABLE,
1131 slot->intmask |= SDHCI_INT_RESPONSE);
1133 /* Unload rest of data from DMA buffer. */
1134 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
1135 if (data->flags & MMC_DATA_READ) {
1136 size_t left = data->len - slot->offset;
1137 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1138 BUS_DMASYNC_POSTREAD);
1139 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1140 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1142 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1143 BUS_DMASYNC_POSTWRITE);
1145 slot->data_done = 1;
1146 /* If there was error - reset the host. */
1147 if (slot->curcmd->error) {
1148 sdhci_reset(slot, SDHCI_RESET_CMD);
1149 sdhci_reset(slot, SDHCI_RESET_DATA);
1153 /* If we already have command response - finish. */
1159 sdhci_start(struct sdhci_slot *slot)
1161 struct mmc_request *req;
1167 if (!(slot->flags & CMD_STARTED)) {
1168 slot->flags |= CMD_STARTED;
1169 sdhci_start_command(slot, req->cmd);
1172 /* We don't need this until using Auto-CMD12 feature
1173 if (!(slot->flags & STOP_STARTED) && req->stop) {
1174 slot->flags |= STOP_STARTED;
1175 sdhci_start_command(slot, req->stop);
1179 if (sdhci_debug > 1)
1180 slot_printf(slot, "result: %d\n", req->cmd->error);
1181 if (!req->cmd->error &&
1182 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1183 sdhci_reset(slot, SDHCI_RESET_CMD);
1184 sdhci_reset(slot, SDHCI_RESET_DATA);
1187 sdhci_req_done(slot);
1191 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1193 struct sdhci_slot *slot = device_get_ivars(reqdev);
1196 if (slot->req != NULL) {
1200 if (sdhci_debug > 1) {
1202 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1203 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1204 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1205 (req->cmd->data)?req->cmd->data->flags:0);
1212 while (slot->req != NULL) {
1213 sdhci_generic_intr(slot);
1221 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1223 struct sdhci_slot *slot = device_get_ivars(reqdev);
1227 val = RD4(slot, SDHCI_PRESENT_STATE);
1229 return (!(val & SDHCI_WRITE_PROTECT));
1233 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1235 struct sdhci_slot *slot = device_get_ivars(reqdev);
1239 while (slot->bus_busy)
1240 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1243 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1249 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1251 struct sdhci_slot *slot = device_get_ivars(reqdev);
1254 /* Deactivate led. */
1255 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1263 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1266 if (!slot->curcmd) {
1267 slot_printf(slot, "Got command interrupt 0x%08x, but "
1268 "there is no active command.\n", intmask);
1269 sdhci_dumpregs(slot);
1272 if (intmask & SDHCI_INT_TIMEOUT)
1273 slot->curcmd->error = MMC_ERR_TIMEOUT;
1274 else if (intmask & SDHCI_INT_CRC)
1275 slot->curcmd->error = MMC_ERR_BADCRC;
1276 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1277 slot->curcmd->error = MMC_ERR_FIFO;
1279 sdhci_finish_command(slot);
1283 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1285 struct mmc_data *data;
1288 if (!slot->curcmd) {
1289 slot_printf(slot, "Got data interrupt 0x%08x, but "
1290 "there is no active command.\n", intmask);
1291 sdhci_dumpregs(slot);
1294 if (slot->curcmd->data == NULL &&
1295 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1296 slot_printf(slot, "Got data interrupt 0x%08x, but "
1297 "there is no active data operation.\n",
1299 sdhci_dumpregs(slot);
1302 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1303 slot->curcmd->error = MMC_ERR_TIMEOUT;
1304 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1305 slot->curcmd->error = MMC_ERR_BADCRC;
1306 if (slot->curcmd->data == NULL &&
1307 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1308 SDHCI_INT_DMA_END))) {
1309 slot_printf(slot, "Got data interrupt 0x%08x, but "
1310 "there is busy-only command.\n", intmask);
1311 sdhci_dumpregs(slot);
1312 slot->curcmd->error = MMC_ERR_INVALID;
1314 if (slot->curcmd->error) {
1315 /* No need to continue after any error. */
1319 /* Handle PIO interrupt. */
1320 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1321 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1322 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1323 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
1325 slot->flags |= PLATFORM_DATA_STARTED;
1327 sdhci_transfer_pio(slot);
1329 /* Handle DMA border. */
1330 if (intmask & SDHCI_INT_DMA_END) {
1331 data = slot->curcmd->data;
1333 /* Unload DMA buffer... */
1334 left = data->len - slot->offset;
1335 if (data->flags & MMC_DATA_READ) {
1336 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1337 BUS_DMASYNC_POSTREAD);
1338 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1339 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
1341 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1342 BUS_DMASYNC_POSTWRITE);
1344 /* ... and reload it again. */
1345 slot->offset += DMA_BLOCK_SIZE;
1346 left = data->len - slot->offset;
1347 if (data->flags & MMC_DATA_READ) {
1348 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1349 BUS_DMASYNC_PREREAD);
1351 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1352 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
1353 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1354 BUS_DMASYNC_PREWRITE);
1356 /* Interrupt aggregation: Mask border interrupt
1357 * for the last page. */
1358 if (left == DMA_BLOCK_SIZE) {
1359 slot->intmask &= ~SDHCI_INT_DMA_END;
1360 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1363 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1365 /* We have got all data. */
1366 if (intmask & SDHCI_INT_DATA_END) {
1367 if (slot->flags & PLATFORM_DATA_STARTED) {
1368 slot->flags &= ~PLATFORM_DATA_STARTED;
1369 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1371 sdhci_finish_data(slot);
1374 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1375 if (slot->flags & PLATFORM_DATA_STARTED) {
1376 slot->flags &= ~PLATFORM_DATA_STARTED;
1377 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1379 sdhci_finish_data(slot);
1384 sdhci_acmd_irq(struct sdhci_slot *slot)
1388 err = RD4(slot, SDHCI_ACMD12_ERR);
1389 if (!slot->curcmd) {
1390 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1391 "there is no active command.\n", err);
1392 sdhci_dumpregs(slot);
1395 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1396 sdhci_reset(slot, SDHCI_RESET_CMD);
1400 sdhci_generic_intr(struct sdhci_slot *slot)
1402 uint32_t intmask, present;
1405 /* Read slot interrupt status. */
1406 intmask = RD4(slot, SDHCI_INT_STATUS);
1407 if (intmask == 0 || intmask == 0xffffffff) {
1411 if (sdhci_debug > 2)
1412 slot_printf(slot, "Interrupt %#x\n", intmask);
1414 /* Handle card presence interrupts. */
1415 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1416 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
1418 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1419 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
1420 SDHCI_INT_CARD_INSERT;
1421 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1422 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1423 WR4(slot, SDHCI_INT_STATUS, intmask &
1424 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1425 sdhci_handle_card_present_locked(slot, present);
1426 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1428 /* Handle command interrupts. */
1429 if (intmask & SDHCI_INT_CMD_MASK) {
1430 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1431 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1433 /* Handle data interrupts. */
1434 if (intmask & SDHCI_INT_DATA_MASK) {
1435 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1436 /* Dont call data_irq in case of errored command */
1437 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
1438 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1440 /* Handle AutoCMD12 error interrupt. */
1441 if (intmask & SDHCI_INT_ACMD12ERR) {
1442 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1443 sdhci_acmd_irq(slot);
1445 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1446 intmask &= ~SDHCI_INT_ACMD12ERR;
1447 intmask &= ~SDHCI_INT_ERROR;
1448 /* Handle bus power interrupt. */
1449 if (intmask & SDHCI_INT_BUS_POWER) {
1450 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1452 "Card is consuming too much power!\n");
1453 intmask &= ~SDHCI_INT_BUS_POWER;
1455 /* The rest is unknown. */
1457 WR4(slot, SDHCI_INT_STATUS, intmask);
1458 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1460 sdhci_dumpregs(slot);
1467 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
1470 struct sdhci_slot *slot = device_get_ivars(child);
1475 case MMCBR_IVAR_BUS_MODE:
1476 *result = slot->host.ios.bus_mode;
1478 case MMCBR_IVAR_BUS_WIDTH:
1479 *result = slot->host.ios.bus_width;
1481 case MMCBR_IVAR_CHIP_SELECT:
1482 *result = slot->host.ios.chip_select;
1484 case MMCBR_IVAR_CLOCK:
1485 *result = slot->host.ios.clock;
1487 case MMCBR_IVAR_F_MIN:
1488 *result = slot->host.f_min;
1490 case MMCBR_IVAR_F_MAX:
1491 *result = slot->host.f_max;
1493 case MMCBR_IVAR_HOST_OCR:
1494 *result = slot->host.host_ocr;
1496 case MMCBR_IVAR_MODE:
1497 *result = slot->host.mode;
1499 case MMCBR_IVAR_OCR:
1500 *result = slot->host.ocr;
1502 case MMCBR_IVAR_POWER_MODE:
1503 *result = slot->host.ios.power_mode;
1505 case MMCBR_IVAR_VDD:
1506 *result = slot->host.ios.vdd;
1508 case MMCBR_IVAR_CAPS:
1509 *result = slot->host.caps;
1511 case MMCBR_IVAR_TIMING:
1512 *result = slot->host.ios.timing;
1514 case MMCBR_IVAR_MAX_DATA:
1522 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
1525 struct sdhci_slot *slot = device_get_ivars(child);
1530 case MMCBR_IVAR_BUS_MODE:
1531 slot->host.ios.bus_mode = value;
1533 case MMCBR_IVAR_BUS_WIDTH:
1534 slot->host.ios.bus_width = value;
1536 case MMCBR_IVAR_CHIP_SELECT:
1537 slot->host.ios.chip_select = value;
1539 case MMCBR_IVAR_CLOCK:
1545 max_clock = slot->max_clk;
1548 if (slot->version < SDHCI_SPEC_300) {
1549 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1557 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1561 clock = max_clock / (i + 2);
1565 slot->host.ios.clock = clock;
1567 slot->host.ios.clock = 0;
1569 case MMCBR_IVAR_MODE:
1570 slot->host.mode = value;
1572 case MMCBR_IVAR_OCR:
1573 slot->host.ocr = value;
1575 case MMCBR_IVAR_POWER_MODE:
1576 slot->host.ios.power_mode = value;
1578 case MMCBR_IVAR_VDD:
1579 slot->host.ios.vdd = value;
1581 case MMCBR_IVAR_TIMING:
1582 slot->host.ios.timing = value;
1584 case MMCBR_IVAR_CAPS:
1585 case MMCBR_IVAR_HOST_OCR:
1586 case MMCBR_IVAR_F_MIN:
1587 case MMCBR_IVAR_F_MAX:
1588 case MMCBR_IVAR_MAX_DATA:
1594 MODULE_VERSION(sdhci, 1);