2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define DMA_BLOCK_SIZE 4096
32 #define DMA_BOUNDARY 0 /* DMA reload every 4K */
34 /* Controller doesn't honor resets unless we touch the clock register */
35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
36 /* Controller really supports DMA */
37 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
38 /* Controller has unusable DMA engine */
39 #define SDHCI_QUIRK_BROKEN_DMA (1<<2)
40 /* Controller doesn't like to be reset when there is no card inserted. */
41 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
42 /* Controller has flaky internal state so reset it on each ios change */
43 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
44 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
45 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
46 /* Controller needs to be reset after each request to stay stable */
47 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
48 /* Controller has an off-by-one issue with timeout value */
49 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
50 /* Controller has broken read timings */
51 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
52 /* Controller needs lowered frequency */
53 #define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
54 /* Data timeout is invalid, should use SD clock */
55 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10)
56 /* Timeout value is invalid, should be overriden */
57 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11)
58 /* SDHCI_CAPABILITIES is invalid */
59 #define SDHCI_QUIRK_MISSING_CAPS (1<<12)
60 /* Hardware shifts the 136-bit response, don't do it in software. */
61 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13)
62 /* Wait to see reset bit asserted before waiting for de-asserted */
63 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14)
64 /* Leave controller in standard mode when putting card in HS mode. */
65 #define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1<<15)
66 /* Alternate clock source is required when supplying a 400 KHz clock. */
67 #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1<<16)
70 * Controller registers
72 #define SDHCI_DMA_ADDRESS 0x00
74 #define SDHCI_BLOCK_SIZE 0x04
75 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
77 #define SDHCI_BLOCK_COUNT 0x06
79 #define SDHCI_ARGUMENT 0x08
81 #define SDHCI_TRANSFER_MODE 0x0C
82 #define SDHCI_TRNS_DMA 0x01
83 #define SDHCI_TRNS_BLK_CNT_EN 0x02
84 #define SDHCI_TRNS_ACMD12 0x04
85 #define SDHCI_TRNS_READ 0x10
86 #define SDHCI_TRNS_MULTI 0x20
88 #define SDHCI_COMMAND_FLAGS 0x0E
89 #define SDHCI_CMD_RESP_NONE 0x00
90 #define SDHCI_CMD_RESP_LONG 0x01
91 #define SDHCI_CMD_RESP_SHORT 0x02
92 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
93 #define SDHCI_CMD_RESP_MASK 0x03
94 #define SDHCI_CMD_CRC 0x08
95 #define SDHCI_CMD_INDEX 0x10
96 #define SDHCI_CMD_DATA 0x20
97 #define SDHCI_CMD_TYPE_NORMAL 0x00
98 #define SDHCI_CMD_TYPE_SUSPEND 0x40
99 #define SDHCI_CMD_TYPE_RESUME 0x80
100 #define SDHCI_CMD_TYPE_ABORT 0xc0
101 #define SDHCI_CMD_TYPE_MASK 0xc0
103 #define SDHCI_COMMAND 0x0F
105 #define SDHCI_RESPONSE 0x10
107 #define SDHCI_BUFFER 0x20
109 #define SDHCI_PRESENT_STATE 0x24
110 #define SDHCI_CMD_INHIBIT 0x00000001
111 #define SDHCI_DAT_INHIBIT 0x00000002
112 #define SDHCI_DAT_ACTIVE 0x00000004
113 #define SDHCI_RETUNE_REQUEST 0x00000008
114 #define SDHCI_DOING_WRITE 0x00000100
115 #define SDHCI_DOING_READ 0x00000200
116 #define SDHCI_SPACE_AVAILABLE 0x00000400
117 #define SDHCI_DATA_AVAILABLE 0x00000800
118 #define SDHCI_CARD_PRESENT 0x00010000
119 #define SDHCI_CARD_STABLE 0x00020000
120 #define SDHCI_CARD_PIN 0x00040000
121 #define SDHCI_WRITE_PROTECT 0x00080000
122 #define SDHCI_STATE_DAT_MASK 0x00f00000
123 #define SDHCI_STATE_CMD 0x01000000
125 #define SDHCI_HOST_CONTROL 0x28
126 #define SDHCI_CTRL_LED 0x01
127 #define SDHCI_CTRL_4BITBUS 0x02
128 #define SDHCI_CTRL_HISPD 0x04
129 #define SDHCI_CTRL_SDMA 0x08
130 #define SDHCI_CTRL_ADMA2 0x10
131 #define SDHCI_CTRL_ADMA264 0x18
132 #define SDHCI_CTRL_DMA_MASK 0x18
133 #define SDHCI_CTRL_8BITBUS 0x20
134 #define SDHCI_CTRL_CARD_DET 0x40
135 #define SDHCI_CTRL_FORCE_CARD 0x80
137 #define SDHCI_POWER_CONTROL 0x29
138 #define SDHCI_POWER_ON 0x01
139 #define SDHCI_POWER_180 0x0A
140 #define SDHCI_POWER_300 0x0C
141 #define SDHCI_POWER_330 0x0E
143 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
145 #define SDHCI_WAKE_UP_CONTROL 0x2B
147 #define SDHCI_CLOCK_CONTROL 0x2C
148 #define SDHCI_DIVIDER_MASK 0xff
149 #define SDHCI_DIVIDER_MASK_LEN 8
150 #define SDHCI_DIVIDER_SHIFT 8
151 #define SDHCI_DIVIDER_HI_MASK 3
152 #define SDHCI_DIVIDER_HI_SHIFT 6
153 #define SDHCI_CLOCK_CARD_EN 0x0004
154 #define SDHCI_CLOCK_INT_STABLE 0x0002
155 #define SDHCI_CLOCK_INT_EN 0x0001
156 #define SDHCI_DIVIDERS_MASK \
157 ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \
158 (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT))
160 #define SDHCI_TIMEOUT_CONTROL 0x2E
162 #define SDHCI_SOFTWARE_RESET 0x2F
163 #define SDHCI_RESET_ALL 0x01
164 #define SDHCI_RESET_CMD 0x02
165 #define SDHCI_RESET_DATA 0x04
167 #define SDHCI_INT_STATUS 0x30
168 #define SDHCI_INT_ENABLE 0x34
169 #define SDHCI_SIGNAL_ENABLE 0x38
170 #define SDHCI_INT_RESPONSE 0x00000001
171 #define SDHCI_INT_DATA_END 0x00000002
172 #define SDHCI_INT_BLOCK_GAP 0x00000004
173 #define SDHCI_INT_DMA_END 0x00000008
174 #define SDHCI_INT_SPACE_AVAIL 0x00000010
175 #define SDHCI_INT_DATA_AVAIL 0x00000020
176 #define SDHCI_INT_CARD_INSERT 0x00000040
177 #define SDHCI_INT_CARD_REMOVE 0x00000080
178 #define SDHCI_INT_CARD_INT 0x00000100
179 #define SDHCI_INT_INT_A 0x00000200
180 #define SDHCI_INT_INT_B 0x00000400
181 #define SDHCI_INT_INT_C 0x00000800
182 #define SDHCI_INT_RETUNE 0x00001000
183 #define SDHCI_INT_ERROR 0x00008000
184 #define SDHCI_INT_TIMEOUT 0x00010000
185 #define SDHCI_INT_CRC 0x00020000
186 #define SDHCI_INT_END_BIT 0x00040000
187 #define SDHCI_INT_INDEX 0x00080000
188 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
189 #define SDHCI_INT_DATA_CRC 0x00200000
190 #define SDHCI_INT_DATA_END_BIT 0x00400000
191 #define SDHCI_INT_BUS_POWER 0x00800000
192 #define SDHCI_INT_ACMD12ERR 0x01000000
193 #define SDHCI_INT_ADMAERR 0x02000000
194 #define SDHCI_INT_TUNEERR 0x04000000
196 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
197 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
199 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \
200 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
202 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
204 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
205 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
206 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
207 SDHCI_INT_DATA_END_BIT)
209 #define SDHCI_ACMD12_ERR 0x3C
210 #define SDHCI_HOST_CONTROL2 0x3E
212 #define SDHCI_CAPABILITIES 0x40
213 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
214 #define SDHCI_TIMEOUT_CLK_SHIFT 0
215 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
216 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
217 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
218 #define SDHCI_CLOCK_BASE_SHIFT 8
219 #define SDHCI_MAX_BLOCK_MASK 0x00030000
220 #define SDHCI_MAX_BLOCK_SHIFT 16
221 #define SDHCI_CAN_DO_8BITBUS 0x00040000
222 #define SDHCI_CAN_DO_ADMA2 0x00080000
223 #define SDHCI_CAN_DO_HISPD 0x00200000
224 #define SDHCI_CAN_DO_DMA 0x00400000
225 #define SDHCI_CAN_DO_SUSPEND 0x00800000
226 #define SDHCI_CAN_VDD_330 0x01000000
227 #define SDHCI_CAN_VDD_300 0x02000000
228 #define SDHCI_CAN_VDD_180 0x04000000
229 #define SDHCI_CAN_DO_64BIT 0x10000000
230 #define SDHCI_CAN_ASYNC_INTR 0x20000000
232 #define SDHCI_CAPABILITIES2 0x44
233 #define SDHCI_CAN_SDR50 0x00000001
234 #define SDHCI_CAN_SDR104 0x00000002
235 #define SDHCI_CAN_DDR50 0x00000004
236 #define SDHCI_CAN_DRIVE_TYPE_A 0x00000010
237 #define SDHCI_CAN_DRIVE_TYPE_B 0x00000020
238 #define SDHCI_CAN_DRIVE_TYPE_C 0x00000040
239 #define SDHCI_RETUNE_CNT_MASK 0x00000F00
240 #define SDHCI_RETUNE_CNT_SHIFT 8
241 #define SDHCI_TUNE_SDR50 0x00002000
242 #define SDHCI_RETUNE_MODES_MASK 0x0000C000
243 #define SDHCI_RETUNE_MODES_SHIFT 14
244 #define SDHCI_CLOCK_MULT_MASK 0x00FF0000
245 #define SDHCI_CLOCK_MULT_SHIFT 16
247 #define SDHCI_MAX_CURRENT 0x48
248 #define SDHCI_FORCE_AUTO_EVENT 0x50
249 #define SDHCI_FORCE_INTR_EVENT 0x52
250 #define SDHCI_ADMA_ERR 0x54
251 #define SDHCI_ADMA_ADDRESS_LOW 0x58
252 #define SDHCI_ADMA_ADDRESS_HI 0x5C
253 #define SDHCI_PRESET_VALUE 0x60
254 #define SDHCI_SHARED_BUS_CTRL 0xE0
256 #define SDHCI_SLOT_INT_STATUS 0xFC
258 #define SDHCI_HOST_VERSION 0xFE
259 #define SDHCI_VENDOR_VER_MASK 0xFF00
260 #define SDHCI_VENDOR_VER_SHIFT 8
261 #define SDHCI_SPEC_VER_MASK 0x00FF
262 #define SDHCI_SPEC_VER_SHIFT 0
263 #define SDHCI_SPEC_100 0
264 #define SDHCI_SPEC_200 1
265 #define SDHCI_SPEC_300 2
267 SYSCTL_DECL(_hw_sdhci);
270 u_int quirks; /* Chip specific quirks */
271 u_int caps; /* Override SDHCI_CAPABILITIES */
272 device_t bus; /* Bus device */
273 device_t dev; /* Slot device */
274 u_char num; /* Slot number */
275 u_char opt; /* Slot options */
276 #define SDHCI_HAVE_DMA 1
277 #define SDHCI_PLATFORM_TRANSFER 2
279 int timeout; /* Transfer timeout */
280 uint32_t max_clk; /* Max possible freq */
281 uint32_t timeout_clk; /* Timeout freq */
282 bus_dma_tag_t dmatag;
285 bus_addr_t paddr; /* DMA buffer address */
286 struct task card_task; /* Card presence check task */
287 struct callout card_callout; /* Card insert delay callout */
288 struct callout timeout_callout;/* Card command/data response timeout */
289 struct mmc_host host; /* Host parameters */
290 struct mmc_request *req; /* Current request */
291 struct mmc_command *curcmd; /* Current command of current request */
293 uint32_t intmask; /* Current interrupt mask */
294 uint32_t clock; /* Current clock freq. */
295 size_t offset; /* Data buffer offset */
296 uint8_t hostctrl; /* Current host control register */
297 u_char power; /* Current power */
298 u_char bus_busy; /* Bus busy status */
299 u_char cmd_done; /* CMD command part done flag */
300 u_char data_done; /* DAT command part done flag */
301 u_char flags; /* Request execution flags */
302 #define CMD_STARTED 1
303 #define STOP_STARTED 2
304 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */
305 #define PLATFORM_DATA_STARTED 8 /* Data transfer is handled by platform */
306 struct mtx mtx; /* Slot mutex */
309 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result);
310 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value);
311 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num);
312 void sdhci_start_slot(struct sdhci_slot *slot);
313 /* performs generic clean-up for platform transfers */
314 void sdhci_finish_data(struct sdhci_slot *slot);
315 int sdhci_cleanup_slot(struct sdhci_slot *slot);
316 int sdhci_generic_suspend(struct sdhci_slot *slot);
317 int sdhci_generic_resume(struct sdhci_slot *slot);
318 int sdhci_generic_update_ios(device_t brdev, device_t reqdev);
319 int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req);
320 int sdhci_generic_get_ro(device_t brdev, device_t reqdev);
321 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev);
322 int sdhci_generic_release_host(device_t brdev, device_t reqdev);
323 void sdhci_generic_intr(struct sdhci_slot *slot);
324 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot);
325 bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot);
327 #endif /* __SDHCI_H__ */