2 * Copyright (c) 2017 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/resource.h>
38 #include <sys/sysctl.h>
39 #include <sys/taskqueue.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
44 #include <contrib/dev/acpica/include/acpi.h>
45 #include <dev/acpica/acpivar.h>
47 #include <dev/mmc/bridge.h>
49 #include <dev/sdhci/sdhci.h>
54 static const struct sdhci_acpi_device {
59 } sdhci_acpi_devices[] = {
60 { "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
61 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
62 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
63 SDHCI_QUIRK_WAIT_WHILE_BUSY |
64 SDHCI_QUIRK_MMC_DDR52 |
65 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
66 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
67 { "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller",
68 SDHCI_QUIRK_WAIT_WHILE_BUSY |
69 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
70 { "80860F16", 0, "Intel Bay Trail/Braswell SDXC Controller",
71 SDHCI_QUIRK_WAIT_WHILE_BUSY |
72 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
73 { "80865ACA", 0, "Intel Apollo Lake SDXC Controller",
74 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
75 SDHCI_QUIRK_WAIT_WHILE_BUSY |
76 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
77 { "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",
78 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
79 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
80 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
81 SDHCI_QUIRK_WAIT_WHILE_BUSY |
82 SDHCI_QUIRK_MMC_DDR52 |
83 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
84 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
88 static char *sdhci_ids[] = {
96 struct sdhci_acpi_softc {
97 u_int quirks; /* Chip specific quirks */
98 struct resource *irq_res; /* IRQ resource */
99 void *intrhand; /* Interrupt handle */
101 struct sdhci_slot slot;
102 struct resource *mem_res; /* Memory resource */
105 static void sdhci_acpi_intr(void *arg);
106 static int sdhci_acpi_detach(device_t dev);
109 sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused,
112 struct sdhci_acpi_softc *sc = device_get_softc(dev);
114 bus_barrier(sc->mem_res, 0, 0xFF,
115 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
116 return bus_read_1(sc->mem_res, off);
120 sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused,
121 bus_size_t off, uint8_t val)
123 struct sdhci_acpi_softc *sc = device_get_softc(dev);
125 bus_barrier(sc->mem_res, 0, 0xFF,
126 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
127 bus_write_1(sc->mem_res, off, val);
131 sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused,
134 struct sdhci_acpi_softc *sc = device_get_softc(dev);
136 bus_barrier(sc->mem_res, 0, 0xFF,
137 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
138 return bus_read_2(sc->mem_res, off);
142 sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused,
143 bus_size_t off, uint16_t val)
145 struct sdhci_acpi_softc *sc = device_get_softc(dev);
147 bus_barrier(sc->mem_res, 0, 0xFF,
148 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
149 bus_write_2(sc->mem_res, off, val);
153 sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused,
156 struct sdhci_acpi_softc *sc = device_get_softc(dev);
158 bus_barrier(sc->mem_res, 0, 0xFF,
159 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
160 return bus_read_4(sc->mem_res, off);
164 sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused,
165 bus_size_t off, uint32_t val)
167 struct sdhci_acpi_softc *sc = device_get_softc(dev);
169 bus_barrier(sc->mem_res, 0, 0xFF,
170 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
171 bus_write_4(sc->mem_res, off, val);
175 sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
176 bus_size_t off, uint32_t *data, bus_size_t count)
178 struct sdhci_acpi_softc *sc = device_get_softc(dev);
180 bus_read_multi_stream_4(sc->mem_res, off, data, count);
184 sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
185 bus_size_t off, uint32_t *data, bus_size_t count)
187 struct sdhci_acpi_softc *sc = device_get_softc(dev);
189 bus_write_multi_stream_4(sc->mem_res, off, data, count);
192 static const struct sdhci_acpi_device *
193 sdhci_acpi_find_device(device_t dev)
200 hid = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids);
204 handle = acpi_get_handle(dev);
205 status = acpi_GetInteger(handle, "_UID", &uid);
206 if (ACPI_FAILURE(status))
209 for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) {
210 if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0)
212 if ((sdhci_acpi_devices[i].uid != 0) &&
213 (sdhci_acpi_devices[i].uid != uid))
215 return (&sdhci_acpi_devices[i]);
222 sdhci_acpi_probe(device_t dev)
224 const struct sdhci_acpi_device *acpi_dev;
226 acpi_dev = sdhci_acpi_find_device(dev);
227 if (acpi_dev == NULL)
230 device_set_desc(dev, acpi_dev->desc);
232 return (BUS_PROBE_DEFAULT);
236 sdhci_acpi_attach(device_t dev)
238 struct sdhci_acpi_softc *sc = device_get_softc(dev);
240 const struct sdhci_acpi_device *acpi_dev;
242 acpi_dev = sdhci_acpi_find_device(dev);
243 if (acpi_dev == NULL)
246 sc->quirks = acpi_dev->quirks;
250 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
252 if (sc->irq_res == NULL) {
253 device_printf(dev, "can't allocate IRQ\n");
258 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
260 if (sc->mem_res == NULL) {
261 device_printf(dev, "can't allocate memory resource for slot\n");
262 sdhci_acpi_detach(dev);
266 /* Intel Braswell eMMC 4.5.1 controller quirk */
267 if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
268 SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
269 SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
270 sc->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
271 sc->quirks &= ~sdhci_quirk_clear;
272 sc->quirks |= sdhci_quirk_set;
273 sc->slot.quirks = sc->quirks;
275 err = sdhci_init_slot(dev, &sc->slot, 0);
277 device_printf(dev, "failed to init slot\n");
278 sdhci_acpi_detach(dev);
282 /* Activate the interrupt */
283 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
284 NULL, sdhci_acpi_intr, sc, &sc->intrhand);
286 device_printf(dev, "can't setup IRQ\n");
287 sdhci_acpi_detach(dev);
291 /* Process cards detection. */
292 sdhci_start_slot(&sc->slot);
298 sdhci_acpi_detach(device_t dev)
300 struct sdhci_acpi_softc *sc = device_get_softc(dev);
303 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
305 bus_release_resource(dev, SYS_RES_IRQ,
306 rman_get_rid(sc->irq_res), sc->irq_res);
309 sdhci_cleanup_slot(&sc->slot);
310 bus_release_resource(dev, SYS_RES_MEMORY,
311 rman_get_rid(sc->mem_res), sc->mem_res);
318 sdhci_acpi_shutdown(device_t dev)
325 sdhci_acpi_suspend(device_t dev)
327 struct sdhci_acpi_softc *sc = device_get_softc(dev);
330 err = bus_generic_suspend(dev);
333 sdhci_generic_suspend(&sc->slot);
338 sdhci_acpi_resume(device_t dev)
340 struct sdhci_acpi_softc *sc = device_get_softc(dev);
343 sdhci_generic_resume(&sc->slot);
344 err = bus_generic_resume(dev);
351 sdhci_acpi_intr(void *arg)
353 struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg;
355 sdhci_generic_intr(&sc->slot);
358 static device_method_t sdhci_methods[] = {
360 DEVMETHOD(device_probe, sdhci_acpi_probe),
361 DEVMETHOD(device_attach, sdhci_acpi_attach),
362 DEVMETHOD(device_detach, sdhci_acpi_detach),
363 DEVMETHOD(device_shutdown, sdhci_acpi_shutdown),
364 DEVMETHOD(device_suspend, sdhci_acpi_suspend),
365 DEVMETHOD(device_resume, sdhci_acpi_resume),
368 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
369 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
372 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
373 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
374 DEVMETHOD(mmcbr_request, sdhci_generic_request),
375 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
376 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
377 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
379 /* SDHCI accessors */
380 DEVMETHOD(sdhci_read_1, sdhci_acpi_read_1),
381 DEVMETHOD(sdhci_read_2, sdhci_acpi_read_2),
382 DEVMETHOD(sdhci_read_4, sdhci_acpi_read_4),
383 DEVMETHOD(sdhci_read_multi_4, sdhci_acpi_read_multi_4),
384 DEVMETHOD(sdhci_write_1, sdhci_acpi_write_1),
385 DEVMETHOD(sdhci_write_2, sdhci_acpi_write_2),
386 DEVMETHOD(sdhci_write_4, sdhci_acpi_write_4),
387 DEVMETHOD(sdhci_write_multi_4, sdhci_acpi_write_multi_4),
388 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
393 static driver_t sdhci_acpi_driver = {
396 sizeof(struct sdhci_acpi_softc),
398 static devclass_t sdhci_acpi_devclass;
400 DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, sdhci_acpi_devclass, NULL,
402 MODULE_DEPEND(sdhci_acpi, sdhci, 1, 1, 1);
403 MMC_DECLARE_BRIDGE(sdhci_acpi);