sys/dev/sdhci/sdhci_acpi.c

   1 /*-
   2  * Copyright (c) 2017 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 #include <sys/cdefs.h>
  27 __FBSDID("$FreeBSD$");
  28
  29 #include <sys/param.h>
  30 #include <sys/systm.h>
  31 #include <sys/bus.h>
  32 #include <sys/kernel.h>
  33 #include <sys/lock.h>
  34 #include <sys/module.h>
  35 #include <sys/mutex.h>
  36 #include <sys/resource.h>
  37 #include <sys/rman.h>
  38 #include <sys/sysctl.h>
  39 #include <sys/taskqueue.h>
  40
  41 #include <machine/bus.h>
  42 #include <machine/resource.h>
  43
  44 #include <contrib/dev/acpica/include/acpi.h>
  45 #include <dev/acpica/acpivar.h>
  46
  47 #include <dev/mmc/bridge.h>
  48
  49 #include <dev/sdhci/sdhci.h>
  50
  51 #include "mmcbr_if.h"
  52 #include "sdhci_if.h"
  53
  54 static const struct sdhci_acpi_device {
  55         const char*     hid;
  56         int             uid;
  57         const char      *desc;
  58         u_int           quirks;
  59 } sdhci_acpi_devices[] = {
  60         { "80860F14",   1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
  61             SDHCI_QUIRK_INTEL_POWER_UP_RESET |
  62             SDHCI_QUIRK_WAIT_WHILE_BUSY |
  63             SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
  64             SDHCI_QUIRK_PRESET_VALUE_BROKEN },
  65         { "80860F14",   3, "Intel Bay Trail/Braswell SDXC Controller",
  66             SDHCI_QUIRK_WAIT_WHILE_BUSY |
  67             SDHCI_QUIRK_PRESET_VALUE_BROKEN },
  68         { "80860F16",   0, "Intel Bay Trail/Braswell SDXC Controller",
  69             SDHCI_QUIRK_WAIT_WHILE_BUSY |
  70             SDHCI_QUIRK_PRESET_VALUE_BROKEN },
  71         { "80865ACA",   0, "Intel Apollo Lake SDXC Controller",
  72             SDHCI_QUIRK_BROKEN_DMA |    /* APL18 erratum */
  73             SDHCI_QUIRK_WAIT_WHILE_BUSY |
  74             SDHCI_QUIRK_PRESET_VALUE_BROKEN },
  75         { "80865ACC",   0, "Intel Apollo Lake eMMC 5.0 Controller",
  76             SDHCI_QUIRK_BROKEN_DMA |    /* APL18 erratum */
  77             SDHCI_QUIRK_INTEL_POWER_UP_RESET |
  78             SDHCI_QUIRK_WAIT_WHILE_BUSY |
  79             SDHCI_QUIRK_MMC_DDR52 |
  80             SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
  81             SDHCI_QUIRK_PRESET_VALUE_BROKEN },
  82         { "AMDI0040",   0, "AMD eMMC 5.0 Controller",
  83             SDHCI_QUIRK_32BIT_DMA_SIZE },
  84         { NULL, 0, NULL, 0}
  85 };
  86
  87 static char *sdhci_ids[] = {
  88         "80860F14",
  89         "80860F16",
  90         "80865ACA",
  91         "80865ACC",
  92         "AMDI0040",
  93         NULL
  94 };
  95
  96 struct sdhci_acpi_softc {
  97         u_int           quirks;         /* Chip specific quirks */
  98         struct resource *irq_res;       /* IRQ resource */
  99         void            *intrhand;      /* Interrupt handle */
 100
 101         struct sdhci_slot slot;
 102         struct resource *mem_res;       /* Memory resource */
 103 };
 104
 105 static void sdhci_acpi_intr(void *arg);
 106 static int sdhci_acpi_detach(device_t dev);
 107
 108 static uint8_t
 109 sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused,
 110     bus_size_t off)
 111 {
 112         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 113
 114         bus_barrier(sc->mem_res, 0, 0xFF,
 115             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 116         return bus_read_1(sc->mem_res, off);
 117 }
 118
 119 static void
 120 sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused,
 121     bus_size_t off, uint8_t val)
 122 {
 123         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 124
 125         bus_barrier(sc->mem_res, 0, 0xFF,
 126             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 127         bus_write_1(sc->mem_res, off, val);
 128 }
 129
 130 static uint16_t
 131 sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused,
 132     bus_size_t off)
 133 {
 134         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 135
 136         bus_barrier(sc->mem_res, 0, 0xFF,
 137             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 138         return bus_read_2(sc->mem_res, off);
 139 }
 140
 141 static void
 142 sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused,
 143     bus_size_t off, uint16_t val)
 144 {
 145         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 146
 147         bus_barrier(sc->mem_res, 0, 0xFF,
 148             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 149         bus_write_2(sc->mem_res, off, val);
 150 }
 151
 152 static uint32_t
 153 sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused,
 154     bus_size_t off)
 155 {
 156         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 157
 158         bus_barrier(sc->mem_res, 0, 0xFF,
 159             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 160         return bus_read_4(sc->mem_res, off);
 161 }
 162
 163 static void
 164 sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused,
 165     bus_size_t off, uint32_t val)
 166 {
 167         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 168
 169         bus_barrier(sc->mem_res, 0, 0xFF,
 170             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 171         bus_write_4(sc->mem_res, off, val);
 172 }
 173
 174 static void
 175 sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
 176     bus_size_t off, uint32_t *data, bus_size_t count)
 177 {
 178         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 179
 180         bus_read_multi_stream_4(sc->mem_res, off, data, count);
 181 }
 182
 183 static void
 184 sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
 185     bus_size_t off, uint32_t *data, bus_size_t count)
 186 {
 187         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 188
 189         bus_write_multi_stream_4(sc->mem_res, off, data, count);
 190 }
 191
 192 static const struct sdhci_acpi_device *
 193 sdhci_acpi_find_device(device_t dev)
 194 {
 195         const char *hid;
 196         int i, uid;
 197         ACPI_HANDLE handle;
 198         ACPI_STATUS status;
 199
 200         hid = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids);
 201         if (hid == NULL)
 202                 return (NULL);
 203
 204         handle = acpi_get_handle(dev);
 205         status = acpi_GetInteger(handle, "_UID", &uid);
 206         if (ACPI_FAILURE(status))
 207                 uid = 0;
 208
 209         for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) {
 210                 if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0)
 211                         continue;
 212                 if ((sdhci_acpi_devices[i].uid != 0) &&
 213                     (sdhci_acpi_devices[i].uid != uid))
 214                         continue;
 215                 return (&sdhci_acpi_devices[i]);
 216         }
 217
 218         return (NULL);
 219 }
 220
 221 static int
 222 sdhci_acpi_probe(device_t dev)
 223 {
 224         const struct sdhci_acpi_device *acpi_dev;
 225
 226         acpi_dev = sdhci_acpi_find_device(dev);
 227         if (acpi_dev == NULL)
 228                 return (ENXIO);
 229
 230         device_set_desc(dev, acpi_dev->desc);
 231
 232         return (BUS_PROBE_DEFAULT);
 233 }
 234
 235 static int
 236 sdhci_acpi_attach(device_t dev)
 237 {
 238         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 239         int rid, err;
 240         const struct sdhci_acpi_device *acpi_dev;
 241
 242         acpi_dev = sdhci_acpi_find_device(dev);
 243         if (acpi_dev == NULL)
 244                 return (ENXIO);
 245
 246         sc->quirks = acpi_dev->quirks;
 247
 248         /* Allocate IRQ. */
 249         rid = 0;
 250         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 251                 RF_ACTIVE);
 252         if (sc->irq_res == NULL) {
 253                 device_printf(dev, "can't allocate IRQ\n");
 254                 return (ENOMEM);
 255         }
 256
 257         rid = 0;
 258         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 259             &rid, RF_ACTIVE);
 260         if (sc->mem_res == NULL) {
 261                 device_printf(dev, "can't allocate memory resource for slot\n");
 262                 sdhci_acpi_detach(dev);
 263                 return (ENOMEM);
 264         }
 265
 266         /*
 267          * Intel Bay Trail and Braswell eMMC controllers share the same IDs,
 268          * but while with these former DDR52 is affected by the VLI54 erratum,
 269          * these latter require the timeout clock to be hardcoded to 1 MHz.
 270          */
 271         if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
 272             SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
 273             SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
 274                 sc->quirks |= SDHCI_QUIRK_MMC_DDR52 |
 275                     SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
 276         sc->quirks &= ~sdhci_quirk_clear;
 277         sc->quirks |= sdhci_quirk_set;
 278         sc->slot.quirks = sc->quirks;
 279
 280         err = sdhci_init_slot(dev, &sc->slot, 0);
 281         if (err) {
 282                 device_printf(dev, "failed to init slot\n");
 283                 sdhci_acpi_detach(dev);
 284                 return (err);
 285         }
 286
 287         /* Activate the interrupt */
 288         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
 289             NULL, sdhci_acpi_intr, sc, &sc->intrhand);
 290         if (err) {
 291                 device_printf(dev, "can't setup IRQ\n");
 292                 sdhci_acpi_detach(dev);
 293                 return (err);
 294         }
 295
 296         /* Process cards detection. */
 297         sdhci_start_slot(&sc->slot);
 298
 299         return (0);
 300 }
 301
 302 static int
 303 sdhci_acpi_detach(device_t dev)
 304 {
 305         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 306
 307         if (sc->intrhand)
 308                 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
 309         if (sc->irq_res)
 310                 bus_release_resource(dev, SYS_RES_IRQ,
 311                     rman_get_rid(sc->irq_res), sc->irq_res);
 312
 313         if (sc->mem_res) {
 314                 sdhci_cleanup_slot(&sc->slot);
 315                 bus_release_resource(dev, SYS_RES_MEMORY,
 316                     rman_get_rid(sc->mem_res), sc->mem_res);
 317         }
 318
 319         return (0);
 320 }
 321
 322 static int
 323 sdhci_acpi_shutdown(device_t dev)
 324 {
 325
 326         return (0);
 327 }
 328
 329 static int
 330 sdhci_acpi_suspend(device_t dev)
 331 {
 332         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 333         int err;
 334
 335         err = bus_generic_suspend(dev);
 336         if (err)
 337                 return (err);
 338         sdhci_generic_suspend(&sc->slot);
 339         return (0);
 340 }
 341
 342 static int
 343 sdhci_acpi_resume(device_t dev)
 344 {
 345         struct sdhci_acpi_softc *sc = device_get_softc(dev);
 346         int err;
 347
 348         sdhci_generic_resume(&sc->slot);
 349         err = bus_generic_resume(dev);
 350         if (err)
 351                 return (err);
 352         return (0);
 353 }
 354
 355 static void
 356 sdhci_acpi_intr(void *arg)
 357 {
 358         struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg;
 359
 360         sdhci_generic_intr(&sc->slot);
 361 }
 362
 363 static device_method_t sdhci_methods[] = {
 364         /* device_if */
 365         DEVMETHOD(device_probe, sdhci_acpi_probe),
 366         DEVMETHOD(device_attach, sdhci_acpi_attach),
 367         DEVMETHOD(device_detach, sdhci_acpi_detach),
 368         DEVMETHOD(device_shutdown, sdhci_acpi_shutdown),
 369         DEVMETHOD(device_suspend, sdhci_acpi_suspend),
 370         DEVMETHOD(device_resume, sdhci_acpi_resume),
 371
 372         /* Bus interface */
 373         DEVMETHOD(bus_read_ivar,        sdhci_generic_read_ivar),
 374         DEVMETHOD(bus_write_ivar,       sdhci_generic_write_ivar),
 375
 376         /* mmcbr_if */
 377         DEVMETHOD(mmcbr_update_ios,     sdhci_generic_update_ios),
 378         DEVMETHOD(mmcbr_switch_vccq,    sdhci_generic_switch_vccq),
 379         DEVMETHOD(mmcbr_tune,           sdhci_generic_tune),
 380         DEVMETHOD(mmcbr_retune,         sdhci_generic_retune),
 381         DEVMETHOD(mmcbr_request,        sdhci_generic_request),
 382         DEVMETHOD(mmcbr_get_ro,         sdhci_generic_get_ro),
 383         DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
 384         DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
 385
 386         /* SDHCI accessors */
 387         DEVMETHOD(sdhci_read_1,         sdhci_acpi_read_1),
 388         DEVMETHOD(sdhci_read_2,         sdhci_acpi_read_2),
 389         DEVMETHOD(sdhci_read_4,         sdhci_acpi_read_4),
 390         DEVMETHOD(sdhci_read_multi_4,   sdhci_acpi_read_multi_4),
 391         DEVMETHOD(sdhci_write_1,        sdhci_acpi_write_1),
 392         DEVMETHOD(sdhci_write_2,        sdhci_acpi_write_2),
 393         DEVMETHOD(sdhci_write_4,        sdhci_acpi_write_4),
 394         DEVMETHOD(sdhci_write_multi_4,  sdhci_acpi_write_multi_4),
 395         DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
 396
 397         DEVMETHOD_END
 398 };
 399
 400 static driver_t sdhci_acpi_driver = {
 401         "sdhci_acpi",
 402         sdhci_methods,
 403         sizeof(struct sdhci_acpi_softc),
 404 };
 405 static devclass_t sdhci_acpi_devclass;
 406
 407 DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, sdhci_acpi_devclass, NULL,
 408     NULL);
 409 MODULE_DEPEND(sdhci_acpi, sdhci, 1, 1, 1);
 410
 411 #ifndef MMCCAM
 412 MMC_DECLARE_BRIDGE(sdhci_acpi);
 413 #endif