sys/dev/sdhci/sdhci_fdt.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2012 Thomas Skibo
   5  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* Generic driver to attach sdhci controllers on simplebus.
  30  * Derived mainly from sdhci_pci.c
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/lock.h>
  41 #include <sys/module.h>
  42 #include <sys/mutex.h>
  43 #include <sys/resource.h>
  44 #include <sys/rman.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <machine/bus.h>
  49 #include <machine/resource.h>
  50
  51 #include <dev/fdt/fdt_common.h>
  52 #include <dev/ofw/ofw_bus.h>
  53 #include <dev/ofw/ofw_bus_subr.h>
  54
  55 #ifdef EXT_RESOURCES
  56 #include <dev/ofw/ofw_subr.h>
  57 #include <dev/extres/clk/clk.h>
  58 #include <dev/extres/clk/clk_fixed.h>
  59 #include <dev/extres/syscon/syscon.h>
  60 #include <dev/extres/phy/phy.h>
  61 #endif
  62
  63 #include <dev/mmc/bridge.h>
  64
  65 #include <dev/sdhci/sdhci.h>
  66
  67 #include "mmcbr_if.h"
  68 #include "sdhci_if.h"
  69
  70 #include "opt_mmccam.h"
  71
  72 #ifdef EXT_RESOURCES
  73 #include "clkdev_if.h"
  74 #include "syscon_if.h"
  75 #endif
  76
  77 #define MAX_SLOTS               6
  78 #define SDHCI_FDT_ARMADA38X     1
  79 #define SDHCI_FDT_GENERIC       2
  80 #define SDHCI_FDT_XLNX_ZY7      3
  81 #define SDHCI_FDT_QUALCOMM      4
  82 #define SDHCI_FDT_RK3399        5
  83
  84 #ifdef EXT_RESOURCES
  85 #define RK3399_GRF_EMMCCORE_CON0                0xf000
  86 #define  RK3399_CORECFG_BASECLKFREQ             0xff00
  87 #define  RK3399_CORECFG_TIMEOUTCLKUNIT          (1 << 7)
  88 #define  RK3399_CORECFG_TUNINGCOUNT             0x3f
  89 #define RK3399_GRF_EMMCCORE_CON11               0xf02c
  90 #define  RK3399_CORECFG_CLOCKMULTIPLIER         0xff
  91
  92 #define LOWEST_SET_BIT(mask)    ((((mask) - 1) & (mask)) ^ (mask))
  93 #define SHIFTIN(x, mask)        ((x) * LOWEST_SET_BIT(mask))
  94
  95 #define EMMCCARDCLK_ID          1000
  96 #endif
  97
  98 static struct ofw_compat_data compat_data[] = {
  99         { "marvell,armada-380-sdhci",   SDHCI_FDT_ARMADA38X },
 100         { "sdhci_generic",              SDHCI_FDT_GENERIC },
 101         { "qcom,sdhci-msm-v4",          SDHCI_FDT_QUALCOMM },
 102         { "rockchip,rk3399-sdhci-5.1",  SDHCI_FDT_RK3399 },
 103         { "xlnx,zy7_sdhci",             SDHCI_FDT_XLNX_ZY7 },
 104         { NULL, 0 }
 105 };
 106
 107 struct sdhci_fdt_softc {
 108         device_t        dev;            /* Controller device */
 109         u_int           quirks;         /* Chip specific quirks */
 110         u_int           caps;           /* If we override SDHCI_CAPABILITIES */
 111         uint32_t        max_clk;        /* Max possible freq */
 112         uint8_t         sdma_boundary;  /* If we override the SDMA boundary */
 113         struct resource *irq_res;       /* IRQ resource */
 114         void            *intrhand;      /* Interrupt handle */
 115
 116         int             num_slots;      /* Number of slots on this controller*/
 117         struct sdhci_slot slots[MAX_SLOTS];
 118         struct resource *mem_res[MAX_SLOTS];    /* Memory resource */
 119
 120         bool            wp_inverted;    /* WP pin is inverted */
 121         bool            no_18v;         /* No 1.8V support */
 122
 123 #ifdef EXT_RESOURCES
 124         clk_t           clk_xin;        /* xin24m fixed clock */
 125         clk_t           clk_ahb;        /* ahb clock */
 126         phy_t           phy;            /* phy to be used */
 127 #endif
 128 };
 129
 130 #ifdef EXT_RESOURCES
 131 struct rk3399_emmccardclk_sc {
 132         device_t        clkdev;
 133         bus_addr_t      reg;
 134 };
 135
 136 static int
 137 rk3399_emmccardclk_init(struct clknode *clk, device_t dev)
 138 {
 139
 140         clknode_init_parent_idx(clk, 0);
 141         return (0);
 142 }
 143
 144 static clknode_method_t rk3399_emmccardclk_clknode_methods[] = {
 145         /* Device interface */
 146         CLKNODEMETHOD(clknode_init,     rk3399_emmccardclk_init),
 147         CLKNODEMETHOD_END
 148 };
 149 DEFINE_CLASS_1(rk3399_emmccardclk_clknode, rk3399_emmccardclk_clknode_class,
 150     rk3399_emmccardclk_clknode_methods, sizeof(struct rk3399_emmccardclk_sc),
 151     clknode_class);
 152
 153 static int
 154 rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells,
 155     phandle_t *cells, struct clknode **clk)
 156 {
 157
 158         if (ncells == 0)
 159                 *clk = clknode_find_by_id(clkdom, EMMCCARDCLK_ID);
 160         else
 161                 return (ERANGE);
 162
 163         if (*clk == NULL)
 164                 return (ENXIO);
 165         return (0);
 166 }
 167
 168 static void
 169 sdhci_init_rk3399_emmccardclk(device_t dev)
 170 {
 171         struct clknode_init_def def;
 172         struct rk3399_emmccardclk_sc *sc;
 173         struct clkdom *clkdom;
 174         struct clknode *clk;
 175         clk_t clk_parent;
 176         bus_addr_t paddr;
 177         bus_size_t psize;
 178         const char **clknames;
 179         phandle_t node;
 180         int i, nclocks, ncells, error;
 181
 182         node = ofw_bus_get_node(dev);
 183
 184         if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
 185                 device_printf(dev, "cannot parse 'reg' property\n");
 186                 return;
 187         }
 188
 189         error = ofw_bus_parse_xref_list_get_length(node, "clocks",
 190             "#clock-cells", &ncells);
 191         if (error != 0 || ncells != 2) {
 192                 device_printf(dev, "couldn't find parent clocks\n");
 193                 return;
 194         }
 195
 196         nclocks = ofw_bus_string_list_to_array(node, "clock-output-names",
 197             &clknames);
 198         /* No clocks to export */
 199         if (nclocks <= 0)
 200                 return;
 201
 202         if (nclocks != 1) {
 203                 device_printf(dev, "Having %d clock instead of 1, aborting\n",
 204                     nclocks);
 205                 return;
 206         }
 207
 208         clkdom = clkdom_create(dev);
 209         clkdom_set_ofw_mapper(clkdom, rk3399_ofw_map);
 210
 211         memset(&def, 0, sizeof(def));
 212         def.id = EMMCCARDCLK_ID;
 213         def.name = clknames[0];
 214         def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
 215         for (i = 0; i < ncells; i++) {
 216                 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
 217                 if (error != 0) {
 218                         device_printf(dev, "cannot get clock %d\n", error);
 219                         return;
 220                 }
 221                 def.parent_names[i] = clk_get_name(clk_parent);
 222                 if (bootverbose)
 223                         device_printf(dev, "clk parent: %s\n",
 224                             def.parent_names[i]);
 225                 clk_release(clk_parent);
 226         }
 227         def.parent_cnt = ncells;
 228
 229         clk = clknode_create(clkdom, &rk3399_emmccardclk_clknode_class, &def);
 230         if (clk == NULL) {
 231                 device_printf(dev, "cannot create clknode\n");
 232                 return;
 233         }
 234
 235         sc = clknode_get_softc(clk);
 236         sc->reg = paddr;
 237         sc->clkdev = device_get_parent(dev);
 238
 239         clknode_register(clkdom, clk);
 240
 241         if (clkdom_finit(clkdom) != 0) {
 242                 device_printf(dev, "cannot finalize clkdom initialization\n");
 243                 return;
 244         }
 245
 246         if (bootverbose)
 247                 clkdom_dump(clkdom);
 248 }
 249
 250 static int
 251 sdhci_init_rk3399(device_t dev)
 252 {
 253         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 254         struct syscon *grf = NULL;
 255         phandle_t node;
 256         uint64_t freq;
 257         uint32_t mask, val;
 258         int error;
 259
 260         /* Get and activate clocks */
 261         error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin);
 262         if (error != 0) {
 263                 device_printf(dev, "cannot get xin clock\n");
 264                 return (ENXIO);
 265         }
 266         error = clk_enable(sc->clk_xin);
 267         if (error != 0) {
 268                 device_printf(dev, "cannot enable xin clock\n");
 269                 return (ENXIO);
 270         }
 271         error = clk_get_freq(sc->clk_xin, &freq);
 272         if (error != 0) {
 273                 device_printf(dev, "cannot get xin clock frequency\n");
 274                 return (ENXIO);
 275         }
 276         error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb);
 277         if (error != 0) {
 278                 device_printf(dev, "cannot get ahb clock\n");
 279                 return (ENXIO);
 280         }
 281         error = clk_enable(sc->clk_ahb);
 282         if (error != 0) {
 283                 device_printf(dev, "cannot enable ahb clock\n");
 284                 return (ENXIO);
 285         }
 286
 287         /* Register clock */
 288         sdhci_init_rk3399_emmccardclk(dev);
 289
 290         /* Enable PHY */
 291         error = phy_get_by_ofw_name(dev, 0, "phy_arasan", &sc->phy);
 292         if (error != 0) {
 293                 device_printf(dev, "Could not get phy\n");
 294                 return (ENXIO);
 295         }
 296         error = phy_enable(sc->phy);
 297         if (error != 0) {
 298                 device_printf(dev, "Could not enable phy\n");
 299                 return (ENXIO);
 300         }
 301         /* Get syscon */
 302         node = ofw_bus_get_node(dev);
 303         if (OF_hasprop(node, "arasan,soc-ctl-syscon") &&
 304             syscon_get_by_ofw_property(dev, node,
 305             "arasan,soc-ctl-syscon", &grf) != 0) {
 306                 device_printf(dev, "cannot get grf driver handle\n");
 307                 return (ENXIO);
 308         }
 309
 310         /* Disable clock multiplier */
 311         mask = RK3399_CORECFG_CLOCKMULTIPLIER;
 312         val = 0;
 313         SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val);
 314
 315         /* Set base clock frequency */
 316         mask = RK3399_CORECFG_BASECLKFREQ;
 317         val = SHIFTIN((freq + (1000000 / 2)) / 1000000,
 318             RK3399_CORECFG_BASECLKFREQ);
 319         SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val);
 320
 321         return (0);
 322 }
 323 #endif
 324
 325 static uint8_t
 326 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 327 {
 328         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 329
 330         return (bus_read_1(sc->mem_res[slot->num], off));
 331 }
 332
 333 static void
 334 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 335     uint8_t val)
 336 {
 337         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 338
 339         bus_write_1(sc->mem_res[slot->num], off, val);
 340 }
 341
 342 static uint16_t
 343 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 344 {
 345         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 346
 347         return (bus_read_2(sc->mem_res[slot->num], off));
 348 }
 349
 350 static void
 351 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 352     uint16_t val)
 353 {
 354         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 355
 356         bus_write_2(sc->mem_res[slot->num], off, val);
 357 }
 358
 359 static uint32_t
 360 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 361 {
 362         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 363         uint32_t val32;
 364
 365         val32 = bus_read_4(sc->mem_res[slot->num], off);
 366         if (off == SDHCI_CAPABILITIES && sc->no_18v)
 367                 val32 &= ~SDHCI_CAN_VDD_180;
 368
 369         return (val32);
 370 }
 371
 372 static void
 373 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 374     uint32_t val)
 375 {
 376         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 377
 378         bus_write_4(sc->mem_res[slot->num], off, val);
 379 }
 380
 381 static void
 382 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot,
 383     bus_size_t off, uint32_t *data, bus_size_t count)
 384 {
 385         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 386
 387         bus_read_multi_4(sc->mem_res[slot->num], off, data, count);
 388 }
 389
 390 static void
 391 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
 392     bus_size_t off, uint32_t *data, bus_size_t count)
 393 {
 394         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 395
 396         bus_write_multi_4(sc->mem_res[slot->num], off, data, count);
 397 }
 398
 399 static void
 400 sdhci_fdt_intr(void *arg)
 401 {
 402         struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg;
 403         int i;
 404
 405         for (i = 0; i < sc->num_slots; i++)
 406                 sdhci_generic_intr(&sc->slots[i]);
 407 }
 408
 409 static int
 410 sdhci_fdt_get_ro(device_t bus, device_t dev)
 411 {
 412         struct sdhci_fdt_softc *sc = device_get_softc(bus);
 413
 414         return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
 415 }
 416
 417 static int
 418 sdhci_fdt_probe(device_t dev)
 419 {
 420         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 421         phandle_t node;
 422         pcell_t cid;
 423
 424         sc->quirks = 0;
 425         sc->num_slots = 1;
 426         sc->max_clk = 0;
 427
 428         if (!ofw_bus_status_okay(dev))
 429                 return (ENXIO);
 430
 431         switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
 432         case SDHCI_FDT_ARMADA38X:
 433                 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP;
 434                 device_set_desc(dev, "ARMADA38X SDHCI controller");
 435                 break;
 436         case SDHCI_FDT_GENERIC:
 437                 device_set_desc(dev, "generic fdt SDHCI controller");
 438                 break;
 439         case SDHCI_FDT_QUALCOMM:
 440                 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
 441                     SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY;
 442                 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
 443                 device_set_desc(dev, "Qualcomm FDT SDHCI controller");
 444                 break;
 445         case SDHCI_FDT_RK3399:
 446                 device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller");
 447                 break;
 448         case SDHCI_FDT_XLNX_ZY7:
 449                 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
 450                 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
 451                 break;
 452         default:
 453                 return (ENXIO);
 454         }
 455
 456         node = ofw_bus_get_node(dev);
 457
 458         /* Allow dts to patch quirks, slots, and max-frequency. */
 459         if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
 460                 sc->quirks = cid;
 461         if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0)
 462                 sc->num_slots = cid;
 463         if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
 464                 sc->max_clk = cid;
 465         if (OF_hasprop(node, "no-1-8-v"))
 466                 sc->no_18v = true;
 467         if (OF_hasprop(node, "wp-inverted"))
 468                 sc->wp_inverted = true;
 469
 470         return (0);
 471 }
 472
 473 static int
 474 sdhci_fdt_attach(device_t dev)
 475 {
 476         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 477         struct sdhci_slot *slot;
 478         int err, slots, rid, i;
 479
 480         sc->dev = dev;
 481
 482         /* Allocate IRQ. */
 483         rid = 0;
 484         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 485             RF_ACTIVE);
 486         if (sc->irq_res == NULL) {
 487                 device_printf(dev, "Can't allocate IRQ\n");
 488                 return (ENOMEM);
 489         }
 490
 491 #ifdef EXT_RESOURCES
 492         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
 493             SDHCI_FDT_RK3399) {
 494                 /* Initialize SDHCI */
 495                 err = sdhci_init_rk3399(dev);
 496                 if (err != 0) {
 497                         device_printf(dev, "Cannot init RK3399 SDHCI\n");
 498                         return (err);
 499                 }
 500         }
 501 #endif
 502
 503         /* Scan all slots. */
 504         slots = sc->num_slots;  /* number of slots determined in probe(). */
 505         sc->num_slots = 0;
 506         for (i = 0; i < slots; i++) {
 507                 slot = &sc->slots[sc->num_slots];
 508
 509                 /* Allocate memory. */
 510                 rid = 0;
 511                 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 512                                                         &rid, RF_ACTIVE);
 513                 if (sc->mem_res[i] == NULL) {
 514                         device_printf(dev,
 515                             "Can't allocate memory for slot %d\n", i);
 516                         continue;
 517                 }
 518
 519                 slot->quirks = sc->quirks;
 520                 slot->caps = sc->caps;
 521                 slot->max_clk = sc->max_clk;
 522                 slot->sdma_boundary = sc->sdma_boundary;
 523
 524                 if (sdhci_init_slot(dev, slot, i) != 0)
 525                         continue;
 526
 527                 sc->num_slots++;
 528         }
 529         device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
 530
 531         /* Activate the interrupt */
 532         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
 533             NULL, sdhci_fdt_intr, sc, &sc->intrhand);
 534         if (err) {
 535                 device_printf(dev, "Cannot setup IRQ\n");
 536                 return (err);
 537         }
 538
 539         /* Process cards detection. */
 540         for (i = 0; i < sc->num_slots; i++)
 541                 sdhci_start_slot(&sc->slots[i]);
 542
 543         return (0);
 544 }
 545
 546 static int
 547 sdhci_fdt_detach(device_t dev)
 548 {
 549         struct sdhci_fdt_softc *sc = device_get_softc(dev);
 550         int i;
 551
 552         bus_generic_detach(dev);
 553         bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
 554         bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
 555             sc->irq_res);
 556
 557         for (i = 0; i < sc->num_slots; i++) {
 558                 sdhci_cleanup_slot(&sc->slots[i]);
 559                 bus_release_resource(dev, SYS_RES_MEMORY,
 560                     rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
 561         }
 562
 563         return (0);
 564 }
 565
 566 static device_method_t sdhci_fdt_methods[] = {
 567         /* device_if */
 568         DEVMETHOD(device_probe,         sdhci_fdt_probe),
 569         DEVMETHOD(device_attach,        sdhci_fdt_attach),
 570         DEVMETHOD(device_detach,        sdhci_fdt_detach),
 571
 572         /* Bus interface */
 573         DEVMETHOD(bus_read_ivar,        sdhci_generic_read_ivar),
 574         DEVMETHOD(bus_write_ivar,       sdhci_generic_write_ivar),
 575
 576         /* mmcbr_if */
 577         DEVMETHOD(mmcbr_update_ios,     sdhci_generic_update_ios),
 578         DEVMETHOD(mmcbr_request,        sdhci_generic_request),
 579         DEVMETHOD(mmcbr_get_ro,         sdhci_fdt_get_ro),
 580         DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
 581         DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
 582
 583         /* SDHCI registers accessors */
 584         DEVMETHOD(sdhci_read_1,         sdhci_fdt_read_1),
 585         DEVMETHOD(sdhci_read_2,         sdhci_fdt_read_2),
 586         DEVMETHOD(sdhci_read_4,         sdhci_fdt_read_4),
 587         DEVMETHOD(sdhci_read_multi_4,   sdhci_fdt_read_multi_4),
 588         DEVMETHOD(sdhci_write_1,        sdhci_fdt_write_1),
 589         DEVMETHOD(sdhci_write_2,        sdhci_fdt_write_2),
 590         DEVMETHOD(sdhci_write_4,        sdhci_fdt_write_4),
 591         DEVMETHOD(sdhci_write_multi_4,  sdhci_fdt_write_multi_4),
 592
 593         DEVMETHOD_END
 594 };
 595
 596 static driver_t sdhci_fdt_driver = {
 597         "sdhci_fdt",
 598         sdhci_fdt_methods,
 599         sizeof(struct sdhci_fdt_softc),
 600 };
 601 static devclass_t sdhci_fdt_devclass;
 602
 603 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass,
 604     NULL, NULL);
 605 SDHCI_DEPEND(sdhci_fdt);
 606 #ifndef MMCCAM
 607 MMC_DECLARE_BRIDGE(sdhci_fdt);
 608 #endif