2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2020 Alstom Group.
5 * Copyright (c) 2020 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
45 #include <dev/extres/clk/clk.h>
46 #include <dev/mmc/bridge.h>
47 #include <dev/mmc/mmcbrvar.h>
48 #include <dev/mmc/mmc_fdt_helpers.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/sdhci/sdhci.h>
52 #include <dev/sdhci/sdhci_fdt_gpio.h>
57 #define RD4 (sc->read)
58 #define WR4 (sc->write)
60 #define SDHCI_FSL_PRES_STATE 0x24
61 #define SDHCI_FSL_PRES_SDSTB (1 << 3)
62 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07
64 #define SDHCI_FSL_PROT_CTRL 0x28
65 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1)
66 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1)
67 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1)
68 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1)
69 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4)
70 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4)
71 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4)
72 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8)
74 #define SDHCI_FSL_SYS_CTRL 0x2c
75 #define SDHCI_FSL_CLK_IPGEN (1 << 0)
76 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3)
77 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0
78 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4
79 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00
80 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8
82 #define SDHCI_FSL_WTMK_LVL 0x44
83 #define SDHCI_FSL_WTMK_RD_512B (0 << 0)
84 #define SDHCI_FSL_WTMK_WR_512B (0 << 15)
86 #define SDHCI_FSL_HOST_VERSION 0xfc
87 #define SDHCI_FSL_CAPABILITIES2 0x114
89 #define SDHCI_FSL_ESDHC_CTRL 0x40c
90 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6)
91 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19)
93 #define SDHCI_FSL_CAN_VDD_MASK \
94 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330)
96 struct sdhci_fsl_fdt_softc {
98 const struct sdhci_fsl_fdt_soc_data *soc_data;
99 struct resource *mem_res;
100 struct resource *irq_res;
104 struct sdhci_fdt_gpio *gpio;
105 struct sdhci_slot slot;
107 uint32_t cmd_and_mode;
109 struct mmc_fdt_helper fdt_helper;
111 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t);
112 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t);
115 struct sdhci_fsl_fdt_soc_data {
120 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = {
121 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT |
122 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
126 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = {
127 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP,
131 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = {
136 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = {
137 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data},
138 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data},
139 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data},
144 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
147 return (be32toh(bus_read_4(sc->mem_res, off)));
151 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
154 bus_write_4(sc->mem_res, off, htobe32(val));
158 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
161 return (bus_read_4(sc->mem_res, off));
165 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
168 bus_write_4(sc->mem_res, off, val);
173 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc)
177 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN;
178 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)
179 val |= SDHCI_CLOCK_INT_STABLE;
180 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)
181 val |= SDHCI_CLOCK_CARD_EN;
187 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, uint16_t val)
189 uint32_t div, freq, prescale, val32;
191 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK;
192 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
194 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
195 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN);
199 div = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
200 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
201 SDHCI_DIVIDER_MASK_LEN;
203 freq = sc->maxclk_hz;
205 freq = sc->maxclk_hz / (2 * div);
207 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16); )
209 for (div = 1; freq < sc->baseclk_hz / (prescale * div); )
213 device_printf(sc->dev,
214 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n",
215 freq, sc->baseclk_hz / (prescale * div),
216 sc->baseclk_hz, prescale, div);
222 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK);
223 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT;
224 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT;
225 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN;
226 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
230 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
232 struct sdhci_fsl_fdt_softc *sc;
233 uint32_t wrk32, val32;
235 sc = device_get_softc(dev);
238 case SDHCI_HOST_CONTROL:
239 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
240 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
241 SDHCI_CTRL_FORCE_CARD);
242 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT)
243 val32 |= SDHCI_CTRL_4BITBUS;
244 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT)
245 val32 |= SDHCI_CTRL_8BITBUS;
247 case SDHCI_POWER_CONTROL:
248 return (SDHCI_POWER_ON | SDHCI_POWER_300);
253 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);
257 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
259 struct sdhci_fsl_fdt_softc *sc;
262 sc = device_get_softc(dev);
265 case SDHCI_CLOCK_CONTROL:
266 return (sdhci_fsl_fdt_get_clock(sc));
267 case SDHCI_HOST_VERSION:
268 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);
269 case SDHCI_TRANSFER_MODE:
270 return (sc->cmd_and_mode & UINT16_MAX);
271 case SDHCI_COMMAND_FLAGS:
272 return (sc->cmd_and_mode >> 16);
273 case SDHCI_SLOT_INT_STATUS:
275 * eSDHC hardware manages only a single slot.
276 * Synthesize a slot interrupt status register for slot 1 below.
278 val32 = RD4(sc, SDHCI_INT_STATUS);
279 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
282 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX);
287 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
289 struct sdhci_fsl_fdt_softc *sc;
290 uint32_t wrk32, val32;
292 sc = device_get_softc(dev);
294 if (off == SDHCI_BUFFER)
295 return (bus_read_4(sc->mem_res, off));
296 if (off == SDHCI_CAPABILITIES2)
297 off = SDHCI_FSL_CAPABILITIES2;
299 val32 = RD4(sc, off);
301 if (off == SDHCI_PRESENT_STATE) {
303 val32 &= SDHCI_FSL_PRES_COMPAT_MASK;
304 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
305 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD;
312 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
313 uint32_t *data, bus_size_t count)
315 struct sdhci_fsl_fdt_softc *sc;
317 sc = device_get_softc(dev);
318 bus_read_multi_4(sc->mem_res, off, data, count);
322 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
325 struct sdhci_fsl_fdt_softc *sc;
328 sc = device_get_softc(dev);
331 case SDHCI_HOST_CONTROL:
332 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
333 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK;
334 val32 |= (val & SDHCI_CTRL_LED);
336 if (val & SDHCI_CTRL_8BITBUS)
337 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT;
339 /* Bus width is 1-bit when this flag is not set. */
340 val32 |= (val & SDHCI_CTRL_4BITBUS);
341 /* Enable SDMA by masking out this field. */
342 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK;
343 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD);
344 val32 |= (val & (SDHCI_CTRL_CARD_DET |
345 SDHCI_CTRL_FORCE_CARD));
346 WR4(sc, SDHCI_FSL_PROT_CTRL, val32);
348 case SDHCI_POWER_CONTROL:
350 case SDHCI_SOFTWARE_RESET:
351 val &= ~SDHCI_RESET_ALL;
354 val32 = RD4(sc, off & ~3);
355 val32 &= ~(UINT8_MAX << (off & 3) * 8);
356 val32 |= (val << (off & 3) * 8);
357 WR4(sc, off & ~3, val32);
363 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
366 struct sdhci_fsl_fdt_softc *sc;
369 sc = device_get_softc(dev);
372 case SDHCI_CLOCK_CONTROL:
373 fsl_sdhc_fdt_set_clock(sc, val);
376 * eSDHC hardware combines command and mode into a single
377 * register. Cache it here, so that command isn't written
380 case SDHCI_TRANSFER_MODE:
381 sc->cmd_and_mode = val;
383 case SDHCI_COMMAND_FLAGS:
385 (sc->cmd_and_mode & UINT16_MAX) | (val << 16);
386 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
387 sc->cmd_and_mode = 0;
390 val32 = RD4(sc, off & ~3);
391 val32 &= ~(UINT16_MAX << (off & 3) * 8);
392 val32 |= ((val & UINT16_MAX) << (off & 3) * 8);
393 WR4(sc, off & ~3, val32);
399 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
402 struct sdhci_fsl_fdt_softc *sc;
404 sc = device_get_softc(dev);
408 bus_write_4(sc->mem_res, off, val);
411 * eSDHC hardware lacks support for the SDMA buffer boundary
412 * feature and instead generates SDHCI_INT_DMA_END interrupts
413 * after each completed DMA data transfer.
414 * Since this duplicates the SDHCI_INT_DATA_END functionality,
415 * mask out the unneeded SDHCI_INT_DMA_END interrupt.
417 case SDHCI_INT_ENABLE:
418 case SDHCI_SIGNAL_ENABLE:
419 val &= ~SDHCI_INT_DMA_END;
428 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
429 bus_size_t off, uint32_t *data, bus_size_t count)
431 struct sdhci_fsl_fdt_softc *sc;
433 sc = device_get_softc(dev);
434 bus_write_multi_4(sc->mem_res, off, data, count);
438 sdhci_fsl_fdt_irq(void *arg)
440 struct sdhci_fsl_fdt_softc *sc;
443 sdhci_generic_intr(&sc->slot);
448 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev)
451 struct sdhci_fsl_fdt_softc *sc;
453 struct sdhci_slot *slot;
455 err = sdhci_generic_update_ios(brdev, reqdev);
459 sc = device_get_softc(brdev);
460 slot = device_get_ivars(reqdev);
461 ios = &slot->host.ios;
463 switch (ios->power_mode) {
468 device_printf(sc->dev, "Powering down sd/mmc\n");
470 if (sc->fdt_helper.vmmc_supply)
471 regulator_disable(sc->fdt_helper.vmmc_supply);
472 if (sc->fdt_helper.vqmmc_supply)
473 regulator_disable(sc->fdt_helper.vqmmc_supply);
477 device_printf(sc->dev, "Powering up sd/mmc\n");
479 if (sc->fdt_helper.vmmc_supply)
480 regulator_enable(sc->fdt_helper.vmmc_supply);
481 if (sc->fdt_helper.vqmmc_supply)
482 regulator_enable(sc->fdt_helper.vqmmc_supply);
490 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev)
492 struct sdhci_fsl_fdt_softc *sc;
493 struct sdhci_slot *slot;
496 sc = device_get_softc(brdev);
498 if (sc->fdt_helper.vqmmc_supply == NULL)
501 err = sdhci_generic_switch_vccq(brdev, reqdev);
505 slot = device_get_ivars(reqdev);
506 switch (slot->host.ios.vccq) {
517 err = regulator_set_voltage(sc->fdt_helper.vqmmc_supply, uvolt, uvolt);
519 device_printf(sc->dev,
520 "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt);
528 sdhci_fsl_fdt_get_ro(device_t bus, device_t child)
530 struct sdhci_fsl_fdt_softc *sc;
532 sc = device_get_softc(bus);
533 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
537 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot)
539 struct sdhci_fsl_fdt_softc *sc;
541 sc = device_get_softc(dev);
542 return (sdhci_fdt_gpio_get_present(sc->gpio));
546 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len)
548 uint32_t vdd_min, vdd_max;
549 uint32_t vdd_mask = 0;
552 /* Ranges are organized as pairs of values. */
553 if ((len % 2) != 0) {
554 device_printf(dev, "Invalid voltage range\n");
559 for (i = 0; i < len; i++) {
560 vdd_min = vdd_ranges[2 * i];
561 vdd_max = vdd_ranges[2 * i + 1];
563 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 ||
564 vdd_max < 1650 || vdd_max > 3600) {
565 device_printf(dev, "Voltage range %d - %d is out of bounds\n",
570 if (vdd_min <= 1800 && vdd_max >= 1800)
571 vdd_mask |= SDHCI_CAN_VDD_180;
572 if (vdd_min <= 3000 && vdd_max >= 3000)
573 vdd_mask |= SDHCI_CAN_VDD_300;
574 if (vdd_min <= 3300 && vdd_max >= 3300)
575 vdd_mask |= SDHCI_CAN_VDD_330;
582 sdhci_fsl_fdt_of_parse(device_t dev)
584 struct sdhci_fsl_fdt_softc *sc;
586 pcell_t *voltage_ranges;
587 uint32_t vdd_mask = 0;
590 sc = device_get_softc(dev);
591 node = ofw_bus_get_node(dev);
593 /* Call mmc_fdt_parse in order to get mmc related properties. */
594 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host);
596 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot,
597 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND);
598 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot,
599 SDHCI_CAPABILITIES2);
601 /* Parse the "voltage-ranges" dts property. */
602 num_ranges = OF_getencprop_alloc(node, "voltage-ranges",
603 (void **) &voltage_ranges);
606 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges,
607 num_ranges / sizeof(uint32_t));
608 OF_prop_free(voltage_ranges);
610 /* Overwrite voltage caps only if we got something from dts. */
612 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) {
613 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK);
614 sc->slot.caps |= vdd_mask;
615 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS;
620 sdhci_fsl_fdt_attach(device_t dev)
622 struct sdhci_fsl_fdt_softc *sc;
623 struct mmc_host *host;
624 uint32_t val, buf_order;
631 node = ofw_bus_get_node(dev);
632 sc = device_get_softc(dev);
633 ocd_data = ofw_bus_search_compatible(dev,
634 sdhci_fsl_fdt_compat_data)->ocd_data;
635 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data;
637 sc->slot.quirks = sc->soc_data->quirks;
638 host = &sc->slot.host;
641 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
643 if (sc->mem_res == NULL) {
645 "Could not allocate resources for controller\n");
650 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
652 if (sc->irq_res == NULL) {
654 "Could not allocate irq resources for controller\n");
659 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
660 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie);
662 device_printf(dev, "Could not setup IRQ handler\n");
663 goto err_free_irq_res;
666 ret = clk_get_by_ofw_index(dev, node, 0, &clk);
668 device_printf(dev, "Parent clock not found\n");
672 ret = clk_get_freq(clk, &clk_hz);
675 "Could not get parent clock frequency\n");
679 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div;
681 /* Figure out eSDHC block endianness before we touch any HW regs. */
682 if (OF_hasprop(node, "little-endian")) {
684 sc->write = write_le;
685 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE;
688 sc->write = write_be;
689 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP;
692 sdhci_fsl_fdt_of_parse(dev);
693 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz;
696 * Setting this register affects byte order in SDHCI_BUFFER only.
697 * If the eSDHC block is connected over a big-endian bus, the data
698 * read from/written to the buffer will be already byte swapped.
699 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert
700 * the byte order again, resulting in a native byte order.
701 * The read/write callbacks accommodate for this behavior.
703 val = RD4(sc, SDHCI_FSL_PROT_CTRL);
704 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK;
705 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order);
708 * Gate the SD clock and set its source to
709 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set
712 val = RD4(sc, SDHCI_CLOCK_CONTROL);
713 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN);
714 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
715 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2);
716 sc->slot.max_clk = sc->maxclk_hz;
717 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
720 * Set the buffer watermark level to 128 words (512 bytes) for both
721 * read and write. The hardware has a restriction that when the read or
722 * write ready status is asserted, that means you can read exactly the
723 * number of words set in the watermark register before you have to
724 * re-check the status and potentially wait for more data. The main
725 * sdhci driver provides no hook for doing status checking on less than
726 * a full block boundary, so we set the watermark level to be a full
727 * block. Reads and writes where the block size is less than the
728 * watermark size will work correctly too, no need to change the
729 * watermark for different size blocks. However, 128 is the maximum
730 * allowed for the watermark, so PIO is limitted to 512 byte blocks.
732 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B |
733 SDHCI_FSL_WTMK_RD_512B);
735 ret = sdhci_init_slot(dev, &sc->slot, 0);
738 sc->slot_init_done = true;
739 sdhci_start_slot(&sc->slot);
741 return (bus_generic_attach(dev));
744 sdhci_fdt_gpio_teardown(sc->gpio);
746 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
748 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
750 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
755 sdhci_fsl_fdt_detach(device_t dev)
757 struct sdhci_fsl_fdt_softc *sc;
759 sc = device_get_softc(dev);
760 if (sc->slot_init_done)
761 sdhci_cleanup_slot(&sc->slot);
762 if (sc->gpio != NULL)
763 sdhci_fdt_gpio_teardown(sc->gpio);
764 if (sc->irq_cookie != NULL)
765 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
766 if (sc->irq_res != NULL)
767 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
768 if (sc->mem_res != NULL)
769 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
774 sdhci_fsl_fdt_probe(device_t dev)
777 if (!ofw_bus_status_okay(dev))
780 if (!ofw_bus_search_compatible(dev,
781 sdhci_fsl_fdt_compat_data)->ocd_data)
784 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller");
785 return (BUS_PROBE_DEFAULT);
789 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which,
792 struct sdhci_slot *slot = device_get_ivars(child);
794 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) {
796 * In the absence of SDMA buffer boundary functionality,
797 * limit the maximum data length per read/write command
798 * to bounce buffer size.
800 *result = howmany(slot->sdma_bbufsz, 512);
803 return (sdhci_generic_read_ivar(bus, child, which, result));
806 static const device_method_t sdhci_fsl_fdt_methods[] = {
807 /* Device interface. */
808 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe),
809 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach),
810 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach),
813 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar),
814 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
816 /* MMC bridge interface. */
817 DEVMETHOD(mmcbr_request, sdhci_generic_request),
818 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro),
819 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
820 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
821 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq),
822 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios),
824 /* SDHCI accessors. */
825 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1),
826 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2),
827 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4),
828 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4),
829 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1),
830 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2),
831 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4),
832 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4),
833 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present),
837 static devclass_t sdhci_fsl_fdt_devclass;
838 static driver_t sdhci_fsl_fdt_driver = {
840 sdhci_fsl_fdt_methods,
841 sizeof(struct sdhci_fsl_fdt_softc),
844 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver,
845 sdhci_fsl_fdt_devclass, NULL, NULL);
846 SDHCI_DEPEND(sdhci_fsl_fdt);
849 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt);