2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_mmccam.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/resource.h>
42 #include <sys/sysctl.h>
43 #include <sys/taskqueue.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
51 #include <dev/mmc/bridge.h>
53 #include <dev/sdhci/sdhci.h>
61 #define PCI_SDHCI_IFPIO 0x00
62 #define PCI_SDHCI_IFDMA 0x01
63 #define PCI_SDHCI_IFVENDOR 0x02
65 #define PCI_SLOT_INFO 0x40 /* 8 bits */
66 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
67 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
70 * RICOH specific PCI registers
72 #define SDHC_PCI_MODE_KEY 0xf9
73 #define SDHC_PCI_MODE 0x150
74 #define SDHC_PCI_MODE_SD20 0x10
75 #define SDHC_PCI_BASE_FREQ_KEY 0xfc
76 #define SDHC_PCI_BASE_FREQ 0xe1
78 static const struct sdhci_device {
84 { 0x08221180, 0xffff, "RICOH R5C822 SD",
85 SDHCI_QUIRK_FORCE_DMA },
86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD",
87 SDHCI_QUIRK_FORCE_DMA |
88 SDHCI_QUIRK_LOWER_FREQUENCY },
89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
90 SDHCI_QUIRK_LOWER_FREQUENCY },
91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
92 SDHCI_QUIRK_FORCE_DMA },
93 { 0x05501524, 0xffff, "ENE CB712 SD",
94 SDHCI_QUIRK_BROKEN_TIMINGS },
95 { 0x05511524, 0xffff, "ENE CB712 SD 2",
96 SDHCI_QUIRK_BROKEN_TIMINGS },
97 { 0x07501524, 0xffff, "ENE CB714 SD",
98 SDHCI_QUIRK_RESET_ON_IOS |
99 SDHCI_QUIRK_BROKEN_TIMINGS },
100 { 0x07511524, 0xffff, "ENE CB714 SD 2",
101 SDHCI_QUIRK_RESET_ON_IOS |
102 SDHCI_QUIRK_BROKEN_TIMINGS },
103 { 0x410111ab, 0xffff, "Marvell CaFe SD",
104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
105 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
106 SDHCI_QUIRK_32BIT_DMA_SIZE |
107 SDHCI_QUIRK_RESET_AFTER_REQUEST },
108 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
109 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
110 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
111 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
112 SDHCI_QUIRK_WAIT_WHILE_BUSY |
113 SDHCI_QUIRK_MMC_DDR52 |
114 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
115 SDHCI_QUIRK_PRESET_VALUE_BROKEN},
116 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
117 SDHCI_QUIRK_WAIT_WHILE_BUSY |
118 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
119 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
120 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
121 SDHCI_QUIRK_WAIT_WHILE_BUSY |
122 SDHCI_QUIRK_MMC_DDR52 |
123 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
124 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
125 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
126 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
127 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
128 SDHCI_QUIRK_WAIT_WHILE_BUSY |
129 SDHCI_QUIRK_MMC_DDR52 |
130 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
131 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
132 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
133 SDHCI_QUIRK_WAIT_WHILE_BUSY |
134 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
135 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
136 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
137 SDHCI_QUIRK_WAIT_WHILE_BUSY |
138 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
139 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
140 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
141 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
142 SDHCI_QUIRK_WAIT_WHILE_BUSY |
143 SDHCI_QUIRK_MMC_DDR52 |
144 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
145 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
150 struct sdhci_pci_softc {
151 u_int quirks; /* Chip specific quirks */
152 struct resource *irq_res; /* IRQ resource */
153 void *intrhand; /* Interrupt handle */
155 int num_slots; /* Number of slots on this controller */
156 struct sdhci_slot slots[6];
157 struct resource *mem_res[6]; /* Memory resource */
158 uint8_t cfg_freq; /* Saved frequency */
159 uint8_t cfg_mode; /* Saved mode */
162 static int sdhci_enable_msi = 1;
163 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
164 0, "Enable MSI interrupts");
167 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
169 struct sdhci_pci_softc *sc = device_get_softc(dev);
171 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
172 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
173 return bus_read_1(sc->mem_res[slot->num], off);
177 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
178 bus_size_t off, uint8_t val)
180 struct sdhci_pci_softc *sc = device_get_softc(dev);
182 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
183 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
184 bus_write_1(sc->mem_res[slot->num], off, val);
188 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
190 struct sdhci_pci_softc *sc = device_get_softc(dev);
192 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
193 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
194 return bus_read_2(sc->mem_res[slot->num], off);
198 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
199 bus_size_t off, uint16_t val)
201 struct sdhci_pci_softc *sc = device_get_softc(dev);
203 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
204 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
205 bus_write_2(sc->mem_res[slot->num], off, val);
209 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
211 struct sdhci_pci_softc *sc = device_get_softc(dev);
213 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
214 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
215 return bus_read_4(sc->mem_res[slot->num], off);
219 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
220 bus_size_t off, uint32_t val)
222 struct sdhci_pci_softc *sc = device_get_softc(dev);
224 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
225 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
226 bus_write_4(sc->mem_res[slot->num], off, val);
230 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
231 bus_size_t off, uint32_t *data, bus_size_t count)
233 struct sdhci_pci_softc *sc = device_get_softc(dev);
235 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
239 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
240 bus_size_t off, uint32_t *data, bus_size_t count)
242 struct sdhci_pci_softc *sc = device_get_softc(dev);
244 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
247 static void sdhci_pci_intr(void *arg);
250 sdhci_lower_frequency(device_t dev)
252 struct sdhci_pci_softc *sc = device_get_softc(dev);
256 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
258 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
259 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
260 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
261 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
264 * Some SD/MMC cards don't work with the default base
265 * clock frequency of 200 MHz. Lower it to 50 MHz.
267 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
268 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
269 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
270 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
274 sdhci_restore_frequency(device_t dev)
276 struct sdhci_pci_softc *sc = device_get_softc(dev);
279 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
280 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
281 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
283 /* Restore frequency. */
284 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
285 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
286 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
290 sdhci_pci_probe(device_t dev)
294 uint8_t class, subclass;
297 model = (uint32_t)pci_get_device(dev) << 16;
298 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
299 subvendor = pci_get_subvendor(dev);
300 class = pci_get_class(dev);
301 subclass = pci_get_subclass(dev);
304 for (i = 0; sdhci_devices[i].model != 0; i++) {
305 if (sdhci_devices[i].model == model &&
306 (sdhci_devices[i].subvendor == 0xffff ||
307 sdhci_devices[i].subvendor == subvendor)) {
308 device_set_desc(dev, sdhci_devices[i].desc);
309 result = BUS_PROBE_DEFAULT;
313 if (result == ENXIO && class == PCIC_BASEPERIPH &&
314 subclass == PCIS_BASEPERIPH_SDHC) {
315 device_set_desc(dev, "Generic SD HCI");
316 result = BUS_PROBE_GENERIC;
323 sdhci_pci_attach(device_t dev)
325 struct sdhci_pci_softc *sc = device_get_softc(dev);
326 struct sdhci_slot *slot;
329 int bar, err, rid, slots, i;
331 model = (uint32_t)pci_get_device(dev) << 16;
332 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
333 subvendor = pci_get_subvendor(dev);
334 /* Apply chip specific quirks. */
335 for (i = 0; sdhci_devices[i].model != 0; i++) {
336 if (sdhci_devices[i].model == model &&
337 (sdhci_devices[i].subvendor == 0xffff ||
338 sdhci_devices[i].subvendor == subvendor)) {
339 sc->quirks = sdhci_devices[i].quirks;
343 sc->quirks &= ~sdhci_quirk_clear;
344 sc->quirks |= sdhci_quirk_set;
346 /* Some controllers need to be bumped into the right mode. */
347 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
348 sdhci_lower_frequency(dev);
349 /* Read slots info from PCI registers. */
350 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
351 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
352 slots = PCI_SLOT_INFO_SLOTS(slots);
353 if (slots > 6 || bar > 5) {
354 device_printf(dev, "Incorrect slots information (%d, %d).\n",
361 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
363 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
364 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
365 if (sc->irq_res == NULL) {
366 device_printf(dev, "Can't allocate IRQ\n");
367 pci_release_msi(dev);
370 /* Scan all slots. */
371 for (i = 0; i < slots; i++) {
372 slot = &sc->slots[sc->num_slots];
374 /* Allocate memory. */
375 rid = PCIR_BAR(bar + i);
376 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
378 if (sc->mem_res[i] == NULL) {
380 "Can't allocate memory for slot %d\n", i);
384 slot->quirks = sc->quirks;
386 if (sdhci_init_slot(dev, slot, i) != 0)
391 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
392 /* Activate the interrupt */
393 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
394 NULL, sdhci_pci_intr, sc, &sc->intrhand);
396 device_printf(dev, "Can't setup IRQ\n");
397 pci_enable_busmaster(dev);
398 /* Process cards detection. */
399 for (i = 0; i < sc->num_slots; i++) {
400 sdhci_start_slot(&sc->slots[i]);
407 sdhci_pci_detach(device_t dev)
409 struct sdhci_pci_softc *sc = device_get_softc(dev);
412 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
413 bus_release_resource(dev, SYS_RES_IRQ,
414 rman_get_rid(sc->irq_res), sc->irq_res);
415 pci_release_msi(dev);
417 for (i = 0; i < sc->num_slots; i++) {
418 sdhci_cleanup_slot(&sc->slots[i]);
419 bus_release_resource(dev, SYS_RES_MEMORY,
420 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
422 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
423 sdhci_restore_frequency(dev);
428 sdhci_pci_shutdown(device_t dev)
430 struct sdhci_pci_softc *sc = device_get_softc(dev);
432 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
433 sdhci_restore_frequency(dev);
438 sdhci_pci_suspend(device_t dev)
440 struct sdhci_pci_softc *sc = device_get_softc(dev);
443 err = bus_generic_suspend(dev);
446 for (i = 0; i < sc->num_slots; i++)
447 sdhci_generic_suspend(&sc->slots[i]);
452 sdhci_pci_resume(device_t dev)
454 struct sdhci_pci_softc *sc = device_get_softc(dev);
457 for (i = 0; i < sc->num_slots; i++)
458 sdhci_generic_resume(&sc->slots[i]);
459 err = bus_generic_resume(dev);
462 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
463 sdhci_lower_frequency(dev);
468 sdhci_pci_intr(void *arg)
470 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
473 for (i = 0; i < sc->num_slots; i++)
474 sdhci_generic_intr(&sc->slots[i]);
477 static device_method_t sdhci_methods[] = {
479 DEVMETHOD(device_probe, sdhci_pci_probe),
480 DEVMETHOD(device_attach, sdhci_pci_attach),
481 DEVMETHOD(device_detach, sdhci_pci_detach),
482 DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
483 DEVMETHOD(device_suspend, sdhci_pci_suspend),
484 DEVMETHOD(device_resume, sdhci_pci_resume),
487 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
488 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
491 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
492 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
493 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
494 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
495 DEVMETHOD(mmcbr_request, sdhci_generic_request),
496 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
497 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
498 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
500 /* SDHCI accessors */
501 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
502 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
503 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
504 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
505 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
506 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
507 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
508 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
509 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
514 static driver_t sdhci_pci_driver = {
517 sizeof(struct sdhci_pci_softc),
519 static devclass_t sdhci_pci_devclass;
521 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
523 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
526 MMC_DECLARE_BRIDGE(sdhci_pci);