2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/resource.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/stdarg.h>
49 #include <dev/mmc/bridge.h>
50 #include <dev/mmc/mmcreg.h>
51 #include <dev/mmc/mmcbrvar.h>
61 #define PCI_SDHCI_IFPIO 0x00
62 #define PCI_SDHCI_IFDMA 0x01
63 #define PCI_SDHCI_IFVENDOR 0x02
65 #define PCI_SLOT_INFO 0x40 /* 8 bits */
66 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
67 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
70 * RICOH specific PCI registers
72 #define SDHC_PCI_MODE_KEY 0xf9
73 #define SDHC_PCI_MODE 0x150
74 #define SDHC_PCI_MODE_SD20 0x10
75 #define SDHC_PCI_BASE_FREQ_KEY 0xfc
76 #define SDHC_PCI_BASE_FREQ 0xe1
78 static const struct sdhci_device {
84 { 0x08221180, 0xffff, "RICOH R5C822 SD",
85 SDHCI_QUIRK_FORCE_DMA },
86 { 0xe8221180, 0xffff, "RICOH SD",
87 SDHCI_QUIRK_FORCE_DMA },
88 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
89 SDHCI_QUIRK_LOWER_FREQUENCY },
90 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
91 SDHCI_QUIRK_FORCE_DMA },
92 { 0x05501524, 0xffff, "ENE CB712 SD",
93 SDHCI_QUIRK_BROKEN_TIMINGS },
94 { 0x05511524, 0xffff, "ENE CB712 SD 2",
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x07501524, 0xffff, "ENE CB714 SD",
97 SDHCI_QUIRK_RESET_ON_IOS |
98 SDHCI_QUIRK_BROKEN_TIMINGS },
99 { 0x07511524, 0xffff, "ENE CB714 SD 2",
100 SDHCI_QUIRK_RESET_ON_IOS |
101 SDHCI_QUIRK_BROKEN_TIMINGS },
102 { 0x410111ab, 0xffff, "Marvell CaFe SD",
103 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
104 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
105 SDHCI_QUIRK_32BIT_DMA_SIZE |
106 SDHCI_QUIRK_RESET_AFTER_REQUEST },
111 struct sdhci_pci_softc {
112 device_t dev; /* Controller device */
113 u_int quirks; /* Chip specific quirks */
114 struct resource *irq_res; /* IRQ resource */
115 void *intrhand; /* Interrupt handle */
117 int num_slots; /* Number of slots on this controller */
118 struct sdhci_slot slots[6];
119 struct resource *mem_res[6]; /* Memory resource */
122 static int sdhci_enable_msi = 1;
123 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
124 0, "Enable MSI interrupts");
127 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
129 struct sdhci_pci_softc *sc = device_get_softc(dev);
131 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
132 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
133 return bus_read_1(sc->mem_res[slot->num], off);
137 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
139 struct sdhci_pci_softc *sc = device_get_softc(dev);
141 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
142 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
143 bus_write_1(sc->mem_res[slot->num], off, val);
147 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
149 struct sdhci_pci_softc *sc = device_get_softc(dev);
151 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
152 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
153 return bus_read_2(sc->mem_res[slot->num], off);
157 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
159 struct sdhci_pci_softc *sc = device_get_softc(dev);
161 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
162 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
163 bus_write_2(sc->mem_res[slot->num], off, val);
167 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
169 struct sdhci_pci_softc *sc = device_get_softc(dev);
171 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
172 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
173 return bus_read_4(sc->mem_res[slot->num], off);
177 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
179 struct sdhci_pci_softc *sc = device_get_softc(dev);
181 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
182 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
183 bus_write_4(sc->mem_res[slot->num], off, val);
187 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot,
188 bus_size_t off, uint32_t *data, bus_size_t count)
190 struct sdhci_pci_softc *sc = device_get_softc(dev);
192 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
196 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot,
197 bus_size_t off, uint32_t *data, bus_size_t count)
199 struct sdhci_pci_softc *sc = device_get_softc(dev);
201 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
204 static void sdhci_pci_intr(void *arg);
207 sdhci_lower_frequency(device_t dev)
210 /* Enable SD2.0 mode. */
211 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
212 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
213 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
216 * Some SD/MMC cards don't work with the default base
217 * clock frequency of 200MHz. Lower it to 50Hz.
219 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
220 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
221 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
225 sdhci_pci_probe(device_t dev)
229 uint8_t class, subclass;
232 model = (uint32_t)pci_get_device(dev) << 16;
233 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
234 subvendor = pci_get_subvendor(dev);
235 class = pci_get_class(dev);
236 subclass = pci_get_subclass(dev);
239 for (i = 0; sdhci_devices[i].model != 0; i++) {
240 if (sdhci_devices[i].model == model &&
241 (sdhci_devices[i].subvendor == 0xffff ||
242 sdhci_devices[i].subvendor == subvendor)) {
243 device_set_desc(dev, sdhci_devices[i].desc);
244 result = BUS_PROBE_DEFAULT;
248 if (result == ENXIO && class == PCIC_BASEPERIPH &&
249 subclass == PCIS_BASEPERIPH_SDHC) {
250 device_set_desc(dev, "Generic SD HCI");
251 result = BUS_PROBE_GENERIC;
258 sdhci_pci_attach(device_t dev)
260 struct sdhci_pci_softc *sc = device_get_softc(dev);
263 int bar, err, rid, slots, i;
266 model = (uint32_t)pci_get_device(dev) << 16;
267 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
268 subvendor = pci_get_subvendor(dev);
269 /* Apply chip specific quirks. */
270 for (i = 0; sdhci_devices[i].model != 0; i++) {
271 if (sdhci_devices[i].model == model &&
272 (sdhci_devices[i].subvendor == 0xffff ||
273 sdhci_devices[i].subvendor == subvendor)) {
274 sc->quirks = sdhci_devices[i].quirks;
278 /* Some controllers need to be bumped into the right mode. */
279 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
280 sdhci_lower_frequency(dev);
281 /* Read slots info from PCI registers. */
282 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
283 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
284 slots = PCI_SLOT_INFO_SLOTS(slots);
285 if (slots > 6 || bar > 5) {
286 device_printf(dev, "Incorrect slots information (%d, %d).\n",
293 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
295 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
296 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
297 if (sc->irq_res == NULL) {
298 device_printf(dev, "Can't allocate IRQ\n");
299 pci_release_msi(dev);
302 /* Scan all slots. */
303 for (i = 0; i < slots; i++) {
304 struct sdhci_slot *slot = &sc->slots[sc->num_slots];
306 /* Allocate memory. */
307 rid = PCIR_BAR(bar + i);
308 sc->mem_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY,
309 &rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
310 if (sc->mem_res[i] == NULL) {
311 device_printf(dev, "Can't allocate memory for slot %d\n", i);
315 if (sdhci_init_slot(dev, slot, i) != 0)
320 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
321 /* Activate the interrupt */
322 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
323 NULL, sdhci_pci_intr, sc, &sc->intrhand);
325 device_printf(dev, "Can't setup IRQ\n");
326 pci_enable_busmaster(dev);
327 /* Process cards detection. */
328 for (i = 0; i < sc->num_slots; i++) {
329 struct sdhci_slot *slot = &sc->slots[i];
331 sdhci_start_slot(slot);
338 sdhci_pci_detach(device_t dev)
340 struct sdhci_pci_softc *sc = device_get_softc(dev);
343 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
344 bus_release_resource(dev, SYS_RES_IRQ,
345 rman_get_rid(sc->irq_res), sc->irq_res);
346 pci_release_msi(dev);
348 for (i = 0; i < sc->num_slots; i++) {
349 struct sdhci_slot *slot = &sc->slots[i];
351 sdhci_cleanup_slot(slot);
352 bus_release_resource(dev, SYS_RES_MEMORY,
353 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
359 sdhci_pci_suspend(device_t dev)
361 struct sdhci_pci_softc *sc = device_get_softc(dev);
364 err = bus_generic_suspend(dev);
367 for (i = 0; i < sc->num_slots; i++)
368 sdhci_generic_suspend(&sc->slots[i]);
373 sdhci_pci_resume(device_t dev)
375 struct sdhci_pci_softc *sc = device_get_softc(dev);
378 for (i = 0; i < sc->num_slots; i++)
379 sdhci_generic_resume(&sc->slots[i]);
380 return (bus_generic_resume(dev));
384 sdhci_pci_intr(void *arg)
386 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
389 for (i = 0; i < sc->num_slots; i++) {
390 struct sdhci_slot *slot = &sc->slots[i];
391 sdhci_generic_intr(slot);
395 static device_method_t sdhci_methods[] = {
397 DEVMETHOD(device_probe, sdhci_pci_probe),
398 DEVMETHOD(device_attach, sdhci_pci_attach),
399 DEVMETHOD(device_detach, sdhci_pci_detach),
400 DEVMETHOD(device_suspend, sdhci_pci_suspend),
401 DEVMETHOD(device_resume, sdhci_pci_resume),
404 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
405 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
408 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
409 DEVMETHOD(mmcbr_request, sdhci_generic_request),
410 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
411 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
412 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
414 /* SDHCI registers accessors */
415 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
416 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
417 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
418 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
419 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
420 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
421 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
422 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
427 static driver_t sdhci_pci_driver = {
430 sizeof(struct sdhci_pci_softc),
432 static devclass_t sdhci_pci_devclass;
434 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
436 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);