sys/dev/sdhci/sdhci_xenon.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * Marvell Xenon SDHCI controller driver.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/bus.h>
  38 #include <sys/kernel.h>
  39 #include <sys/lock.h>
  40 #include <sys/module.h>
  41 #include <sys/mutex.h>
  42 #include <sys/resource.h>
  43 #include <sys/rman.h>
  44 #include <sys/sysctl.h>
  45 #include <sys/taskqueue.h>
  46
  47 #include <machine/bus.h>
  48 #include <machine/resource.h>
  49
  50 #include <dev/extres/regulator/regulator.h>
  51
  52 #include <dev/mmc/bridge.h>
  53 #include <dev/mmc/mmcbrvar.h>
  54 #include <dev/mmc/mmcreg.h>
  55
  56 #include <dev/sdhci/sdhci.h>
  57 #include <dev/sdhci/sdhci_xenon.h>
  58
  59 #include "mmcbr_if.h"
  60 #include "sdhci_if.h"
  61
  62 #include "opt_mmccam.h"
  63 #include "opt_soc.h"
  64
  65 #define MAX_SLOTS               6
  66
  67 static uint8_t
  68 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused,
  69     bus_size_t off)
  70 {
  71         struct sdhci_xenon_softc *sc = device_get_softc(dev);
  72
  73         return (bus_read_1(sc->mem_res, off));
  74 }
  75
  76 static void
  77 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused,
  78     bus_size_t off, uint8_t val)
  79 {
  80         struct sdhci_xenon_softc *sc = device_get_softc(dev);
  81
  82         bus_write_1(sc->mem_res, off, val);
  83 }
  84
  85 static uint16_t
  86 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused,
  87     bus_size_t off)
  88 {
  89         struct sdhci_xenon_softc *sc = device_get_softc(dev);
  90
  91         return (bus_read_2(sc->mem_res, off));
  92 }
  93
  94 static void
  95 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused,
  96     bus_size_t off, uint16_t val)
  97 {
  98         struct sdhci_xenon_softc *sc = device_get_softc(dev);
  99
 100         bus_write_2(sc->mem_res, off, val);
 101 }
 102
 103 static uint32_t
 104 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused,
 105     bus_size_t off)
 106 {
 107         struct sdhci_xenon_softc *sc = device_get_softc(dev);
 108
 109         return bus_read_4(sc->mem_res, off);
 110 }
 111
 112 static void
 113 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused,
 114     bus_size_t off, uint32_t val)
 115 {
 116         struct sdhci_xenon_softc *sc = device_get_softc(dev);
 117
 118         bus_write_4(sc->mem_res, off, val);
 119 }
 120
 121 static void
 122 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
 123     bus_size_t off, uint32_t *data, bus_size_t count)
 124 {
 125         struct sdhci_xenon_softc *sc = device_get_softc(dev);
 126
 127         bus_read_multi_4(sc->mem_res, off, data, count);
 128 }
 129
 130 static void
 131 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
 132     bus_size_t off, uint32_t *data, bus_size_t count)
 133 {
 134         struct sdhci_xenon_softc *sc = device_get_softc(dev);
 135
 136         bus_write_multi_4(sc->mem_res, off, data, count);
 137 }
 138
 139 static void
 140 sdhci_xenon_intr(void *arg)
 141 {
 142         struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg;
 143
 144         sdhci_generic_intr(sc->slot);
 145 }
 146
 147 static int
 148 sdhci_xenon_get_ro(device_t bus, device_t dev)
 149 {
 150         struct sdhci_xenon_softc *sc = device_get_softc(bus);
 151
 152         return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
 153 }
 154
 155 static void
 156 sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot)
 157 {
 158         const struct mmc_ios *ios;
 159         uint16_t hostctrl2;
 160
 161         if (slot->version < SDHCI_SPEC_300)
 162                 return;
 163
 164         mtx_assert(&slot->mtx, MA_OWNED);
 165         ios = &slot->host.ios;
 166
 167         /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */
 168         hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2);
 169         hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
 170         if (ios->clock > SD_SDR50_MAX) {
 171                 if (ios->timing == bus_timing_mmc_hs400 ||
 172                     ios->timing == bus_timing_mmc_hs400es)
 173                         hostctrl2 |= XENON_CTRL2_MMC_HS400;
 174                 else if (ios->timing == bus_timing_mmc_hs200)
 175                         hostctrl2 |= XENON_CTRL2_MMC_HS200;
 176                 else
 177                         hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
 178         }
 179         else if (ios->clock > SD_SDR25_MAX)
 180                 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
 181         else if (ios->clock > SD_SDR12_MAX) {
 182                 if (ios->timing == bus_timing_uhs_ddr50 ||
 183                     ios->timing == bus_timing_mmc_ddr52)
 184                         hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
 185                 else
 186                         hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
 187         } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
 188                 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
 189         sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2);
 190 }
 191
 192 static int
 193 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
 194 {
 195         int i;
 196         struct sdhci_xenon_softc *sc;
 197         uint32_t reg;
 198
 199         sc = device_get_softc(brdev);
 200         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
 201         reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT;
 202         switch (ios->timing) {
 203         case bus_timing_normal:
 204         case bus_timing_hs:
 205         case bus_timing_uhs_sdr12:
 206         case bus_timing_uhs_sdr25:
 207         case bus_timing_uhs_sdr50:
 208                 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
 209                 break;
 210         default:
 211                 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
 212         }
 213         if (sc->slow_mode)
 214                 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
 215         bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
 216
 217         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
 218         reg |= XENON_PHY_INITIALIZATION;
 219         bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
 220
 221         /* Wait for the eMMC PHY init. */
 222         for (i = 100; i > 0; i--) {
 223                 DELAY(100);
 224
 225                 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
 226                 if ((reg & XENON_PHY_INITIALIZATION) == 0)
 227                         break;
 228         }
 229
 230         if (i == 0) {
 231                 device_printf(brdev, "eMMC PHY failed to initialize\n");
 232                 return (ETIMEDOUT);
 233         }
 234
 235         return (0);
 236 }
 237
 238 static int
 239 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios)
 240 {
 241         struct sdhci_xenon_softc *sc;
 242         uint32_t reg;
 243
 244         sc = device_get_softc(brdev);
 245         /* Setup pad, set bit[28] and bits[26:24] */
 246         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);
 247         reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
 248                 XENON_FC_QSP_RECEN | XENON_OEN_QSN);
 249         /* All FC_XX_RECEIVCE should be set as CMOS Type */
 250         reg |= XENON_FC_ALL_CMOS_RECEIVER;
 251         bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);
 252
 253         /* Set CMD and DQ Pull Up */
 254         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
 255         reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU);
 256         reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD);
 257         bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
 258
 259         if (ios->timing == bus_timing_normal)
 260                 return (sdhci_xenon_phy_init(brdev, ios));
 261
 262         /* Clear SDIO mode, no SDIO support for now. */
 263         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
 264         reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
 265         bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
 266
 267         /*
 268          * Set preferred ZNR and ZPR value.
 269          * The ZNR and ZPR value vary between different boards.
 270          * Define them both in the DTS for the board!
 271          */
 272         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);
 273         reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
 274         reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr);
 275         bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);
 276
 277         /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */
 278         reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
 279         reg &= ~SDHCI_CLOCK_CARD_EN;
 280         bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
 281
 282         reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);
 283         switch (ios->timing) {
 284         case bus_timing_mmc_hs400:
 285                 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
 286                     XENON_CMD_DDR_MODE;
 287                 reg &= ~XENON_DQ_ASYNC_MODE;
 288                 break;
 289         case bus_timing_uhs_ddr50:
 290         case bus_timing_mmc_ddr52:
 291                 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
 292                     XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
 293                 break;
 294         default:
 295                 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
 296                     XENON_CMD_DDR_MODE);
 297                 reg |= XENON_DQ_ASYNC_MODE;
 298         }
 299         bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);
 300
 301         /* Enable SD clock. */
 302         reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
 303         reg |= SDHCI_CLOCK_CARD_EN;
 304         bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
 305
 306         if (ios->timing == bus_timing_mmc_hs400)
 307                 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
 308                     XENON_LOGIC_TIMING_VALUE);
 309         else {
 310                 /* Disable both SDHC Data Strobe and Enhanced Strobe. */
 311                 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);
 312                 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
 313                 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);
 314
 315                 /* Clear Strobe line Pull down or Pull up. */
 316                 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
 317                 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU);
 318                 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
 319         }
 320
 321         return (sdhci_xenon_phy_init(brdev, ios));
 322 }
 323
 324 static int
 325 sdhci_xenon_update_ios(device_t brdev, device_t reqdev)
 326 {
 327         int err;
 328         struct sdhci_xenon_softc *sc;
 329         struct mmc_ios *ios;
 330         struct sdhci_slot *slot;
 331         uint32_t reg;
 332
 333         err = sdhci_generic_update_ios(brdev, reqdev);
 334         if (err != 0)
 335                 return (err);
 336
 337         sc = device_get_softc(brdev);
 338         slot = device_get_ivars(reqdev);
 339         ios = &slot->host.ios;
 340
 341         switch (ios->power_mode) {
 342         case power_on:
 343                 break;
 344         case power_off:
 345                 if (bootverbose)
 346                         device_printf(sc->dev, "Powering down sd/mmc\n");
 347
 348                 if (sc->vmmc_supply)
 349                         regulator_disable(sc->vmmc_supply);
 350                 if (sc->vqmmc_supply)
 351                         regulator_disable(sc->vqmmc_supply);
 352                 break;
 353         case power_up:
 354                 if (bootverbose)
 355                         device_printf(sc->dev, "Powering up sd/mmc\n");
 356
 357                 if (sc->vmmc_supply)
 358                         regulator_enable(sc->vmmc_supply);
 359                 if (sc->vqmmc_supply)
 360                         regulator_enable(sc->vqmmc_supply);
 361                 break;
 362         };
 363
 364         /* Update the PHY settings. */
 365         if (ios->clock != 0)
 366                 sdhci_xenon_phy_set(brdev, ios);
 367
 368         if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) {
 369                 /* Enable SDCLK_IDLEOFF. */
 370                 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
 371                 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id);
 372                 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
 373         }
 374
 375         return (0);
 376 }
 377
 378 static int
 379 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev)
 380 {
 381         struct sdhci_xenon_softc *sc;
 382         struct sdhci_slot *slot;
 383         uint16_t hostctrl2;
 384         int uvolt, err;
 385
 386         slot = device_get_ivars(reqdev);
 387
 388         if (slot->version < SDHCI_SPEC_300)
 389                 return (0);
 390
 391         sc = device_get_softc(brdev);
 392
 393         if (sc->vqmmc_supply == NULL && !sc->skip_regulators)
 394                 return (EOPNOTSUPP);
 395
 396         err = 0;
 397
 398         hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
 399         switch (slot->host.ios.vccq) {
 400         case vccq_330:
 401                 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
 402                         return (0);
 403                 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
 404                 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);
 405
 406                 if (!sc->skip_regulators) {
 407                         uvolt = 3300000;
 408                         err = regulator_set_voltage(sc->vqmmc_supply,
 409                             uvolt, uvolt);
 410                         if (err != 0) {
 411                                 device_printf(sc->dev,
 412                                     "Cannot set vqmmc to %d<->%d\n",
 413                                     uvolt,
 414                                     uvolt);
 415                                 return (err);
 416                         }
 417                 }
 418
 419                 /*
 420                  * According to the 'SD Host Controller Simplified
 421                  * Specification 4.20 the host driver should take more
 422                  * than 5ms for stable time of host voltage regulator
 423                  * from changing 1.8V Signaling Enable.
 424                  */
 425                 DELAY(5000);
 426                 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
 427                 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
 428                         return (0);
 429                 return (EAGAIN);
 430         case vccq_180:
 431                 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
 432                         return (EINVAL);
 433                 }
 434                 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
 435                         return (0);
 436                 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
 437                 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);
 438
 439                 if (!sc->skip_regulators) {
 440                         uvolt = 1800000;
 441                         err = regulator_set_voltage(sc->vqmmc_supply,
 442                                 uvolt, uvolt);
 443                         if (err != 0) {
 444                                 device_printf(sc->dev,
 445                                         "Cannot set vqmmc to %d<->%d\n",
 446                                         uvolt,
 447                                         uvolt);
 448                                 return (err);
 449                         }
 450                 }
 451
 452                 /*
 453                  * According to the 'SD Host Controller Simplified
 454                  * Specification 4.20 the host driver should take more
 455                  * than 5ms for stable time of host voltage regulator
 456                  * from changing 1.8V Signaling Enable.
 457                  */
 458                 DELAY(5000);
 459                 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
 460                 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
 461                         return (0);
 462                 return (EAGAIN);
 463         default:
 464                 device_printf(brdev,
 465                     "Attempt to set unsupported signaling voltage\n");
 466                 return (EINVAL);
 467         }
 468 }
 469
 470 static void
 471 sdhci_xenon_parse_prop(device_t dev)
 472 {
 473         struct sdhci_xenon_softc *sc;
 474         uint64_t val;
 475
 476         sc = device_get_softc(dev);
 477         val = 0;
 478
 479         if (device_get_property(dev, "quirks", &val, sizeof(val)) > 0)
 480                 sc->slot->quirks = val;
 481         sc->znr = XENON_ZNR_DEF_VALUE;
 482         if (device_get_property(dev, "marvell,xenon-phy-znr",
 483             &val, sizeof(val)) > 0)
 484                 sc->znr = val & XENON_ZNR_MASK;
 485         sc->zpr = XENON_ZPR_DEF_VALUE;
 486         if (device_get_property(dev, "marvell,xenon-phy-zpr",
 487             &val, sizeof(val)) > 0)
 488                 sc->zpr = val & XENON_ZPR_MASK;
 489         if (device_has_property(dev, "marvell,xenon-phy-slow-mode"))
 490                 sc->slow_mode = true;
 491 }
 492
 493 int
 494 sdhci_xenon_attach(device_t dev)
 495 {
 496         struct sdhci_xenon_softc *sc = device_get_softc(dev);
 497         int err, rid;
 498         uint32_t reg;
 499
 500         sc->dev = dev;
 501         sc->slot_id = 0;
 502
 503         /* Allocate IRQ. */
 504         rid = 0;
 505         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 506             RF_ACTIVE);
 507         if (sc->irq_res == NULL) {
 508                 device_printf(dev, "Can't allocate IRQ\n");
 509                 return (ENOMEM);
 510         }
 511
 512         /* Allocate memory. */
 513         rid = 0;
 514         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 515             &rid, RF_ACTIVE);
 516         if (sc->mem_res == NULL) {
 517                 bus_release_resource(dev, SYS_RES_IRQ,
 518                     rman_get_rid(sc->irq_res), sc->irq_res);
 519                 device_printf(dev, "Can't allocate memory for slot\n");
 520                 return (ENOMEM);
 521         }
 522
 523         sdhci_xenon_parse_prop(dev);
 524
 525         sc->slot->max_clk = XENON_MMC_MAX_CLK;
 526         if (sc->slot->host.f_max > 0)
 527                 sc->slot->max_clk = sc->slot->host.f_max;
 528
 529         if (sdhci_init_slot(dev, sc->slot, 0))
 530                 goto fail;
 531
 532         /* 1.2V signaling is not supported. */
 533         sc->slot->host.caps &= ~MMC_CAP_SIGNALING_120;
 534
 535         /* Disable UHS in case of the PHY slow mode. */
 536         if (sc->slow_mode)
 537                 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_180;
 538
 539         /* Activate the interrupt */
 540         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
 541             NULL, sdhci_xenon_intr, sc, &sc->intrhand);
 542         if (err) {
 543                 device_printf(dev, "Cannot setup IRQ\n");
 544                 goto fail;
 545         }
 546
 547         /* Disable Auto Clock Gating. */
 548         reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
 549         reg |= XENON_AUTO_CLKGATE_DISABLE;
 550         bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
 551
 552         /* Enable this SD controller. */
 553         reg |= (1 << sc->slot_id);
 554         bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
 555
 556         /* Enable Parallel Transfer. */
 557         reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
 558         reg |= (1 << sc->slot_id);
 559         bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
 560
 561         /* Enable Auto Clock Gating. */
 562         reg &= ~XENON_AUTO_CLKGATE_DISABLE;
 563         bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
 564
 565         /* Disable SDCLK_IDLEOFF before the card initialization. */
 566         reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
 567         reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id));
 568         bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
 569
 570         /* Mask command conflict errors. */
 571         reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
 572         reg |= XENON_MASK_CMD_CONFLICT_ERR;
 573         bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
 574
 575         /* Process cards detection. */
 576         sdhci_start_slot(sc->slot);
 577
 578         return (0);
 579
 580 fail:
 581         bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
 582             sc->irq_res);
 583         bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
 584             sc->mem_res);
 585         free(sc->slot, M_DEVBUF);
 586         sc->slot = NULL;
 587
 588         return (ENXIO);
 589 }
 590
 591 int
 592 sdhci_xenon_detach(device_t dev)
 593 {
 594         struct sdhci_xenon_softc *sc = device_get_softc(dev);
 595
 596         bus_generic_detach(dev);
 597         bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
 598         bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
 599             sc->irq_res);
 600         sdhci_cleanup_slot(sc->slot);
 601         bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
 602             sc->mem_res);
 603         free(sc->slot, M_DEVBUF);
 604         sc->slot = NULL;
 605
 606         return (0);
 607 }
 608
 609 static device_method_t sdhci_xenon_methods[] = {
 610         /* Bus interface */
 611         DEVMETHOD(bus_read_ivar,        sdhci_generic_read_ivar),
 612         DEVMETHOD(bus_write_ivar,       sdhci_generic_write_ivar),
 613
 614         /* mmcbr_if */
 615         DEVMETHOD(mmcbr_update_ios,     sdhci_xenon_update_ios),
 616         DEVMETHOD(mmcbr_request,        sdhci_generic_request),
 617         DEVMETHOD(mmcbr_get_ro,         sdhci_xenon_get_ro),
 618         DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
 619         DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
 620         DEVMETHOD(mmcbr_switch_vccq,    sdhci_xenon_switch_vccq),
 621         DEVMETHOD(mmcbr_tune,           sdhci_generic_tune),
 622         DEVMETHOD(mmcbr_retune,         sdhci_generic_retune),
 623
 624         /* SDHCI registers accessors */
 625         DEVMETHOD(sdhci_read_1,         sdhci_xenon_read_1),
 626         DEVMETHOD(sdhci_read_2,         sdhci_xenon_read_2),
 627         DEVMETHOD(sdhci_read_4,         sdhci_xenon_read_4),
 628         DEVMETHOD(sdhci_read_multi_4,   sdhci_xenon_read_multi_4),
 629         DEVMETHOD(sdhci_write_1,        sdhci_xenon_write_1),
 630         DEVMETHOD(sdhci_write_2,        sdhci_xenon_write_2),
 631         DEVMETHOD(sdhci_write_4,        sdhci_xenon_write_4),
 632         DEVMETHOD(sdhci_write_multi_4,  sdhci_xenon_write_multi_4),
 633         DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing),
 634
 635         DEVMETHOD_END
 636 };
 637
 638 DEFINE_CLASS_0(sdhci_xenon, sdhci_xenon_driver, sdhci_xenon_methods,
 639     sizeof(struct sdhci_xenon_softc));
 640
 641 SDHCI_DEPEND(sdhci_xenon);
 642 #ifndef MMCCAM
 643 MMC_DECLARE_BRIDGE(sdhci_xenon);
 644 #endif