2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Marvell Xenon SDHCI controller driver.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
47 #include <machine/bus.h>
48 #include <machine/resource.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/mmc/bridge.h>
55 #include <dev/mmc/mmcbrvar.h>
56 #include <dev/mmc/mmcreg.h>
58 #include <dev/sdhci/sdhci.h>
59 #include <dev/sdhci/sdhci_xenon.h>
64 #include "opt_mmccam.h"
69 static struct ofw_compat_data compat_data[] = {
70 { "marvell,armada-3700-sdhci", 1 },
72 { "marvell,armada-cp110-sdhci", 1 },
73 { "marvell,armada-ap806-sdhci", 1 },
78 struct sdhci_xenon_softc {
79 device_t dev; /* Controller device */
80 int slot_id; /* Controller ID */
81 phandle_t node; /* FDT node */
82 uint32_t quirks; /* Chip specific quirks */
83 uint32_t caps; /* If we override SDHCI_CAPABILITIES */
84 uint32_t max_clk; /* Max possible freq */
85 struct resource *irq_res; /* IRQ resource */
86 void *intrhand; /* Interrupt handle */
88 struct sdhci_slot *slot; /* SDHCI internal data */
89 struct resource *mem_res; /* Memory resource */
91 uint8_t znr; /* PHY ZNR */
92 uint8_t zpr; /* PHY ZPR */
93 bool no_18v; /* No 1.8V support */
94 bool slow_mode; /* PHY slow mode */
95 bool wp_inverted; /* WP pin is inverted */
99 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused,
102 struct sdhci_xenon_softc *sc = device_get_softc(dev);
104 return (bus_read_1(sc->mem_res, off));
108 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused,
109 bus_size_t off, uint8_t val)
111 struct sdhci_xenon_softc *sc = device_get_softc(dev);
113 bus_write_1(sc->mem_res, off, val);
117 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused,
120 struct sdhci_xenon_softc *sc = device_get_softc(dev);
122 return (bus_read_2(sc->mem_res, off));
126 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused,
127 bus_size_t off, uint16_t val)
129 struct sdhci_xenon_softc *sc = device_get_softc(dev);
131 bus_write_2(sc->mem_res, off, val);
135 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused,
138 struct sdhci_xenon_softc *sc = device_get_softc(dev);
141 val32 = bus_read_4(sc->mem_res, off);
142 if (off == SDHCI_CAPABILITIES && sc->no_18v)
143 val32 &= ~SDHCI_CAN_VDD_180;
149 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused,
150 bus_size_t off, uint32_t val)
152 struct sdhci_xenon_softc *sc = device_get_softc(dev);
154 bus_write_4(sc->mem_res, off, val);
158 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
159 bus_size_t off, uint32_t *data, bus_size_t count)
161 struct sdhci_xenon_softc *sc = device_get_softc(dev);
163 bus_read_multi_4(sc->mem_res, off, data, count);
167 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
168 bus_size_t off, uint32_t *data, bus_size_t count)
170 struct sdhci_xenon_softc *sc = device_get_softc(dev);
172 bus_write_multi_4(sc->mem_res, off, data, count);
176 sdhci_xenon_intr(void *arg)
178 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg;
180 sdhci_generic_intr(sc->slot);
184 sdhci_xenon_get_ro(device_t bus, device_t dev)
186 struct sdhci_xenon_softc *sc = device_get_softc(bus);
188 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
192 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
195 struct sdhci_xenon_softc *sc;
198 sc = device_get_softc(brdev);
199 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
200 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT;
201 switch (ios->timing) {
202 case bus_timing_normal:
204 case bus_timing_uhs_sdr12:
205 case bus_timing_uhs_sdr25:
206 case bus_timing_uhs_sdr50:
207 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
210 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
213 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
214 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
216 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
217 reg |= XENON_PHY_INITIALIZATION;
218 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
220 /* Wait for the eMMC PHY init. */
221 for (i = 100; i > 0; i--) {
224 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
225 if ((reg & XENON_PHY_INITIALIZATION) == 0)
230 device_printf(brdev, "eMMC PHY failed to initialize\n");
238 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios)
240 struct sdhci_xenon_softc *sc;
243 sc = device_get_softc(brdev);
244 /* Setup pad, set bit[28] and bits[26:24] */
245 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);
246 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
247 XENON_FC_QSP_RECEN | XENON_OEN_QSN);
248 /* All FC_XX_RECEIVCE should be set as CMOS Type */
249 reg |= XENON_FC_ALL_CMOS_RECEIVER;
250 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);
252 /* Set CMD and DQ Pull Up */
253 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
254 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU);
255 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD);
256 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
258 if (ios->timing == bus_timing_normal)
259 return (sdhci_xenon_phy_init(brdev, ios));
261 /* Clear SDIO mode, no SDIO support for now. */
262 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);
263 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
264 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);
267 * Set preferred ZNR and ZPR value.
268 * The ZNR and ZPR value vary between different boards.
269 * Define them both in the DTS for the board!
271 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);
272 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
273 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr);
274 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);
276 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */
277 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
278 reg &= ~SDHCI_CLOCK_CARD_EN;
279 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
281 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);
282 switch (ios->timing) {
283 case bus_timing_mmc_hs400:
284 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
286 reg &= ~XENON_DQ_ASYNC_MODE;
288 case bus_timing_uhs_ddr50:
289 case bus_timing_mmc_ddr52:
290 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
291 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
294 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
296 reg |= XENON_DQ_ASYNC_MODE;
298 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);
300 /* Enable SD clock. */
301 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);
302 reg |= SDHCI_CLOCK_CARD_EN;
303 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);
305 if (ios->timing == bus_timing_mmc_hs400)
306 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
307 XENON_LOGIC_TIMING_VALUE);
309 /* Disable both SDHC Data Strobe and Enhanced Strobe. */
310 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);
311 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
312 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);
314 /* Clear Strobe line Pull down or Pull up. */
315 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);
316 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU);
317 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);
320 return (sdhci_xenon_phy_init(brdev, ios));
324 sdhci_xenon_update_ios(device_t brdev, device_t reqdev)
327 struct sdhci_xenon_softc *sc;
329 struct sdhci_slot *slot;
332 err = sdhci_generic_update_ios(brdev, reqdev);
336 sc = device_get_softc(brdev);
337 slot = device_get_ivars(reqdev);
338 ios = &slot->host.ios;
340 /* Update the PHY settings. */
342 sdhci_xenon_phy_set(brdev, ios);
344 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) {
345 /* Enable SDCLK_IDLEOFF. */
346 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
347 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id);
348 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
355 sdhci_xenon_probe(device_t dev)
357 struct sdhci_xenon_softc *sc = device_get_softc(dev);
362 sc->max_clk = XENON_MMC_MAX_CLK;
364 if (!ofw_bus_status_okay(dev))
367 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
370 sc->node = ofw_bus_get_node(dev);
371 device_set_desc(dev, "Armada Xenon SDHCI controller");
373 /* Allow dts to patch quirks, slots, and max-frequency. */
374 if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0)
376 if ((OF_getencprop(sc->node, "max-frequency", &cid, sizeof(cid))) > 0)
378 if (OF_hasprop(sc->node, "no-1-8-v"))
380 if (OF_hasprop(sc->node, "wp-inverted"))
381 sc->wp_inverted = true;
382 if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode"))
383 sc->slow_mode = true;
384 sc->znr = XENON_ZNR_DEF_VALUE;
385 if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid,
387 sc->znr = cid & XENON_ZNR_MASK;
388 sc->zpr = XENON_ZPR_DEF_VALUE;
389 if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid,
391 sc->zpr = cid & XENON_ZPR_MASK;
397 sdhci_xenon_attach(device_t dev)
399 struct sdhci_xenon_softc *sc = device_get_softc(dev);
400 struct sdhci_slot *slot;
408 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
410 if (sc->irq_res == NULL) {
411 device_printf(dev, "Can't allocate IRQ\n");
415 /* Allocate memory. */
417 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
419 if (sc->mem_res == NULL) {
420 bus_release_resource(dev, SYS_RES_IRQ,
421 rman_get_rid(sc->irq_res), sc->irq_res);
422 device_printf(dev, "Can't allocate memory for slot\n");
426 slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK);
428 /* Check if the device is flagged as non-removable. */
429 if (OF_hasprop(sc->node, "non-removable")) {
430 slot->opt |= SDHCI_NON_REMOVABLE;
432 device_printf(dev, "Non-removable media\n");
435 slot->quirks = sc->quirks;
436 slot->caps = sc->caps;
437 slot->max_clk = sc->max_clk;
440 if (sdhci_init_slot(dev, sc->slot, 0))
443 /* Activate the interrupt */
444 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
445 NULL, sdhci_xenon_intr, sc, &sc->intrhand);
447 device_printf(dev, "Cannot setup IRQ\n");
451 /* Disable Auto Clock Gating. */
452 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
453 reg |= XENON_AUTO_CLKGATE_DISABLE;
454 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
456 /* Enable this SD controller. */
457 reg |= (1 << sc->slot_id);
458 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
460 /* Enable Parallel Transfer. */
461 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
462 reg |= (1 << sc->slot_id);
463 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
465 /* Enable Auto Clock Gating. */
466 reg &= ~XENON_AUTO_CLKGATE_DISABLE;
467 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
469 /* Disable SDCLK_IDLEOFF before the card initialization. */
470 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);
471 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id));
472 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);
474 /* Mask command conflict errors. */
475 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);
476 reg |= XENON_MASK_CMD_CONFLICT_ERR;
477 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);
479 /* Process cards detection. */
480 sdhci_start_slot(sc->slot);
485 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
487 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
489 free(sc->slot, M_DEVBUF);
496 sdhci_xenon_detach(device_t dev)
498 struct sdhci_xenon_softc *sc = device_get_softc(dev);
500 bus_generic_detach(dev);
501 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
502 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
504 sdhci_cleanup_slot(sc->slot);
505 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res),
507 free(sc->slot, M_DEVBUF);
513 static device_method_t sdhci_xenon_methods[] = {
515 DEVMETHOD(device_probe, sdhci_xenon_probe),
516 DEVMETHOD(device_attach, sdhci_xenon_attach),
517 DEVMETHOD(device_detach, sdhci_xenon_detach),
520 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
521 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
524 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios),
525 DEVMETHOD(mmcbr_request, sdhci_generic_request),
526 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro),
527 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
528 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
530 /* SDHCI registers accessors */
531 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1),
532 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2),
533 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4),
534 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4),
535 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1),
536 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2),
537 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4),
538 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4),
543 static driver_t sdhci_xenon_driver = {
546 sizeof(struct sdhci_xenon_softc),
548 static devclass_t sdhci_xenon_devclass;
550 DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass,
553 SDHCI_DEPEND(sdhci_xenon);
555 MMC_DECLARE_BRIDGE(sdhci_xenon);