2 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
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14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Marvel Xenon SDHCI driver defines.
32 #ifndef _SDHCI_XENON_H_
33 #define _SDHCI_XENON_H_
35 #define XENON_LOWEST_SDCLK_FREQ 100000
36 #define XENON_MMC_MAX_CLK 400000000
38 #define XENON_SYS_OP_CTRL 0x0108
39 #define XENON_AUTO_CLKGATE_DISABLE (1 << 20)
40 #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
42 #define XENON_SYS_EXT_OP_CTRL 0x010C
43 #define XENON_MASK_CMD_CONFLICT_ERR (1 << 8)
45 #define XENON_SLOT_EMMC_CTRL 0x0130
46 #define XENON_ENABLE_DATA_STROBE (1 << 24)
47 #define XENON_ENABLE_RESP_STROBE (1 << 25)
50 #define XENON_EMMC_PHY_REG_BASE 0x170
52 #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE
53 #define XENON_SAMPL_INV_QSP_PHASE_SELECT (1 << 18)
54 #define XENON_TIMING_ADJUST_SDIO_MODE (1 << 28)
55 #define XENON_TIMING_ADJUST_SLOW_MODE (1 << 29)
56 #define XENON_PHY_INITIALIZATION (1U << 31)
57 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
58 #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12
59 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF
60 #define XENON_FC_SYNC_EN_DURATION_SHIFT 8
61 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
62 #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4
63 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF
64 #define XENON_FC_SYNC_RST_DURATION_SHIFT 0
66 #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)
67 #define XENON_DQ_ASYNC_MODE (1 << 4)
68 #define XENON_CMD_DDR_MODE (1 << 16)
69 #define XENON_DQ_DDR_MODE_SHIFT 8
70 #define XENON_DQ_DDR_MODE_MASK 0xFF
71 #define XENON_ASYNC_DDRMODE_MASK (1 << 23)
72 #define XENON_ASYNC_DDRMODE_SHIFT 23
74 #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)
75 #define XENON_FC_DQ_RECEN (1 << 24)
76 #define XENON_FC_CMD_RECEN (1 << 25)
77 #define XENON_FC_QSP_RECEN (1 << 26)
78 #define XENON_FC_QSN_RECEN (1 << 27)
79 #define XENON_OEN_QSN (1 << 28)
80 #define XENON_FC_ALL_CMOS_RECEIVER 0xF000
82 #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)
83 #define XENON_EMMC_FC_CMD_PD (1 << 8)
84 #define XENON_EMMC_FC_QSP_PD (1 << 9)
85 #define XENON_EMMC_FC_CMD_PU (1 << 24)
86 #define XENON_EMMC_FC_QSP_PU (1 << 25)
87 #define XENON_EMMC_FC_DQ_PD 0xFF
88 #define XENON_EMMC_FC_DQ_PU (0xFF << 16)
90 #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)
91 #define XENON_ZNR_MASK 0x1F
92 #define XENON_ZNR_SHIFT 8
93 #define XENON_ZPR_MASK 0x1F
94 #define XENON_ZNR_DEF_VALUE 0xF
95 #define XENON_ZPR_DEF_VALUE 0xF
97 #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
98 #define XENON_LOGIC_TIMING_VALUE 0x00AA8977
100 #endif /* _SDHCI_XENON_H_ */