2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type2 transmit frame
53 * descriptors to take full advantage of fragmented packets buffers
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the strict alignment architecture, where the
63 * packet payload should be longword aligned. There is no simple way
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
83 #ifdef HAVE_KERNEL_OPTION_HEADERS
84 #include "opt_device_polling.h"
87 #include <sys/param.h>
88 #include <sys/systm.h>
90 #include <sys/endian.h>
91 #include <sys/kernel.h>
92 #include <sys/malloc.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/sysctl.h>
102 #include <net/if_var.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
108 #include <net/if_vlan_var.h>
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
113 #include <dev/pci/pcireg.h>
114 #include <dev/pci/pcivar.h>
116 #include <machine/bus.h>
118 #include <dev/sf/if_sfreg.h>
119 #include <dev/sf/starfire_rx.h>
120 #include <dev/sf/starfire_tx.h>
122 /* "device miibus" required. See GENERIC if you get errors here. */
123 #include "miibus_if.h"
125 MODULE_DEPEND(sf, pci, 1, 1, 1);
126 MODULE_DEPEND(sf, ether, 1, 1, 1);
127 MODULE_DEPEND(sf, miibus, 1, 1, 1);
130 #define SF_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
131 /* Define this to activate partial TCP/UDP checksum offload. */
132 #undef SF_PARTIAL_CSUM_SUPPORT
134 static struct sf_type sf_devs[] = {
135 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
136 AD_SUBSYSID_62011_REV0, "Adaptec ANA-62011 (rev 0) 10/100BaseTX" },
137 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
138 AD_SUBSYSID_62011_REV1, "Adaptec ANA-62011 (rev 1) 10/100BaseTX" },
139 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
140 AD_SUBSYSID_62022, "Adaptec ANA-62022 10/100BaseTX" },
141 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
142 AD_SUBSYSID_62044_REV0, "Adaptec ANA-62044 (rev 0) 10/100BaseTX" },
143 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
144 AD_SUBSYSID_62044_REV1, "Adaptec ANA-62044 (rev 1) 10/100BaseTX" },
145 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
146 AD_SUBSYSID_62020, "Adaptec ANA-62020 10/100BaseFX" },
147 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX",
148 AD_SUBSYSID_69011, "Adaptec ANA-69011 10/100BaseTX" },
151 static int sf_probe(device_t);
152 static int sf_attach(device_t);
153 static int sf_detach(device_t);
154 static int sf_shutdown(device_t);
155 static int sf_suspend(device_t);
156 static int sf_resume(device_t);
157 static void sf_intr(void *);
158 static void sf_tick(void *);
159 static void sf_stats_update(struct sf_softc *);
160 #ifndef __NO_STRICT_ALIGNMENT
161 static __inline void sf_fixup_rx(struct mbuf *);
163 static int sf_rxeof(struct sf_softc *);
164 static void sf_txeof(struct sf_softc *);
165 static int sf_encap(struct sf_softc *, struct mbuf **);
166 static void sf_start(struct ifnet *);
167 static void sf_start_locked(struct ifnet *);
168 static int sf_ioctl(struct ifnet *, u_long, caddr_t);
169 static void sf_download_fw(struct sf_softc *);
170 static void sf_init(void *);
171 static void sf_init_locked(struct sf_softc *);
172 static void sf_stop(struct sf_softc *);
173 static void sf_watchdog(struct sf_softc *);
174 static int sf_ifmedia_upd(struct ifnet *);
175 static int sf_ifmedia_upd_locked(struct ifnet *);
176 static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *);
177 static void sf_reset(struct sf_softc *);
178 static int sf_dma_alloc(struct sf_softc *);
179 static void sf_dma_free(struct sf_softc *);
180 static int sf_init_rx_ring(struct sf_softc *);
181 static void sf_init_tx_ring(struct sf_softc *);
182 static int sf_newbuf(struct sf_softc *, int);
183 static void sf_rxfilter(struct sf_softc *);
184 static int sf_setperf(struct sf_softc *, int, uint8_t *);
185 static int sf_sethash(struct sf_softc *, caddr_t, int);
187 static int sf_setvlan(struct sf_softc *, int, uint32_t);
190 static uint8_t sf_read_eeprom(struct sf_softc *, int);
192 static int sf_miibus_readreg(device_t, int, int);
193 static int sf_miibus_writereg(device_t, int, int, int);
194 static void sf_miibus_statchg(device_t);
195 #ifdef DEVICE_POLLING
196 static int sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
199 static uint32_t csr_read_4(struct sf_softc *, int);
200 static void csr_write_4(struct sf_softc *, int, uint32_t);
201 static void sf_txthresh_adjust(struct sf_softc *);
202 static int sf_sysctl_stats(SYSCTL_HANDLER_ARGS);
203 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
204 static int sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS);
206 static device_method_t sf_methods[] = {
207 /* Device interface */
208 DEVMETHOD(device_probe, sf_probe),
209 DEVMETHOD(device_attach, sf_attach),
210 DEVMETHOD(device_detach, sf_detach),
211 DEVMETHOD(device_shutdown, sf_shutdown),
212 DEVMETHOD(device_suspend, sf_suspend),
213 DEVMETHOD(device_resume, sf_resume),
216 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
217 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
218 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
223 static driver_t sf_driver = {
226 sizeof(struct sf_softc),
229 static devclass_t sf_devclass;
231 DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0);
232 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
234 #define SF_SETBIT(sc, reg, x) \
235 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
237 #define SF_CLRBIT(sc, reg, x) \
238 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
241 csr_read_4(struct sf_softc *sc, int reg)
245 if (sc->sf_restype == SYS_RES_MEMORY)
246 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
248 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
249 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
256 sf_read_eeprom(struct sf_softc *sc, int reg)
260 val = (csr_read_4(sc, SF_EEADDR_BASE +
261 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
267 csr_write_4(struct sf_softc *sc, int reg, uint32_t val)
270 if (sc->sf_restype == SYS_RES_MEMORY)
271 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
273 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
274 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
279 * Copy the address 'mac' into the perfect RX filter entry at
280 * offset 'idx.' The perfect filter only has 16 entries so do
284 sf_setperf(struct sf_softc *sc, int idx, uint8_t *mac)
287 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
293 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
294 (idx * SF_RXFILT_PERFECT_SKIP) + 0, mac[5] | (mac[4] << 8));
295 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
296 (idx * SF_RXFILT_PERFECT_SKIP) + 4, mac[3] | (mac[2] << 8));
297 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
298 (idx * SF_RXFILT_PERFECT_SKIP) + 8, mac[1] | (mac[0] << 8));
304 * Set the bit in the 512-bit hash table that corresponds to the
305 * specified mac address 'mac.' If 'prio' is nonzero, update the
306 * priority hash table instead of the filter hash table.
309 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio)
316 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23;
319 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
320 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
322 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
323 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
331 * Set a VLAN tag in the receive filter.
334 sf_setvlan(struct sf_softc *sc, int idx, uint32_t vlan)
337 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
340 csr_write_4(sc, SF_RXFILT_HASH_BASE +
341 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
348 sf_miibus_readreg(device_t dev, int phy, int reg)
354 sc = device_get_softc(dev);
356 for (i = 0; i < SF_TIMEOUT; i++) {
357 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
358 if ((val & SF_MII_DATAVALID) != 0)
365 val &= SF_MII_DATAPORT;
373 sf_miibus_writereg(device_t dev, int phy, int reg, int val)
379 sc = device_get_softc(dev);
381 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
383 for (i = 0; i < SF_TIMEOUT; i++) {
384 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
385 if ((busy & SF_MII_BUSY) == 0)
393 sf_miibus_statchg(device_t dev)
396 struct mii_data *mii;
400 sc = device_get_softc(dev);
401 mii = device_get_softc(sc->sf_miibus);
403 if (mii == NULL || ifp == NULL ||
404 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
408 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
409 (IFM_ACTIVE | IFM_AVALID)) {
410 switch (IFM_SUBTYPE(mii->mii_media_active)) {
418 if (sc->sf_link == 0)
421 val = csr_read_4(sc, SF_MACCFG_1);
422 val &= ~SF_MACCFG1_FULLDUPLEX;
423 val &= ~(SF_MACCFG1_RX_FLOWENB | SF_MACCFG1_TX_FLOWENB);
424 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
425 val |= SF_MACCFG1_FULLDUPLEX;
426 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
428 /* Configure flow-control bits. */
429 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
430 IFM_ETH_RXPAUSE) != 0)
431 val |= SF_MACCFG1_RX_FLOWENB;
432 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
433 IFM_ETH_TXPAUSE) != 0)
434 val |= SF_MACCFG1_TX_FLOWENB;
437 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
439 /* Make sure to reset MAC to take changes effect. */
440 csr_write_4(sc, SF_MACCFG_1, val | SF_MACCFG1_SOFTRESET);
442 csr_write_4(sc, SF_MACCFG_1, val);
444 val = csr_read_4(sc, SF_TIMER_CTL);
445 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
446 val |= SF_TIMER_TIMES_TEN;
448 val &= ~SF_TIMER_TIMES_TEN;
449 csr_write_4(sc, SF_TIMER_CTL, val);
453 sf_rxfilter(struct sf_softc *sc)
457 struct ifmultiaddr *ifma;
458 uint8_t dummy[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
463 /* First zot all the existing filters. */
464 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
465 sf_setperf(sc, i, dummy);
466 for (i = SF_RXFILT_HASH_BASE; i < (SF_RXFILT_HASH_MAX + 1);
467 i += sizeof(uint32_t))
468 csr_write_4(sc, i, 0);
470 rxfilt = csr_read_4(sc, SF_RXFILT);
471 rxfilt &= ~(SF_RXFILT_PROMISC | SF_RXFILT_ALLMULTI | SF_RXFILT_BROAD);
472 if ((ifp->if_flags & IFF_BROADCAST) != 0)
473 rxfilt |= SF_RXFILT_BROAD;
474 if ((ifp->if_flags & IFF_ALLMULTI) != 0 ||
475 (ifp->if_flags & IFF_PROMISC) != 0) {
476 if ((ifp->if_flags & IFF_PROMISC) != 0)
477 rxfilt |= SF_RXFILT_PROMISC;
478 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
479 rxfilt |= SF_RXFILT_ALLMULTI;
483 /* Now program new ones. */
486 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
488 if (ifma->ifma_addr->sa_family != AF_LINK)
491 * Program the first 15 multicast groups
492 * into the perfect filter. For all others,
493 * use the hash table.
495 if (i < SF_RXFILT_PERFECT_CNT) {
497 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
503 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
505 if_maddr_runlock(ifp);
508 csr_write_4(sc, SF_RXFILT, rxfilt);
515 sf_ifmedia_upd(struct ifnet *ifp)
522 error = sf_ifmedia_upd_locked(ifp);
528 sf_ifmedia_upd_locked(struct ifnet *ifp)
531 struct mii_data *mii;
532 struct mii_softc *miisc;
535 mii = device_get_softc(sc->sf_miibus);
536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
538 return (mii_mediachg(mii));
542 * Report current media status.
545 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
548 struct mii_data *mii;
552 if ((ifp->if_flags & IFF_UP) == 0) {
557 mii = device_get_softc(sc->sf_miibus);
559 ifmr->ifm_active = mii->mii_media_active;
560 ifmr->ifm_status = mii->mii_media_status;
565 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
569 struct mii_data *mii;
573 ifr = (struct ifreq *)data;
579 if (ifp->if_flags & IFF_UP) {
580 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
581 if ((ifp->if_flags ^ sc->sf_if_flags) &
582 (IFF_PROMISC | IFF_ALLMULTI))
585 if (sc->sf_detach == 0)
589 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
592 sc->sf_if_flags = ifp->if_flags;
598 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
604 mii = device_get_softc(sc->sf_miibus);
605 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
608 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
609 #ifdef DEVICE_POLLING
610 if ((mask & IFCAP_POLLING) != 0) {
611 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
612 error = ether_poll_register(sf_poll, ifp);
616 /* Disable interrupts. */
617 csr_write_4(sc, SF_IMR, 0);
618 ifp->if_capenable |= IFCAP_POLLING;
621 error = ether_poll_deregister(ifp);
622 /* Enable interrupts. */
624 csr_write_4(sc, SF_IMR, SF_INTRS);
625 ifp->if_capenable &= ~IFCAP_POLLING;
629 #endif /* DEVICE_POLLING */
630 if ((mask & IFCAP_TXCSUM) != 0) {
631 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
633 ifp->if_capenable ^= IFCAP_TXCSUM;
634 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) {
635 ifp->if_hwassist |= SF_CSUM_FEATURES;
636 SF_SETBIT(sc, SF_GEN_ETH_CTL,
637 SF_ETHCTL_TXGFP_ENB);
639 ifp->if_hwassist &= ~SF_CSUM_FEATURES;
640 SF_CLRBIT(sc, SF_GEN_ETH_CTL,
641 SF_ETHCTL_TXGFP_ENB);
646 if ((mask & IFCAP_RXCSUM) != 0) {
647 if ((IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
649 ifp->if_capenable ^= IFCAP_RXCSUM;
650 if ((IFCAP_RXCSUM & ifp->if_capenable) != 0)
651 SF_SETBIT(sc, SF_GEN_ETH_CTL,
652 SF_ETHCTL_RXGFP_ENB);
654 SF_CLRBIT(sc, SF_GEN_ETH_CTL,
655 SF_ETHCTL_RXGFP_ENB);
661 error = ether_ioctl(ifp, command, data);
669 sf_reset(struct sf_softc *sc)
673 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
674 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
676 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
678 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
680 for (i = 0; i < SF_TIMEOUT; i++) {
682 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
687 device_printf(sc->sf_dev, "reset never completed!\n");
689 /* Wait a little while for the chip to get its brains in order. */
694 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
695 * IDs against our list and return a device name if we find a match.
696 * We also check the subsystem ID so that we can identify exactly which
697 * NIC has been found, if possible.
700 sf_probe(device_t dev)
708 vid = pci_get_vendor(dev);
709 did = pci_get_device(dev);
710 sdid = pci_get_subdevice(dev);
713 for (i = 0; i < sizeof(sf_devs) / sizeof(sf_devs[0]); i++, t++) {
714 if (vid == t->sf_vid && did == t->sf_did) {
715 if (sdid == t->sf_sdid) {
716 device_set_desc(dev, t->sf_sname);
717 return (BUS_PROBE_DEFAULT);
722 if (vid == AD_VENDORID && did == AD_DEVICEID_STARFIRE) {
723 /* unkown subdevice */
724 device_set_desc(dev, sf_devs[0].sf_name);
725 return (BUS_PROBE_DEFAULT);
732 * Attach the interface. Allocate softc structures, do ifmedia
733 * setup and ethernet/BPF attach.
736 sf_attach(device_t dev)
743 uint8_t eaddr[ETHER_ADDR_LEN];
745 sc = device_get_softc(dev);
748 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
750 callout_init_mtx(&sc->sf_co, &sc->sf_mtx, 0);
753 * Map control/status registers.
755 pci_enable_busmaster(dev);
758 * Prefer memory space register mapping over I/O space as the
759 * hardware requires lots of register access to get various
760 * producer/consumer index during Tx/Rx operation. However this
761 * requires large memory space(512K) to map the entire register
764 sc->sf_rid = PCIR_BAR(0);
765 sc->sf_restype = SYS_RES_MEMORY;
766 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype, &sc->sf_rid,
768 if (sc->sf_res == NULL) {
769 reg = pci_read_config(dev, PCIR_BAR(0), 4);
770 if ((reg & PCIM_BAR_MEM_64) == PCIM_BAR_MEM_64)
771 sc->sf_rid = PCIR_BAR(2);
773 sc->sf_rid = PCIR_BAR(1);
774 sc->sf_restype = SYS_RES_IOPORT;
775 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype,
776 &sc->sf_rid, RF_ACTIVE);
777 if (sc->sf_res == NULL) {
778 device_printf(dev, "couldn't allocate resources\n");
779 mtx_destroy(&sc->sf_mtx);
784 device_printf(dev, "using %s space register mapping\n",
785 sc->sf_restype == SYS_RES_MEMORY ? "memory" : "I/O");
787 reg = pci_read_config(dev, PCIR_CACHELNSZ, 1);
790 * If cache line size is 0, MWI is not used at all, so set
791 * reasonable default. AIC-6915 supports 0, 4, 8, 16, 32
795 device_printf(dev, "setting PCI cache line size to %u\n", reg);
796 pci_write_config(dev, PCIR_CACHELNSZ, reg, 1);
799 device_printf(dev, "PCI cache line size : %u\n", reg);
802 reg = pci_read_config(dev, PCIR_COMMAND, 2);
803 reg |= PCIM_CMD_MWRICEN;
804 pci_write_config(dev, PCIR_COMMAND, reg, 2);
806 /* Allocate interrupt. */
808 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
809 RF_SHAREABLE | RF_ACTIVE);
811 if (sc->sf_irq == NULL) {
812 device_printf(dev, "couldn't map interrupt\n");
817 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
818 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
819 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
820 sf_sysctl_stats, "I", "Statistics");
822 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
823 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
824 OID_AUTO, "int_mod", CTLTYPE_INT | CTLFLAG_RW,
825 &sc->sf_int_mod, 0, sysctl_hw_sf_int_mod, "I",
826 "sf interrupt moderation");
827 /* Pull in device tunables. */
828 sc->sf_int_mod = SF_IM_DEFAULT;
829 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
830 "int_mod", &sc->sf_int_mod);
832 if (sc->sf_int_mod < SF_IM_MIN ||
833 sc->sf_int_mod > SF_IM_MAX) {
834 device_printf(dev, "int_mod value out of range; "
835 "using default: %d\n", SF_IM_DEFAULT);
836 sc->sf_int_mod = SF_IM_DEFAULT;
840 /* Reset the adapter. */
844 * Get station address from the EEPROM.
846 for (i = 0; i < ETHER_ADDR_LEN; i++)
848 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
850 /* Allocate DMA resources. */
851 if (sf_dma_alloc(sc) != 0) {
856 sc->sf_txthresh = SF_MIN_TX_THRESHOLD;
858 ifp = sc->sf_ifp = if_alloc(IFT_ETHER);
860 device_printf(dev, "can not allocate ifnet structure\n");
866 error = mii_attach(dev, &sc->sf_miibus, ifp, sf_ifmedia_upd,
867 sf_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
869 device_printf(dev, "attaching PHYs failed\n");
874 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
876 ifp->if_ioctl = sf_ioctl;
877 ifp->if_start = sf_start;
878 ifp->if_init = sf_init;
879 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
880 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1;
881 IFQ_SET_READY(&ifp->if_snd);
883 * With the help of firmware, AIC-6915 supports
884 * Tx/Rx TCP/UDP checksum offload.
886 ifp->if_hwassist = SF_CSUM_FEATURES;
887 ifp->if_capabilities = IFCAP_HWCSUM;
890 * Call MI attach routine.
892 ether_ifattach(ifp, eaddr);
894 /* VLAN capability setup. */
895 ifp->if_capabilities |= IFCAP_VLAN_MTU;
896 ifp->if_capenable = ifp->if_capabilities;
897 #ifdef DEVICE_POLLING
898 ifp->if_capabilities |= IFCAP_POLLING;
901 * Tell the upper layer(s) we support long frames.
902 * Must appear after the call to ether_ifattach() because
903 * ether_ifattach() sets ifi_hdrlen to the default value.
905 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
907 /* Hook interrupt last to avoid having to lock softc */
908 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE,
909 NULL, sf_intr, sc, &sc->sf_intrhand);
912 device_printf(dev, "couldn't set up irq\n");
925 * Shutdown hardware and free up resources. This can be called any
926 * time after the mutex has been initialized. It is called in both
927 * the error case in attach and the normal detach case so it needs
928 * to be careful about only freeing resources that have actually been
932 sf_detach(device_t dev)
937 sc = device_get_softc(dev);
940 #ifdef DEVICE_POLLING
941 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
942 ether_poll_deregister(ifp);
945 /* These should only be active if attach succeeded */
946 if (device_is_attached(dev)) {
951 callout_drain(&sc->sf_co);
956 device_delete_child(dev, sc->sf_miibus);
957 sc->sf_miibus = NULL;
959 bus_generic_detach(dev);
961 if (sc->sf_intrhand != NULL)
962 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
963 if (sc->sf_irq != NULL)
964 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
965 if (sc->sf_res != NULL)
966 bus_release_resource(dev, sc->sf_restype, sc->sf_rid,
973 mtx_destroy(&sc->sf_mtx);
978 struct sf_dmamap_arg {
979 bus_addr_t sf_busaddr;
983 sf_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
985 struct sf_dmamap_arg *ctx;
990 ctx->sf_busaddr = segs[0].ds_addr;
994 sf_dma_alloc(struct sf_softc *sc)
996 struct sf_dmamap_arg ctx;
997 struct sf_txdesc *txd;
998 struct sf_rxdesc *rxd;
1000 bus_addr_t rx_ring_end, rx_cring_end;
1001 bus_addr_t tx_ring_end, tx_cring_end;
1004 lowaddr = BUS_SPACE_MAXADDR;
1007 /* Create parent DMA tag. */
1008 error = bus_dma_tag_create(
1009 bus_get_dma_tag(sc->sf_dev), /* parent */
1010 1, 0, /* alignment, boundary */
1011 lowaddr, /* lowaddr */
1012 BUS_SPACE_MAXADDR, /* highaddr */
1013 NULL, NULL, /* filter, filterarg */
1014 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1016 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1018 NULL, NULL, /* lockfunc, lockarg */
1019 &sc->sf_cdata.sf_parent_tag);
1021 device_printf(sc->sf_dev, "failed to create parent DMA tag\n");
1024 /* Create tag for Tx ring. */
1025 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1026 SF_RING_ALIGN, 0, /* alignment, boundary */
1027 BUS_SPACE_MAXADDR, /* lowaddr */
1028 BUS_SPACE_MAXADDR, /* highaddr */
1029 NULL, NULL, /* filter, filterarg */
1030 SF_TX_DLIST_SIZE, /* maxsize */
1032 SF_TX_DLIST_SIZE, /* maxsegsize */
1034 NULL, NULL, /* lockfunc, lockarg */
1035 &sc->sf_cdata.sf_tx_ring_tag);
1037 device_printf(sc->sf_dev, "failed to create Tx ring DMA tag\n");
1041 /* Create tag for Tx completion ring. */
1042 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1043 SF_RING_ALIGN, 0, /* alignment, boundary */
1044 BUS_SPACE_MAXADDR, /* lowaddr */
1045 BUS_SPACE_MAXADDR, /* highaddr */
1046 NULL, NULL, /* filter, filterarg */
1047 SF_TX_CLIST_SIZE, /* maxsize */
1049 SF_TX_CLIST_SIZE, /* maxsegsize */
1051 NULL, NULL, /* lockfunc, lockarg */
1052 &sc->sf_cdata.sf_tx_cring_tag);
1054 device_printf(sc->sf_dev,
1055 "failed to create Tx completion ring DMA tag\n");
1059 /* Create tag for Rx ring. */
1060 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1061 SF_RING_ALIGN, 0, /* alignment, boundary */
1062 BUS_SPACE_MAXADDR, /* lowaddr */
1063 BUS_SPACE_MAXADDR, /* highaddr */
1064 NULL, NULL, /* filter, filterarg */
1065 SF_RX_DLIST_SIZE, /* maxsize */
1067 SF_RX_DLIST_SIZE, /* maxsegsize */
1069 NULL, NULL, /* lockfunc, lockarg */
1070 &sc->sf_cdata.sf_rx_ring_tag);
1072 device_printf(sc->sf_dev,
1073 "failed to create Rx ring DMA tag\n");
1077 /* Create tag for Rx completion ring. */
1078 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1079 SF_RING_ALIGN, 0, /* alignment, boundary */
1080 BUS_SPACE_MAXADDR, /* lowaddr */
1081 BUS_SPACE_MAXADDR, /* highaddr */
1082 NULL, NULL, /* filter, filterarg */
1083 SF_RX_CLIST_SIZE, /* maxsize */
1085 SF_RX_CLIST_SIZE, /* maxsegsize */
1087 NULL, NULL, /* lockfunc, lockarg */
1088 &sc->sf_cdata.sf_rx_cring_tag);
1090 device_printf(sc->sf_dev,
1091 "failed to create Rx completion ring DMA tag\n");
1095 /* Create tag for Tx buffers. */
1096 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1097 1, 0, /* alignment, boundary */
1098 BUS_SPACE_MAXADDR, /* lowaddr */
1099 BUS_SPACE_MAXADDR, /* highaddr */
1100 NULL, NULL, /* filter, filterarg */
1101 MCLBYTES * SF_MAXTXSEGS, /* maxsize */
1102 SF_MAXTXSEGS, /* nsegments */
1103 MCLBYTES, /* maxsegsize */
1105 NULL, NULL, /* lockfunc, lockarg */
1106 &sc->sf_cdata.sf_tx_tag);
1108 device_printf(sc->sf_dev, "failed to create Tx DMA tag\n");
1112 /* Create tag for Rx buffers. */
1113 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */
1114 SF_RX_ALIGN, 0, /* alignment, boundary */
1115 BUS_SPACE_MAXADDR, /* lowaddr */
1116 BUS_SPACE_MAXADDR, /* highaddr */
1117 NULL, NULL, /* filter, filterarg */
1118 MCLBYTES, /* maxsize */
1120 MCLBYTES, /* maxsegsize */
1122 NULL, NULL, /* lockfunc, lockarg */
1123 &sc->sf_cdata.sf_rx_tag);
1125 device_printf(sc->sf_dev, "failed to create Rx DMA tag\n");
1129 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1130 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_ring_tag,
1131 (void **)&sc->sf_rdata.sf_tx_ring, BUS_DMA_WAITOK |
1132 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_ring_map);
1134 device_printf(sc->sf_dev,
1135 "failed to allocate DMA'able memory for Tx ring\n");
1140 error = bus_dmamap_load(sc->sf_cdata.sf_tx_ring_tag,
1141 sc->sf_cdata.sf_tx_ring_map, sc->sf_rdata.sf_tx_ring,
1142 SF_TX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1143 if (error != 0 || ctx.sf_busaddr == 0) {
1144 device_printf(sc->sf_dev,
1145 "failed to load DMA'able memory for Tx ring\n");
1148 sc->sf_rdata.sf_tx_ring_paddr = ctx.sf_busaddr;
1151 * Allocate DMA'able memory and load the DMA map for Tx completion ring.
1153 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_cring_tag,
1154 (void **)&sc->sf_rdata.sf_tx_cring, BUS_DMA_WAITOK |
1155 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_cring_map);
1157 device_printf(sc->sf_dev,
1158 "failed to allocate DMA'able memory for "
1159 "Tx completion ring\n");
1164 error = bus_dmamap_load(sc->sf_cdata.sf_tx_cring_tag,
1165 sc->sf_cdata.sf_tx_cring_map, sc->sf_rdata.sf_tx_cring,
1166 SF_TX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1167 if (error != 0 || ctx.sf_busaddr == 0) {
1168 device_printf(sc->sf_dev,
1169 "failed to load DMA'able memory for Tx completion ring\n");
1172 sc->sf_rdata.sf_tx_cring_paddr = ctx.sf_busaddr;
1174 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1175 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_ring_tag,
1176 (void **)&sc->sf_rdata.sf_rx_ring, BUS_DMA_WAITOK |
1177 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_ring_map);
1179 device_printf(sc->sf_dev,
1180 "failed to allocate DMA'able memory for Rx ring\n");
1185 error = bus_dmamap_load(sc->sf_cdata.sf_rx_ring_tag,
1186 sc->sf_cdata.sf_rx_ring_map, sc->sf_rdata.sf_rx_ring,
1187 SF_RX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1188 if (error != 0 || ctx.sf_busaddr == 0) {
1189 device_printf(sc->sf_dev,
1190 "failed to load DMA'able memory for Rx ring\n");
1193 sc->sf_rdata.sf_rx_ring_paddr = ctx.sf_busaddr;
1196 * Allocate DMA'able memory and load the DMA map for Rx completion ring.
1198 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_cring_tag,
1199 (void **)&sc->sf_rdata.sf_rx_cring, BUS_DMA_WAITOK |
1200 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_cring_map);
1202 device_printf(sc->sf_dev,
1203 "failed to allocate DMA'able memory for "
1204 "Rx completion ring\n");
1209 error = bus_dmamap_load(sc->sf_cdata.sf_rx_cring_tag,
1210 sc->sf_cdata.sf_rx_cring_map, sc->sf_rdata.sf_rx_cring,
1211 SF_RX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0);
1212 if (error != 0 || ctx.sf_busaddr == 0) {
1213 device_printf(sc->sf_dev,
1214 "failed to load DMA'able memory for Rx completion ring\n");
1217 sc->sf_rdata.sf_rx_cring_paddr = ctx.sf_busaddr;
1220 * Tx desciptor ring and Tx completion ring should be addressed in
1221 * the same 4GB space. The same rule applys to Rx ring and Rx
1222 * completion ring. Unfortunately there is no way to specify this
1223 * boundary restriction with bus_dma(9). So just try to allocate
1224 * without the restriction and check the restriction was satisfied.
1225 * If not, fall back to 32bit dma addressing mode which always
1226 * guarantees the restriction.
1228 tx_ring_end = sc->sf_rdata.sf_tx_ring_paddr + SF_TX_DLIST_SIZE;
1229 tx_cring_end = sc->sf_rdata.sf_tx_cring_paddr + SF_TX_CLIST_SIZE;
1230 rx_ring_end = sc->sf_rdata.sf_rx_ring_paddr + SF_RX_DLIST_SIZE;
1231 rx_cring_end = sc->sf_rdata.sf_rx_cring_paddr + SF_RX_CLIST_SIZE;
1232 if ((SF_ADDR_HI(sc->sf_rdata.sf_tx_ring_paddr) !=
1233 SF_ADDR_HI(tx_cring_end)) ||
1234 (SF_ADDR_HI(sc->sf_rdata.sf_tx_cring_paddr) !=
1235 SF_ADDR_HI(tx_ring_end)) ||
1236 (SF_ADDR_HI(sc->sf_rdata.sf_rx_ring_paddr) !=
1237 SF_ADDR_HI(rx_cring_end)) ||
1238 (SF_ADDR_HI(sc->sf_rdata.sf_rx_cring_paddr) !=
1239 SF_ADDR_HI(rx_ring_end))) {
1240 device_printf(sc->sf_dev,
1241 "switching to 32bit DMA mode\n");
1243 /* Limit DMA address space to 32bit and try again. */
1244 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1248 /* Create DMA maps for Tx buffers. */
1249 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1250 txd = &sc->sf_cdata.sf_txdesc[i];
1253 txd->tx_dmamap = NULL;
1254 error = bus_dmamap_create(sc->sf_cdata.sf_tx_tag, 0,
1257 device_printf(sc->sf_dev,
1258 "failed to create Tx dmamap\n");
1262 /* Create DMA maps for Rx buffers. */
1263 if ((error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0,
1264 &sc->sf_cdata.sf_rx_sparemap)) != 0) {
1265 device_printf(sc->sf_dev,
1266 "failed to create spare Rx dmamap\n");
1269 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1270 rxd = &sc->sf_cdata.sf_rxdesc[i];
1272 rxd->rx_dmamap = NULL;
1273 error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0,
1276 device_printf(sc->sf_dev,
1277 "failed to create Rx dmamap\n");
1287 sf_dma_free(struct sf_softc *sc)
1289 struct sf_txdesc *txd;
1290 struct sf_rxdesc *rxd;
1294 if (sc->sf_cdata.sf_tx_ring_tag) {
1295 if (sc->sf_rdata.sf_tx_ring_paddr)
1296 bus_dmamap_unload(sc->sf_cdata.sf_tx_ring_tag,
1297 sc->sf_cdata.sf_tx_ring_map);
1298 if (sc->sf_rdata.sf_tx_ring)
1299 bus_dmamem_free(sc->sf_cdata.sf_tx_ring_tag,
1300 sc->sf_rdata.sf_tx_ring,
1301 sc->sf_cdata.sf_tx_ring_map);
1302 sc->sf_rdata.sf_tx_ring = NULL;
1303 sc->sf_rdata.sf_tx_ring_paddr = 0;
1304 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_ring_tag);
1305 sc->sf_cdata.sf_tx_ring_tag = NULL;
1307 /* Tx completion ring. */
1308 if (sc->sf_cdata.sf_tx_cring_tag) {
1309 if (sc->sf_rdata.sf_tx_cring_paddr)
1310 bus_dmamap_unload(sc->sf_cdata.sf_tx_cring_tag,
1311 sc->sf_cdata.sf_tx_cring_map);
1312 if (sc->sf_rdata.sf_tx_cring)
1313 bus_dmamem_free(sc->sf_cdata.sf_tx_cring_tag,
1314 sc->sf_rdata.sf_tx_cring,
1315 sc->sf_cdata.sf_tx_cring_map);
1316 sc->sf_rdata.sf_tx_cring = NULL;
1317 sc->sf_rdata.sf_tx_cring_paddr = 0;
1318 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_cring_tag);
1319 sc->sf_cdata.sf_tx_cring_tag = NULL;
1322 if (sc->sf_cdata.sf_rx_ring_tag) {
1323 if (sc->sf_rdata.sf_rx_ring_paddr)
1324 bus_dmamap_unload(sc->sf_cdata.sf_rx_ring_tag,
1325 sc->sf_cdata.sf_rx_ring_map);
1326 if (sc->sf_rdata.sf_rx_ring)
1327 bus_dmamem_free(sc->sf_cdata.sf_rx_ring_tag,
1328 sc->sf_rdata.sf_rx_ring,
1329 sc->sf_cdata.sf_rx_ring_map);
1330 sc->sf_rdata.sf_rx_ring = NULL;
1331 sc->sf_rdata.sf_rx_ring_paddr = 0;
1332 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_ring_tag);
1333 sc->sf_cdata.sf_rx_ring_tag = NULL;
1335 /* Rx completion ring. */
1336 if (sc->sf_cdata.sf_rx_cring_tag) {
1337 if (sc->sf_rdata.sf_rx_cring_paddr)
1338 bus_dmamap_unload(sc->sf_cdata.sf_rx_cring_tag,
1339 sc->sf_cdata.sf_rx_cring_map);
1340 if (sc->sf_rdata.sf_rx_cring)
1341 bus_dmamem_free(sc->sf_cdata.sf_rx_cring_tag,
1342 sc->sf_rdata.sf_rx_cring,
1343 sc->sf_cdata.sf_rx_cring_map);
1344 sc->sf_rdata.sf_rx_cring = NULL;
1345 sc->sf_rdata.sf_rx_cring_paddr = 0;
1346 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_cring_tag);
1347 sc->sf_cdata.sf_rx_cring_tag = NULL;
1350 if (sc->sf_cdata.sf_tx_tag) {
1351 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1352 txd = &sc->sf_cdata.sf_txdesc[i];
1353 if (txd->tx_dmamap) {
1354 bus_dmamap_destroy(sc->sf_cdata.sf_tx_tag,
1356 txd->tx_dmamap = NULL;
1359 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_tag);
1360 sc->sf_cdata.sf_tx_tag = NULL;
1363 if (sc->sf_cdata.sf_rx_tag) {
1364 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1365 rxd = &sc->sf_cdata.sf_rxdesc[i];
1366 if (rxd->rx_dmamap) {
1367 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag,
1369 rxd->rx_dmamap = NULL;
1372 if (sc->sf_cdata.sf_rx_sparemap) {
1373 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag,
1374 sc->sf_cdata.sf_rx_sparemap);
1375 sc->sf_cdata.sf_rx_sparemap = 0;
1377 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_tag);
1378 sc->sf_cdata.sf_rx_tag = NULL;
1381 if (sc->sf_cdata.sf_parent_tag) {
1382 bus_dma_tag_destroy(sc->sf_cdata.sf_parent_tag);
1383 sc->sf_cdata.sf_parent_tag = NULL;
1388 sf_init_rx_ring(struct sf_softc *sc)
1390 struct sf_ring_data *rd;
1393 sc->sf_cdata.sf_rxc_cons = 0;
1396 bzero(rd->sf_rx_ring, SF_RX_DLIST_SIZE);
1397 bzero(rd->sf_rx_cring, SF_RX_CLIST_SIZE);
1399 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1400 if (sf_newbuf(sc, i) != 0)
1404 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag,
1405 sc->sf_cdata.sf_rx_cring_map,
1406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1407 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag,
1408 sc->sf_cdata.sf_rx_ring_map,
1409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1415 sf_init_tx_ring(struct sf_softc *sc)
1417 struct sf_ring_data *rd;
1420 sc->sf_cdata.sf_tx_prod = 0;
1421 sc->sf_cdata.sf_tx_cnt = 0;
1422 sc->sf_cdata.sf_txc_cons = 0;
1425 bzero(rd->sf_tx_ring, SF_TX_DLIST_SIZE);
1426 bzero(rd->sf_tx_cring, SF_TX_CLIST_SIZE);
1427 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1428 rd->sf_tx_ring[i].sf_tx_ctrl = htole32(SF_TX_DESC_ID);
1429 sc->sf_cdata.sf_txdesc[i].tx_m = NULL;
1430 sc->sf_cdata.sf_txdesc[i].ndesc = 0;
1432 rd->sf_tx_ring[i].sf_tx_ctrl |= htole32(SF_TX_DESC_END);
1434 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag,
1435 sc->sf_cdata.sf_tx_ring_map,
1436 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1437 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag,
1438 sc->sf_cdata.sf_tx_cring_map,
1439 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1443 * Initialize an RX descriptor and attach an MBUF cluster.
1446 sf_newbuf(struct sf_softc *sc, int idx)
1448 struct sf_rx_rdesc *desc;
1449 struct sf_rxdesc *rxd;
1451 bus_dma_segment_t segs[1];
1455 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1458 m->m_len = m->m_pkthdr.len = MCLBYTES;
1459 m_adj(m, sizeof(uint32_t));
1461 if (bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_rx_tag,
1462 sc->sf_cdata.sf_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1466 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1468 rxd = &sc->sf_cdata.sf_rxdesc[idx];
1469 if (rxd->rx_m != NULL) {
1470 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap,
1471 BUS_DMASYNC_POSTREAD);
1472 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap);
1474 map = rxd->rx_dmamap;
1475 rxd->rx_dmamap = sc->sf_cdata.sf_rx_sparemap;
1476 sc->sf_cdata.sf_rx_sparemap = map;
1477 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap,
1478 BUS_DMASYNC_PREREAD);
1480 desc = &sc->sf_rdata.sf_rx_ring[idx];
1481 desc->sf_addr = htole64(segs[0].ds_addr);
1486 #ifndef __NO_STRICT_ALIGNMENT
1487 static __inline void
1488 sf_fixup_rx(struct mbuf *m)
1491 uint16_t *src, *dst;
1493 src = mtod(m, uint16_t *);
1496 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1499 m->m_data -= ETHER_ALIGN;
1504 * The starfire is programmed to use 'normal' mode for packet reception,
1505 * which means we use the consumer/producer model for both the buffer
1506 * descriptor queue and the completion descriptor queue. The only problem
1507 * with this is that it involves a lot of register accesses: we have to
1508 * read the RX completion consumer and producer indexes and the RX buffer
1509 * producer index, plus the RX completion consumer and RX buffer producer
1510 * indexes have to be updated. It would have been easier if Adaptec had
1511 * put each index in a separate register, especially given that the damn
1512 * NIC has a 512K register space.
1514 * In spite of all the lovely features that Adaptec crammed into the 6915,
1515 * it is marred by one truly stupid design flaw, which is that receive
1516 * buffer addresses must be aligned on a longword boundary. This forces
1517 * the packet payload to be unaligned, which is suboptimal on the x86 and
1518 * completely unuseable on the Alpha. Our only recourse is to copy received
1519 * packets into properly aligned buffers before handing them off.
1522 sf_rxeof(struct sf_softc *sc)
1526 struct sf_rxdesc *rxd;
1527 struct sf_rx_rcdesc *cur_cmp;
1528 int cons, eidx, prog, rx_npkts;
1529 uint32_t status, status2;
1536 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag,
1537 sc->sf_cdata.sf_rx_ring_map,
1538 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1539 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag,
1540 sc->sf_cdata.sf_rx_cring_map,
1541 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1544 * To reduce register access, directly read Receive completion
1549 for (cons = sc->sf_cdata.sf_rxc_cons;
1550 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1551 SF_INC(cons, SF_RX_CLIST_CNT)) {
1552 cur_cmp = &sc->sf_rdata.sf_rx_cring[cons];
1553 status = le32toh(cur_cmp->sf_rx_status1);
1556 #ifdef DEVICE_POLLING
1557 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
1558 if (sc->rxcycles <= 0)
1564 eidx = (status & SF_RX_CMPDESC_EIDX) >> 16;
1565 rxd = &sc->sf_cdata.sf_rxdesc[eidx];
1569 * Note, IFCOUNTER_IPACKETS and IFCOUNTER_IERRORS
1570 * are handled in sf_stats_update().
1572 if ((status & SF_RXSTAT1_OK) == 0) {
1573 cur_cmp->sf_rx_status1 = 0;
1577 if (sf_newbuf(sc, eidx) != 0) {
1578 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1579 cur_cmp->sf_rx_status1 = 0;
1583 /* AIC-6915 supports TCP/UDP checksum offload. */
1584 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1585 status2 = le32toh(cur_cmp->sf_rx_status2);
1587 * Sometimes AIC-6915 generates an interrupt to
1588 * warn RxGFP stall with bad checksum bit set
1589 * in status word. I'm not sure what conditioan
1590 * triggers it but recevied packet's checksum
1591 * was correct even though AIC-6915 does not
1592 * agree on this. This may be an indication of
1593 * firmware bug. To fix the issue, do not rely
1594 * on bad checksum bit in status word and let
1595 * upper layer verify integrity of received
1597 * Another nice feature of AIC-6915 is hardware
1598 * assistance of checksum calculation by
1599 * providing partial checksum value for received
1600 * frame. The partial checksum value can be used
1601 * to accelerate checksum computation for
1602 * fragmented TCP/UDP packets. Upper network
1603 * stack already takes advantage of the partial
1604 * checksum value in IP reassembly stage. But
1605 * I'm not sure the correctness of the partial
1606 * hardware checksum assistance as frequent
1607 * RxGFP stalls are seen on non-fragmented
1608 * frames. Due to the nature of the complexity
1609 * of checksum computation code in firmware it's
1610 * possible to see another bug in RxGFP so
1611 * ignore checksum assistance for fragmented
1612 * frames. This can be changed in future.
1614 if ((status2 & SF_RXSTAT2_FRAG) == 0) {
1615 if ((status2 & (SF_RXSTAT2_TCP |
1616 SF_RXSTAT2_UDP)) != 0) {
1617 if ((status2 & SF_RXSTAT2_CSUM_OK)) {
1618 m->m_pkthdr.csum_flags =
1621 m->m_pkthdr.csum_data = 0xffff;
1625 #ifdef SF_PARTIAL_CSUM_SUPPORT
1626 else if ((status2 & SF_RXSTAT2_FRAG) != 0) {
1627 if ((status2 & (SF_RXSTAT2_TCP |
1628 SF_RXSTAT2_UDP)) != 0) {
1629 if ((status2 & SF_RXSTAT2_PCSUM_OK)) {
1630 m->m_pkthdr.csum_flags =
1632 m->m_pkthdr.csum_data =
1634 SF_RX_CMPDESC_CSUM2);
1641 m->m_pkthdr.len = m->m_len = status & SF_RX_CMPDESC_LEN;
1642 #ifndef __NO_STRICT_ALIGNMENT
1645 m->m_pkthdr.rcvif = ifp;
1648 (*ifp->if_input)(ifp, m);
1652 /* Clear completion status. */
1653 cur_cmp->sf_rx_status1 = 0;
1657 sc->sf_cdata.sf_rxc_cons = cons;
1658 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag,
1659 sc->sf_cdata.sf_rx_ring_map,
1660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1661 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag,
1662 sc->sf_cdata.sf_rx_cring_map,
1663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1665 /* Update Rx completion Q1 consumer index. */
1666 csr_write_4(sc, SF_CQ_CONSIDX,
1667 (csr_read_4(sc, SF_CQ_CONSIDX) & ~SF_CQ_CONSIDX_RXQ1) |
1668 (cons & SF_CQ_CONSIDX_RXQ1));
1669 /* Update Rx descriptor Q1 ptr. */
1670 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1671 (csr_read_4(sc, SF_RXDQ_PTR_Q1) & ~SF_RXDQ_PRODIDX) |
1672 (eidx & SF_RXDQ_PRODIDX));
1678 * Read the transmit status from the completion queue and release
1679 * mbufs. Note that the buffer descriptor index in the completion
1680 * descriptor is an offset from the start of the transmit buffer
1681 * descriptor list in bytes. This is important because the manual
1682 * gives the impression that it should match the producer/consumer
1683 * index, which is the offset in 8 byte blocks.
1686 sf_txeof(struct sf_softc *sc)
1688 struct sf_txdesc *txd;
1689 struct sf_tx_rcdesc *cur_cmp;
1692 int cons, idx, prod;
1698 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag,
1699 sc->sf_cdata.sf_tx_cring_map,
1700 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1702 cons = sc->sf_cdata.sf_txc_cons;
1703 prod = (csr_read_4(sc, SF_CQ_PRODIDX) & SF_TXDQ_PRODIDX_HIPRIO) >> 16;
1707 for (; cons != prod; SF_INC(cons, SF_TX_CLIST_CNT)) {
1708 cur_cmp = &sc->sf_rdata.sf_tx_cring[cons];
1709 status = le32toh(cur_cmp->sf_tx_status1);
1712 switch (status & SF_TX_CMPDESC_TYPE) {
1713 case SF_TXCMPTYPE_TX:
1714 /* Tx complete entry. */
1716 case SF_TXCMPTYPE_DMA:
1717 /* DMA complete entry. */
1718 idx = status & SF_TX_CMPDESC_IDX;
1719 idx = idx / sizeof(struct sf_tx_rdesc);
1721 * We don't need to check Tx status here.
1722 * SF_ISR_TX_LOFIFO intr would handle this.
1723 * Note, IFCOUNTER_OPACKETS, IFCOUNTER_COLLISIONS
1724 * and IFCOUNTER_OERROR are handled in
1725 * sf_stats_update().
1727 txd = &sc->sf_cdata.sf_txdesc[idx];
1728 if (txd->tx_m != NULL) {
1729 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag,
1731 BUS_DMASYNC_POSTWRITE);
1732 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag,
1737 sc->sf_cdata.sf_tx_cnt -= txd->ndesc;
1738 KASSERT(sc->sf_cdata.sf_tx_cnt >= 0,
1739 ("%s: Active Tx desc counter was garbled\n",
1742 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1745 /* It should not happen. */
1746 device_printf(sc->sf_dev,
1747 "unknown Tx completion type : 0x%08x : %d : %d\n",
1748 status, cons, prod);
1751 cur_cmp->sf_tx_status1 = 0;
1754 sc->sf_cdata.sf_txc_cons = cons;
1755 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag,
1756 sc->sf_cdata.sf_tx_cring_map,
1757 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1759 if (sc->sf_cdata.sf_tx_cnt == 0)
1760 sc->sf_watchdog_timer = 0;
1762 /* Update Tx completion consumer index. */
1763 csr_write_4(sc, SF_CQ_CONSIDX,
1764 (csr_read_4(sc, SF_CQ_CONSIDX) & 0xffff) |
1765 ((cons << 16) & 0xffff0000));
1769 sf_txthresh_adjust(struct sf_softc *sc)
1773 device_printf(sc->sf_dev, "Tx underrun -- ");
1774 if (sc->sf_txthresh < SF_MAX_TX_THRESHOLD) {
1775 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1776 /* Increase Tx threshold 256 bytes. */
1777 sc->sf_txthresh += 16;
1778 if (sc->sf_txthresh > SF_MAX_TX_THRESHOLD)
1779 sc->sf_txthresh = SF_MAX_TX_THRESHOLD;
1780 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1781 txfctl |= sc->sf_txthresh;
1782 printf("increasing Tx threshold to %d bytes\n",
1783 sc->sf_txthresh * SF_TX_THRESHOLD_UNIT);
1784 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1789 #ifdef DEVICE_POLLING
1791 sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1793 struct sf_softc *sc;
1801 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1806 sc->rxcycles = count;
1807 rx_npkts = sf_rxeof(sc);
1809 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1810 sf_start_locked(ifp);
1812 if (cmd == POLL_AND_CHECK_STATUS) {
1813 /* Reading the ISR register clears all interrrupts. */
1814 status = csr_read_4(sc, SF_ISR);
1816 if ((status & SF_ISR_ABNORMALINTR) != 0) {
1817 if ((status & SF_ISR_STATSOFLOW) != 0)
1818 sf_stats_update(sc);
1819 else if ((status & SF_ISR_TX_LOFIFO) != 0)
1820 sf_txthresh_adjust(sc);
1821 else if ((status & SF_ISR_DMAERR) != 0) {
1822 device_printf(sc->sf_dev,
1823 "DMA error, resetting\n");
1824 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1828 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) {
1829 sc->sf_statistics.sf_tx_gfp_stall++;
1831 device_printf(sc->sf_dev,
1832 "TxGFP is not responding!\n");
1834 } else if ((status & SF_ISR_RXGFP_NORESP) != 0) {
1835 sc->sf_statistics.sf_rx_gfp_stall++;
1837 device_printf(sc->sf_dev,
1838 "RxGFP is not responding!\n");
1847 #endif /* DEVICE_POLLING */
1852 struct sf_softc *sc;
1857 sc = (struct sf_softc *)arg;
1860 if (sc->sf_suspended != 0)
1863 /* Reading the ISR register clears all interrrupts. */
1864 status = csr_read_4(sc, SF_ISR);
1865 if (status == 0 || status == 0xffffffff ||
1866 (status & SF_ISR_PCIINT_ASSERTED) == 0)
1870 #ifdef DEVICE_POLLING
1871 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1875 /* Disable interrupts. */
1876 csr_write_4(sc, SF_IMR, 0x00000000);
1878 for (cnt = 32; (status & SF_INTRS) != 0;) {
1879 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1881 if ((status & SF_ISR_RXDQ1_DMADONE) != 0)
1884 if ((status & (SF_ISR_TX_TXDONE | SF_ISR_TX_DMADONE |
1885 SF_ISR_TX_QUEUEDONE)) != 0)
1888 if ((status & SF_ISR_ABNORMALINTR) != 0) {
1889 if ((status & SF_ISR_STATSOFLOW) != 0)
1890 sf_stats_update(sc);
1891 else if ((status & SF_ISR_TX_LOFIFO) != 0)
1892 sf_txthresh_adjust(sc);
1893 else if ((status & SF_ISR_DMAERR) != 0) {
1894 device_printf(sc->sf_dev,
1895 "DMA error, resetting\n");
1896 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1900 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) {
1901 sc->sf_statistics.sf_tx_gfp_stall++;
1903 device_printf(sc->sf_dev,
1904 "TxGFP is not responding!\n");
1907 else if ((status & SF_ISR_RXGFP_NORESP) != 0) {
1908 sc->sf_statistics.sf_rx_gfp_stall++;
1910 device_printf(sc->sf_dev,
1911 "RxGFP is not responding!\n");
1915 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1916 sf_start_locked(ifp);
1919 /* Reading the ISR register clears all interrrupts. */
1920 status = csr_read_4(sc, SF_ISR);
1923 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1924 /* Re-enable interrupts. */
1925 csr_write_4(sc, SF_IMR, SF_INTRS);
1933 sf_download_fw(struct sf_softc *sc)
1940 * A FP instruction is composed of 48bits so we have to
1941 * write it with two parts.
1945 for (i = 0; i < sizeof(txfwdata) / SF_GFP_INST_BYTES; i++) {
1946 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5];
1947 csr_write_4(sc, SF_TXGFP_MEM_BASE + ndx * 4, gfpinst);
1948 gfpinst = p[0] << 8 | p[1];
1949 csr_write_4(sc, SF_TXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst);
1950 p += SF_GFP_INST_BYTES;
1954 device_printf(sc->sf_dev, "%d Tx instructions downloaded\n", i);
1958 for (i = 0; i < sizeof(rxfwdata) / SF_GFP_INST_BYTES; i++) {
1959 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5];
1960 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx * 4), gfpinst);
1961 gfpinst = p[0] << 8 | p[1];
1962 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst);
1963 p += SF_GFP_INST_BYTES;
1967 device_printf(sc->sf_dev, "%d Rx instructions downloaded\n", i);
1973 struct sf_softc *sc;
1975 sc = (struct sf_softc *)xsc;
1982 sf_init_locked(struct sf_softc *sc)
1985 uint8_t eaddr[ETHER_ADDR_LEN];
1991 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1995 /* Reset the hardware to a known state. */
1998 /* Init all the receive filter registers */
1999 for (i = SF_RXFILT_PERFECT_BASE;
2000 i < (SF_RXFILT_HASH_MAX + 1); i += sizeof(uint32_t))
2001 csr_write_4(sc, i, 0);
2003 /* Empty stats counter registers. */
2004 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t))
2005 csr_write_4(sc, i, 0);
2007 /* Init our MAC address. */
2008 bcopy(IF_LLADDR(sc->sf_ifp), eaddr, sizeof(eaddr));
2009 csr_write_4(sc, SF_PAR0,
2010 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2011 csr_write_4(sc, SF_PAR1, eaddr[0] << 8 | eaddr[1]);
2012 sf_setperf(sc, 0, eaddr);
2014 if (sf_init_rx_ring(sc) == ENOBUFS) {
2015 device_printf(sc->sf_dev,
2016 "initialization failed: no memory for rx buffers\n");
2021 sf_init_tx_ring(sc);
2024 * 16 perfect address filtering.
2025 * Hash only multicast destination address, Accept matching
2026 * frames regardless of VLAN ID.
2028 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL | SF_HASHMODE_ANYVLAN);
2035 /* Init the completion queue indexes. */
2036 csr_write_4(sc, SF_CQ_CONSIDX, 0);
2037 csr_write_4(sc, SF_CQ_PRODIDX, 0);
2039 /* Init the RX completion queue. */
2040 addr = sc->sf_rdata.sf_rx_cring_paddr;
2041 csr_write_4(sc, SF_CQ_ADDR_HI, SF_ADDR_HI(addr));
2042 csr_write_4(sc, SF_RXCQ_CTL_1, SF_ADDR_LO(addr) & SF_RXCQ_ADDR);
2043 if (SF_ADDR_HI(addr) != 0)
2044 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQ_USE_64BIT);
2045 /* Set RX completion queue type 2. */
2046 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_2);
2047 csr_write_4(sc, SF_RXCQ_CTL_2, 0);
2050 * Init RX DMA control.
2051 * default RxHighPriority Threshold,
2052 * default RxBurstSize, 128bytes.
2054 SF_SETBIT(sc, SF_RXDMA_CTL,
2055 SF_RXDMA_REPORTBADPKTS |
2056 (SF_RXDMA_HIGHPRIO_THRESH << 8) |
2059 /* Init the RX buffer descriptor queue. */
2060 addr = sc->sf_rdata.sf_rx_ring_paddr;
2061 csr_write_4(sc, SF_RXDQ_ADDR_HI, SF_ADDR_HI(addr));
2062 csr_write_4(sc, SF_RXDQ_ADDR_Q1, SF_ADDR_LO(addr));
2064 /* Set RX queue buffer length. */
2065 csr_write_4(sc, SF_RXDQ_CTL_1,
2066 ((MCLBYTES - sizeof(uint32_t)) << 16) |
2067 SF_RXDQCTL_64BITBADDR | SF_RXDQCTL_VARIABLE);
2069 if (SF_ADDR_HI(addr) != 0)
2070 SF_SETBIT(sc, SF_RXDQ_CTL_1, SF_RXDQCTL_64BITDADDR);
2071 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
2072 csr_write_4(sc, SF_RXDQ_CTL_2, 0);
2074 /* Init the TX completion queue */
2075 addr = sc->sf_rdata.sf_tx_cring_paddr;
2076 csr_write_4(sc, SF_TXCQ_CTL, SF_ADDR_LO(addr) & SF_TXCQ_ADDR);
2077 if (SF_ADDR_HI(addr) != 0)
2078 SF_SETBIT(sc, SF_TXCQ_CTL, SF_TXCQ_USE_64BIT);
2080 /* Init the TX buffer descriptor queue. */
2081 addr = sc->sf_rdata.sf_tx_ring_paddr;
2082 csr_write_4(sc, SF_TXDQ_ADDR_HI, SF_ADDR_HI(addr));
2083 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
2084 csr_write_4(sc, SF_TXDQ_ADDR_LOPRIO, SF_ADDR_LO(addr));
2085 csr_write_4(sc, SF_TX_FRAMCTL,
2086 SF_TXFRMCTL_CPLAFTERTX | sc->sf_txthresh);
2087 csr_write_4(sc, SF_TXDQ_CTL,
2088 SF_TXDMA_HIPRIO_THRESH << 24 |
2089 SF_TXSKIPLEN_0BYTES << 16 |
2090 SF_TXDDMA_BURST << 8 |
2091 SF_TXBUFDESC_TYPE2 | SF_TXMINSPACE_UNLIMIT);
2092 if (SF_ADDR_HI(addr) != 0)
2093 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_64BITADDR);
2095 /* Set VLAN Type register. */
2096 csr_write_4(sc, SF_VLANTYPE, ETHERTYPE_VLAN);
2098 /* Set TxPause Timer. */
2099 csr_write_4(sc, SF_TXPAUSETIMER, 0xffff);
2101 /* Enable autopadding of short TX frames. */
2102 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
2103 SF_SETBIT(sc, SF_MACCFG_2, SF_MACCFG2_AUTOVLANPAD);
2104 /* Make sure to reset MAC to take changes effect. */
2105 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
2107 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
2109 /* Enable PCI bus master. */
2110 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_PCIMEN);
2112 /* Load StarFire firmware. */
2115 /* Intialize interrupt moderation. */
2116 csr_write_4(sc, SF_TIMER_CTL, SF_TIMER_IMASK_MODE | SF_TIMER_TIMES_TEN |
2117 (sc->sf_int_mod & SF_TIMER_IMASK_INTERVAL));
2119 #ifdef DEVICE_POLLING
2120 /* Disable interrupts if we are polling. */
2121 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2122 csr_write_4(sc, SF_IMR, 0x00000000);
2125 /* Enable interrupts. */
2126 csr_write_4(sc, SF_IMR, SF_INTRS);
2127 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
2129 /* Enable the RX and TX engines. */
2130 csr_write_4(sc, SF_GEN_ETH_CTL,
2131 SF_ETHCTL_RX_ENB | SF_ETHCTL_RXDMA_ENB |
2132 SF_ETHCTL_TX_ENB | SF_ETHCTL_TXDMA_ENB);
2134 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2135 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB);
2137 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB);
2138 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2139 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB);
2141 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB);
2143 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2144 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2147 sf_ifmedia_upd_locked(ifp);
2149 callout_reset(&sc->sf_co, hz, sf_tick, sc);
2153 sf_encap(struct sf_softc *sc, struct mbuf **m_head)
2155 struct sf_txdesc *txd;
2156 struct sf_tx_rdesc *desc;
2159 bus_dma_segment_t txsegs[SF_MAXTXSEGS];
2160 int error, i, nsegs, prod, si;
2166 prod = sc->sf_cdata.sf_tx_prod;
2167 txd = &sc->sf_cdata.sf_txdesc[prod];
2168 map = txd->tx_dmamap;
2169 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag, map,
2170 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
2171 if (error == EFBIG) {
2172 m = m_collapse(*m_head, M_NOWAIT, SF_MAXTXSEGS);
2179 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag,
2180 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
2186 } else if (error != 0)
2194 /* Check number of available descriptors. */
2195 avail = (SF_TX_DLIST_CNT - 1) - sc->sf_cdata.sf_tx_cnt;
2196 if (avail < nsegs) {
2197 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map);
2201 if (prod + nsegs >= SF_TX_DLIST_CNT) {
2202 nskip = SF_TX_DLIST_CNT - prod - 1;
2203 if (avail < nsegs + nskip) {
2204 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map);
2209 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, map, BUS_DMASYNC_PREWRITE);
2212 for (i = 0; i < nsegs; i++) {
2213 desc = &sc->sf_rdata.sf_tx_ring[prod];
2214 desc->sf_tx_ctrl = htole32(SF_TX_DESC_ID |
2215 (txsegs[i].ds_len & SF_TX_DESC_FRAGLEN));
2216 desc->sf_tx_reserved = 0;
2217 desc->sf_addr = htole64(txsegs[i].ds_addr);
2218 if (i == 0 && prod + nsegs >= SF_TX_DLIST_CNT) {
2220 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_END);
2223 SF_INC(prod, SF_TX_DLIST_CNT);
2225 /* Update producer index. */
2226 sc->sf_cdata.sf_tx_prod = prod;
2227 sc->sf_cdata.sf_tx_cnt += nsegs + nskip;
2229 desc = &sc->sf_rdata.sf_tx_ring[si];
2230 /* Check TDP/UDP checksum offload request. */
2231 if ((m->m_pkthdr.csum_flags & SF_CSUM_FEATURES) != 0)
2232 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_CALTCP);
2234 htole32(SF_TX_DESC_CRCEN | SF_TX_DESC_INTR | (nsegs << 16));
2236 txd->tx_dmamap = map;
2238 txd->ndesc = nsegs + nskip;
2244 sf_start(struct ifnet *ifp)
2246 struct sf_softc *sc;
2250 sf_start_locked(ifp);
2255 sf_start_locked(struct ifnet *ifp)
2257 struct sf_softc *sc;
2258 struct mbuf *m_head;
2264 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2265 IFF_DRV_RUNNING || sc->sf_link == 0)
2269 * Since we don't know when descriptor wrap occurrs in advance
2270 * limit available number of active Tx descriptor counter to be
2271 * higher than maximum number of DMA segments allowed in driver.
2273 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2274 sc->sf_cdata.sf_tx_cnt < SF_TX_DLIST_CNT - SF_MAXTXSEGS; ) {
2275 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2279 * Pack the data into the transmit ring. If we
2280 * don't have room, set the OACTIVE flag and wait
2281 * for the NIC to drain the ring.
2283 if (sf_encap(sc, &m_head)) {
2286 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2287 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2293 * If there's a BPF listener, bounce a copy of this frame
2296 ETHER_BPF_MTAP(ifp, m_head);
2300 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag,
2301 sc->sf_cdata.sf_tx_ring_map,
2302 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2303 /* Kick transmit. */
2304 csr_write_4(sc, SF_TXDQ_PRODIDX,
2305 sc->sf_cdata.sf_tx_prod * (sizeof(struct sf_tx_rdesc) / 8));
2307 /* Set a timeout in case the chip goes out to lunch. */
2308 sc->sf_watchdog_timer = 5;
2313 sf_stop(struct sf_softc *sc)
2315 struct sf_txdesc *txd;
2316 struct sf_rxdesc *rxd;
2324 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2326 callout_stop(&sc->sf_co);
2327 sc->sf_watchdog_timer = 0;
2329 /* Reading the ISR register clears all interrrupts. */
2330 csr_read_4(sc, SF_ISR);
2331 /* Disable further interrupts. */
2332 csr_write_4(sc, SF_IMR, 0);
2334 /* Disable Tx/Rx egine. */
2335 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
2337 /* Give hardware chance to drain active DMA cycles. */
2340 csr_write_4(sc, SF_CQ_CONSIDX, 0);
2341 csr_write_4(sc, SF_CQ_PRODIDX, 0);
2342 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
2343 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
2344 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
2345 csr_write_4(sc, SF_TXCQ_CTL, 0);
2346 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
2347 csr_write_4(sc, SF_TXDQ_CTL, 0);
2350 * Free RX and TX mbufs still in the queues.
2352 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
2353 rxd = &sc->sf_cdata.sf_rxdesc[i];
2354 if (rxd->rx_m != NULL) {
2355 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag,
2356 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2357 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag,
2363 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
2364 txd = &sc->sf_cdata.sf_txdesc[i];
2365 if (txd->tx_m != NULL) {
2366 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag,
2367 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2368 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag,
2380 struct sf_softc *sc;
2381 struct mii_data *mii;
2385 mii = device_get_softc(sc->sf_miibus);
2387 sf_stats_update(sc);
2389 callout_reset(&sc->sf_co, hz, sf_tick, sc);
2393 * Note: it is important that this function not be interrupted. We
2394 * use a two-stage register access scheme: if we are interrupted in
2395 * between setting the indirect address register and reading from the
2396 * indirect data register, the contents of the address register could
2397 * be changed out from under us.
2400 sf_stats_update(struct sf_softc *sc)
2403 struct sf_stats now, *stats, *nstats;
2411 stats->sf_tx_frames =
2412 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAMES);
2413 stats->sf_tx_single_colls =
2414 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_SINGLE_COL);
2415 stats->sf_tx_multi_colls =
2416 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI_COL);
2417 stats->sf_tx_crcerrs =
2418 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CRC_ERRS);
2419 stats->sf_tx_bytes =
2420 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BYTES);
2421 stats->sf_tx_deferred =
2422 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_DEFERRED);
2423 stats->sf_tx_late_colls =
2424 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_LATE_COL);
2425 stats->sf_tx_pause_frames =
2426 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_PAUSE);
2427 stats->sf_tx_control_frames =
2428 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CTL_FRAME);
2429 stats->sf_tx_excess_colls =
2430 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_COL);
2431 stats->sf_tx_excess_defer =
2432 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_DEF);
2433 stats->sf_tx_mcast_frames =
2434 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI);
2435 stats->sf_tx_bcast_frames =
2436 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BCAST);
2437 stats->sf_tx_frames_lost =
2438 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAME_LOST);
2439 stats->sf_rx_frames =
2440 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAMES);
2441 stats->sf_rx_crcerrs =
2442 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CRC_ERRS);
2443 stats->sf_rx_alignerrs =
2444 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_ALIGN_ERRS);
2445 stats->sf_rx_bytes =
2446 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_BYTES);
2447 stats->sf_rx_pause_frames =
2448 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_PAUSE);
2449 stats->sf_rx_control_frames =
2450 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CTL_FRAME);
2451 stats->sf_rx_unsup_control_frames =
2452 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_UNSUP_FRAME);
2453 stats->sf_rx_giants =
2454 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_GIANTS);
2455 stats->sf_rx_runts =
2456 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_RUNTS);
2457 stats->sf_rx_jabbererrs =
2458 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_JABBER);
2459 stats->sf_rx_fragments =
2460 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAGMENTS);
2461 stats->sf_rx_pkts_64 =
2462 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_64);
2463 stats->sf_rx_pkts_65_127 =
2464 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_65_127);
2465 stats->sf_rx_pkts_128_255 =
2466 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_128_255);
2467 stats->sf_rx_pkts_256_511 =
2468 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_256_511);
2469 stats->sf_rx_pkts_512_1023 =
2470 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_512_1023);
2471 stats->sf_rx_pkts_1024_1518 =
2472 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_1024_1518);
2473 stats->sf_rx_frames_lost =
2474 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAME_LOST);
2475 /* Lower 16bits are valid. */
2476 stats->sf_tx_underruns =
2477 (csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_UNDERRUN) & 0xffff);
2479 /* Empty stats counter registers. */
2480 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t))
2481 csr_write_4(sc, i, 0);
2483 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)stats->sf_tx_frames);
2485 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2486 (u_long)stats->sf_tx_single_colls +
2487 (u_long)stats->sf_tx_multi_colls);
2489 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2490 (u_long)stats->sf_tx_excess_colls +
2491 (u_long)stats->sf_tx_excess_defer +
2492 (u_long)stats->sf_tx_frames_lost);
2494 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)stats->sf_rx_frames);
2496 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2497 (u_long)stats->sf_rx_crcerrs +
2498 (u_long)stats->sf_rx_alignerrs +
2499 (u_long)stats->sf_rx_giants +
2500 (u_long)stats->sf_rx_runts +
2501 (u_long)stats->sf_rx_jabbererrs +
2502 (u_long)stats->sf_rx_frames_lost);
2504 nstats = &sc->sf_statistics;
2506 nstats->sf_tx_frames += stats->sf_tx_frames;
2507 nstats->sf_tx_single_colls += stats->sf_tx_single_colls;
2508 nstats->sf_tx_multi_colls += stats->sf_tx_multi_colls;
2509 nstats->sf_tx_crcerrs += stats->sf_tx_crcerrs;
2510 nstats->sf_tx_bytes += stats->sf_tx_bytes;
2511 nstats->sf_tx_deferred += stats->sf_tx_deferred;
2512 nstats->sf_tx_late_colls += stats->sf_tx_late_colls;
2513 nstats->sf_tx_pause_frames += stats->sf_tx_pause_frames;
2514 nstats->sf_tx_control_frames += stats->sf_tx_control_frames;
2515 nstats->sf_tx_excess_colls += stats->sf_tx_excess_colls;
2516 nstats->sf_tx_excess_defer += stats->sf_tx_excess_defer;
2517 nstats->sf_tx_mcast_frames += stats->sf_tx_mcast_frames;
2518 nstats->sf_tx_bcast_frames += stats->sf_tx_bcast_frames;
2519 nstats->sf_tx_frames_lost += stats->sf_tx_frames_lost;
2520 nstats->sf_rx_frames += stats->sf_rx_frames;
2521 nstats->sf_rx_crcerrs += stats->sf_rx_crcerrs;
2522 nstats->sf_rx_alignerrs += stats->sf_rx_alignerrs;
2523 nstats->sf_rx_bytes += stats->sf_rx_bytes;
2524 nstats->sf_rx_pause_frames += stats->sf_rx_pause_frames;
2525 nstats->sf_rx_control_frames += stats->sf_rx_control_frames;
2526 nstats->sf_rx_unsup_control_frames += stats->sf_rx_unsup_control_frames;
2527 nstats->sf_rx_giants += stats->sf_rx_giants;
2528 nstats->sf_rx_runts += stats->sf_rx_runts;
2529 nstats->sf_rx_jabbererrs += stats->sf_rx_jabbererrs;
2530 nstats->sf_rx_fragments += stats->sf_rx_fragments;
2531 nstats->sf_rx_pkts_64 += stats->sf_rx_pkts_64;
2532 nstats->sf_rx_pkts_65_127 += stats->sf_rx_pkts_65_127;
2533 nstats->sf_rx_pkts_128_255 += stats->sf_rx_pkts_128_255;
2534 nstats->sf_rx_pkts_256_511 += stats->sf_rx_pkts_256_511;
2535 nstats->sf_rx_pkts_512_1023 += stats->sf_rx_pkts_512_1023;
2536 nstats->sf_rx_pkts_1024_1518 += stats->sf_rx_pkts_1024_1518;
2537 nstats->sf_rx_frames_lost += stats->sf_rx_frames_lost;
2538 nstats->sf_tx_underruns += stats->sf_tx_underruns;
2542 sf_watchdog(struct sf_softc *sc)
2548 if (sc->sf_watchdog_timer == 0 || --sc->sf_watchdog_timer)
2553 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2554 if (sc->sf_link == 0) {
2556 if_printf(sc->sf_ifp, "watchdog timeout "
2559 if_printf(ifp, "watchdog timeout, %d Tx descs are active\n",
2560 sc->sf_cdata.sf_tx_cnt);
2562 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2565 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2566 sf_start_locked(ifp);
2570 sf_shutdown(device_t dev)
2572 struct sf_softc *sc;
2574 sc = device_get_softc(dev);
2584 sf_suspend(device_t dev)
2586 struct sf_softc *sc;
2588 sc = device_get_softc(dev);
2592 sc->sf_suspended = 1;
2593 bus_generic_suspend(dev);
2600 sf_resume(device_t dev)
2602 struct sf_softc *sc;
2605 sc = device_get_softc(dev);
2608 bus_generic_resume(dev);
2610 if ((ifp->if_flags & IFF_UP) != 0)
2613 sc->sf_suspended = 0;
2620 sf_sysctl_stats(SYSCTL_HANDLER_ARGS)
2622 struct sf_softc *sc;
2623 struct sf_stats *stats;
2628 error = sysctl_handle_int(oidp, &result, 0, req);
2630 if (error != 0 || req->newptr == NULL)
2636 sc = (struct sf_softc *)arg1;
2637 stats = &sc->sf_statistics;
2639 printf("%s statistics:\n", device_get_nameunit(sc->sf_dev));
2640 printf("Transmit good frames : %ju\n",
2641 (uintmax_t)stats->sf_tx_frames);
2642 printf("Transmit good octets : %ju\n",
2643 (uintmax_t)stats->sf_tx_bytes);
2644 printf("Transmit single collisions : %u\n",
2645 stats->sf_tx_single_colls);
2646 printf("Transmit multiple collisions : %u\n",
2647 stats->sf_tx_multi_colls);
2648 printf("Transmit late collisions : %u\n",
2649 stats->sf_tx_late_colls);
2650 printf("Transmit abort due to excessive collisions : %u\n",
2651 stats->sf_tx_excess_colls);
2652 printf("Transmit CRC errors : %u\n",
2653 stats->sf_tx_crcerrs);
2654 printf("Transmit deferrals : %u\n",
2655 stats->sf_tx_deferred);
2656 printf("Transmit abort due to excessive deferrals : %u\n",
2657 stats->sf_tx_excess_defer);
2658 printf("Transmit pause control frames : %u\n",
2659 stats->sf_tx_pause_frames);
2660 printf("Transmit control frames : %u\n",
2661 stats->sf_tx_control_frames);
2662 printf("Transmit good multicast frames : %u\n",
2663 stats->sf_tx_mcast_frames);
2664 printf("Transmit good broadcast frames : %u\n",
2665 stats->sf_tx_bcast_frames);
2666 printf("Transmit frames lost due to internal transmit errors : %u\n",
2667 stats->sf_tx_frames_lost);
2668 printf("Transmit FIFO underflows : %u\n",
2669 stats->sf_tx_underruns);
2670 printf("Transmit GFP stalls : %u\n", stats->sf_tx_gfp_stall);
2671 printf("Receive good frames : %ju\n",
2672 (uint64_t)stats->sf_rx_frames);
2673 printf("Receive good octets : %ju\n",
2674 (uint64_t)stats->sf_rx_bytes);
2675 printf("Receive CRC errors : %u\n",
2676 stats->sf_rx_crcerrs);
2677 printf("Receive alignment errors : %u\n",
2678 stats->sf_rx_alignerrs);
2679 printf("Receive pause frames : %u\n",
2680 stats->sf_rx_pause_frames);
2681 printf("Receive control frames : %u\n",
2682 stats->sf_rx_control_frames);
2683 printf("Receive control frames with unsupported opcode : %u\n",
2684 stats->sf_rx_unsup_control_frames);
2685 printf("Receive frames too long : %u\n",
2686 stats->sf_rx_giants);
2687 printf("Receive frames too short : %u\n",
2688 stats->sf_rx_runts);
2689 printf("Receive frames jabber errors : %u\n",
2690 stats->sf_rx_jabbererrs);
2691 printf("Receive frames fragments : %u\n",
2692 stats->sf_rx_fragments);
2693 printf("Receive packets 64 bytes : %ju\n",
2694 (uint64_t)stats->sf_rx_pkts_64);
2695 printf("Receive packets 65 to 127 bytes : %ju\n",
2696 (uint64_t)stats->sf_rx_pkts_65_127);
2697 printf("Receive packets 128 to 255 bytes : %ju\n",
2698 (uint64_t)stats->sf_rx_pkts_128_255);
2699 printf("Receive packets 256 to 511 bytes : %ju\n",
2700 (uint64_t)stats->sf_rx_pkts_256_511);
2701 printf("Receive packets 512 to 1023 bytes : %ju\n",
2702 (uint64_t)stats->sf_rx_pkts_512_1023);
2703 printf("Receive packets 1024 to 1518 bytes : %ju\n",
2704 (uint64_t)stats->sf_rx_pkts_1024_1518);
2705 printf("Receive frames lost due to internal receive errors : %u\n",
2706 stats->sf_rx_frames_lost);
2707 printf("Receive GFP stalls : %u\n", stats->sf_rx_gfp_stall);
2713 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2719 value = *(int *)arg1;
2720 error = sysctl_handle_int(oidp, &value, 0, req);
2721 if (error || !req->newptr)
2723 if (value < low || value > high)
2725 *(int *)arg1 = value;
2731 sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS)
2734 return (sysctl_int_range(oidp, arg1, arg2, req, SF_IM_MIN, SF_IM_MAX));