2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_STATS
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
43 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
45 (_eep)->ee_stat[_stat]++; \
46 _NOTE(CONSTANTCONDITION) \
49 #define EFX_EV_QSTAT_INCR(_eep, _stat)
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
67 static __checkReturn boolean_t
70 __in efx_qword_t *eqp,
71 __in const efx_ev_callbacks_t *eecp,
74 static __checkReturn boolean_t
77 __in efx_qword_t *eqp,
78 __in const efx_ev_callbacks_t *eecp,
81 static __checkReturn boolean_t
84 __in efx_qword_t *eqp,
85 __in const efx_ev_callbacks_t *eecp,
89 static __checkReturn efx_rc_t
92 __in unsigned int instance,
93 __in efsys_mem_t *esmp,
98 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
101 MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
102 MC_CMD_INIT_EVQ_OUT_LEN)];
103 efx_qword_t *dma_addr;
107 int supports_rx_batching;
110 npages = EFX_EVQ_NBUFS(nevs);
111 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
116 (void) memset(payload, 0, sizeof (payload));
117 req.emr_cmd = MC_CMD_INIT_EVQ;
118 req.emr_in_buf = payload;
119 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
120 req.emr_out_buf = payload;
121 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
123 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
124 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
125 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
128 * On Huntington RX and TX event batching can only be requested
129 * together (even if the datapath firmware doesn't actually support RX
131 * Cut through is incompatible with RX batching and so enabling cut
132 * through disables RX batching (but it does not affect TX batching).
134 * So always enable RX and TX event batching, and enable cut through
135 * if RX event batching isn't supported (i.e. on low latency firmware).
137 supports_rx_batching = enp->en_nic_cfg.enc_rx_batching_enabled ? 1 : 0;
138 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
139 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
140 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
141 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
142 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_batching,
143 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
144 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
147 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
148 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
149 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
154 /* Calculate the timer value in quanta */
155 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
157 /* Moderation value is base 0 so we need to deduct 1 */
161 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
162 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
163 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, timer_val);
164 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, timer_val);
167 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
168 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
169 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
171 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
172 addr = EFSYS_MEM_ADDR(esmp);
174 for (i = 0; i < npages; i++) {
175 EFX_POPULATE_QWORD_2(*dma_addr,
176 EFX_DWORD_1, (uint32_t)(addr >> 32),
177 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
180 addr += EFX_BUF_SIZE;
183 efx_mcdi_execute(enp, &req);
185 if (req.emr_rc != 0) {
190 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
195 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
204 EFSYS_PROBE1(fail1, efx_rc_t, rc);
209 static __checkReturn efx_rc_t
212 __in uint32_t instance)
215 uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN,
216 MC_CMD_FINI_EVQ_OUT_LEN)];
219 (void) memset(payload, 0, sizeof (payload));
220 req.emr_cmd = MC_CMD_FINI_EVQ;
221 req.emr_in_buf = payload;
222 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
223 req.emr_out_buf = payload;
224 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
226 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
228 efx_mcdi_execute_quiet(enp, &req);
230 if (req.emr_rc != 0) {
238 EFSYS_PROBE1(fail1, efx_rc_t, rc);
245 __checkReturn efx_rc_t
249 _NOTE(ARGUNUSED(enp))
257 _NOTE(ARGUNUSED(enp))
260 __checkReturn efx_rc_t
263 __in unsigned int index,
264 __in efsys_mem_t *esmp,
270 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
274 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
275 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
276 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
278 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
283 if (index >= encp->enc_evq_limit) {
288 if (us > encp->enc_evq_timer_max_us) {
293 /* Set up the handler table */
294 eep->ee_rx = ef10_ev_rx;
295 eep->ee_tx = ef10_ev_tx;
296 eep->ee_driver = ef10_ev_driver;
297 eep->ee_drv_gen = ef10_ev_drv_gen;
298 eep->ee_mcdi = ef10_ev_mcdi;
300 /* Set up the event queue */
301 irq = index; /* INIT_EVQ expects function-relative vector number */
304 * Interrupts may be raised for events immediately after the queue is
305 * created. See bug58606.
307 if ((rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, us)) != 0)
319 EFSYS_PROBE1(fail1, efx_rc_t, rc);
328 efx_nic_t *enp = eep->ee_enp;
330 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
331 enp->en_family == EFX_FAMILY_MEDFORD);
333 (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
336 __checkReturn efx_rc_t
339 __in unsigned int count)
341 efx_nic_t *enp = eep->ee_enp;
345 rptr = count & eep->ee_mask;
347 if (enp->en_nic_cfg.enc_bug35388_workaround) {
348 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
349 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
350 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
351 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
353 EFX_POPULATE_DWORD_2(dword,
354 ERF_DD_EVQ_IND_RPTR_FLAGS,
355 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
357 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
358 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
361 EFX_POPULATE_DWORD_2(dword,
362 ERF_DD_EVQ_IND_RPTR_FLAGS,
363 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
365 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
366 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
369 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
370 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
377 static __checkReturn efx_rc_t
378 efx_mcdi_driver_event(
381 __in efx_qword_t data)
384 uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN,
385 MC_CMD_DRIVER_EVENT_OUT_LEN)];
388 req.emr_cmd = MC_CMD_DRIVER_EVENT;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
394 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
396 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
397 EFX_QWORD_FIELD(data, EFX_DWORD_0));
398 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
399 EFX_QWORD_FIELD(data, EFX_DWORD_1));
401 efx_mcdi_execute(enp, &req);
403 if (req.emr_rc != 0) {
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
421 efx_nic_t *enp = eep->ee_enp;
424 EFX_POPULATE_QWORD_3(event,
425 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
426 ESF_DZ_DRV_SUB_CODE, 0,
427 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
429 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
432 __checkReturn efx_rc_t
435 __in unsigned int us)
437 efx_nic_t *enp = eep->ee_enp;
438 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
440 uint32_t timer_val, mode;
443 if (us > encp->enc_evq_timer_max_us) {
448 /* If the value is zero then disable the timer */
451 mode = FFE_CZ_TIMER_MODE_DIS;
453 /* Calculate the timer value in quanta */
454 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
456 /* Moderation value is base 0 so we need to deduct 1 */
460 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
463 if (encp->enc_bug35388_workaround) {
464 EFX_POPULATE_DWORD_3(dword,
465 ERF_DD_EVQ_IND_TIMER_FLAGS,
466 EFE_DD_EVQ_IND_TIMER_FLAGS,
467 ERF_DD_EVQ_IND_TIMER_MODE, mode,
468 ERF_DD_EVQ_IND_TIMER_VAL, timer_val);
469 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
470 eep->ee_index, &dword, 0);
472 EFX_POPULATE_DWORD_2(dword,
473 ERF_DZ_TC_TIMER_MODE, mode,
474 ERF_DZ_TC_TIMER_VAL, timer_val);
475 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
476 eep->ee_index, &dword, 0);
482 EFSYS_PROBE1(fail1, efx_rc_t, rc);
490 ef10_ev_qstats_update(
492 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
496 for (id = 0; id < EV_NQSTATS; id++) {
497 efsys_stat_t *essp = &stat[id];
499 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
500 eep->ee_stat[id] = 0;
503 #endif /* EFSYS_OPT_QSTATS */
506 static __checkReturn boolean_t
509 __in efx_qword_t *eqp,
510 __in const efx_ev_callbacks_t *eecp,
513 efx_nic_t *enp = eep->ee_enp;
517 uint32_t eth_tag_class;
520 uint32_t next_read_lbits;
523 boolean_t should_abort;
524 efx_evq_rxq_state_t *eersp;
525 unsigned int desc_count;
526 unsigned int last_used_id;
528 EFX_EV_QSTAT_INCR(eep, EV_RX);
530 /* Discard events after RXQ/TXQ errors */
531 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
534 /* Basic packet information */
535 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
536 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
537 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
538 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
539 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
540 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
541 l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
542 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
544 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
545 /* Drop this event */
552 * This may be part of a scattered frame, or it may be a
553 * truncated frame if scatter is disabled on this RXQ.
554 * Overlength frames can be received if e.g. a VF is configured
555 * for 1500 MTU but connected to a port set to 9000 MTU
557 * FIXME: There is not yet any driver that supports scatter on
558 * Huntington. Scatter support is required for OSX.
560 flags |= EFX_PKT_CONT;
563 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
564 flags |= EFX_PKT_UNICAST;
566 /* Increment the count of descriptors read */
567 eersp = &eep->ee_rxq_state[label];
568 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
569 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
570 eersp->eers_rx_read_ptr += desc_count;
573 * FIXME: add error checking to make sure this a batched event.
574 * This could also be an aborted scatter, see Bug36629.
576 if (desc_count > 1) {
577 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
578 flags |= EFX_PKT_PREFIX_LEN;
581 /* Calculate the index of the last descriptor consumed */
582 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
584 /* Check for errors that invalidate checksum and L3/L4 fields */
585 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
586 /* RX frame truncated (error flag is misnamed) */
587 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
588 flags |= EFX_DISCARD;
591 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
592 /* Bad Ethernet frame CRC */
593 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
594 flags |= EFX_DISCARD;
597 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
599 * Hardware parse failed, due to malformed headers
600 * or headers that are too long for the parser.
601 * Headers and checksums must be validated by the host.
603 // TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
607 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
608 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
609 flags |= EFX_PKT_VLAN_TAGGED;
613 case ESE_DZ_L3_CLASS_IP4:
614 case ESE_DZ_L3_CLASS_IP4_FRAG:
615 flags |= EFX_PKT_IPV4;
616 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
617 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
619 flags |= EFX_CKSUM_IPV4;
622 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
623 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
624 flags |= EFX_PKT_TCP;
625 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
626 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
627 flags |= EFX_PKT_UDP;
629 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
633 case ESE_DZ_L3_CLASS_IP6:
634 case ESE_DZ_L3_CLASS_IP6_FRAG:
635 flags |= EFX_PKT_IPV6;
637 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
638 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
639 flags |= EFX_PKT_TCP;
640 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
641 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
642 flags |= EFX_PKT_UDP;
644 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
649 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
653 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
654 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
655 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
657 flags |= EFX_CKSUM_TCPUDP;
662 /* If we're not discarding the packet then it is ok */
663 if (~flags & EFX_DISCARD)
664 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
666 EFSYS_ASSERT(eecp->eec_rx != NULL);
667 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
669 return (should_abort);
672 static __checkReturn boolean_t
675 __in efx_qword_t *eqp,
676 __in const efx_ev_callbacks_t *eecp,
679 efx_nic_t *enp = eep->ee_enp;
682 boolean_t should_abort;
684 EFX_EV_QSTAT_INCR(eep, EV_TX);
686 /* Discard events after RXQ/TXQ errors */
687 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
690 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
691 /* Drop this event */
695 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
696 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
697 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
699 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
701 EFSYS_ASSERT(eecp->eec_tx != NULL);
702 should_abort = eecp->eec_tx(arg, label, id);
704 return (should_abort);
707 static __checkReturn boolean_t
710 __in efx_qword_t *eqp,
711 __in const efx_ev_callbacks_t *eecp,
715 boolean_t should_abort;
717 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
718 should_abort = B_FALSE;
720 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
722 case ESE_DZ_DRV_TIMER_EV: {
725 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
727 EFSYS_ASSERT(eecp->eec_timer != NULL);
728 should_abort = eecp->eec_timer(arg, id);
732 case ESE_DZ_DRV_WAKE_UP_EV: {
735 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
737 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
738 should_abort = eecp->eec_wake_up(arg, id);
742 case ESE_DZ_DRV_START_UP_EV:
743 EFSYS_ASSERT(eecp->eec_initialized != NULL);
744 should_abort = eecp->eec_initialized(arg);
748 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
749 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
750 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
754 return (should_abort);
757 static __checkReturn boolean_t
760 __in efx_qword_t *eqp,
761 __in const efx_ev_callbacks_t *eecp,
765 boolean_t should_abort;
767 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
768 should_abort = B_FALSE;
770 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
771 if (data >= ((uint32_t)1 << 16)) {
772 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
773 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
774 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
779 EFSYS_ASSERT(eecp->eec_software != NULL);
780 should_abort = eecp->eec_software(arg, (uint16_t)data);
782 return (should_abort);
785 static __checkReturn boolean_t
788 __in efx_qword_t *eqp,
789 __in const efx_ev_callbacks_t *eecp,
792 efx_nic_t *enp = eep->ee_enp;
794 boolean_t should_abort = B_FALSE;
796 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
798 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
800 case MCDI_EVENT_CODE_BADSSERT:
801 efx_mcdi_ev_death(enp, EINTR);
804 case MCDI_EVENT_CODE_CMDDONE:
806 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
807 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
808 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
811 #if EFSYS_OPT_MCDI_PROXY_AUTH
812 case MCDI_EVENT_CODE_PROXY_RESPONSE:
814 * This event notifies a function that an authorization request
815 * has been processed. If the request was authorized then the
816 * function can now re-send the original MCDI request.
817 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
819 efx_mcdi_ev_proxy_response(enp,
820 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
821 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
823 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
825 case MCDI_EVENT_CODE_LINKCHANGE: {
826 efx_link_mode_t link_mode;
828 ef10_phy_link_ev(enp, eqp, &link_mode);
829 should_abort = eecp->eec_link_change(arg, link_mode);
833 case MCDI_EVENT_CODE_SENSOREVT: {
834 #if EFSYS_OPT_MON_STATS
836 efx_mon_stat_value_t value;
839 /* Decode monitor stat for MCDI sensor (if supported) */
840 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
841 /* Report monitor stat change */
842 should_abort = eecp->eec_monitor(arg, id, value);
843 } else if (rc == ENOTSUP) {
844 should_abort = eecp->eec_exception(arg,
845 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
846 MCDI_EV_FIELD(eqp, DATA));
848 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
854 case MCDI_EVENT_CODE_SCHEDERR:
855 /* Informational only */
858 case MCDI_EVENT_CODE_REBOOT:
859 /* Falcon/Siena only (should not been seen with Huntington). */
860 efx_mcdi_ev_death(enp, EIO);
863 case MCDI_EVENT_CODE_MC_REBOOT:
864 /* MC_REBOOT event is used for Huntington (EF10) and later. */
865 efx_mcdi_ev_death(enp, EIO);
868 case MCDI_EVENT_CODE_MAC_STATS_DMA:
869 #if EFSYS_OPT_MAC_STATS
870 if (eecp->eec_mac_stats != NULL) {
871 eecp->eec_mac_stats(arg,
872 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
877 case MCDI_EVENT_CODE_FWALERT: {
878 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
880 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
881 should_abort = eecp->eec_exception(arg,
882 EFX_EXCEPTION_FWALERT_SRAM,
883 MCDI_EV_FIELD(eqp, FWALERT_DATA));
885 should_abort = eecp->eec_exception(arg,
886 EFX_EXCEPTION_UNKNOWN_FWALERT,
887 MCDI_EV_FIELD(eqp, DATA));
891 case MCDI_EVENT_CODE_TX_ERR: {
893 * After a TXQ error is detected, firmware sends a TX_ERR event.
894 * This may be followed by TX completions (which we discard),
895 * and then finally by a TX_FLUSH event. Firmware destroys the
896 * TXQ automatically after sending the TX_FLUSH event.
898 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
900 EFSYS_PROBE2(tx_descq_err,
901 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
902 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
904 /* Inform the driver that a reset is required. */
905 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
906 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
910 case MCDI_EVENT_CODE_TX_FLUSH: {
911 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
914 * EF10 firmware sends two TX_FLUSH events: one to the txq's
915 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
916 * We want to wait for all completions, so ignore the events
917 * with TX_FLUSH_TO_DRIVER.
919 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
920 should_abort = B_FALSE;
924 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
926 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
928 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
929 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
933 case MCDI_EVENT_CODE_RX_ERR: {
935 * After an RXQ error is detected, firmware sends an RX_ERR
936 * event. This may be followed by RX events (which we discard),
937 * and then finally by an RX_FLUSH event. Firmware destroys the
938 * RXQ automatically after sending the RX_FLUSH event.
940 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
942 EFSYS_PROBE2(rx_descq_err,
943 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
944 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
946 /* Inform the driver that a reset is required. */
947 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
948 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
952 case MCDI_EVENT_CODE_RX_FLUSH: {
953 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
956 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
957 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
958 * We want to wait for all completions, so ignore the events
959 * with RX_FLUSH_TO_DRIVER.
961 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
962 should_abort = B_FALSE;
966 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
968 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
970 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
971 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
976 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
977 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
978 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
982 return (should_abort);
986 ef10_ev_rxlabel_init(
989 __in unsigned int label)
991 efx_evq_rxq_state_t *eersp;
993 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
994 eersp = &eep->ee_rxq_state[label];
996 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
998 eersp->eers_rx_read_ptr = 0;
999 eersp->eers_rx_mask = erp->er_mask;
1003 ef10_ev_rxlabel_fini(
1004 __in efx_evq_t *eep,
1005 __in unsigned int label)
1007 efx_evq_rxq_state_t *eersp;
1009 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1010 eersp = &eep->ee_rxq_state[label];
1012 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1014 eersp->eers_rx_read_ptr = 0;
1015 eersp->eers_rx_mask = 0;
1018 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */