2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_EF10_IMPL_H
34 #define _SYS_EF10_IMPL_H
41 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
42 #define EF10_MAX_PIOBUF_NBUFS (16)
44 #if EFSYS_OPT_HUNTINGTON
45 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
46 # error "EF10_MAX_PIOBUF_NBUFS too small"
48 #endif /* EFSYS_OPT_HUNTINGTON */
50 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
51 # error "EF10_MAX_PIOBUF_NBUFS too small"
53 #endif /* EFSYS_OPT_MEDFORD */
54 #if EFSYS_OPT_MEDFORD2
55 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
56 # error "EF10_MAX_PIOBUF_NBUFS too small"
58 #endif /* EFSYS_OPT_MEDFORD2 */
63 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
64 * possibly be increased, or the write size reported by newer firmware used
67 #define EF10_NVRAM_CHUNK 0x80
70 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
71 * to an 8 descriptor boundary.
73 #define EF10_RX_WPTR_ALIGN 8
76 * Max byte offset into the packet the TCP header must start for the hardware
77 * to be able to parse the packet correctly.
79 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
81 /* Invalid RSS context handle */
82 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
87 __checkReturn efx_rc_t
95 __checkReturn efx_rc_t
98 __in unsigned int index,
99 __in efsys_mem_t *esmp,
104 __in efx_evq_t *eep);
108 __in efx_evq_t *eep);
110 __checkReturn efx_rc_t
113 __in unsigned int count);
120 __checkReturn efx_rc_t
123 __in unsigned int us);
127 ef10_ev_qstats_update(
129 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
130 #endif /* EFSYS_OPT_QSTATS */
133 ef10_ev_rxlabel_init(
136 __in unsigned int label,
137 __in efx_rxq_type_t type);
140 ef10_ev_rxlabel_fini(
142 __in unsigned int label);
146 __checkReturn efx_rc_t
149 __in efx_intr_type_t type,
150 __in efsys_mem_t *esmp);
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
161 ef10_intr_disable_unlocked(
162 __in efx_nic_t *enp);
164 __checkReturn efx_rc_t
167 __in unsigned int level);
170 ef10_intr_status_line(
172 __out boolean_t *fatalp,
173 __out uint32_t *qmaskp);
176 ef10_intr_status_message(
178 __in unsigned int message,
179 __out boolean_t *fatalp);
183 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 extern __checkReturn efx_rc_t
192 __in efx_nic_t *enp);
194 extern __checkReturn efx_rc_t
195 ef10_nic_set_drv_limits(
196 __inout efx_nic_t *enp,
197 __in efx_drv_limits_t *edlp);
199 extern __checkReturn efx_rc_t
200 ef10_nic_get_vi_pool(
202 __out uint32_t *vi_countp);
204 extern __checkReturn efx_rc_t
205 ef10_nic_get_bar_region(
207 __in efx_nic_region_t region,
208 __out uint32_t *offsetp,
209 __out size_t *sizep);
211 extern __checkReturn efx_rc_t
213 __in efx_nic_t *enp);
215 extern __checkReturn efx_rc_t
217 __in efx_nic_t *enp);
219 extern __checkReturn boolean_t
220 ef10_nic_hw_unavailable(
221 __in efx_nic_t *enp);
224 ef10_nic_set_hw_unavailable(
225 __in efx_nic_t *enp);
229 extern __checkReturn efx_rc_t
230 ef10_nic_register_test(
231 __in efx_nic_t *enp);
233 #endif /* EFSYS_OPT_DIAG */
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
246 extern __checkReturn efx_rc_t
249 __out efx_link_mode_t *link_modep);
251 extern __checkReturn efx_rc_t
254 __out boolean_t *mac_upp);
256 extern __checkReturn efx_rc_t
258 __in efx_nic_t *enp);
260 extern __checkReturn efx_rc_t
262 __in efx_nic_t *enp);
264 extern __checkReturn efx_rc_t
269 extern __checkReturn efx_rc_t
270 ef10_mac_reconfigure(
271 __in efx_nic_t *enp);
273 extern __checkReturn efx_rc_t
274 ef10_mac_multicast_list_set(
275 __in efx_nic_t *enp);
277 extern __checkReturn efx_rc_t
278 ef10_mac_filter_default_rxq_set(
281 __in boolean_t using_rss);
284 ef10_mac_filter_default_rxq_clear(
285 __in efx_nic_t *enp);
287 #if EFSYS_OPT_LOOPBACK
289 extern __checkReturn efx_rc_t
290 ef10_mac_loopback_set(
292 __in efx_link_mode_t link_mode,
293 __in efx_loopback_type_t loopback_type);
295 #endif /* EFSYS_OPT_LOOPBACK */
297 #if EFSYS_OPT_MAC_STATS
299 extern __checkReturn efx_rc_t
300 ef10_mac_stats_get_mask(
302 __inout_bcount(mask_size) uint32_t *maskp,
303 __in size_t mask_size);
305 extern __checkReturn efx_rc_t
306 ef10_mac_stats_update(
308 __in efsys_mem_t *esmp,
309 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
310 __inout_opt uint32_t *generationp);
312 #endif /* EFSYS_OPT_MAC_STATS */
319 extern __checkReturn efx_rc_t
322 __in const efx_mcdi_transport_t *mtp);
326 __in efx_nic_t *enp);
329 ef10_mcdi_send_request(
331 __in_bcount(hdr_len) void *hdrp,
333 __in_bcount(sdu_len) void *sdup,
334 __in size_t sdu_len);
336 extern __checkReturn boolean_t
337 ef10_mcdi_poll_response(
338 __in efx_nic_t *enp);
341 ef10_mcdi_read_response(
343 __out_bcount(length) void *bufferp,
348 ef10_mcdi_poll_reboot(
349 __in efx_nic_t *enp);
351 extern __checkReturn efx_rc_t
352 ef10_mcdi_feature_supported(
354 __in efx_mcdi_feature_id_t id,
355 __out boolean_t *supportedp);
358 ef10_mcdi_get_timeout(
360 __in efx_mcdi_req_t *emrp,
361 __out uint32_t *timeoutp);
363 #endif /* EFSYS_OPT_MCDI */
367 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
369 extern __checkReturn efx_rc_t
370 ef10_nvram_buf_read_tlv(
372 __in_bcount(max_seg_size) caddr_t seg_data,
373 __in size_t max_seg_size,
375 __deref_out_bcount_opt(*sizep) caddr_t *datap,
376 __out size_t *sizep);
378 extern __checkReturn efx_rc_t
379 ef10_nvram_buf_write_tlv(
380 __inout_bcount(partn_size) caddr_t partn_data,
381 __in size_t partn_size,
383 __in_bcount(tag_size) caddr_t tag_data,
384 __in size_t tag_size,
385 __out size_t *total_lengthp);
387 extern __checkReturn efx_rc_t
388 ef10_nvram_partn_read_tlv(
392 __deref_out_bcount_opt(*sizep) caddr_t *datap,
393 __out size_t *sizep);
395 extern __checkReturn efx_rc_t
396 ef10_nvram_partn_write_tlv(
400 __in_bcount(size) caddr_t data,
403 extern __checkReturn efx_rc_t
404 ef10_nvram_partn_write_segment_tlv(
408 __in_bcount(size) caddr_t data,
410 __in boolean_t all_segments);
412 extern __checkReturn efx_rc_t
413 ef10_nvram_partn_lock(
415 __in uint32_t partn);
417 extern __checkReturn efx_rc_t
418 ef10_nvram_partn_unlock(
421 __out_opt uint32_t *resultp);
423 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
429 extern __checkReturn efx_rc_t
431 __in efx_nic_t *enp);
433 #endif /* EFSYS_OPT_DIAG */
435 extern __checkReturn efx_rc_t
436 ef10_nvram_type_to_partn(
438 __in efx_nvram_type_t type,
439 __out uint32_t *partnp);
441 extern __checkReturn efx_rc_t
442 ef10_nvram_partn_size(
445 __out size_t *sizep);
447 extern __checkReturn efx_rc_t
448 ef10_nvram_partn_rw_start(
451 __out size_t *chunk_sizep);
453 extern __checkReturn efx_rc_t
454 ef10_nvram_partn_read_mode(
457 __in unsigned int offset,
458 __out_bcount(size) caddr_t data,
462 extern __checkReturn efx_rc_t
463 ef10_nvram_partn_read(
466 __in unsigned int offset,
467 __in_bcount(size) caddr_t data,
470 extern __checkReturn efx_rc_t
471 ef10_nvram_partn_read_backup(
474 __in unsigned int offset,
475 __out_bcount(size) caddr_t data,
478 extern __checkReturn efx_rc_t
479 ef10_nvram_partn_erase(
482 __in unsigned int offset,
485 extern __checkReturn efx_rc_t
486 ef10_nvram_partn_write(
489 __in unsigned int offset,
490 __out_bcount(size) caddr_t data,
493 extern __checkReturn efx_rc_t
494 ef10_nvram_partn_rw_finish(
497 __out_opt uint32_t *verify_resultp);
499 extern __checkReturn efx_rc_t
500 ef10_nvram_partn_get_version(
503 __out uint32_t *subtypep,
504 __out_ecount(4) uint16_t version[4]);
506 extern __checkReturn efx_rc_t
507 ef10_nvram_partn_set_version(
510 __in_ecount(4) uint16_t version[4]);
512 extern __checkReturn efx_rc_t
513 ef10_nvram_buffer_validate(
515 __in_bcount(buffer_size)
517 __in size_t buffer_size);
520 ef10_nvram_buffer_init(
521 __out_bcount(buffer_size)
523 __in size_t buffer_size);
525 extern __checkReturn efx_rc_t
526 ef10_nvram_buffer_create(
527 __in uint32_t partn_type,
528 __out_bcount(buffer_size)
530 __in size_t buffer_size);
532 extern __checkReturn efx_rc_t
533 ef10_nvram_buffer_find_item_start(
534 __in_bcount(buffer_size)
536 __in size_t buffer_size,
537 __out uint32_t *startp);
539 extern __checkReturn efx_rc_t
540 ef10_nvram_buffer_find_end(
541 __in_bcount(buffer_size)
543 __in size_t buffer_size,
544 __in uint32_t offset,
545 __out uint32_t *endp);
547 extern __checkReturn __success(return != B_FALSE) boolean_t
548 ef10_nvram_buffer_find_item(
549 __in_bcount(buffer_size)
551 __in size_t buffer_size,
552 __in uint32_t offset,
553 __out uint32_t *startp,
554 __out uint32_t *lengthp);
556 extern __checkReturn efx_rc_t
557 ef10_nvram_buffer_peek_item(
558 __in_bcount(buffer_size)
560 __in size_t buffer_size,
561 __in uint32_t offset,
562 __out uint32_t *tagp,
563 __out uint32_t *lengthp,
564 __out uint32_t *value_offsetp);
566 extern __checkReturn efx_rc_t
567 ef10_nvram_buffer_get_item(
568 __in_bcount(buffer_size)
570 __in size_t buffer_size,
571 __in uint32_t offset,
572 __in uint32_t length,
573 __out uint32_t *tagp,
574 __out_bcount_part(value_max_size, *lengthp)
576 __in size_t value_max_size,
577 __out uint32_t *lengthp);
579 extern __checkReturn efx_rc_t
580 ef10_nvram_buffer_insert_item(
581 __in_bcount(buffer_size)
583 __in size_t buffer_size,
584 __in uint32_t offset,
586 __in_bcount(length) caddr_t valuep,
587 __in uint32_t length,
588 __out uint32_t *lengthp);
590 extern __checkReturn efx_rc_t
591 ef10_nvram_buffer_modify_item(
592 __in_bcount(buffer_size)
594 __in size_t buffer_size,
595 __in uint32_t offset,
597 __in_bcount(length) caddr_t valuep,
598 __in uint32_t length,
599 __out uint32_t *lengthp);
601 extern __checkReturn efx_rc_t
602 ef10_nvram_buffer_delete_item(
603 __in_bcount(buffer_size)
605 __in size_t buffer_size,
606 __in uint32_t offset,
607 __in uint32_t length,
610 extern __checkReturn efx_rc_t
611 ef10_nvram_buffer_finish(
612 __in_bcount(buffer_size)
614 __in size_t buffer_size);
616 #endif /* EFSYS_OPT_NVRAM */
621 typedef struct ef10_link_state_s {
622 uint32_t els_adv_cap_mask;
623 uint32_t els_lp_cap_mask;
624 unsigned int els_fcntl;
625 efx_link_mode_t els_link_mode;
626 #if EFSYS_OPT_LOOPBACK
627 efx_loopback_type_t els_loopback;
629 boolean_t els_mac_up;
635 __in efx_qword_t *eqp,
636 __out efx_link_mode_t *link_modep);
638 extern __checkReturn efx_rc_t
641 __out ef10_link_state_t *elsp);
643 extern __checkReturn efx_rc_t
648 extern __checkReturn efx_rc_t
649 ef10_phy_reconfigure(
650 __in efx_nic_t *enp);
652 extern __checkReturn efx_rc_t
654 __in efx_nic_t *enp);
656 extern __checkReturn efx_rc_t
659 __out uint32_t *ouip);
661 #if EFSYS_OPT_PHY_STATS
663 extern __checkReturn efx_rc_t
664 ef10_phy_stats_update(
666 __in efsys_mem_t *esmp,
667 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
669 #endif /* EFSYS_OPT_PHY_STATS */
673 extern __checkReturn efx_rc_t
674 ef10_bist_enable_offline(
675 __in efx_nic_t *enp);
677 extern __checkReturn efx_rc_t
680 __in efx_bist_type_t type);
682 extern __checkReturn efx_rc_t
685 __in efx_bist_type_t type,
686 __out efx_bist_result_t *resultp,
687 __out_opt __drv_when(count > 0, __notnull)
688 uint32_t *value_maskp,
689 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
690 unsigned long *valuesp,
696 __in efx_bist_type_t type);
698 #endif /* EFSYS_OPT_BIST */
702 extern __checkReturn efx_rc_t
704 __in efx_nic_t *enp);
708 __in efx_nic_t *enp);
710 extern __checkReturn efx_rc_t
713 __in unsigned int index,
714 __in unsigned int label,
715 __in efsys_mem_t *esmp,
721 __out unsigned int *addedp);
725 __in efx_txq_t *etp);
727 extern __checkReturn efx_rc_t
730 __in_ecount(ndescs) efx_buffer_t *ebp,
731 __in unsigned int ndescs,
732 __in unsigned int completed,
733 __inout unsigned int *addedp);
738 __in unsigned int added,
739 __in unsigned int pushed);
741 #if EFSYS_OPT_RX_PACKED_STREAM
743 ef10_rx_qpush_ps_credits(
744 __in efx_rxq_t *erp);
746 extern __checkReturn uint8_t *
747 ef10_rx_qps_packet_info(
749 __in uint8_t *buffer,
750 __in uint32_t buffer_length,
751 __in uint32_t current_offset,
752 __out uint16_t *lengthp,
753 __out uint32_t *next_offsetp,
754 __out uint32_t *timestamp);
757 extern __checkReturn efx_rc_t
760 __in unsigned int ns);
762 extern __checkReturn efx_rc_t
764 __in efx_txq_t *etp);
768 __in efx_txq_t *etp);
770 extern __checkReturn efx_rc_t
772 __in efx_txq_t *etp);
775 ef10_tx_qpio_disable(
776 __in efx_txq_t *etp);
778 extern __checkReturn efx_rc_t
781 __in_ecount(buf_length) uint8_t *buffer,
782 __in size_t buf_length,
783 __in size_t pio_buf_offset);
785 extern __checkReturn efx_rc_t
788 __in size_t pkt_length,
789 __in unsigned int completed,
790 __inout unsigned int *addedp);
792 extern __checkReturn efx_rc_t
795 __in_ecount(n) efx_desc_t *ed,
797 __in unsigned int completed,
798 __inout unsigned int *addedp);
801 ef10_tx_qdesc_dma_create(
803 __in efsys_dma_addr_t addr,
806 __out efx_desc_t *edp);
809 ef10_tx_qdesc_tso_create(
811 __in uint16_t ipv4_id,
812 __in uint32_t tcp_seq,
813 __in uint8_t tcp_flags,
814 __out efx_desc_t *edp);
817 ef10_tx_qdesc_tso2_create(
819 __in uint16_t ipv4_id,
820 __in uint16_t outer_ipv4_id,
821 __in uint32_t tcp_seq,
822 __in uint16_t tcp_mss,
823 __out_ecount(count) efx_desc_t *edp,
827 ef10_tx_qdesc_vlantci_create(
829 __in uint16_t vlan_tci,
830 __out efx_desc_t *edp);
833 ef10_tx_qdesc_checksum_create(
836 __out efx_desc_t *edp);
841 ef10_tx_qstats_update(
843 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
845 #endif /* EFSYS_OPT_QSTATS */
847 typedef uint32_t efx_piobuf_handle_t;
849 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
851 extern __checkReturn efx_rc_t
853 __inout efx_nic_t *enp,
854 __out uint32_t *bufnump,
855 __out efx_piobuf_handle_t *handlep,
856 __out uint32_t *blknump,
857 __out uint32_t *offsetp,
858 __out size_t *sizep);
860 extern __checkReturn efx_rc_t
862 __inout efx_nic_t *enp,
863 __in uint32_t bufnum,
864 __in uint32_t blknum);
866 extern __checkReturn efx_rc_t
868 __inout efx_nic_t *enp,
869 __in uint32_t vi_index,
870 __in efx_piobuf_handle_t handle);
872 extern __checkReturn efx_rc_t
874 __inout efx_nic_t *enp,
875 __in uint32_t vi_index);
882 extern __checkReturn efx_rc_t
884 __in efx_nic_t *enp);
886 extern __checkReturn efx_rc_t
889 __out size_t *sizep);
891 extern __checkReturn efx_rc_t
894 __out_bcount(size) caddr_t data,
897 extern __checkReturn efx_rc_t
900 __in_bcount(size) caddr_t data,
903 extern __checkReturn efx_rc_t
906 __in_bcount(size) caddr_t data,
909 extern __checkReturn efx_rc_t
912 __in_bcount(size) caddr_t data,
914 __inout efx_vpd_value_t *evvp);
916 extern __checkReturn efx_rc_t
919 __in_bcount(size) caddr_t data,
921 __in efx_vpd_value_t *evvp);
923 extern __checkReturn efx_rc_t
926 __in_bcount(size) caddr_t data,
928 __out efx_vpd_value_t *evvp,
929 __inout unsigned int *contp);
931 extern __checkReturn efx_rc_t
934 __in_bcount(size) caddr_t data,
939 __in efx_nic_t *enp);
941 #endif /* EFSYS_OPT_VPD */
946 extern __checkReturn efx_rc_t
948 __in efx_nic_t *enp);
950 #if EFSYS_OPT_RX_SCATTER
951 extern __checkReturn efx_rc_t
952 ef10_rx_scatter_enable(
954 __in unsigned int buf_size);
955 #endif /* EFSYS_OPT_RX_SCATTER */
958 #if EFSYS_OPT_RX_SCALE
960 extern __checkReturn efx_rc_t
961 ef10_rx_scale_context_alloc(
963 __in efx_rx_scale_context_type_t type,
964 __in uint32_t num_queues,
965 __out uint32_t *rss_contextp);
967 extern __checkReturn efx_rc_t
968 ef10_rx_scale_context_free(
970 __in uint32_t rss_context);
972 extern __checkReturn efx_rc_t
973 ef10_rx_scale_mode_set(
975 __in uint32_t rss_context,
976 __in efx_rx_hash_alg_t alg,
977 __in efx_rx_hash_type_t type,
978 __in boolean_t insert);
980 extern __checkReturn efx_rc_t
981 ef10_rx_scale_key_set(
983 __in uint32_t rss_context,
984 __in_ecount(n) uint8_t *key,
987 extern __checkReturn efx_rc_t
988 ef10_rx_scale_tbl_set(
990 __in uint32_t rss_context,
991 __in_ecount(n) unsigned int *table,
994 extern __checkReturn uint32_t
997 __in efx_rx_hash_alg_t func,
998 __in uint8_t *buffer);
1000 #endif /* EFSYS_OPT_RX_SCALE */
1002 extern __checkReturn efx_rc_t
1003 ef10_rx_prefix_pktlen(
1004 __in efx_nic_t *enp,
1005 __in uint8_t *buffer,
1006 __out uint16_t *lengthp);
1010 __in efx_rxq_t *erp,
1011 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1013 __in unsigned int ndescs,
1014 __in unsigned int completed,
1015 __in unsigned int added);
1019 __in efx_rxq_t *erp,
1020 __in unsigned int added,
1021 __inout unsigned int *pushedp);
1023 extern __checkReturn efx_rc_t
1025 __in efx_rxq_t *erp);
1029 __in efx_rxq_t *erp);
1031 union efx_rxq_type_data_u;
1033 extern __checkReturn efx_rc_t
1035 __in efx_nic_t *enp,
1036 __in unsigned int index,
1037 __in unsigned int label,
1038 __in efx_rxq_type_t type,
1039 __in const union efx_rxq_type_data_u *type_data,
1040 __in efsys_mem_t *esmp,
1043 __in unsigned int flags,
1044 __in efx_evq_t *eep,
1045 __in efx_rxq_t *erp);
1049 __in efx_rxq_t *erp);
1053 __in efx_nic_t *enp);
1055 #if EFSYS_OPT_FILTER
1057 typedef struct ef10_filter_handle_s {
1060 } ef10_filter_handle_t;
1062 typedef struct ef10_filter_entry_s {
1063 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1064 ef10_filter_handle_t efe_handle;
1065 } ef10_filter_entry_t;
1068 * BUSY flag indicates that an update is in progress.
1069 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1071 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1072 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1073 #define EFX_EF10_FILTER_FLAGS 3U
1076 * Size of the hash table used by the driver. Doesn't need to be the
1077 * same size as the hardware's table.
1079 #define EFX_EF10_FILTER_TBL_ROWS 8192
1081 /* Only need to allow for one directed and one unknown unicast filter */
1082 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1084 /* Allow for the broadcast address to be added to the multicast list */
1085 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1088 * For encapsulated packets, there is one filter each for each combination of
1089 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1090 * multicast inner frames.
1092 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1094 typedef struct ef10_filter_table_s {
1095 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1096 efx_rxq_t *eft_default_rxq;
1097 boolean_t eft_using_rss;
1098 uint32_t eft_unicst_filter_indexes[
1099 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1100 uint32_t eft_unicst_filter_count;
1101 uint32_t eft_mulcst_filter_indexes[
1102 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1103 uint32_t eft_mulcst_filter_count;
1104 boolean_t eft_using_all_mulcst;
1105 uint32_t eft_encap_filter_indexes[
1106 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1107 uint32_t eft_encap_filter_count;
1108 } ef10_filter_table_t;
1110 __checkReturn efx_rc_t
1112 __in efx_nic_t *enp);
1116 __in efx_nic_t *enp);
1118 __checkReturn efx_rc_t
1119 ef10_filter_restore(
1120 __in efx_nic_t *enp);
1122 __checkReturn efx_rc_t
1124 __in efx_nic_t *enp,
1125 __inout efx_filter_spec_t *spec,
1126 __in boolean_t may_replace);
1128 __checkReturn efx_rc_t
1130 __in efx_nic_t *enp,
1131 __inout efx_filter_spec_t *spec);
1133 extern __checkReturn efx_rc_t
1134 ef10_filter_supported_filters(
1135 __in efx_nic_t *enp,
1136 __out_ecount(buffer_length) uint32_t *buffer,
1137 __in size_t buffer_length,
1138 __out size_t *list_lengthp);
1140 extern __checkReturn efx_rc_t
1141 ef10_filter_reconfigure(
1142 __in efx_nic_t *enp,
1143 __in_ecount(6) uint8_t const *mac_addr,
1144 __in boolean_t all_unicst,
1145 __in boolean_t mulcst,
1146 __in boolean_t all_mulcst,
1147 __in boolean_t brdcst,
1148 __in_ecount(6*count) uint8_t const *addrs,
1149 __in uint32_t count);
1152 ef10_filter_get_default_rxq(
1153 __in efx_nic_t *enp,
1154 __out efx_rxq_t **erpp,
1155 __out boolean_t *using_rss);
1158 ef10_filter_default_rxq_set(
1159 __in efx_nic_t *enp,
1160 __in efx_rxq_t *erp,
1161 __in boolean_t using_rss);
1164 ef10_filter_default_rxq_clear(
1165 __in efx_nic_t *enp);
1168 #endif /* EFSYS_OPT_FILTER */
1170 extern __checkReturn efx_rc_t
1171 efx_mcdi_get_function_info(
1172 __in efx_nic_t *enp,
1173 __out uint32_t *pfp,
1174 __out_opt uint32_t *vfp);
1176 extern __checkReturn efx_rc_t
1177 efx_mcdi_privilege_mask(
1178 __in efx_nic_t *enp,
1181 __out uint32_t *maskp);
1183 extern __checkReturn efx_rc_t
1184 efx_mcdi_get_port_assignment(
1185 __in efx_nic_t *enp,
1186 __out uint32_t *portp);
1188 extern __checkReturn efx_rc_t
1189 efx_mcdi_get_port_modes(
1190 __in efx_nic_t *enp,
1191 __out uint32_t *modesp,
1192 __out_opt uint32_t *current_modep,
1193 __out_opt uint32_t *default_modep);
1195 extern __checkReturn efx_rc_t
1196 ef10_nic_get_port_mode_bandwidth(
1197 __in uint32_t port_mode,
1198 __out uint32_t *bandwidth_mbpsp);
1200 extern __checkReturn efx_rc_t
1201 efx_mcdi_get_mac_address_pf(
1202 __in efx_nic_t *enp,
1203 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1205 extern __checkReturn efx_rc_t
1206 efx_mcdi_get_mac_address_vf(
1207 __in efx_nic_t *enp,
1208 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1210 extern __checkReturn efx_rc_t
1212 __in efx_nic_t *enp,
1213 __out uint32_t *sys_freqp,
1214 __out uint32_t *dpcpu_freqp);
1217 extern __checkReturn efx_rc_t
1218 efx_mcdi_get_rxdp_config(
1219 __in efx_nic_t *enp,
1220 __out uint32_t *end_paddingp);
1222 extern __checkReturn efx_rc_t
1223 efx_mcdi_get_vector_cfg(
1224 __in efx_nic_t *enp,
1225 __out_opt uint32_t *vec_basep,
1226 __out_opt uint32_t *pf_nvecp,
1227 __out_opt uint32_t *vf_nvecp);
1229 extern __checkReturn efx_rc_t
1230 ef10_get_privilege_mask(
1231 __in efx_nic_t *enp,
1232 __out uint32_t *maskp);
1234 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1236 extern __checkReturn efx_rc_t
1237 efx_mcdi_get_nic_global(
1238 __in efx_nic_t *enp,
1240 __out uint32_t *valuep);
1242 extern __checkReturn efx_rc_t
1243 efx_mcdi_set_nic_global(
1244 __in efx_nic_t *enp,
1246 __in uint32_t value);
1248 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1251 #if EFSYS_OPT_RX_PACKED_STREAM
1253 /* Data space per credit in packed stream mode */
1254 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1257 * Received packets are always aligned at this boundary. Also there always
1258 * exists a gap of this size between packets.
1259 * (see SF-112241-TC, 4.5)
1261 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1264 * Size of a pseudo-header prepended to received packets
1265 * in packed stream mode
1267 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1269 /* Minimum space for packet in packed stream mode */
1270 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1271 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1273 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1274 EFX_RX_PACKED_STREAM_ALIGNMENT)
1276 /* Maximum number of credits */
1277 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1279 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1281 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1284 * Maximum DMA length and buffer stride alignment.
1285 * (see SF-119419-TC, 3.2)
1287 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1295 #endif /* _SYS_EF10_IMPL_H */