2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_EF10_IMPL_H
34 #define _SYS_EF10_IMPL_H
41 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
42 #define EF10_MAX_PIOBUF_NBUFS (16)
44 #if EFSYS_OPT_HUNTINGTON
45 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
46 # error "EF10_MAX_PIOBUF_NBUFS too small"
48 #endif /* EFSYS_OPT_HUNTINGTON */
50 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
51 # error "EF10_MAX_PIOBUF_NBUFS too small"
53 #endif /* EFSYS_OPT_MEDFORD */
54 #if EFSYS_OPT_MEDFORD2
55 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
56 # error "EF10_MAX_PIOBUF_NBUFS too small"
58 #endif /* EFSYS_OPT_MEDFORD2 */
63 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
64 * possibly be increased, or the write size reported by newer firmware used
67 #define EF10_NVRAM_CHUNK 0x80
70 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
71 * to an 8 descriptor boundary.
73 #define EF10_RX_WPTR_ALIGN 8
76 * Max byte offset into the packet the TCP header must start for the hardware
77 * to be able to parse the packet correctly.
79 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
81 /* Invalid RSS context handle */
82 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
87 __checkReturn efx_rc_t
95 __checkReturn efx_rc_t
98 __in unsigned int index,
99 __in efsys_mem_t *esmp,
104 __in efx_evq_t *eep);
108 __in efx_evq_t *eep);
110 __checkReturn efx_rc_t
113 __in unsigned int count);
120 __checkReturn efx_rc_t
123 __in unsigned int us);
127 ef10_ev_qstats_update(
129 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
130 #endif /* EFSYS_OPT_QSTATS */
133 ef10_ev_rxlabel_init(
136 __in unsigned int label,
137 __in efx_rxq_type_t type);
140 ef10_ev_rxlabel_fini(
142 __in unsigned int label);
146 __checkReturn efx_rc_t
149 __in efx_intr_type_t type,
150 __in efsys_mem_t *esmp);
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
161 ef10_intr_disable_unlocked(
162 __in efx_nic_t *enp);
164 __checkReturn efx_rc_t
167 __in unsigned int level);
170 ef10_intr_status_line(
172 __out boolean_t *fatalp,
173 __out uint32_t *qmaskp);
176 ef10_intr_status_message(
178 __in unsigned int message,
179 __out boolean_t *fatalp);
183 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 extern __checkReturn efx_rc_t
192 __in efx_nic_t *enp);
194 extern __checkReturn efx_rc_t
195 ef10_nic_set_drv_limits(
196 __inout efx_nic_t *enp,
197 __in efx_drv_limits_t *edlp);
199 extern __checkReturn efx_rc_t
200 ef10_nic_get_vi_pool(
202 __out uint32_t *vi_countp);
204 extern __checkReturn efx_rc_t
205 ef10_nic_get_bar_region(
207 __in efx_nic_region_t region,
208 __out uint32_t *offsetp,
209 __out size_t *sizep);
211 extern __checkReturn efx_rc_t
213 __in efx_nic_t *enp);
215 extern __checkReturn efx_rc_t
217 __in efx_nic_t *enp);
221 extern __checkReturn efx_rc_t
222 ef10_nic_register_test(
223 __in efx_nic_t *enp);
225 #endif /* EFSYS_OPT_DIAG */
229 __in efx_nic_t *enp);
233 __in efx_nic_t *enp);
238 extern __checkReturn efx_rc_t
241 __out efx_link_mode_t *link_modep);
243 extern __checkReturn efx_rc_t
246 __out boolean_t *mac_upp);
248 extern __checkReturn efx_rc_t
250 __in efx_nic_t *enp);
252 extern __checkReturn efx_rc_t
254 __in efx_nic_t *enp);
256 extern __checkReturn efx_rc_t
261 extern __checkReturn efx_rc_t
262 ef10_mac_reconfigure(
263 __in efx_nic_t *enp);
265 extern __checkReturn efx_rc_t
266 ef10_mac_multicast_list_set(
267 __in efx_nic_t *enp);
269 extern __checkReturn efx_rc_t
270 ef10_mac_filter_default_rxq_set(
273 __in boolean_t using_rss);
276 ef10_mac_filter_default_rxq_clear(
277 __in efx_nic_t *enp);
279 #if EFSYS_OPT_LOOPBACK
281 extern __checkReturn efx_rc_t
282 ef10_mac_loopback_set(
284 __in efx_link_mode_t link_mode,
285 __in efx_loopback_type_t loopback_type);
287 #endif /* EFSYS_OPT_LOOPBACK */
289 #if EFSYS_OPT_MAC_STATS
291 extern __checkReturn efx_rc_t
292 ef10_mac_stats_get_mask(
294 __inout_bcount(mask_size) uint32_t *maskp,
295 __in size_t mask_size);
297 extern __checkReturn efx_rc_t
298 ef10_mac_stats_update(
300 __in efsys_mem_t *esmp,
301 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
302 __inout_opt uint32_t *generationp);
304 #endif /* EFSYS_OPT_MAC_STATS */
311 extern __checkReturn efx_rc_t
314 __in const efx_mcdi_transport_t *mtp);
318 __in efx_nic_t *enp);
321 ef10_mcdi_send_request(
323 __in_bcount(hdr_len) void *hdrp,
325 __in_bcount(sdu_len) void *sdup,
326 __in size_t sdu_len);
328 extern __checkReturn boolean_t
329 ef10_mcdi_poll_response(
330 __in efx_nic_t *enp);
333 ef10_mcdi_read_response(
335 __out_bcount(length) void *bufferp,
340 ef10_mcdi_poll_reboot(
341 __in efx_nic_t *enp);
343 extern __checkReturn efx_rc_t
344 ef10_mcdi_feature_supported(
346 __in efx_mcdi_feature_id_t id,
347 __out boolean_t *supportedp);
350 ef10_mcdi_get_timeout(
352 __in efx_mcdi_req_t *emrp,
353 __out uint32_t *timeoutp);
355 #endif /* EFSYS_OPT_MCDI */
359 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
361 extern __checkReturn efx_rc_t
362 ef10_nvram_buf_read_tlv(
364 __in_bcount(max_seg_size) caddr_t seg_data,
365 __in size_t max_seg_size,
367 __deref_out_bcount_opt(*sizep) caddr_t *datap,
368 __out size_t *sizep);
370 extern __checkReturn efx_rc_t
371 ef10_nvram_buf_write_tlv(
372 __inout_bcount(partn_size) caddr_t partn_data,
373 __in size_t partn_size,
375 __in_bcount(tag_size) caddr_t tag_data,
376 __in size_t tag_size,
377 __out size_t *total_lengthp);
379 extern __checkReturn efx_rc_t
380 ef10_nvram_partn_read_tlv(
384 __deref_out_bcount_opt(*sizep) caddr_t *datap,
385 __out size_t *sizep);
387 extern __checkReturn efx_rc_t
388 ef10_nvram_partn_write_tlv(
392 __in_bcount(size) caddr_t data,
395 extern __checkReturn efx_rc_t
396 ef10_nvram_partn_write_segment_tlv(
400 __in_bcount(size) caddr_t data,
402 __in boolean_t all_segments);
404 extern __checkReturn efx_rc_t
405 ef10_nvram_partn_lock(
407 __in uint32_t partn);
409 extern __checkReturn efx_rc_t
410 ef10_nvram_partn_unlock(
413 __out_opt uint32_t *resultp);
415 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
421 extern __checkReturn efx_rc_t
423 __in efx_nic_t *enp);
425 #endif /* EFSYS_OPT_DIAG */
427 extern __checkReturn efx_rc_t
428 ef10_nvram_type_to_partn(
430 __in efx_nvram_type_t type,
431 __out uint32_t *partnp);
433 extern __checkReturn efx_rc_t
434 ef10_nvram_partn_size(
437 __out size_t *sizep);
439 extern __checkReturn efx_rc_t
440 ef10_nvram_partn_rw_start(
443 __out size_t *chunk_sizep);
445 extern __checkReturn efx_rc_t
446 ef10_nvram_partn_read_mode(
449 __in unsigned int offset,
450 __out_bcount(size) caddr_t data,
454 extern __checkReturn efx_rc_t
455 ef10_nvram_partn_read(
458 __in unsigned int offset,
459 __in_bcount(size) caddr_t data,
462 extern __checkReturn efx_rc_t
463 ef10_nvram_partn_read_backup(
466 __in unsigned int offset,
467 __out_bcount(size) caddr_t data,
470 extern __checkReturn efx_rc_t
471 ef10_nvram_partn_erase(
474 __in unsigned int offset,
477 extern __checkReturn efx_rc_t
478 ef10_nvram_partn_write(
481 __in unsigned int offset,
482 __out_bcount(size) caddr_t data,
485 extern __checkReturn efx_rc_t
486 ef10_nvram_partn_rw_finish(
489 __out_opt uint32_t *verify_resultp);
491 extern __checkReturn efx_rc_t
492 ef10_nvram_partn_get_version(
495 __out uint32_t *subtypep,
496 __out_ecount(4) uint16_t version[4]);
498 extern __checkReturn efx_rc_t
499 ef10_nvram_partn_set_version(
502 __in_ecount(4) uint16_t version[4]);
504 extern __checkReturn efx_rc_t
505 ef10_nvram_buffer_validate(
508 __in_bcount(buffer_size)
510 __in size_t buffer_size);
512 extern __checkReturn efx_rc_t
513 ef10_nvram_buffer_create(
515 __in uint16_t partn_type,
516 __in_bcount(buffer_size)
518 __in size_t buffer_size);
520 extern __checkReturn efx_rc_t
521 ef10_nvram_buffer_find_item_start(
522 __in_bcount(buffer_size)
524 __in size_t buffer_size,
525 __out uint32_t *startp);
527 extern __checkReturn efx_rc_t
528 ef10_nvram_buffer_find_end(
529 __in_bcount(buffer_size)
531 __in size_t buffer_size,
532 __in uint32_t offset,
533 __out uint32_t *endp);
535 extern __checkReturn __success(return != B_FALSE) boolean_t
536 ef10_nvram_buffer_find_item(
537 __in_bcount(buffer_size)
539 __in size_t buffer_size,
540 __in uint32_t offset,
541 __out uint32_t *startp,
542 __out uint32_t *lengthp);
544 extern __checkReturn efx_rc_t
545 ef10_nvram_buffer_get_item(
546 __in_bcount(buffer_size)
548 __in size_t buffer_size,
549 __in uint32_t offset,
550 __in uint32_t length,
551 __out_bcount_part(item_max_size, *lengthp)
553 __in size_t item_max_size,
554 __out uint32_t *lengthp);
556 extern __checkReturn efx_rc_t
557 ef10_nvram_buffer_insert_item(
558 __in_bcount(buffer_size)
560 __in size_t buffer_size,
561 __in uint32_t offset,
562 __in_bcount(length) caddr_t keyp,
563 __in uint32_t length,
564 __out uint32_t *lengthp);
566 extern __checkReturn efx_rc_t
567 ef10_nvram_buffer_delete_item(
568 __in_bcount(buffer_size)
570 __in size_t buffer_size,
571 __in uint32_t offset,
572 __in uint32_t length,
575 extern __checkReturn efx_rc_t
576 ef10_nvram_buffer_finish(
577 __in_bcount(buffer_size)
579 __in size_t buffer_size);
581 #endif /* EFSYS_OPT_NVRAM */
586 typedef struct ef10_link_state_s {
587 uint32_t els_adv_cap_mask;
588 uint32_t els_lp_cap_mask;
589 unsigned int els_fcntl;
590 efx_link_mode_t els_link_mode;
591 #if EFSYS_OPT_LOOPBACK
592 efx_loopback_type_t els_loopback;
594 boolean_t els_mac_up;
600 __in efx_qword_t *eqp,
601 __out efx_link_mode_t *link_modep);
603 extern __checkReturn efx_rc_t
606 __out ef10_link_state_t *elsp);
608 extern __checkReturn efx_rc_t
613 extern __checkReturn efx_rc_t
614 ef10_phy_reconfigure(
615 __in efx_nic_t *enp);
617 extern __checkReturn efx_rc_t
619 __in efx_nic_t *enp);
621 extern __checkReturn efx_rc_t
624 __out uint32_t *ouip);
626 #if EFSYS_OPT_PHY_STATS
628 extern __checkReturn efx_rc_t
629 ef10_phy_stats_update(
631 __in efsys_mem_t *esmp,
632 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
634 #endif /* EFSYS_OPT_PHY_STATS */
638 extern __checkReturn efx_rc_t
639 ef10_bist_enable_offline(
640 __in efx_nic_t *enp);
642 extern __checkReturn efx_rc_t
645 __in efx_bist_type_t type);
647 extern __checkReturn efx_rc_t
650 __in efx_bist_type_t type,
651 __out efx_bist_result_t *resultp,
652 __out_opt __drv_when(count > 0, __notnull)
653 uint32_t *value_maskp,
654 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
655 unsigned long *valuesp,
661 __in efx_bist_type_t type);
663 #endif /* EFSYS_OPT_BIST */
667 extern __checkReturn efx_rc_t
669 __in efx_nic_t *enp);
673 __in efx_nic_t *enp);
675 extern __checkReturn efx_rc_t
678 __in unsigned int index,
679 __in unsigned int label,
680 __in efsys_mem_t *esmp,
686 __out unsigned int *addedp);
690 __in efx_txq_t *etp);
692 extern __checkReturn efx_rc_t
695 __in_ecount(ndescs) efx_buffer_t *ebp,
696 __in unsigned int ndescs,
697 __in unsigned int completed,
698 __inout unsigned int *addedp);
703 __in unsigned int added,
704 __in unsigned int pushed);
706 #if EFSYS_OPT_RX_PACKED_STREAM
708 ef10_rx_qpush_ps_credits(
709 __in efx_rxq_t *erp);
711 extern __checkReturn uint8_t *
712 ef10_rx_qps_packet_info(
714 __in uint8_t *buffer,
715 __in uint32_t buffer_length,
716 __in uint32_t current_offset,
717 __out uint16_t *lengthp,
718 __out uint32_t *next_offsetp,
719 __out uint32_t *timestamp);
722 extern __checkReturn efx_rc_t
725 __in unsigned int ns);
727 extern __checkReturn efx_rc_t
729 __in efx_txq_t *etp);
733 __in efx_txq_t *etp);
735 extern __checkReturn efx_rc_t
737 __in efx_txq_t *etp);
740 ef10_tx_qpio_disable(
741 __in efx_txq_t *etp);
743 extern __checkReturn efx_rc_t
746 __in_ecount(buf_length) uint8_t *buffer,
747 __in size_t buf_length,
748 __in size_t pio_buf_offset);
750 extern __checkReturn efx_rc_t
753 __in size_t pkt_length,
754 __in unsigned int completed,
755 __inout unsigned int *addedp);
757 extern __checkReturn efx_rc_t
760 __in_ecount(n) efx_desc_t *ed,
762 __in unsigned int completed,
763 __inout unsigned int *addedp);
766 ef10_tx_qdesc_dma_create(
768 __in efsys_dma_addr_t addr,
771 __out efx_desc_t *edp);
774 ef10_tx_qdesc_tso_create(
776 __in uint16_t ipv4_id,
777 __in uint32_t tcp_seq,
778 __in uint8_t tcp_flags,
779 __out efx_desc_t *edp);
782 ef10_tx_qdesc_tso2_create(
784 __in uint16_t ipv4_id,
785 __in uint16_t outer_ipv4_id,
786 __in uint32_t tcp_seq,
787 __in uint16_t tcp_mss,
788 __out_ecount(count) efx_desc_t *edp,
792 ef10_tx_qdesc_vlantci_create(
794 __in uint16_t vlan_tci,
795 __out efx_desc_t *edp);
798 ef10_tx_qdesc_checksum_create(
801 __out efx_desc_t *edp);
806 ef10_tx_qstats_update(
808 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
810 #endif /* EFSYS_OPT_QSTATS */
812 typedef uint32_t efx_piobuf_handle_t;
814 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
816 extern __checkReturn efx_rc_t
818 __inout efx_nic_t *enp,
819 __out uint32_t *bufnump,
820 __out efx_piobuf_handle_t *handlep,
821 __out uint32_t *blknump,
822 __out uint32_t *offsetp,
823 __out size_t *sizep);
825 extern __checkReturn efx_rc_t
827 __inout efx_nic_t *enp,
828 __in uint32_t bufnum,
829 __in uint32_t blknum);
831 extern __checkReturn efx_rc_t
833 __inout efx_nic_t *enp,
834 __in uint32_t vi_index,
835 __in efx_piobuf_handle_t handle);
837 extern __checkReturn efx_rc_t
839 __inout efx_nic_t *enp,
840 __in uint32_t vi_index);
847 extern __checkReturn efx_rc_t
849 __in efx_nic_t *enp);
851 extern __checkReturn efx_rc_t
854 __out size_t *sizep);
856 extern __checkReturn efx_rc_t
859 __out_bcount(size) caddr_t data,
862 extern __checkReturn efx_rc_t
865 __in_bcount(size) caddr_t data,
868 extern __checkReturn efx_rc_t
871 __in_bcount(size) caddr_t data,
874 extern __checkReturn efx_rc_t
877 __in_bcount(size) caddr_t data,
879 __inout efx_vpd_value_t *evvp);
881 extern __checkReturn efx_rc_t
884 __in_bcount(size) caddr_t data,
886 __in efx_vpd_value_t *evvp);
888 extern __checkReturn efx_rc_t
891 __in_bcount(size) caddr_t data,
893 __out efx_vpd_value_t *evvp,
894 __inout unsigned int *contp);
896 extern __checkReturn efx_rc_t
899 __in_bcount(size) caddr_t data,
904 __in efx_nic_t *enp);
906 #endif /* EFSYS_OPT_VPD */
911 extern __checkReturn efx_rc_t
913 __in efx_nic_t *enp);
915 #if EFSYS_OPT_RX_SCATTER
916 extern __checkReturn efx_rc_t
917 ef10_rx_scatter_enable(
919 __in unsigned int buf_size);
920 #endif /* EFSYS_OPT_RX_SCATTER */
923 #if EFSYS_OPT_RX_SCALE
925 extern __checkReturn efx_rc_t
926 ef10_rx_scale_context_alloc(
928 __in efx_rx_scale_context_type_t type,
929 __in uint32_t num_queues,
930 __out uint32_t *rss_contextp);
932 extern __checkReturn efx_rc_t
933 ef10_rx_scale_context_free(
935 __in uint32_t rss_context);
937 extern __checkReturn efx_rc_t
938 ef10_rx_scale_mode_set(
940 __in uint32_t rss_context,
941 __in efx_rx_hash_alg_t alg,
942 __in efx_rx_hash_type_t type,
943 __in boolean_t insert);
945 extern __checkReturn efx_rc_t
946 ef10_rx_scale_key_set(
948 __in uint32_t rss_context,
949 __in_ecount(n) uint8_t *key,
952 extern __checkReturn efx_rc_t
953 ef10_rx_scale_tbl_set(
955 __in uint32_t rss_context,
956 __in_ecount(n) unsigned int *table,
959 extern __checkReturn uint32_t
962 __in efx_rx_hash_alg_t func,
963 __in uint8_t *buffer);
965 #endif /* EFSYS_OPT_RX_SCALE */
967 extern __checkReturn efx_rc_t
968 ef10_rx_prefix_pktlen(
970 __in uint8_t *buffer,
971 __out uint16_t *lengthp);
976 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
978 __in unsigned int ndescs,
979 __in unsigned int completed,
980 __in unsigned int added);
985 __in unsigned int added,
986 __inout unsigned int *pushedp);
988 extern __checkReturn efx_rc_t
990 __in efx_rxq_t *erp);
994 __in efx_rxq_t *erp);
996 union efx_rxq_type_data_u;
998 extern __checkReturn efx_rc_t
1000 __in efx_nic_t *enp,
1001 __in unsigned int index,
1002 __in unsigned int label,
1003 __in efx_rxq_type_t type,
1004 __in const union efx_rxq_type_data_u *type_data,
1005 __in efsys_mem_t *esmp,
1008 __in unsigned int flags,
1009 __in efx_evq_t *eep,
1010 __in efx_rxq_t *erp);
1014 __in efx_rxq_t *erp);
1018 __in efx_nic_t *enp);
1020 #if EFSYS_OPT_FILTER
1022 typedef struct ef10_filter_handle_s {
1025 } ef10_filter_handle_t;
1027 typedef struct ef10_filter_entry_s {
1028 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1029 ef10_filter_handle_t efe_handle;
1030 } ef10_filter_entry_t;
1033 * BUSY flag indicates that an update is in progress.
1034 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1036 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1037 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1038 #define EFX_EF10_FILTER_FLAGS 3U
1041 * Size of the hash table used by the driver. Doesn't need to be the
1042 * same size as the hardware's table.
1044 #define EFX_EF10_FILTER_TBL_ROWS 8192
1046 /* Only need to allow for one directed and one unknown unicast filter */
1047 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1049 /* Allow for the broadcast address to be added to the multicast list */
1050 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1053 * For encapsulated packets, there is one filter each for each combination of
1054 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1055 * multicast inner frames.
1057 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1059 typedef struct ef10_filter_table_s {
1060 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1061 efx_rxq_t *eft_default_rxq;
1062 boolean_t eft_using_rss;
1063 uint32_t eft_unicst_filter_indexes[
1064 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1065 uint32_t eft_unicst_filter_count;
1066 uint32_t eft_mulcst_filter_indexes[
1067 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1068 uint32_t eft_mulcst_filter_count;
1069 boolean_t eft_using_all_mulcst;
1070 uint32_t eft_encap_filter_indexes[
1071 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1072 uint32_t eft_encap_filter_count;
1073 } ef10_filter_table_t;
1075 __checkReturn efx_rc_t
1077 __in efx_nic_t *enp);
1081 __in efx_nic_t *enp);
1083 __checkReturn efx_rc_t
1084 ef10_filter_restore(
1085 __in efx_nic_t *enp);
1087 __checkReturn efx_rc_t
1089 __in efx_nic_t *enp,
1090 __inout efx_filter_spec_t *spec,
1091 __in boolean_t may_replace);
1093 __checkReturn efx_rc_t
1095 __in efx_nic_t *enp,
1096 __inout efx_filter_spec_t *spec);
1098 extern __checkReturn efx_rc_t
1099 ef10_filter_supported_filters(
1100 __in efx_nic_t *enp,
1101 __out_ecount(buffer_length) uint32_t *buffer,
1102 __in size_t buffer_length,
1103 __out size_t *list_lengthp);
1105 extern __checkReturn efx_rc_t
1106 ef10_filter_reconfigure(
1107 __in efx_nic_t *enp,
1108 __in_ecount(6) uint8_t const *mac_addr,
1109 __in boolean_t all_unicst,
1110 __in boolean_t mulcst,
1111 __in boolean_t all_mulcst,
1112 __in boolean_t brdcst,
1113 __in_ecount(6*count) uint8_t const *addrs,
1114 __in uint32_t count);
1117 ef10_filter_get_default_rxq(
1118 __in efx_nic_t *enp,
1119 __out efx_rxq_t **erpp,
1120 __out boolean_t *using_rss);
1123 ef10_filter_default_rxq_set(
1124 __in efx_nic_t *enp,
1125 __in efx_rxq_t *erp,
1126 __in boolean_t using_rss);
1129 ef10_filter_default_rxq_clear(
1130 __in efx_nic_t *enp);
1133 #endif /* EFSYS_OPT_FILTER */
1135 extern __checkReturn efx_rc_t
1136 efx_mcdi_get_function_info(
1137 __in efx_nic_t *enp,
1138 __out uint32_t *pfp,
1139 __out_opt uint32_t *vfp);
1141 extern __checkReturn efx_rc_t
1142 efx_mcdi_privilege_mask(
1143 __in efx_nic_t *enp,
1146 __out uint32_t *maskp);
1148 extern __checkReturn efx_rc_t
1149 efx_mcdi_get_port_assignment(
1150 __in efx_nic_t *enp,
1151 __out uint32_t *portp);
1153 extern __checkReturn efx_rc_t
1154 efx_mcdi_get_port_modes(
1155 __in efx_nic_t *enp,
1156 __out uint32_t *modesp,
1157 __out_opt uint32_t *current_modep);
1159 extern __checkReturn efx_rc_t
1160 ef10_nic_get_port_mode_bandwidth(
1161 __in uint32_t port_mode,
1162 __out uint32_t *bandwidth_mbpsp);
1164 extern __checkReturn efx_rc_t
1165 efx_mcdi_get_mac_address_pf(
1166 __in efx_nic_t *enp,
1167 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1169 extern __checkReturn efx_rc_t
1170 efx_mcdi_get_mac_address_vf(
1171 __in efx_nic_t *enp,
1172 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1174 extern __checkReturn efx_rc_t
1176 __in efx_nic_t *enp,
1177 __out uint32_t *sys_freqp,
1178 __out uint32_t *dpcpu_freqp);
1181 extern __checkReturn efx_rc_t
1182 efx_mcdi_get_rxdp_config(
1183 __in efx_nic_t *enp,
1184 __out uint32_t *end_paddingp);
1186 extern __checkReturn efx_rc_t
1187 efx_mcdi_get_vector_cfg(
1188 __in efx_nic_t *enp,
1189 __out_opt uint32_t *vec_basep,
1190 __out_opt uint32_t *pf_nvecp,
1191 __out_opt uint32_t *vf_nvecp);
1193 extern __checkReturn efx_rc_t
1194 ef10_get_privilege_mask(
1195 __in efx_nic_t *enp,
1196 __out uint32_t *maskp);
1198 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1200 extern __checkReturn efx_rc_t
1201 efx_mcdi_get_nic_global(
1202 __in efx_nic_t *enp,
1204 __out uint32_t *valuep);
1206 extern __checkReturn efx_rc_t
1207 efx_mcdi_set_nic_global(
1208 __in efx_nic_t *enp,
1210 __in uint32_t value);
1212 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1215 #if EFSYS_OPT_RX_PACKED_STREAM
1217 /* Data space per credit in packed stream mode */
1218 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1221 * Received packets are always aligned at this boundary. Also there always
1222 * exists a gap of this size between packets.
1223 * (see SF-112241-TC, 4.5)
1225 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1228 * Size of a pseudo-header prepended to received packets
1229 * in packed stream mode
1231 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1233 /* Minimum space for packet in packed stream mode */
1234 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1235 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1237 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1238 EFX_RX_PACKED_STREAM_ALIGNMENT)
1240 /* Maximum number of credits */
1241 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1243 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1245 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1248 * Maximum DMA length and buffer stride alignment.
1249 * (see SF-119419-TC, 3.2)
1251 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1259 #endif /* _SYS_EF10_IMPL_H */