2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_EF10_IMPL_H
34 #define _SYS_EF10_IMPL_H
40 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
41 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
42 #elif EFSYS_OPT_HUNTINGTON
43 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
44 #elif EFSYS_OPT_MEDFORD
45 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
50 * possibly be increased, or the write size reported by newer firmware used
53 #define EF10_NVRAM_CHUNK 0x80
55 /* Alignment requirement for value written to RX WPTR:
56 * the WPTR must be aligned to an 8 descriptor boundary
58 #define EF10_RX_WPTR_ALIGN 8
61 * Max byte offset into the packet the TCP header must start for the hardware
62 * to be able to parse the packet correctly.
64 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
66 /* Invalid RSS context handle */
67 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
72 __checkReturn efx_rc_t
80 __checkReturn efx_rc_t
83 __in unsigned int index,
84 __in efsys_mem_t *esmp,
95 __checkReturn efx_rc_t
98 __in unsigned int count);
105 __checkReturn efx_rc_t
108 __in unsigned int us);
112 ef10_ev_qstats_update(
114 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
115 #endif /* EFSYS_OPT_QSTATS */
118 ef10_ev_rxlabel_init(
121 __in unsigned int label,
122 __in efx_rxq_type_t type);
125 ef10_ev_rxlabel_fini(
127 __in unsigned int label);
131 __checkReturn efx_rc_t
134 __in efx_intr_type_t type,
135 __in efsys_mem_t *esmp);
139 __in efx_nic_t *enp);
143 __in efx_nic_t *enp);
146 ef10_intr_disable_unlocked(
147 __in efx_nic_t *enp);
149 __checkReturn efx_rc_t
152 __in unsigned int level);
155 ef10_intr_status_line(
157 __out boolean_t *fatalp,
158 __out uint32_t *qmaskp);
161 ef10_intr_status_message(
163 __in unsigned int message,
164 __out boolean_t *fatalp);
168 __in efx_nic_t *enp);
171 __in efx_nic_t *enp);
175 extern __checkReturn efx_rc_t
177 __in efx_nic_t *enp);
179 extern __checkReturn efx_rc_t
180 ef10_nic_set_drv_limits(
181 __inout efx_nic_t *enp,
182 __in efx_drv_limits_t *edlp);
184 extern __checkReturn efx_rc_t
185 ef10_nic_get_vi_pool(
187 __out uint32_t *vi_countp);
189 extern __checkReturn efx_rc_t
190 ef10_nic_get_bar_region(
192 __in efx_nic_region_t region,
193 __out uint32_t *offsetp,
194 __out size_t *sizep);
196 extern __checkReturn efx_rc_t
198 __in efx_nic_t *enp);
200 extern __checkReturn efx_rc_t
202 __in efx_nic_t *enp);
206 extern __checkReturn efx_rc_t
207 ef10_nic_register_test(
208 __in efx_nic_t *enp);
210 #endif /* EFSYS_OPT_DIAG */
214 __in efx_nic_t *enp);
218 __in efx_nic_t *enp);
223 extern __checkReturn efx_rc_t
226 __out efx_link_mode_t *link_modep);
228 extern __checkReturn efx_rc_t
231 __out boolean_t *mac_upp);
233 extern __checkReturn efx_rc_t
235 __in efx_nic_t *enp);
237 extern __checkReturn efx_rc_t
239 __in efx_nic_t *enp);
241 extern __checkReturn efx_rc_t
246 extern __checkReturn efx_rc_t
247 ef10_mac_reconfigure(
248 __in efx_nic_t *enp);
250 extern __checkReturn efx_rc_t
251 ef10_mac_multicast_list_set(
252 __in efx_nic_t *enp);
254 extern __checkReturn efx_rc_t
255 ef10_mac_filter_default_rxq_set(
258 __in boolean_t using_rss);
261 ef10_mac_filter_default_rxq_clear(
262 __in efx_nic_t *enp);
264 #if EFSYS_OPT_LOOPBACK
266 extern __checkReturn efx_rc_t
267 ef10_mac_loopback_set(
269 __in efx_link_mode_t link_mode,
270 __in efx_loopback_type_t loopback_type);
272 #endif /* EFSYS_OPT_LOOPBACK */
274 #if EFSYS_OPT_MAC_STATS
276 extern __checkReturn efx_rc_t
277 ef10_mac_stats_get_mask(
279 __inout_bcount(mask_size) uint32_t *maskp,
280 __in size_t mask_size);
282 extern __checkReturn efx_rc_t
283 ef10_mac_stats_update(
285 __in efsys_mem_t *esmp,
286 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
287 __inout_opt uint32_t *generationp);
289 #endif /* EFSYS_OPT_MAC_STATS */
296 extern __checkReturn efx_rc_t
299 __in const efx_mcdi_transport_t *mtp);
303 __in efx_nic_t *enp);
306 ef10_mcdi_send_request(
308 __in_bcount(hdr_len) void *hdrp,
310 __in_bcount(sdu_len) void *sdup,
311 __in size_t sdu_len);
313 extern __checkReturn boolean_t
314 ef10_mcdi_poll_response(
315 __in efx_nic_t *enp);
318 ef10_mcdi_read_response(
320 __out_bcount(length) void *bufferp,
325 ef10_mcdi_poll_reboot(
326 __in efx_nic_t *enp);
328 extern __checkReturn efx_rc_t
329 ef10_mcdi_feature_supported(
331 __in efx_mcdi_feature_id_t id,
332 __out boolean_t *supportedp);
335 ef10_mcdi_get_timeout(
337 __in efx_mcdi_req_t *emrp,
338 __out uint32_t *timeoutp);
340 #endif /* EFSYS_OPT_MCDI */
344 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
346 extern __checkReturn efx_rc_t
347 ef10_nvram_buf_read_tlv(
349 __in_bcount(max_seg_size) caddr_t seg_data,
350 __in size_t max_seg_size,
352 __deref_out_bcount_opt(*sizep) caddr_t *datap,
353 __out size_t *sizep);
355 extern __checkReturn efx_rc_t
356 ef10_nvram_buf_write_tlv(
357 __inout_bcount(partn_size) caddr_t partn_data,
358 __in size_t partn_size,
360 __in_bcount(tag_size) caddr_t tag_data,
361 __in size_t tag_size,
362 __out size_t *total_lengthp);
364 extern __checkReturn efx_rc_t
365 ef10_nvram_partn_read_tlv(
369 __deref_out_bcount_opt(*sizep) caddr_t *datap,
370 __out size_t *sizep);
372 extern __checkReturn efx_rc_t
373 ef10_nvram_partn_write_tlv(
377 __in_bcount(size) caddr_t data,
380 extern __checkReturn efx_rc_t
381 ef10_nvram_partn_write_segment_tlv(
385 __in_bcount(size) caddr_t data,
387 __in boolean_t all_segments);
389 extern __checkReturn efx_rc_t
390 ef10_nvram_partn_lock(
392 __in uint32_t partn);
394 extern __checkReturn efx_rc_t
395 ef10_nvram_partn_unlock(
398 __out_opt uint32_t *resultp);
400 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
406 extern __checkReturn efx_rc_t
408 __in efx_nic_t *enp);
410 #endif /* EFSYS_OPT_DIAG */
412 extern __checkReturn efx_rc_t
413 ef10_nvram_type_to_partn(
415 __in efx_nvram_type_t type,
416 __out uint32_t *partnp);
418 extern __checkReturn efx_rc_t
419 ef10_nvram_partn_size(
422 __out size_t *sizep);
424 extern __checkReturn efx_rc_t
425 ef10_nvram_partn_rw_start(
428 __out size_t *chunk_sizep);
430 extern __checkReturn efx_rc_t
431 ef10_nvram_partn_read_mode(
434 __in unsigned int offset,
435 __out_bcount(size) caddr_t data,
439 extern __checkReturn efx_rc_t
440 ef10_nvram_partn_read(
443 __in unsigned int offset,
444 __out_bcount(size) caddr_t data,
447 extern __checkReturn efx_rc_t
448 ef10_nvram_partn_read_backup(
451 __in unsigned int offset,
452 __out_bcount(size) caddr_t data,
455 extern __checkReturn efx_rc_t
456 ef10_nvram_partn_erase(
459 __in unsigned int offset,
462 extern __checkReturn efx_rc_t
463 ef10_nvram_partn_write(
466 __in unsigned int offset,
467 __out_bcount(size) caddr_t data,
470 extern __checkReturn efx_rc_t
471 ef10_nvram_partn_rw_finish(
474 __out_opt uint32_t *verify_resultp);
476 extern __checkReturn efx_rc_t
477 ef10_nvram_partn_get_version(
480 __out uint32_t *subtypep,
481 __out_ecount(4) uint16_t version[4]);
483 extern __checkReturn efx_rc_t
484 ef10_nvram_partn_set_version(
487 __in_ecount(4) uint16_t version[4]);
489 extern __checkReturn efx_rc_t
490 ef10_nvram_buffer_validate(
493 __in_bcount(buffer_size)
495 __in size_t buffer_size);
497 extern __checkReturn efx_rc_t
498 ef10_nvram_buffer_create(
500 __in uint16_t partn_type,
501 __in_bcount(buffer_size)
503 __in size_t buffer_size);
505 extern __checkReturn efx_rc_t
506 ef10_nvram_buffer_find_item_start(
507 __in_bcount(buffer_size)
509 __in size_t buffer_size,
510 __out uint32_t *startp
513 extern __checkReturn efx_rc_t
514 ef10_nvram_buffer_find_end(
515 __in_bcount(buffer_size)
517 __in size_t buffer_size,
518 __in uint32_t offset,
522 extern __checkReturn __success(return != B_FALSE) boolean_t
523 ef10_nvram_buffer_find_item(
524 __in_bcount(buffer_size)
526 __in size_t buffer_size,
527 __in uint32_t offset,
528 __out uint32_t *startp,
529 __out uint32_t *lengthp
532 extern __checkReturn efx_rc_t
533 ef10_nvram_buffer_get_item(
534 __in_bcount(buffer_size)
536 __in size_t buffer_size,
537 __in uint32_t offset,
538 __in uint32_t length,
539 __out_bcount_part(item_max_size, *lengthp)
541 __in size_t item_max_size,
542 __out uint32_t *lengthp
545 extern __checkReturn efx_rc_t
546 ef10_nvram_buffer_insert_item(
547 __in_bcount(buffer_size)
549 __in size_t buffer_size,
550 __in uint32_t offset,
551 __in_bcount(length) caddr_t keyp,
552 __in uint32_t length,
553 __out uint32_t *lengthp
556 extern __checkReturn efx_rc_t
557 ef10_nvram_buffer_delete_item(
558 __in_bcount(buffer_size)
560 __in size_t buffer_size,
561 __in uint32_t offset,
562 __in uint32_t length,
566 extern __checkReturn efx_rc_t
567 ef10_nvram_buffer_finish(
568 __in_bcount(buffer_size)
570 __in size_t buffer_size
573 #endif /* EFSYS_OPT_NVRAM */
578 typedef struct ef10_link_state_s {
579 uint32_t els_adv_cap_mask;
580 uint32_t els_lp_cap_mask;
581 unsigned int els_fcntl;
582 efx_link_mode_t els_link_mode;
583 #if EFSYS_OPT_LOOPBACK
584 efx_loopback_type_t els_loopback;
586 boolean_t els_mac_up;
592 __in efx_qword_t *eqp,
593 __out efx_link_mode_t *link_modep);
595 extern __checkReturn efx_rc_t
598 __out ef10_link_state_t *elsp);
600 extern __checkReturn efx_rc_t
605 extern __checkReturn efx_rc_t
606 ef10_phy_reconfigure(
607 __in efx_nic_t *enp);
609 extern __checkReturn efx_rc_t
611 __in efx_nic_t *enp);
613 extern __checkReturn efx_rc_t
616 __out uint32_t *ouip);
618 #if EFSYS_OPT_PHY_STATS
620 extern __checkReturn efx_rc_t
621 ef10_phy_stats_update(
623 __in efsys_mem_t *esmp,
624 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
626 #endif /* EFSYS_OPT_PHY_STATS */
630 extern __checkReturn efx_rc_t
631 ef10_bist_enable_offline(
632 __in efx_nic_t *enp);
634 extern __checkReturn efx_rc_t
637 __in efx_bist_type_t type);
639 extern __checkReturn efx_rc_t
642 __in efx_bist_type_t type,
643 __out efx_bist_result_t *resultp,
644 __out_opt __drv_when(count > 0, __notnull)
645 uint32_t *value_maskp,
646 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
647 unsigned long *valuesp,
653 __in efx_bist_type_t type);
655 #endif /* EFSYS_OPT_BIST */
659 extern __checkReturn efx_rc_t
661 __in efx_nic_t *enp);
665 __in efx_nic_t *enp);
667 extern __checkReturn efx_rc_t
670 __in unsigned int index,
671 __in unsigned int label,
672 __in efsys_mem_t *esmp,
678 __out unsigned int *addedp);
682 __in efx_txq_t *etp);
684 extern __checkReturn efx_rc_t
687 __in_ecount(n) efx_buffer_t *eb,
689 __in unsigned int completed,
690 __inout unsigned int *addedp);
695 __in unsigned int added,
696 __in unsigned int pushed);
698 #if EFSYS_OPT_RX_PACKED_STREAM
700 ef10_rx_qpush_ps_credits(
701 __in efx_rxq_t *erp);
703 extern __checkReturn uint8_t *
704 ef10_rx_qps_packet_info(
706 __in uint8_t *buffer,
707 __in uint32_t buffer_length,
708 __in uint32_t current_offset,
709 __out uint16_t *lengthp,
710 __out uint32_t *next_offsetp,
711 __out uint32_t *timestamp);
714 extern __checkReturn efx_rc_t
717 __in unsigned int ns);
719 extern __checkReturn efx_rc_t
721 __in efx_txq_t *etp);
725 __in efx_txq_t *etp);
727 extern __checkReturn efx_rc_t
729 __in efx_txq_t *etp);
732 ef10_tx_qpio_disable(
733 __in efx_txq_t *etp);
735 extern __checkReturn efx_rc_t
738 __in_ecount(buf_length) uint8_t *buffer,
739 __in size_t buf_length,
740 __in size_t pio_buf_offset);
742 extern __checkReturn efx_rc_t
745 __in size_t pkt_length,
746 __in unsigned int completed,
747 __inout unsigned int *addedp);
749 extern __checkReturn efx_rc_t
752 __in_ecount(n) efx_desc_t *ed,
754 __in unsigned int completed,
755 __inout unsigned int *addedp);
758 ef10_tx_qdesc_dma_create(
760 __in efsys_dma_addr_t addr,
763 __out efx_desc_t *edp);
766 ef10_tx_qdesc_tso_create(
768 __in uint16_t ipv4_id,
769 __in uint32_t tcp_seq,
770 __in uint8_t tcp_flags,
771 __out efx_desc_t *edp);
774 ef10_tx_qdesc_tso2_create(
776 __in uint16_t ipv4_id,
777 __in uint32_t tcp_seq,
778 __in uint16_t tcp_mss,
779 __out_ecount(count) efx_desc_t *edp,
783 ef10_tx_qdesc_vlantci_create(
785 __in uint16_t vlan_tci,
786 __out efx_desc_t *edp);
792 ef10_tx_qstats_update(
794 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
796 #endif /* EFSYS_OPT_QSTATS */
798 typedef uint32_t efx_piobuf_handle_t;
800 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
802 extern __checkReturn efx_rc_t
804 __inout efx_nic_t *enp,
805 __out uint32_t *bufnump,
806 __out efx_piobuf_handle_t *handlep,
807 __out uint32_t *blknump,
808 __out uint32_t *offsetp,
809 __out size_t *sizep);
811 extern __checkReturn efx_rc_t
813 __inout efx_nic_t *enp,
814 __in uint32_t bufnum,
815 __in uint32_t blknum);
817 extern __checkReturn efx_rc_t
819 __inout efx_nic_t *enp,
820 __in uint32_t vi_index,
821 __in efx_piobuf_handle_t handle);
823 extern __checkReturn efx_rc_t
825 __inout efx_nic_t *enp,
826 __in uint32_t vi_index);
833 extern __checkReturn efx_rc_t
835 __in efx_nic_t *enp);
837 extern __checkReturn efx_rc_t
840 __out size_t *sizep);
842 extern __checkReturn efx_rc_t
845 __out_bcount(size) caddr_t data,
848 extern __checkReturn efx_rc_t
851 __in_bcount(size) caddr_t data,
854 extern __checkReturn efx_rc_t
857 __in_bcount(size) caddr_t data,
860 extern __checkReturn efx_rc_t
863 __in_bcount(size) caddr_t data,
865 __inout efx_vpd_value_t *evvp);
867 extern __checkReturn efx_rc_t
870 __in_bcount(size) caddr_t data,
872 __in efx_vpd_value_t *evvp);
874 extern __checkReturn efx_rc_t
877 __in_bcount(size) caddr_t data,
879 __out efx_vpd_value_t *evvp,
880 __inout unsigned int *contp);
882 extern __checkReturn efx_rc_t
885 __in_bcount(size) caddr_t data,
890 __in efx_nic_t *enp);
892 #endif /* EFSYS_OPT_VPD */
897 extern __checkReturn efx_rc_t
899 __in efx_nic_t *enp);
901 #if EFSYS_OPT_RX_SCATTER
902 extern __checkReturn efx_rc_t
903 ef10_rx_scatter_enable(
905 __in unsigned int buf_size);
906 #endif /* EFSYS_OPT_RX_SCATTER */
909 #if EFSYS_OPT_RX_SCALE
911 extern __checkReturn efx_rc_t
912 ef10_rx_scale_context_alloc(
914 __in efx_rx_scale_context_type_t type,
915 __in uint32_t num_queues,
916 __out uint32_t *rss_contextp);
918 extern __checkReturn efx_rc_t
919 ef10_rx_scale_context_free(
921 __in uint32_t rss_context);
923 extern __checkReturn efx_rc_t
924 ef10_rx_scale_mode_set(
926 __in uint32_t rss_context,
927 __in efx_rx_hash_alg_t alg,
928 __in efx_rx_hash_type_t type,
929 __in boolean_t insert);
931 extern __checkReturn efx_rc_t
932 ef10_rx_scale_key_set(
934 __in uint32_t rss_context,
935 __in_ecount(n) uint8_t *key,
938 extern __checkReturn efx_rc_t
939 ef10_rx_scale_tbl_set(
941 __in uint32_t rss_context,
942 __in_ecount(n) unsigned int *table,
945 extern __checkReturn uint32_t
948 __in efx_rx_hash_alg_t func,
949 __in uint8_t *buffer);
951 #endif /* EFSYS_OPT_RX_SCALE */
953 extern __checkReturn efx_rc_t
954 ef10_rx_prefix_pktlen(
956 __in uint8_t *buffer,
957 __out uint16_t *lengthp);
962 __in_ecount(n) efsys_dma_addr_t *addrp,
965 __in unsigned int completed,
966 __in unsigned int added);
971 __in unsigned int added,
972 __inout unsigned int *pushedp);
974 extern __checkReturn efx_rc_t
976 __in efx_rxq_t *erp);
980 __in efx_rxq_t *erp);
982 extern __checkReturn efx_rc_t
985 __in unsigned int index,
986 __in unsigned int label,
987 __in efx_rxq_type_t type,
988 __in efsys_mem_t *esmp,
992 __in efx_rxq_t *erp);
996 __in efx_rxq_t *erp);
1000 __in efx_nic_t *enp);
1002 #if EFSYS_OPT_FILTER
1004 typedef struct ef10_filter_handle_s {
1007 } ef10_filter_handle_t;
1009 typedef struct ef10_filter_entry_s {
1010 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1011 ef10_filter_handle_t efe_handle;
1012 } ef10_filter_entry_t;
1015 * BUSY flag indicates that an update is in progress.
1016 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1018 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1019 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1020 #define EFX_EF10_FILTER_FLAGS 3U
1023 * Size of the hash table used by the driver. Doesn't need to be the
1024 * same size as the hardware's table.
1026 #define EFX_EF10_FILTER_TBL_ROWS 8192
1028 /* Only need to allow for one directed and one unknown unicast filter */
1029 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1031 /* Allow for the broadcast address to be added to the multicast list */
1032 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1035 * For encapsulated packets, there is one filter each for each combination of
1036 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1037 * multicast inner frames.
1039 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1041 typedef struct ef10_filter_table_s {
1042 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1043 efx_rxq_t *eft_default_rxq;
1044 boolean_t eft_using_rss;
1045 uint32_t eft_unicst_filter_indexes[
1046 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1047 uint32_t eft_unicst_filter_count;
1048 uint32_t eft_mulcst_filter_indexes[
1049 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1050 uint32_t eft_mulcst_filter_count;
1051 boolean_t eft_using_all_mulcst;
1052 uint32_t eft_encap_filter_indexes[
1053 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1054 uint32_t eft_encap_filter_count;
1055 } ef10_filter_table_t;
1057 __checkReturn efx_rc_t
1059 __in efx_nic_t *enp);
1063 __in efx_nic_t *enp);
1065 __checkReturn efx_rc_t
1066 ef10_filter_restore(
1067 __in efx_nic_t *enp);
1069 __checkReturn efx_rc_t
1071 __in efx_nic_t *enp,
1072 __inout efx_filter_spec_t *spec,
1073 __in boolean_t may_replace);
1075 __checkReturn efx_rc_t
1077 __in efx_nic_t *enp,
1078 __inout efx_filter_spec_t *spec);
1080 extern __checkReturn efx_rc_t
1081 ef10_filter_supported_filters(
1082 __in efx_nic_t *enp,
1083 __out_ecount(buffer_length) uint32_t *buffer,
1084 __in size_t buffer_length,
1085 __out size_t *list_lengthp);
1087 extern __checkReturn efx_rc_t
1088 ef10_filter_reconfigure(
1089 __in efx_nic_t *enp,
1090 __in_ecount(6) uint8_t const *mac_addr,
1091 __in boolean_t all_unicst,
1092 __in boolean_t mulcst,
1093 __in boolean_t all_mulcst,
1094 __in boolean_t brdcst,
1095 __in_ecount(6*count) uint8_t const *addrs,
1096 __in uint32_t count);
1099 ef10_filter_get_default_rxq(
1100 __in efx_nic_t *enp,
1101 __out efx_rxq_t **erpp,
1102 __out boolean_t *using_rss);
1105 ef10_filter_default_rxq_set(
1106 __in efx_nic_t *enp,
1107 __in efx_rxq_t *erp,
1108 __in boolean_t using_rss);
1111 ef10_filter_default_rxq_clear(
1112 __in efx_nic_t *enp);
1115 #endif /* EFSYS_OPT_FILTER */
1117 extern __checkReturn efx_rc_t
1118 efx_mcdi_get_function_info(
1119 __in efx_nic_t *enp,
1120 __out uint32_t *pfp,
1121 __out_opt uint32_t *vfp);
1123 extern __checkReturn efx_rc_t
1124 efx_mcdi_privilege_mask(
1125 __in efx_nic_t *enp,
1128 __out uint32_t *maskp);
1130 extern __checkReturn efx_rc_t
1131 efx_mcdi_get_port_assignment(
1132 __in efx_nic_t *enp,
1133 __out uint32_t *portp);
1135 extern __checkReturn efx_rc_t
1136 efx_mcdi_get_port_modes(
1137 __in efx_nic_t *enp,
1138 __out uint32_t *modesp,
1139 __out_opt uint32_t *current_modep);
1141 extern __checkReturn efx_rc_t
1142 ef10_nic_get_port_mode_bandwidth(
1143 __in uint32_t port_mode,
1144 __out uint32_t *bandwidth_mbpsp);
1146 extern __checkReturn efx_rc_t
1147 efx_mcdi_get_mac_address_pf(
1148 __in efx_nic_t *enp,
1149 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1151 extern __checkReturn efx_rc_t
1152 efx_mcdi_get_mac_address_vf(
1153 __in efx_nic_t *enp,
1154 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1156 extern __checkReturn efx_rc_t
1158 __in efx_nic_t *enp,
1159 __out uint32_t *sys_freqp,
1160 __out uint32_t *dpcpu_freqp);
1163 extern __checkReturn efx_rc_t
1164 efx_mcdi_get_vector_cfg(
1165 __in efx_nic_t *enp,
1166 __out_opt uint32_t *vec_basep,
1167 __out_opt uint32_t *pf_nvecp,
1168 __out_opt uint32_t *vf_nvecp);
1170 extern __checkReturn efx_rc_t
1171 ef10_get_datapath_caps(
1172 __in efx_nic_t *enp);
1174 extern __checkReturn efx_rc_t
1175 ef10_get_privilege_mask(
1176 __in efx_nic_t *enp,
1177 __out uint32_t *maskp);
1179 extern __checkReturn efx_rc_t
1180 ef10_external_port_mapping(
1181 __in efx_nic_t *enp,
1183 __out uint8_t *external_portp);
1185 #if EFSYS_OPT_RX_PACKED_STREAM
1187 /* Data space per credit in packed stream mode */
1188 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1191 * Received packets are always aligned at this boundary. Also there always
1192 * exists a gap of this size between packets.
1193 * (see SF-112241-TC, 4.5)
1195 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1198 * Size of a pseudo-header prepended to received packets
1199 * in packed stream mode
1201 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1203 /* Minimum space for packet in packed stream mode */
1204 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1205 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1207 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1208 EFX_RX_PACKED_STREAM_ALIGNMENT)
1210 /* Maximum number of credits */
1211 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1213 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1219 #endif /* _SYS_EF10_IMPL_H */