2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_EF10_IMPL_H
34 #define _SYS_EF10_IMPL_H
40 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
41 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
42 #elif EFSYS_OPT_HUNTINGTON
43 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
44 #elif EFSYS_OPT_MEDFORD
45 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
50 * possibly be increased, or the write size reported by newer firmware used
53 #define EF10_NVRAM_CHUNK 0x80
56 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
57 * to an 8 descriptor boundary.
59 #define EF10_RX_WPTR_ALIGN 8
62 * Max byte offset into the packet the TCP header must start for the hardware
63 * to be able to parse the packet correctly.
65 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
67 /* Invalid RSS context handle */
68 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
73 __checkReturn efx_rc_t
81 __checkReturn efx_rc_t
84 __in unsigned int index,
85 __in efsys_mem_t *esmp,
96 __checkReturn efx_rc_t
99 __in unsigned int count);
106 __checkReturn efx_rc_t
109 __in unsigned int us);
113 ef10_ev_qstats_update(
115 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
116 #endif /* EFSYS_OPT_QSTATS */
119 ef10_ev_rxlabel_init(
122 __in unsigned int label,
123 __in efx_rxq_type_t type);
126 ef10_ev_rxlabel_fini(
128 __in unsigned int label);
132 __checkReturn efx_rc_t
135 __in efx_intr_type_t type,
136 __in efsys_mem_t *esmp);
140 __in efx_nic_t *enp);
144 __in efx_nic_t *enp);
147 ef10_intr_disable_unlocked(
148 __in efx_nic_t *enp);
150 __checkReturn efx_rc_t
153 __in unsigned int level);
156 ef10_intr_status_line(
158 __out boolean_t *fatalp,
159 __out uint32_t *qmaskp);
162 ef10_intr_status_message(
164 __in unsigned int message,
165 __out boolean_t *fatalp);
169 __in efx_nic_t *enp);
172 __in efx_nic_t *enp);
176 extern __checkReturn efx_rc_t
178 __in efx_nic_t *enp);
180 extern __checkReturn efx_rc_t
181 ef10_nic_set_drv_limits(
182 __inout efx_nic_t *enp,
183 __in efx_drv_limits_t *edlp);
185 extern __checkReturn efx_rc_t
186 ef10_nic_get_vi_pool(
188 __out uint32_t *vi_countp);
190 extern __checkReturn efx_rc_t
191 ef10_nic_get_bar_region(
193 __in efx_nic_region_t region,
194 __out uint32_t *offsetp,
195 __out size_t *sizep);
197 extern __checkReturn efx_rc_t
199 __in efx_nic_t *enp);
201 extern __checkReturn efx_rc_t
203 __in efx_nic_t *enp);
207 extern __checkReturn efx_rc_t
208 ef10_nic_register_test(
209 __in efx_nic_t *enp);
211 #endif /* EFSYS_OPT_DIAG */
215 __in efx_nic_t *enp);
219 __in efx_nic_t *enp);
224 extern __checkReturn efx_rc_t
227 __out efx_link_mode_t *link_modep);
229 extern __checkReturn efx_rc_t
232 __out boolean_t *mac_upp);
234 extern __checkReturn efx_rc_t
236 __in efx_nic_t *enp);
238 extern __checkReturn efx_rc_t
240 __in efx_nic_t *enp);
242 extern __checkReturn efx_rc_t
247 extern __checkReturn efx_rc_t
248 ef10_mac_reconfigure(
249 __in efx_nic_t *enp);
251 extern __checkReturn efx_rc_t
252 ef10_mac_multicast_list_set(
253 __in efx_nic_t *enp);
255 extern __checkReturn efx_rc_t
256 ef10_mac_filter_default_rxq_set(
259 __in boolean_t using_rss);
262 ef10_mac_filter_default_rxq_clear(
263 __in efx_nic_t *enp);
265 #if EFSYS_OPT_LOOPBACK
267 extern __checkReturn efx_rc_t
268 ef10_mac_loopback_set(
270 __in efx_link_mode_t link_mode,
271 __in efx_loopback_type_t loopback_type);
273 #endif /* EFSYS_OPT_LOOPBACK */
275 #if EFSYS_OPT_MAC_STATS
277 extern __checkReturn efx_rc_t
278 ef10_mac_stats_get_mask(
280 __inout_bcount(mask_size) uint32_t *maskp,
281 __in size_t mask_size);
283 extern __checkReturn efx_rc_t
284 ef10_mac_stats_update(
286 __in efsys_mem_t *esmp,
287 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
288 __inout_opt uint32_t *generationp);
290 #endif /* EFSYS_OPT_MAC_STATS */
297 extern __checkReturn efx_rc_t
300 __in const efx_mcdi_transport_t *mtp);
304 __in efx_nic_t *enp);
307 ef10_mcdi_send_request(
309 __in_bcount(hdr_len) void *hdrp,
311 __in_bcount(sdu_len) void *sdup,
312 __in size_t sdu_len);
314 extern __checkReturn boolean_t
315 ef10_mcdi_poll_response(
316 __in efx_nic_t *enp);
319 ef10_mcdi_read_response(
321 __out_bcount(length) void *bufferp,
326 ef10_mcdi_poll_reboot(
327 __in efx_nic_t *enp);
329 extern __checkReturn efx_rc_t
330 ef10_mcdi_feature_supported(
332 __in efx_mcdi_feature_id_t id,
333 __out boolean_t *supportedp);
336 ef10_mcdi_get_timeout(
338 __in efx_mcdi_req_t *emrp,
339 __out uint32_t *timeoutp);
341 #endif /* EFSYS_OPT_MCDI */
345 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
347 extern __checkReturn efx_rc_t
348 ef10_nvram_buf_read_tlv(
350 __in_bcount(max_seg_size) caddr_t seg_data,
351 __in size_t max_seg_size,
353 __deref_out_bcount_opt(*sizep) caddr_t *datap,
354 __out size_t *sizep);
356 extern __checkReturn efx_rc_t
357 ef10_nvram_buf_write_tlv(
358 __inout_bcount(partn_size) caddr_t partn_data,
359 __in size_t partn_size,
361 __in_bcount(tag_size) caddr_t tag_data,
362 __in size_t tag_size,
363 __out size_t *total_lengthp);
365 extern __checkReturn efx_rc_t
366 ef10_nvram_partn_read_tlv(
370 __deref_out_bcount_opt(*sizep) caddr_t *datap,
371 __out size_t *sizep);
373 extern __checkReturn efx_rc_t
374 ef10_nvram_partn_write_tlv(
378 __in_bcount(size) caddr_t data,
381 extern __checkReturn efx_rc_t
382 ef10_nvram_partn_write_segment_tlv(
386 __in_bcount(size) caddr_t data,
388 __in boolean_t all_segments);
390 extern __checkReturn efx_rc_t
391 ef10_nvram_partn_lock(
393 __in uint32_t partn);
395 extern __checkReturn efx_rc_t
396 ef10_nvram_partn_unlock(
399 __out_opt uint32_t *resultp);
401 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
407 extern __checkReturn efx_rc_t
409 __in efx_nic_t *enp);
411 #endif /* EFSYS_OPT_DIAG */
413 extern __checkReturn efx_rc_t
414 ef10_nvram_type_to_partn(
416 __in efx_nvram_type_t type,
417 __out uint32_t *partnp);
419 extern __checkReturn efx_rc_t
420 ef10_nvram_partn_size(
423 __out size_t *sizep);
425 extern __checkReturn efx_rc_t
426 ef10_nvram_partn_rw_start(
429 __out size_t *chunk_sizep);
431 extern __checkReturn efx_rc_t
432 ef10_nvram_partn_read_mode(
435 __in unsigned int offset,
436 __out_bcount(size) caddr_t data,
440 extern __checkReturn efx_rc_t
441 ef10_nvram_partn_read(
444 __in unsigned int offset,
445 __out_bcount(size) caddr_t data,
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_read_backup(
452 __in unsigned int offset,
453 __out_bcount(size) caddr_t data,
456 extern __checkReturn efx_rc_t
457 ef10_nvram_partn_erase(
460 __in unsigned int offset,
463 extern __checkReturn efx_rc_t
464 ef10_nvram_partn_write(
467 __in unsigned int offset,
468 __out_bcount(size) caddr_t data,
471 extern __checkReturn efx_rc_t
472 ef10_nvram_partn_rw_finish(
475 __out_opt uint32_t *verify_resultp);
477 extern __checkReturn efx_rc_t
478 ef10_nvram_partn_get_version(
481 __out uint32_t *subtypep,
482 __out_ecount(4) uint16_t version[4]);
484 extern __checkReturn efx_rc_t
485 ef10_nvram_partn_set_version(
488 __in_ecount(4) uint16_t version[4]);
490 extern __checkReturn efx_rc_t
491 ef10_nvram_buffer_validate(
494 __in_bcount(buffer_size)
496 __in size_t buffer_size);
498 extern __checkReturn efx_rc_t
499 ef10_nvram_buffer_create(
501 __in uint16_t partn_type,
502 __in_bcount(buffer_size)
504 __in size_t buffer_size);
506 extern __checkReturn efx_rc_t
507 ef10_nvram_buffer_find_item_start(
508 __in_bcount(buffer_size)
510 __in size_t buffer_size,
511 __out uint32_t *startp);
513 extern __checkReturn efx_rc_t
514 ef10_nvram_buffer_find_end(
515 __in_bcount(buffer_size)
517 __in size_t buffer_size,
518 __in uint32_t offset,
519 __out uint32_t *endp);
521 extern __checkReturn __success(return != B_FALSE) boolean_t
522 ef10_nvram_buffer_find_item(
523 __in_bcount(buffer_size)
525 __in size_t buffer_size,
526 __in uint32_t offset,
527 __out uint32_t *startp,
528 __out uint32_t *lengthp);
530 extern __checkReturn efx_rc_t
531 ef10_nvram_buffer_get_item(
532 __in_bcount(buffer_size)
534 __in size_t buffer_size,
535 __in uint32_t offset,
536 __in uint32_t length,
537 __out_bcount_part(item_max_size, *lengthp)
539 __in size_t item_max_size,
540 __out uint32_t *lengthp);
542 extern __checkReturn efx_rc_t
543 ef10_nvram_buffer_insert_item(
544 __in_bcount(buffer_size)
546 __in size_t buffer_size,
547 __in uint32_t offset,
548 __in_bcount(length) caddr_t keyp,
549 __in uint32_t length,
550 __out uint32_t *lengthp);
552 extern __checkReturn efx_rc_t
553 ef10_nvram_buffer_delete_item(
554 __in_bcount(buffer_size)
556 __in size_t buffer_size,
557 __in uint32_t offset,
558 __in uint32_t length,
561 extern __checkReturn efx_rc_t
562 ef10_nvram_buffer_finish(
563 __in_bcount(buffer_size)
565 __in size_t buffer_size);
567 #endif /* EFSYS_OPT_NVRAM */
572 typedef struct ef10_link_state_s {
573 uint32_t els_adv_cap_mask;
574 uint32_t els_lp_cap_mask;
575 unsigned int els_fcntl;
576 efx_link_mode_t els_link_mode;
577 #if EFSYS_OPT_LOOPBACK
578 efx_loopback_type_t els_loopback;
580 boolean_t els_mac_up;
586 __in efx_qword_t *eqp,
587 __out efx_link_mode_t *link_modep);
589 extern __checkReturn efx_rc_t
592 __out ef10_link_state_t *elsp);
594 extern __checkReturn efx_rc_t
599 extern __checkReturn efx_rc_t
600 ef10_phy_reconfigure(
601 __in efx_nic_t *enp);
603 extern __checkReturn efx_rc_t
605 __in efx_nic_t *enp);
607 extern __checkReturn efx_rc_t
610 __out uint32_t *ouip);
612 #if EFSYS_OPT_PHY_STATS
614 extern __checkReturn efx_rc_t
615 ef10_phy_stats_update(
617 __in efsys_mem_t *esmp,
618 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
620 #endif /* EFSYS_OPT_PHY_STATS */
624 extern __checkReturn efx_rc_t
625 ef10_bist_enable_offline(
626 __in efx_nic_t *enp);
628 extern __checkReturn efx_rc_t
631 __in efx_bist_type_t type);
633 extern __checkReturn efx_rc_t
636 __in efx_bist_type_t type,
637 __out efx_bist_result_t *resultp,
638 __out_opt __drv_when(count > 0, __notnull)
639 uint32_t *value_maskp,
640 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
641 unsigned long *valuesp,
647 __in efx_bist_type_t type);
649 #endif /* EFSYS_OPT_BIST */
653 extern __checkReturn efx_rc_t
655 __in efx_nic_t *enp);
659 __in efx_nic_t *enp);
661 extern __checkReturn efx_rc_t
664 __in unsigned int index,
665 __in unsigned int label,
666 __in efsys_mem_t *esmp,
672 __out unsigned int *addedp);
676 __in efx_txq_t *etp);
678 extern __checkReturn efx_rc_t
681 __in_ecount(ndescs) efx_buffer_t *ebp,
682 __in unsigned int ndescs,
683 __in unsigned int completed,
684 __inout unsigned int *addedp);
689 __in unsigned int added,
690 __in unsigned int pushed);
692 #if EFSYS_OPT_RX_PACKED_STREAM
694 ef10_rx_qpush_ps_credits(
695 __in efx_rxq_t *erp);
697 extern __checkReturn uint8_t *
698 ef10_rx_qps_packet_info(
700 __in uint8_t *buffer,
701 __in uint32_t buffer_length,
702 __in uint32_t current_offset,
703 __out uint16_t *lengthp,
704 __out uint32_t *next_offsetp,
705 __out uint32_t *timestamp);
708 extern __checkReturn efx_rc_t
711 __in unsigned int ns);
713 extern __checkReturn efx_rc_t
715 __in efx_txq_t *etp);
719 __in efx_txq_t *etp);
721 extern __checkReturn efx_rc_t
723 __in efx_txq_t *etp);
726 ef10_tx_qpio_disable(
727 __in efx_txq_t *etp);
729 extern __checkReturn efx_rc_t
732 __in_ecount(buf_length) uint8_t *buffer,
733 __in size_t buf_length,
734 __in size_t pio_buf_offset);
736 extern __checkReturn efx_rc_t
739 __in size_t pkt_length,
740 __in unsigned int completed,
741 __inout unsigned int *addedp);
743 extern __checkReturn efx_rc_t
746 __in_ecount(n) efx_desc_t *ed,
748 __in unsigned int completed,
749 __inout unsigned int *addedp);
752 ef10_tx_qdesc_dma_create(
754 __in efsys_dma_addr_t addr,
757 __out efx_desc_t *edp);
760 ef10_tx_qdesc_tso_create(
762 __in uint16_t ipv4_id,
763 __in uint32_t tcp_seq,
764 __in uint8_t tcp_flags,
765 __out efx_desc_t *edp);
768 ef10_tx_qdesc_tso2_create(
770 __in uint16_t ipv4_id,
771 __in uint32_t tcp_seq,
772 __in uint16_t tcp_mss,
773 __out_ecount(count) efx_desc_t *edp,
777 ef10_tx_qdesc_vlantci_create(
779 __in uint16_t vlan_tci,
780 __out efx_desc_t *edp);
786 ef10_tx_qstats_update(
788 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
790 #endif /* EFSYS_OPT_QSTATS */
792 typedef uint32_t efx_piobuf_handle_t;
794 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
796 extern __checkReturn efx_rc_t
798 __inout efx_nic_t *enp,
799 __out uint32_t *bufnump,
800 __out efx_piobuf_handle_t *handlep,
801 __out uint32_t *blknump,
802 __out uint32_t *offsetp,
803 __out size_t *sizep);
805 extern __checkReturn efx_rc_t
807 __inout efx_nic_t *enp,
808 __in uint32_t bufnum,
809 __in uint32_t blknum);
811 extern __checkReturn efx_rc_t
813 __inout efx_nic_t *enp,
814 __in uint32_t vi_index,
815 __in efx_piobuf_handle_t handle);
817 extern __checkReturn efx_rc_t
819 __inout efx_nic_t *enp,
820 __in uint32_t vi_index);
827 extern __checkReturn efx_rc_t
829 __in efx_nic_t *enp);
831 extern __checkReturn efx_rc_t
834 __out size_t *sizep);
836 extern __checkReturn efx_rc_t
839 __out_bcount(size) caddr_t data,
842 extern __checkReturn efx_rc_t
845 __in_bcount(size) caddr_t data,
848 extern __checkReturn efx_rc_t
851 __in_bcount(size) caddr_t data,
854 extern __checkReturn efx_rc_t
857 __in_bcount(size) caddr_t data,
859 __inout efx_vpd_value_t *evvp);
861 extern __checkReturn efx_rc_t
864 __in_bcount(size) caddr_t data,
866 __in efx_vpd_value_t *evvp);
868 extern __checkReturn efx_rc_t
871 __in_bcount(size) caddr_t data,
873 __out efx_vpd_value_t *evvp,
874 __inout unsigned int *contp);
876 extern __checkReturn efx_rc_t
879 __in_bcount(size) caddr_t data,
884 __in efx_nic_t *enp);
886 #endif /* EFSYS_OPT_VPD */
891 extern __checkReturn efx_rc_t
893 __in efx_nic_t *enp);
895 #if EFSYS_OPT_RX_SCATTER
896 extern __checkReturn efx_rc_t
897 ef10_rx_scatter_enable(
899 __in unsigned int buf_size);
900 #endif /* EFSYS_OPT_RX_SCATTER */
903 #if EFSYS_OPT_RX_SCALE
905 extern __checkReturn efx_rc_t
906 ef10_rx_scale_context_alloc(
908 __in efx_rx_scale_context_type_t type,
909 __in uint32_t num_queues,
910 __out uint32_t *rss_contextp);
912 extern __checkReturn efx_rc_t
913 ef10_rx_scale_context_free(
915 __in uint32_t rss_context);
917 extern __checkReturn efx_rc_t
918 ef10_rx_scale_mode_set(
920 __in uint32_t rss_context,
921 __in efx_rx_hash_alg_t alg,
922 __in efx_rx_hash_type_t type,
923 __in boolean_t insert);
925 extern __checkReturn efx_rc_t
926 ef10_rx_scale_key_set(
928 __in uint32_t rss_context,
929 __in_ecount(n) uint8_t *key,
932 extern __checkReturn efx_rc_t
933 ef10_rx_scale_tbl_set(
935 __in uint32_t rss_context,
936 __in_ecount(n) unsigned int *table,
939 extern __checkReturn uint32_t
942 __in efx_rx_hash_alg_t func,
943 __in uint8_t *buffer);
945 #endif /* EFSYS_OPT_RX_SCALE */
947 extern __checkReturn efx_rc_t
948 ef10_rx_prefix_pktlen(
950 __in uint8_t *buffer,
951 __out uint16_t *lengthp);
956 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
958 __in unsigned int ndescs,
959 __in unsigned int completed,
960 __in unsigned int added);
965 __in unsigned int added,
966 __inout unsigned int *pushedp);
968 extern __checkReturn efx_rc_t
970 __in efx_rxq_t *erp);
974 __in efx_rxq_t *erp);
976 extern __checkReturn efx_rc_t
979 __in unsigned int index,
980 __in unsigned int label,
981 __in efx_rxq_type_t type,
982 __in efsys_mem_t *esmp,
985 __in unsigned int flags,
987 __in efx_rxq_t *erp);
991 __in efx_rxq_t *erp);
995 __in efx_nic_t *enp);
999 typedef struct ef10_filter_handle_s {
1002 } ef10_filter_handle_t;
1004 typedef struct ef10_filter_entry_s {
1005 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1006 ef10_filter_handle_t efe_handle;
1007 } ef10_filter_entry_t;
1010 * BUSY flag indicates that an update is in progress.
1011 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1013 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1014 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1015 #define EFX_EF10_FILTER_FLAGS 3U
1018 * Size of the hash table used by the driver. Doesn't need to be the
1019 * same size as the hardware's table.
1021 #define EFX_EF10_FILTER_TBL_ROWS 8192
1023 /* Only need to allow for one directed and one unknown unicast filter */
1024 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1026 /* Allow for the broadcast address to be added to the multicast list */
1027 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1030 * For encapsulated packets, there is one filter each for each combination of
1031 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1032 * multicast inner frames.
1034 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1036 typedef struct ef10_filter_table_s {
1037 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1038 efx_rxq_t *eft_default_rxq;
1039 boolean_t eft_using_rss;
1040 uint32_t eft_unicst_filter_indexes[
1041 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1042 uint32_t eft_unicst_filter_count;
1043 uint32_t eft_mulcst_filter_indexes[
1044 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1045 uint32_t eft_mulcst_filter_count;
1046 boolean_t eft_using_all_mulcst;
1047 uint32_t eft_encap_filter_indexes[
1048 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1049 uint32_t eft_encap_filter_count;
1050 } ef10_filter_table_t;
1052 __checkReturn efx_rc_t
1054 __in efx_nic_t *enp);
1058 __in efx_nic_t *enp);
1060 __checkReturn efx_rc_t
1061 ef10_filter_restore(
1062 __in efx_nic_t *enp);
1064 __checkReturn efx_rc_t
1066 __in efx_nic_t *enp,
1067 __inout efx_filter_spec_t *spec,
1068 __in boolean_t may_replace);
1070 __checkReturn efx_rc_t
1072 __in efx_nic_t *enp,
1073 __inout efx_filter_spec_t *spec);
1075 extern __checkReturn efx_rc_t
1076 ef10_filter_supported_filters(
1077 __in efx_nic_t *enp,
1078 __out_ecount(buffer_length) uint32_t *buffer,
1079 __in size_t buffer_length,
1080 __out size_t *list_lengthp);
1082 extern __checkReturn efx_rc_t
1083 ef10_filter_reconfigure(
1084 __in efx_nic_t *enp,
1085 __in_ecount(6) uint8_t const *mac_addr,
1086 __in boolean_t all_unicst,
1087 __in boolean_t mulcst,
1088 __in boolean_t all_mulcst,
1089 __in boolean_t brdcst,
1090 __in_ecount(6*count) uint8_t const *addrs,
1091 __in uint32_t count);
1094 ef10_filter_get_default_rxq(
1095 __in efx_nic_t *enp,
1096 __out efx_rxq_t **erpp,
1097 __out boolean_t *using_rss);
1100 ef10_filter_default_rxq_set(
1101 __in efx_nic_t *enp,
1102 __in efx_rxq_t *erp,
1103 __in boolean_t using_rss);
1106 ef10_filter_default_rxq_clear(
1107 __in efx_nic_t *enp);
1110 #endif /* EFSYS_OPT_FILTER */
1112 extern __checkReturn efx_rc_t
1113 efx_mcdi_get_function_info(
1114 __in efx_nic_t *enp,
1115 __out uint32_t *pfp,
1116 __out_opt uint32_t *vfp);
1118 extern __checkReturn efx_rc_t
1119 efx_mcdi_privilege_mask(
1120 __in efx_nic_t *enp,
1123 __out uint32_t *maskp);
1125 extern __checkReturn efx_rc_t
1126 efx_mcdi_get_port_assignment(
1127 __in efx_nic_t *enp,
1128 __out uint32_t *portp);
1130 extern __checkReturn efx_rc_t
1131 efx_mcdi_get_port_modes(
1132 __in efx_nic_t *enp,
1133 __out uint32_t *modesp,
1134 __out_opt uint32_t *current_modep);
1136 extern __checkReturn efx_rc_t
1137 ef10_nic_get_port_mode_bandwidth(
1138 __in uint32_t port_mode,
1139 __out uint32_t *bandwidth_mbpsp);
1141 extern __checkReturn efx_rc_t
1142 efx_mcdi_get_mac_address_pf(
1143 __in efx_nic_t *enp,
1144 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1146 extern __checkReturn efx_rc_t
1147 efx_mcdi_get_mac_address_vf(
1148 __in efx_nic_t *enp,
1149 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1151 extern __checkReturn efx_rc_t
1153 __in efx_nic_t *enp,
1154 __out uint32_t *sys_freqp,
1155 __out uint32_t *dpcpu_freqp);
1158 extern __checkReturn efx_rc_t
1159 efx_mcdi_get_vector_cfg(
1160 __in efx_nic_t *enp,
1161 __out_opt uint32_t *vec_basep,
1162 __out_opt uint32_t *pf_nvecp,
1163 __out_opt uint32_t *vf_nvecp);
1165 extern __checkReturn efx_rc_t
1166 ef10_get_datapath_caps(
1167 __in efx_nic_t *enp);
1169 extern __checkReturn efx_rc_t
1170 ef10_get_privilege_mask(
1171 __in efx_nic_t *enp,
1172 __out uint32_t *maskp);
1174 extern __checkReturn efx_rc_t
1175 ef10_external_port_mapping(
1176 __in efx_nic_t *enp,
1178 __out uint8_t *external_portp);
1180 #if EFSYS_OPT_RX_PACKED_STREAM
1182 /* Data space per credit in packed stream mode */
1183 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1186 * Received packets are always aligned at this boundary. Also there always
1187 * exists a gap of this size between packets.
1188 * (see SF-112241-TC, 4.5)
1190 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1193 * Size of a pseudo-header prepended to received packets
1194 * in packed stream mode
1196 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1198 /* Minimum space for packet in packed stream mode */
1199 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1200 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1202 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1203 EFX_RX_PACKED_STREAM_ALIGNMENT)
1205 /* Maximum number of credits */
1206 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1208 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1214 #endif /* _SYS_EF10_IMPL_H */