2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD ||
56 enp->en_family == EFX_FAMILY_MEDFORD2);
58 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
59 req.emr_in_buf = payload;
60 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
61 req.emr_out_buf = payload;
62 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
64 efx_mcdi_execute(enp, &req);
66 if (req.emr_rc != 0) {
71 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
76 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
83 EFSYS_PROBE1(fail1, efx_rc_t, rc);
88 __checkReturn efx_rc_t
89 efx_mcdi_get_port_modes(
91 __out uint32_t *modesp,
92 __out_opt uint32_t *current_modep,
93 __out_opt uint32_t *default_modep)
96 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
97 MC_CMD_GET_PORT_MODES_OUT_LEN);
100 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
101 enp->en_family == EFX_FAMILY_MEDFORD ||
102 enp->en_family == EFX_FAMILY_MEDFORD2);
104 req.emr_cmd = MC_CMD_GET_PORT_MODES;
105 req.emr_in_buf = payload;
106 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
107 req.emr_out_buf = payload;
108 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
110 efx_mcdi_execute(enp, &req);
112 if (req.emr_rc != 0) {
118 * Require only Modes and DefaultMode fields, unless the current mode
119 * was requested (CurrentMode field was added for Medford).
121 if (req.emr_out_length_used <
122 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
126 if ((current_modep != NULL) && (req.emr_out_length_used <
127 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
132 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
134 if (current_modep != NULL) {
135 *current_modep = MCDI_OUT_DWORD(req,
136 GET_PORT_MODES_OUT_CURRENT_MODE);
139 if (default_modep != NULL) {
140 *default_modep = MCDI_OUT_DWORD(req,
141 GET_PORT_MODES_OUT_DEFAULT_MODE);
151 EFSYS_PROBE1(fail1, efx_rc_t, rc);
156 __checkReturn efx_rc_t
157 ef10_nic_get_port_mode_bandwidth(
159 __out uint32_t *bandwidth_mbpsp)
162 uint32_t current_mode;
163 efx_port_t *epp = &(enp->en_port);
165 uint32_t single_lane;
171 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
172 ¤t_mode, NULL)) != 0) {
173 /* No port mode info available. */
177 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
182 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
187 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
192 switch (current_mode) {
193 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
194 bandwidth = single_lane;
196 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
197 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
198 bandwidth = dual_lane;
200 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
201 bandwidth = single_lane + single_lane;
203 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
204 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
205 bandwidth = 4 * single_lane;
207 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
208 bandwidth = (2 * single_lane) + (2 * single_lane);
210 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
211 bandwidth = dual_lane + dual_lane;
213 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
214 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
215 bandwidth = dual_lane + (2 * single_lane);
217 /* Legacy Medford-only mode. Do not use (see bug63270) */
218 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
219 bandwidth = 4 * single_lane;
221 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
222 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
223 bandwidth = quad_lane;
225 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
226 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
227 bandwidth = 2 * dual_lane;
229 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
230 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
231 bandwidth = quad_lane + (2 * single_lane);
233 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
234 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
235 bandwidth = quad_lane + dual_lane;
237 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
238 bandwidth = quad_lane + quad_lane;
245 *bandwidth_mbpsp = bandwidth;
252 EFSYS_PROBE1(fail1, efx_rc_t, rc);
257 static __checkReturn efx_rc_t
258 efx_mcdi_vadaptor_alloc(
260 __in uint32_t port_id)
263 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
264 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
267 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
269 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
270 req.emr_in_buf = payload;
271 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
272 req.emr_out_buf = payload;
273 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
275 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
276 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
277 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
278 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
280 efx_mcdi_execute(enp, &req);
282 if (req.emr_rc != 0) {
290 EFSYS_PROBE1(fail1, efx_rc_t, rc);
295 static __checkReturn efx_rc_t
296 efx_mcdi_vadaptor_free(
298 __in uint32_t port_id)
301 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
302 MC_CMD_VADAPTOR_FREE_OUT_LEN);
305 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
306 req.emr_in_buf = payload;
307 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
308 req.emr_out_buf = payload;
309 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
311 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
313 efx_mcdi_execute(enp, &req);
315 if (req.emr_rc != 0) {
323 EFSYS_PROBE1(fail1, efx_rc_t, rc);
328 __checkReturn efx_rc_t
329 efx_mcdi_get_mac_address_pf(
331 __out_ecount_opt(6) uint8_t mac_addrp[6])
334 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
335 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
338 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
339 enp->en_family == EFX_FAMILY_MEDFORD ||
340 enp->en_family == EFX_FAMILY_MEDFORD2);
342 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
343 req.emr_in_buf = payload;
344 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
345 req.emr_out_buf = payload;
346 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
348 efx_mcdi_execute(enp, &req);
350 if (req.emr_rc != 0) {
355 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
360 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
365 if (mac_addrp != NULL) {
368 addrp = MCDI_OUT2(req, uint8_t,
369 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
371 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
381 EFSYS_PROBE1(fail1, efx_rc_t, rc);
386 __checkReturn efx_rc_t
387 efx_mcdi_get_mac_address_vf(
389 __out_ecount_opt(6) uint8_t mac_addrp[6])
392 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
393 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
396 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
397 enp->en_family == EFX_FAMILY_MEDFORD ||
398 enp->en_family == EFX_FAMILY_MEDFORD2);
400 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
401 req.emr_in_buf = payload;
402 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
403 req.emr_out_buf = payload;
404 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
406 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
407 EVB_PORT_ID_ASSIGNED);
409 efx_mcdi_execute(enp, &req);
411 if (req.emr_rc != 0) {
416 if (req.emr_out_length_used <
417 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
422 if (MCDI_OUT_DWORD(req,
423 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
428 if (mac_addrp != NULL) {
431 addrp = MCDI_OUT2(req, uint8_t,
432 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
434 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
444 EFSYS_PROBE1(fail1, efx_rc_t, rc);
449 __checkReturn efx_rc_t
452 __out uint32_t *sys_freqp,
453 __out uint32_t *dpcpu_freqp)
456 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
457 MC_CMD_GET_CLOCK_OUT_LEN);
460 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
461 enp->en_family == EFX_FAMILY_MEDFORD ||
462 enp->en_family == EFX_FAMILY_MEDFORD2);
464 req.emr_cmd = MC_CMD_GET_CLOCK;
465 req.emr_in_buf = payload;
466 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
467 req.emr_out_buf = payload;
468 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
470 efx_mcdi_execute(enp, &req);
472 if (req.emr_rc != 0) {
477 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
482 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
483 if (*sys_freqp == 0) {
487 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
488 if (*dpcpu_freqp == 0) {
502 EFSYS_PROBE1(fail1, efx_rc_t, rc);
507 __checkReturn efx_rc_t
508 efx_mcdi_get_rxdp_config(
510 __out uint32_t *end_paddingp)
513 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
514 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
515 uint32_t end_padding;
518 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
519 req.emr_in_buf = payload;
520 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
521 req.emr_out_buf = payload;
522 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
524 efx_mcdi_execute(enp, &req);
525 if (req.emr_rc != 0) {
530 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
531 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
532 /* RX DMA end padding is disabled */
535 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
536 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
537 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
540 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
543 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
552 *end_paddingp = end_padding;
559 EFSYS_PROBE1(fail1, efx_rc_t, rc);
564 __checkReturn efx_rc_t
565 efx_mcdi_get_vector_cfg(
567 __out_opt uint32_t *vec_basep,
568 __out_opt uint32_t *pf_nvecp,
569 __out_opt uint32_t *vf_nvecp)
572 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
573 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
576 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
577 req.emr_in_buf = payload;
578 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
579 req.emr_out_buf = payload;
580 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
582 efx_mcdi_execute(enp, &req);
584 if (req.emr_rc != 0) {
589 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
594 if (vec_basep != NULL)
595 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
596 if (pf_nvecp != NULL)
597 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
598 if (vf_nvecp != NULL)
599 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
606 EFSYS_PROBE1(fail1, efx_rc_t, rc);
611 static __checkReturn efx_rc_t
614 __in uint32_t min_vi_count,
615 __in uint32_t max_vi_count,
616 __out uint32_t *vi_basep,
617 __out uint32_t *vi_countp,
618 __out uint32_t *vi_shiftp)
621 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
622 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
625 if (vi_countp == NULL) {
630 req.emr_cmd = MC_CMD_ALLOC_VIS;
631 req.emr_in_buf = payload;
632 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
633 req.emr_out_buf = payload;
634 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
636 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
637 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
639 efx_mcdi_execute(enp, &req);
641 if (req.emr_rc != 0) {
646 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
651 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
652 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
654 /* Report VI_SHIFT if available (always zero for Huntington) */
655 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
658 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
667 EFSYS_PROBE1(fail1, efx_rc_t, rc);
672 static __checkReturn efx_rc_t
679 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
680 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
682 req.emr_cmd = MC_CMD_FREE_VIS;
683 req.emr_in_buf = NULL;
684 req.emr_in_length = 0;
685 req.emr_out_buf = NULL;
686 req.emr_out_length = 0;
688 efx_mcdi_execute_quiet(enp, &req);
690 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
691 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
699 EFSYS_PROBE1(fail1, efx_rc_t, rc);
704 static __checkReturn efx_rc_t
705 efx_mcdi_alloc_piobuf(
707 __out efx_piobuf_handle_t *handlep)
710 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
711 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
714 if (handlep == NULL) {
719 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
720 req.emr_in_buf = payload;
721 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
722 req.emr_out_buf = payload;
723 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
725 efx_mcdi_execute_quiet(enp, &req);
727 if (req.emr_rc != 0) {
732 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
737 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
746 EFSYS_PROBE1(fail1, efx_rc_t, rc);
751 static __checkReturn efx_rc_t
752 efx_mcdi_free_piobuf(
754 __in efx_piobuf_handle_t handle)
757 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
758 MC_CMD_FREE_PIOBUF_OUT_LEN);
761 req.emr_cmd = MC_CMD_FREE_PIOBUF;
762 req.emr_in_buf = payload;
763 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
764 req.emr_out_buf = payload;
765 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
767 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
769 efx_mcdi_execute_quiet(enp, &req);
771 if (req.emr_rc != 0) {
779 EFSYS_PROBE1(fail1, efx_rc_t, rc);
784 static __checkReturn efx_rc_t
785 efx_mcdi_link_piobuf(
787 __in uint32_t vi_index,
788 __in efx_piobuf_handle_t handle)
791 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
792 MC_CMD_LINK_PIOBUF_OUT_LEN);
795 req.emr_cmd = MC_CMD_LINK_PIOBUF;
796 req.emr_in_buf = payload;
797 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
798 req.emr_out_buf = payload;
799 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
801 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
802 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
804 efx_mcdi_execute(enp, &req);
806 if (req.emr_rc != 0) {
814 EFSYS_PROBE1(fail1, efx_rc_t, rc);
819 static __checkReturn efx_rc_t
820 efx_mcdi_unlink_piobuf(
822 __in uint32_t vi_index)
825 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
826 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
829 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
830 req.emr_in_buf = payload;
831 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
832 req.emr_out_buf = payload;
833 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
835 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
837 efx_mcdi_execute_quiet(enp, &req);
839 if (req.emr_rc != 0) {
847 EFSYS_PROBE1(fail1, efx_rc_t, rc);
853 ef10_nic_alloc_piobufs(
855 __in uint32_t max_piobuf_count)
857 efx_piobuf_handle_t *handlep;
860 EFSYS_ASSERT3U(max_piobuf_count, <=,
861 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
863 enp->en_arch.ef10.ena_piobuf_count = 0;
865 for (i = 0; i < max_piobuf_count; i++) {
866 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
868 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
871 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
872 enp->en_arch.ef10.ena_piobuf_count++;
878 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
879 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
881 (void) efx_mcdi_free_piobuf(enp, *handlep);
882 *handlep = EFX_PIOBUF_HANDLE_INVALID;
884 enp->en_arch.ef10.ena_piobuf_count = 0;
888 ef10_nic_free_piobufs(
891 efx_piobuf_handle_t *handlep;
894 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
895 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
897 (void) efx_mcdi_free_piobuf(enp, *handlep);
898 *handlep = EFX_PIOBUF_HANDLE_INVALID;
900 enp->en_arch.ef10.ena_piobuf_count = 0;
903 /* Sub-allocate a block from a piobuf */
904 __checkReturn efx_rc_t
906 __inout efx_nic_t *enp,
907 __out uint32_t *bufnump,
908 __out efx_piobuf_handle_t *handlep,
909 __out uint32_t *blknump,
910 __out uint32_t *offsetp,
913 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
914 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
915 uint32_t blk_per_buf;
919 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
920 enp->en_family == EFX_FAMILY_MEDFORD ||
921 enp->en_family == EFX_FAMILY_MEDFORD2);
922 EFSYS_ASSERT(bufnump);
923 EFSYS_ASSERT(handlep);
924 EFSYS_ASSERT(blknump);
925 EFSYS_ASSERT(offsetp);
928 if ((edcp->edc_pio_alloc_size == 0) ||
929 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
933 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
935 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
936 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
941 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
942 for (blk = 0; blk < blk_per_buf; blk++) {
943 if ((*map & (1u << blk)) == 0) {
953 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
956 *sizep = edcp->edc_pio_alloc_size;
957 *offsetp = blk * (*sizep);
964 EFSYS_PROBE1(fail1, efx_rc_t, rc);
969 /* Free a piobuf sub-allocated block */
970 __checkReturn efx_rc_t
972 __inout efx_nic_t *enp,
973 __in uint32_t bufnum,
974 __in uint32_t blknum)
979 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
980 (blknum >= (8 * sizeof (*map)))) {
985 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
986 if ((*map & (1u << blknum)) == 0) {
990 *map &= ~(1u << blknum);
997 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1002 __checkReturn efx_rc_t
1004 __inout efx_nic_t *enp,
1005 __in uint32_t vi_index,
1006 __in efx_piobuf_handle_t handle)
1008 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
1011 __checkReturn efx_rc_t
1012 ef10_nic_pio_unlink(
1013 __inout efx_nic_t *enp,
1014 __in uint32_t vi_index)
1016 return (efx_mcdi_unlink_piobuf(enp, vi_index));
1019 static __checkReturn efx_rc_t
1020 ef10_mcdi_get_pf_count(
1021 __in efx_nic_t *enp,
1022 __out uint32_t *pf_countp)
1025 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
1026 MC_CMD_GET_PF_COUNT_OUT_LEN);
1029 req.emr_cmd = MC_CMD_GET_PF_COUNT;
1030 req.emr_in_buf = payload;
1031 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
1032 req.emr_out_buf = payload;
1033 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
1035 efx_mcdi_execute(enp, &req);
1037 if (req.emr_rc != 0) {
1042 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1047 *pf_countp = *MCDI_OUT(req, uint8_t,
1048 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1050 EFSYS_ASSERT(*pf_countp != 0);
1057 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1062 static __checkReturn efx_rc_t
1063 ef10_get_datapath_caps(
1064 __in efx_nic_t *enp)
1066 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1068 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1069 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1072 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1075 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1076 req.emr_in_buf = payload;
1077 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1078 req.emr_out_buf = payload;
1079 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1081 efx_mcdi_execute_quiet(enp, &req);
1083 if (req.emr_rc != 0) {
1088 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1093 #define CAP_FLAGS1(_req, _flag) \
1094 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1095 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1097 #define CAP_FLAGS2(_req, _flag) \
1098 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1099 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1100 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1103 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1104 * We only support the 14 byte prefix here.
1106 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1110 encp->enc_rx_prefix_size = 14;
1112 #if EFSYS_OPT_RX_SCALE
1113 /* Check if the firmware supports additional RSS modes */
1114 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1115 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1117 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1118 #endif /* EFSYS_OPT_RX_SCALE */
1120 /* Check if the firmware supports TSO */
1121 if (CAP_FLAGS1(req, TX_TSO))
1122 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1124 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1126 /* Check if the firmware supports FATSOv2 */
1127 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1128 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1129 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1130 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1132 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1133 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1136 /* Check if the firmware supports FATSOv2 encap */
1137 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1138 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1140 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1142 /* Check if the firmware has vadapter/vport/vswitch support */
1143 if (CAP_FLAGS1(req, EVB))
1144 encp->enc_datapath_cap_evb = B_TRUE;
1146 encp->enc_datapath_cap_evb = B_FALSE;
1148 /* Check if the firmware supports VLAN insertion */
1149 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1150 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1152 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1154 /* Check if the firmware supports RX event batching */
1155 if (CAP_FLAGS1(req, RX_BATCHING))
1156 encp->enc_rx_batching_enabled = B_TRUE;
1158 encp->enc_rx_batching_enabled = B_FALSE;
1161 * Even if batching isn't reported as supported, we may still get
1164 encp->enc_rx_batch_max = 16;
1166 /* Check if the firmware supports disabling scatter on RXQs */
1167 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1168 encp->enc_rx_disable_scatter_supported = B_TRUE;
1170 encp->enc_rx_disable_scatter_supported = B_FALSE;
1172 /* Check if the firmware supports packed stream mode */
1173 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1174 encp->enc_rx_packed_stream_supported = B_TRUE;
1176 encp->enc_rx_packed_stream_supported = B_FALSE;
1179 * Check if the firmware supports configurable buffer sizes
1180 * for packed stream mode (otherwise buffer size is 1Mbyte)
1182 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1183 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1185 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1187 /* Check if the firmware supports equal stride super-buffer mode */
1188 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1189 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1191 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1193 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1194 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1195 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1197 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1199 /* Check if the firmware supports set mac with running filters */
1200 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1201 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1203 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1206 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1207 * specifying which parameters to configure.
1209 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1210 encp->enc_enhanced_set_mac_supported = B_TRUE;
1212 encp->enc_enhanced_set_mac_supported = B_FALSE;
1215 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1216 * us to let the firmware choose the settings to use on an EVQ.
1218 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1219 encp->enc_init_evq_v2_supported = B_TRUE;
1221 encp->enc_init_evq_v2_supported = B_FALSE;
1224 * Check if firmware-verified NVRAM updates must be used.
1226 * The firmware trusted installer requires all NVRAM updates to use
1227 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1228 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1229 * partition and report the result).
1231 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1232 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1234 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1237 * Check if firmware provides packet memory and Rx datapath
1240 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1241 encp->enc_pm_and_rxdp_counters = B_TRUE;
1243 encp->enc_pm_and_rxdp_counters = B_FALSE;
1246 * Check if the 40G MAC hardware is capable of reporting
1247 * statistics for Tx size bins.
1249 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1250 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1252 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1255 * Check if firmware supports VXLAN and NVGRE tunnels.
1256 * The capability indicates Geneve protocol support as well.
1258 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1259 encp->enc_tunnel_encapsulations_supported =
1260 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1261 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1262 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1264 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1265 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1266 encp->enc_tunnel_config_udp_entries_max =
1267 EFX_TUNNEL_MAXNENTRIES;
1269 encp->enc_tunnel_config_udp_entries_max = 0;
1273 * Check if firmware reports the VI window mode.
1274 * Medford2 has a variable VI window size (8K, 16K or 64K).
1275 * Medford and Huntington have a fixed 8K VI window size.
1277 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1279 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1282 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1283 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1285 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1286 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1288 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1289 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1292 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1295 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1296 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1297 /* Huntington and Medford have fixed 8K window size */
1298 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1300 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1303 /* Check if firmware supports extended MAC stats. */
1304 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1305 /* Extended stats buffer supported */
1306 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1307 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1309 /* Use Siena-compatible legacy MAC stats */
1310 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1313 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1314 encp->enc_fec_counters = B_TRUE;
1316 encp->enc_fec_counters = B_FALSE;
1318 /* Check if the firmware provides head-of-line blocking counters */
1319 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1320 encp->enc_hlb_counters = B_TRUE;
1322 encp->enc_hlb_counters = B_FALSE;
1324 #if EFSYS_OPT_RX_SCALE
1325 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1326 /* Only one exclusive RSS context is available per port. */
1327 encp->enc_rx_scale_max_exclusive_contexts = 1;
1329 switch (enp->en_family) {
1330 case EFX_FAMILY_MEDFORD2:
1331 encp->enc_rx_scale_hash_alg_mask =
1332 (1U << EFX_RX_HASHALG_TOEPLITZ);
1335 case EFX_FAMILY_MEDFORD:
1336 case EFX_FAMILY_HUNTINGTON:
1338 * Packed stream firmware variant maintains a
1339 * non-standard algorithm for hash computation.
1340 * It implies explicit XORing together
1341 * source + destination IP addresses (or last
1342 * four bytes in the case of IPv6) and using the
1343 * resulting value as the input to a Toeplitz hash.
1345 encp->enc_rx_scale_hash_alg_mask =
1346 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1354 /* Port numbers cannot contribute to the hash value */
1355 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1358 * Maximum number of exclusive RSS contexts.
1359 * EF10 hardware supports 64 in total, but 6 are reserved
1360 * for shared contexts. They are a global resource so
1361 * not all may be available.
1363 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1365 encp->enc_rx_scale_hash_alg_mask =
1366 (1U << EFX_RX_HASHALG_TOEPLITZ);
1369 * It is possible to use port numbers as
1370 * the input data for hash computation.
1372 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1374 #endif /* EFSYS_OPT_RX_SCALE */
1376 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1377 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1378 encp->enc_filter_action_flag_supported = B_TRUE;
1380 encp->enc_filter_action_flag_supported = B_FALSE;
1382 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1383 encp->enc_filter_action_mark_supported = B_TRUE;
1385 encp->enc_filter_action_mark_supported = B_FALSE;
1387 /* Get maximum supported value for "MARK" filter action */
1388 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1389 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1390 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1392 encp->enc_filter_action_mark_max = 0;
1399 #if EFSYS_OPT_RX_SCALE
1402 #endif /* EFSYS_OPT_RX_SCALE */
1410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1415 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1416 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1417 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1418 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1419 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1420 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1421 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1422 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1423 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1424 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1425 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1426 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1428 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1430 __checkReturn efx_rc_t
1431 ef10_get_privilege_mask(
1432 __in efx_nic_t *enp,
1433 __out uint32_t *maskp)
1435 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1439 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1444 /* Fallback for old firmware without privilege mask support */
1445 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1446 /* Assume PF has admin privilege */
1447 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1449 /* VF is always unprivileged by default */
1450 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1459 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1464 #define EFX_EXT_PORT_MAX 4
1465 #define EFX_EXT_PORT_NA 0xFF
1468 * Table of mapping schemes from port number to external number.
1470 * Each port number ultimately corresponds to a connector: either as part of
1471 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1472 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1473 * "Salina"). In general:
1475 * Port number (0-based)
1477 * port mapping (n:1)
1480 * External port number (1-based)
1482 * fixed (1:1) or cable assembly (1:m)
1487 * The external numbering refers to the cages or magjacks on the board,
1488 * as visibly annotated on the board or back panel. This table describes
1489 * how to determine which external cage/magjack corresponds to the port
1490 * numbers used by the driver.
1492 * The count of consecutive port numbers that map to each external number,
1493 * is determined by the chip family and the current port mode.
1495 * For the Huntington family, the current port mode cannot be discovered,
1496 * but a single mapping is used by all modes for a given chip variant,
1497 * so the mapping used is instead the last match in the table to the full
1498 * set of port modes to which the NIC can be configured. Therefore the
1499 * ordering of entries in the mapping table is significant.
1501 static struct ef10_external_port_map_s {
1502 efx_family_t family;
1503 uint32_t modes_mask;
1504 uint8_t base_port[EFX_EXT_PORT_MAX];
1505 } __ef10_external_port_mappings[] = {
1507 * Modes used by Huntington family controllers where each port
1508 * number maps to a separate cage.
1509 * SFN7x22F (Torino):
1519 EFX_FAMILY_HUNTINGTON,
1520 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1521 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1522 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1526 * Modes which for Huntington identify a chip variant where 2
1527 * adjacent port numbers map to each cage.
1535 EFX_FAMILY_HUNTINGTON,
1536 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1537 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1538 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1539 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1540 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1543 * Modes that on Medford allocate each port number to a separate
1552 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1553 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1557 * Modes that on Medford allocate 2 adjacent port numbers to each
1566 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1567 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1568 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1569 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1570 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1571 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1572 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1575 * Modes that on Medford allocate 4 adjacent port numbers to each
1576 * connector, starting on cage 1.
1584 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1585 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1586 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1587 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1590 * Modes that on Medford allocate 4 adjacent port numbers to each
1591 * connector, starting on cage 2.
1599 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1600 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1603 * Modes that on Medford2 allocate each port number to a separate
1611 EFX_FAMILY_MEDFORD2,
1612 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1613 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1614 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1615 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1616 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1617 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1618 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1622 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1629 EFX_FAMILY_MEDFORD2,
1630 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1631 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1632 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1635 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1636 * cage, starting on cage 1.
1643 EFX_FAMILY_MEDFORD2,
1644 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1645 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1646 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1647 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1648 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1649 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1650 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1653 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1654 * cage, starting on cage 2.
1659 EFX_FAMILY_MEDFORD2,
1660 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1661 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1664 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1665 * connector, starting on cage 1.
1672 EFX_FAMILY_MEDFORD2,
1673 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1674 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1677 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1678 * connector, starting on cage 2.
1685 EFX_FAMILY_MEDFORD2,
1686 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1687 (1U << TLV_PORT_MODE_NA_1x2), /* mode 11 */
1688 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1692 static __checkReturn efx_rc_t
1693 ef10_external_port_mapping(
1694 __in efx_nic_t *enp,
1696 __out uint8_t *external_portp)
1700 uint32_t port_modes;
1703 struct ef10_external_port_map_s *mapp = NULL;
1704 int ext_index = port; /* Default 1-1 mapping */
1706 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1709 * No current port mode information (i.e. Huntington)
1710 * - infer mapping from available modes
1712 if ((rc = efx_mcdi_get_port_modes(enp,
1713 &port_modes, NULL, NULL)) != 0) {
1715 * No port mode information available
1716 * - use default mapping
1721 /* Only need to scan the current mode */
1722 port_modes = 1 << current;
1726 * Infer the internal port -> external number mapping from
1727 * the possible port modes for this NIC.
1729 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1730 struct ef10_external_port_map_s *eepmp =
1731 &__ef10_external_port_mappings[i];
1732 if (eepmp->family != enp->en_family)
1734 matches = (eepmp->modes_mask & port_modes);
1737 * Some modes match. For some Huntington boards
1738 * there will be multiple matches. The mapping on the
1739 * last match is used.
1742 port_modes &= ~matches;
1746 if (port_modes != 0) {
1747 /* Some advertised modes are not supported */
1755 * External ports are assigned a sequence of consecutive
1756 * port numbers, so find the one with the closest base_port.
1758 uint32_t delta = EFX_EXT_PORT_NA;
1760 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1761 uint32_t base = mapp->base_port[i];
1762 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1763 if ((port - base) < delta) {
1764 delta = (port - base);
1770 *external_portp = (uint8_t)(ext_index + 1);
1775 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1780 static __checkReturn efx_rc_t
1782 __in efx_nic_t *enp)
1784 const efx_nic_ops_t *enop = enp->en_enop;
1785 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1786 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1787 ef10_link_state_t els;
1788 efx_port_t *epp = &(enp->en_port);
1789 uint32_t board_type = 0;
1790 uint32_t base, nvec;
1795 uint8_t mac_addr[6] = { 0 };
1798 /* Get the (zero-based) MCDI port number */
1799 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1802 /* EFX MCDI interface uses one-based port numbers */
1803 emip->emi_port = port + 1;
1805 if ((rc = ef10_external_port_mapping(enp, port,
1806 &encp->enc_external_port)) != 0)
1810 * Get PCIe function number from firmware (used for
1811 * per-function privilege and dynamic config info).
1812 * - PCIe PF: pf = PF number, vf = 0xffff.
1813 * - PCIe VF: pf = parent PF, vf = VF number.
1815 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1821 /* MAC address for this function */
1822 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1823 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1824 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1826 * Disable static config checking, ONLY for manufacturing test
1827 * and setup at the factory, to allow the static config to be
1830 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1831 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1833 * If the static config does not include a global MAC
1834 * address pool then the board may return a locally
1835 * administered MAC address (this should only happen on
1836 * incorrectly programmed boards).
1840 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1842 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1847 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1849 /* Board configuration (legacy) */
1850 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1852 /* Unprivileged functions may not be able to read board cfg */
1859 encp->enc_board_type = board_type;
1860 encp->enc_clk_mult = 1; /* not used for EF10 */
1862 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1863 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1867 * Firmware with support for *_FEC capability bits does not
1868 * report that the corresponding *_FEC_REQUESTED bits are supported.
1869 * Add them here so that drivers understand that they are supported.
1871 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1872 epp->ep_phy_cap_mask |=
1873 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1874 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1875 epp->ep_phy_cap_mask |=
1876 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1877 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1878 epp->ep_phy_cap_mask |=
1879 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1881 /* Obtain the default PHY advertised capabilities */
1882 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1884 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1885 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1887 /* Check capabilities of running datapath firmware */
1888 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1891 /* Alignment for WPTR updates */
1892 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1894 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1895 /* No boundary crossing limits */
1896 encp->enc_tx_dma_desc_boundary = 0;
1899 * Maximum number of bytes into the frame the TCP header can start for
1900 * firmware assisted TSO to work.
1902 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1905 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1906 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1907 * resources (allocated to this PCIe function), which is zero until
1908 * after we have allocated VIs.
1910 encp->enc_evq_limit = 1024;
1911 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1912 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1914 encp->enc_buftbl_limit = 0xFFFFFFFF;
1916 /* Get interrupt vector limits */
1917 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1918 if (EFX_PCI_FUNCTION_IS_PF(encp))
1921 /* Ignore error (cannot query vector limits from a VF). */
1925 encp->enc_intr_vec_base = base;
1926 encp->enc_intr_limit = nvec;
1929 * Get the current privilege mask. Note that this may be modified
1930 * dynamically, so this value is informational only. DO NOT use
1931 * the privilege mask to check for sufficient privileges, as that
1932 * can result in time-of-check/time-of-use bugs.
1934 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1936 encp->enc_privilege_mask = mask;
1938 /* Get remaining controller-specific board config */
1939 if ((rc = enop->eno_board_cfg(enp)) != 0)
1946 EFSYS_PROBE(fail11);
1948 EFSYS_PROBE(fail10);
1966 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1971 __checkReturn efx_rc_t
1973 __in efx_nic_t *enp)
1975 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1976 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1979 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1980 enp->en_family == EFX_FAMILY_MEDFORD ||
1981 enp->en_family == EFX_FAMILY_MEDFORD2);
1983 /* Read and clear any assertion state */
1984 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1987 /* Exit the assertion handler */
1988 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1992 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1995 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1999 * Set default driver config limits (based on board config).
2001 * FIXME: For now allocate a fixed number of VIs which is likely to be
2002 * sufficient and small enough to allow multiple functions on the same
2005 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
2006 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
2008 /* The client driver must configure and enable PIO buffer support */
2009 edcp->edc_max_piobuf_count = 0;
2010 edcp->edc_pio_alloc_size = 0;
2012 #if EFSYS_OPT_MAC_STATS
2013 /* Wipe the MAC statistics */
2014 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2018 #if EFSYS_OPT_LOOPBACK
2019 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2023 #if EFSYS_OPT_MON_STATS
2024 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2025 /* Unprivileged functions do not have access to sensors */
2031 encp->enc_features = enp->en_features;
2035 #if EFSYS_OPT_MON_STATS
2039 #if EFSYS_OPT_LOOPBACK
2043 #if EFSYS_OPT_MAC_STATS
2054 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2059 __checkReturn efx_rc_t
2060 ef10_nic_set_drv_limits(
2061 __inout efx_nic_t *enp,
2062 __in efx_drv_limits_t *edlp)
2064 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2065 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2066 uint32_t min_evq_count, max_evq_count;
2067 uint32_t min_rxq_count, max_rxq_count;
2068 uint32_t min_txq_count, max_txq_count;
2076 /* Get minimum required and maximum usable VI limits */
2077 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2078 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2079 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2081 edcp->edc_min_vi_count =
2082 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2084 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2085 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2086 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2088 edcp->edc_max_vi_count =
2089 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2092 * Check limits for sub-allocated piobuf blocks.
2093 * PIO is optional, so don't fail if the limits are incorrect.
2095 if ((encp->enc_piobuf_size == 0) ||
2096 (encp->enc_piobuf_limit == 0) ||
2097 (edlp->edl_min_pio_alloc_size == 0) ||
2098 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2100 edcp->edc_max_piobuf_count = 0;
2101 edcp->edc_pio_alloc_size = 0;
2103 uint32_t blk_size, blk_count, blks_per_piobuf;
2106 MAX(edlp->edl_min_pio_alloc_size,
2107 encp->enc_piobuf_min_alloc_size);
2109 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2110 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2112 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2114 /* A zero max pio alloc count means unlimited */
2115 if ((edlp->edl_max_pio_alloc_count > 0) &&
2116 (edlp->edl_max_pio_alloc_count < blk_count)) {
2117 blk_count = edlp->edl_max_pio_alloc_count;
2120 edcp->edc_pio_alloc_size = blk_size;
2121 edcp->edc_max_piobuf_count =
2122 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2128 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2133 __checkReturn efx_rc_t
2135 __in efx_nic_t *enp)
2138 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2139 MC_CMD_ENTITY_RESET_OUT_LEN);
2142 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2143 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2145 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2148 req.emr_cmd = MC_CMD_ENTITY_RESET;
2149 req.emr_in_buf = payload;
2150 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2151 req.emr_out_buf = payload;
2152 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2154 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2155 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2157 efx_mcdi_execute(enp, &req);
2159 if (req.emr_rc != 0) {
2164 /* Clear RX/TX DMA queue errors */
2165 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2174 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2179 __checkReturn efx_rc_t
2181 __in efx_nic_t *enp)
2183 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2184 uint32_t min_vi_count, max_vi_count;
2185 uint32_t vi_count, vi_base, vi_shift;
2189 uint32_t vi_window_size;
2192 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2193 enp->en_family == EFX_FAMILY_MEDFORD ||
2194 enp->en_family == EFX_FAMILY_MEDFORD2);
2196 /* Enable reporting of some events (e.g. link change) */
2197 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2200 /* Allocate (optional) on-chip PIO buffers */
2201 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2204 * For best performance, PIO writes should use a write-combined
2205 * (WC) memory mapping. Using a separate WC mapping for the PIO
2206 * aperture of each VI would be a burden to drivers (and not
2207 * possible if the host page size is >4Kbyte).
2209 * To avoid this we use a single uncached (UC) mapping for VI
2210 * register access, and a single WC mapping for extra VIs used
2213 * Each piobuf must be linked to a VI in the WC mapping, and to
2214 * each VI that is using a sub-allocated block from the piobuf.
2216 min_vi_count = edcp->edc_min_vi_count;
2218 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2220 /* Ensure that the previously attached driver's VIs are freed */
2221 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2225 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2226 * fails then retrying the request for fewer VI resources may succeed.
2229 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2230 &vi_base, &vi_count, &vi_shift)) != 0)
2233 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2235 if (vi_count < min_vi_count) {
2240 enp->en_arch.ef10.ena_vi_base = vi_base;
2241 enp->en_arch.ef10.ena_vi_count = vi_count;
2242 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2244 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2245 /* Not enough extra VIs to map piobufs */
2246 ef10_nic_free_piobufs(enp);
2249 enp->en_arch.ef10.ena_pio_write_vi_base =
2250 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2252 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2253 EFX_VI_WINDOW_SHIFT_INVALID);
2254 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2255 EFX_VI_WINDOW_SHIFT_64K);
2256 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2258 /* Save UC memory mapping details */
2259 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2260 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2261 enp->en_arch.ef10.ena_uc_mem_map_size =
2263 enp->en_arch.ef10.ena_pio_write_vi_base);
2265 enp->en_arch.ef10.ena_uc_mem_map_size =
2267 enp->en_arch.ef10.ena_vi_count);
2270 /* Save WC memory mapping details */
2271 enp->en_arch.ef10.ena_wc_mem_map_offset =
2272 enp->en_arch.ef10.ena_uc_mem_map_offset +
2273 enp->en_arch.ef10.ena_uc_mem_map_size;
2275 enp->en_arch.ef10.ena_wc_mem_map_size =
2277 enp->en_arch.ef10.ena_piobuf_count);
2279 /* Link piobufs to extra VIs in WC mapping */
2280 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2281 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2282 rc = efx_mcdi_link_piobuf(enp,
2283 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2284 enp->en_arch.ef10.ena_piobuf_handle[i]);
2291 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2293 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2294 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2295 * retry the request several times after waiting a while. The wait time
2296 * between retries starts small (10ms) and exponentially increases.
2297 * Total wait time is a little over two seconds. Retry logic in the
2298 * client driver may mean this whole loop is repeated if it continues to
2303 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2304 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2307 * Do not retry alloc for PF, or for other errors on
2313 /* VF startup before PF is ready. Retry allocation. */
2315 /* Too many attempts */
2319 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2320 EFSYS_SLEEP(delay_us);
2322 if (delay_us < 500000)
2326 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2327 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2342 ef10_nic_free_piobufs(enp);
2345 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2350 __checkReturn efx_rc_t
2351 ef10_nic_get_vi_pool(
2352 __in efx_nic_t *enp,
2353 __out uint32_t *vi_countp)
2355 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2356 enp->en_family == EFX_FAMILY_MEDFORD ||
2357 enp->en_family == EFX_FAMILY_MEDFORD2);
2360 * Report VIs that the client driver can use.
2361 * Do not include VIs used for PIO buffer writes.
2363 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2368 __checkReturn efx_rc_t
2369 ef10_nic_get_bar_region(
2370 __in efx_nic_t *enp,
2371 __in efx_nic_region_t region,
2372 __out uint32_t *offsetp,
2373 __out size_t *sizep)
2377 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2378 enp->en_family == EFX_FAMILY_MEDFORD ||
2379 enp->en_family == EFX_FAMILY_MEDFORD2);
2382 * TODO: Specify host memory mapping alignment and granularity
2383 * in efx_drv_limits_t so that they can be taken into account
2384 * when allocating extra VIs for PIO writes.
2388 /* UC mapped memory BAR region for VI registers */
2389 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2390 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2393 case EFX_REGION_PIO_WRITE_VI:
2394 /* WC mapped memory BAR region for piobuf writes */
2395 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2396 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2412 __checkReturn boolean_t
2413 ef10_nic_hw_unavailable(
2414 __in efx_nic_t *enp)
2418 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2421 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2422 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2428 ef10_nic_set_hw_unavailable(enp);
2434 ef10_nic_set_hw_unavailable(
2435 __in efx_nic_t *enp)
2437 EFSYS_PROBE(hw_unavail);
2438 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2443 __in efx_nic_t *enp)
2448 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2449 enp->en_vport_id = 0;
2451 /* Unlink piobufs from extra VIs in WC mapping */
2452 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2453 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2454 rc = efx_mcdi_unlink_piobuf(enp,
2455 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2461 ef10_nic_free_piobufs(enp);
2463 (void) efx_mcdi_free_vis(enp);
2464 enp->en_arch.ef10.ena_vi_count = 0;
2469 __in efx_nic_t *enp)
2471 #if EFSYS_OPT_MON_STATS
2472 mcdi_mon_cfg_free(enp);
2473 #endif /* EFSYS_OPT_MON_STATS */
2474 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2479 __checkReturn efx_rc_t
2480 ef10_nic_register_test(
2481 __in efx_nic_t *enp)
2486 _NOTE(ARGUNUSED(enp))
2487 _NOTE(CONSTANTCONDITION)
2497 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2502 #endif /* EFSYS_OPT_DIAG */
2504 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2506 __checkReturn efx_rc_t
2507 efx_mcdi_get_nic_global(
2508 __in efx_nic_t *enp,
2510 __out uint32_t *valuep)
2513 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2514 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2517 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2518 req.emr_in_buf = payload;
2519 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2520 req.emr_out_buf = payload;
2521 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2523 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2525 efx_mcdi_execute(enp, &req);
2527 if (req.emr_rc != 0) {
2532 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2537 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2544 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2549 __checkReturn efx_rc_t
2550 efx_mcdi_set_nic_global(
2551 __in efx_nic_t *enp,
2553 __in uint32_t value)
2556 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2559 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2560 req.emr_in_buf = payload;
2561 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2562 req.emr_out_buf = NULL;
2563 req.emr_out_length = 0;
2565 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2566 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2568 efx_mcdi_execute(enp, &req);
2570 if (req.emr_rc != 0) {
2578 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2583 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2585 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */