2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD ||
56 enp->en_family == EFX_FAMILY_MEDFORD2);
58 (void) memset(payload, 0, sizeof (payload));
59 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
60 req.emr_in_buf = payload;
61 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
62 req.emr_out_buf = payload;
63 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
65 efx_mcdi_execute(enp, &req);
67 if (req.emr_rc != 0) {
72 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
77 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
84 EFSYS_PROBE1(fail1, efx_rc_t, rc);
89 __checkReturn efx_rc_t
90 efx_mcdi_get_port_modes(
92 __out uint32_t *modesp,
93 __out_opt uint32_t *current_modep)
96 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
97 MC_CMD_GET_PORT_MODES_OUT_LEN)];
100 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
101 enp->en_family == EFX_FAMILY_MEDFORD ||
102 enp->en_family == EFX_FAMILY_MEDFORD2);
104 (void) memset(payload, 0, sizeof (payload));
105 req.emr_cmd = MC_CMD_GET_PORT_MODES;
106 req.emr_in_buf = payload;
107 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
108 req.emr_out_buf = payload;
109 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
111 efx_mcdi_execute(enp, &req);
113 if (req.emr_rc != 0) {
119 * Require only Modes and DefaultMode fields, unless the current mode
120 * was requested (CurrentMode field was added for Medford).
122 if (req.emr_out_length_used <
123 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
127 if ((current_modep != NULL) && (req.emr_out_length_used <
128 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
133 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
135 if (current_modep != NULL) {
136 *current_modep = MCDI_OUT_DWORD(req,
137 GET_PORT_MODES_OUT_CURRENT_MODE);
147 EFSYS_PROBE1(fail1, efx_rc_t, rc);
152 __checkReturn efx_rc_t
153 ef10_nic_get_port_mode_bandwidth(
154 __in uint32_t port_mode,
155 __out uint32_t *bandwidth_mbpsp)
161 case TLV_PORT_MODE_10G:
164 case TLV_PORT_MODE_10G_10G:
165 bandwidth = 10000 * 2;
167 case TLV_PORT_MODE_10G_10G_10G_10G:
168 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
169 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
170 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
171 bandwidth = 10000 * 4;
173 case TLV_PORT_MODE_40G:
176 case TLV_PORT_MODE_40G_40G:
177 bandwidth = 40000 * 2;
179 case TLV_PORT_MODE_40G_10G_10G:
180 case TLV_PORT_MODE_10G_10G_40G:
181 bandwidth = 40000 + (10000 * 2);
188 *bandwidth_mbpsp = bandwidth;
193 EFSYS_PROBE1(fail1, efx_rc_t, rc);
198 static __checkReturn efx_rc_t
199 efx_mcdi_vadaptor_alloc(
201 __in uint32_t port_id)
204 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
205 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
208 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
210 (void) memset(payload, 0, sizeof (payload));
211 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
212 req.emr_in_buf = payload;
213 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
214 req.emr_out_buf = payload;
215 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
217 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
218 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
219 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
220 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
222 efx_mcdi_execute(enp, &req);
224 if (req.emr_rc != 0) {
232 EFSYS_PROBE1(fail1, efx_rc_t, rc);
237 static __checkReturn efx_rc_t
238 efx_mcdi_vadaptor_free(
240 __in uint32_t port_id)
243 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
244 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
247 (void) memset(payload, 0, sizeof (payload));
248 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
249 req.emr_in_buf = payload;
250 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
251 req.emr_out_buf = payload;
252 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
254 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
256 efx_mcdi_execute(enp, &req);
258 if (req.emr_rc != 0) {
266 EFSYS_PROBE1(fail1, efx_rc_t, rc);
271 __checkReturn efx_rc_t
272 efx_mcdi_get_mac_address_pf(
274 __out_ecount_opt(6) uint8_t mac_addrp[6])
277 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
278 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
281 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
282 enp->en_family == EFX_FAMILY_MEDFORD ||
283 enp->en_family == EFX_FAMILY_MEDFORD2);
285 (void) memset(payload, 0, sizeof (payload));
286 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
287 req.emr_in_buf = payload;
288 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
289 req.emr_out_buf = payload;
290 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
292 efx_mcdi_execute(enp, &req);
294 if (req.emr_rc != 0) {
299 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
304 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
309 if (mac_addrp != NULL) {
312 addrp = MCDI_OUT2(req, uint8_t,
313 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
315 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
325 EFSYS_PROBE1(fail1, efx_rc_t, rc);
330 __checkReturn efx_rc_t
331 efx_mcdi_get_mac_address_vf(
333 __out_ecount_opt(6) uint8_t mac_addrp[6])
336 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
337 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
340 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
341 enp->en_family == EFX_FAMILY_MEDFORD ||
342 enp->en_family == EFX_FAMILY_MEDFORD2);
344 (void) memset(payload, 0, sizeof (payload));
345 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
346 req.emr_in_buf = payload;
347 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
348 req.emr_out_buf = payload;
349 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
351 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
352 EVB_PORT_ID_ASSIGNED);
354 efx_mcdi_execute(enp, &req);
356 if (req.emr_rc != 0) {
361 if (req.emr_out_length_used <
362 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
367 if (MCDI_OUT_DWORD(req,
368 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
373 if (mac_addrp != NULL) {
376 addrp = MCDI_OUT2(req, uint8_t,
377 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
379 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
389 EFSYS_PROBE1(fail1, efx_rc_t, rc);
394 __checkReturn efx_rc_t
397 __out uint32_t *sys_freqp,
398 __out uint32_t *dpcpu_freqp)
401 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
402 MC_CMD_GET_CLOCK_OUT_LEN)];
405 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
406 enp->en_family == EFX_FAMILY_MEDFORD ||
407 enp->en_family == EFX_FAMILY_MEDFORD2);
409 (void) memset(payload, 0, sizeof (payload));
410 req.emr_cmd = MC_CMD_GET_CLOCK;
411 req.emr_in_buf = payload;
412 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
413 req.emr_out_buf = payload;
414 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
416 efx_mcdi_execute(enp, &req);
418 if (req.emr_rc != 0) {
423 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
428 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
429 if (*sys_freqp == 0) {
433 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
434 if (*dpcpu_freqp == 0) {
448 EFSYS_PROBE1(fail1, efx_rc_t, rc);
453 __checkReturn efx_rc_t
454 efx_mcdi_get_rxdp_config(
456 __out uint32_t *end_paddingp)
459 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
460 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
461 uint32_t end_padding;
464 memset(payload, 0, sizeof (payload));
465 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
466 req.emr_in_buf = payload;
467 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
468 req.emr_out_buf = payload;
469 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
471 efx_mcdi_execute(enp, &req);
472 if (req.emr_rc != 0) {
477 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
478 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
479 /* RX DMA end padding is disabled */
482 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
483 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
484 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
487 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
490 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
499 *end_paddingp = end_padding;
506 EFSYS_PROBE1(fail1, efx_rc_t, rc);
511 __checkReturn efx_rc_t
512 efx_mcdi_get_vector_cfg(
514 __out_opt uint32_t *vec_basep,
515 __out_opt uint32_t *pf_nvecp,
516 __out_opt uint32_t *vf_nvecp)
519 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
520 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
523 (void) memset(payload, 0, sizeof (payload));
524 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
525 req.emr_in_buf = payload;
526 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
527 req.emr_out_buf = payload;
528 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
530 efx_mcdi_execute(enp, &req);
532 if (req.emr_rc != 0) {
537 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
542 if (vec_basep != NULL)
543 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
544 if (pf_nvecp != NULL)
545 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
546 if (vf_nvecp != NULL)
547 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
554 EFSYS_PROBE1(fail1, efx_rc_t, rc);
559 static __checkReturn efx_rc_t
562 __in uint32_t min_vi_count,
563 __in uint32_t max_vi_count,
564 __out uint32_t *vi_basep,
565 __out uint32_t *vi_countp,
566 __out uint32_t *vi_shiftp)
569 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
570 MC_CMD_ALLOC_VIS_EXT_OUT_LEN)];
573 if (vi_countp == NULL) {
578 (void) memset(payload, 0, sizeof (payload));
579 req.emr_cmd = MC_CMD_ALLOC_VIS;
580 req.emr_in_buf = payload;
581 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
582 req.emr_out_buf = payload;
583 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
585 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
586 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
588 efx_mcdi_execute(enp, &req);
590 if (req.emr_rc != 0) {
595 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
600 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
601 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
603 /* Report VI_SHIFT if available (always zero for Huntington) */
604 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
607 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
616 EFSYS_PROBE1(fail1, efx_rc_t, rc);
622 static __checkReturn efx_rc_t
629 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
630 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
632 req.emr_cmd = MC_CMD_FREE_VIS;
633 req.emr_in_buf = NULL;
634 req.emr_in_length = 0;
635 req.emr_out_buf = NULL;
636 req.emr_out_length = 0;
638 efx_mcdi_execute_quiet(enp, &req);
640 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
641 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
649 EFSYS_PROBE1(fail1, efx_rc_t, rc);
655 static __checkReturn efx_rc_t
656 efx_mcdi_alloc_piobuf(
658 __out efx_piobuf_handle_t *handlep)
661 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
662 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
665 if (handlep == NULL) {
670 (void) memset(payload, 0, sizeof (payload));
671 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
672 req.emr_in_buf = payload;
673 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
674 req.emr_out_buf = payload;
675 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
677 efx_mcdi_execute_quiet(enp, &req);
679 if (req.emr_rc != 0) {
684 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
689 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
698 EFSYS_PROBE1(fail1, efx_rc_t, rc);
703 static __checkReturn efx_rc_t
704 efx_mcdi_free_piobuf(
706 __in efx_piobuf_handle_t handle)
709 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
710 MC_CMD_FREE_PIOBUF_OUT_LEN)];
713 (void) memset(payload, 0, sizeof (payload));
714 req.emr_cmd = MC_CMD_FREE_PIOBUF;
715 req.emr_in_buf = payload;
716 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
717 req.emr_out_buf = payload;
718 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
720 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
722 efx_mcdi_execute_quiet(enp, &req);
724 if (req.emr_rc != 0) {
732 EFSYS_PROBE1(fail1, efx_rc_t, rc);
737 static __checkReturn efx_rc_t
738 efx_mcdi_link_piobuf(
740 __in uint32_t vi_index,
741 __in efx_piobuf_handle_t handle)
744 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
745 MC_CMD_LINK_PIOBUF_OUT_LEN)];
748 (void) memset(payload, 0, sizeof (payload));
749 req.emr_cmd = MC_CMD_LINK_PIOBUF;
750 req.emr_in_buf = payload;
751 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
752 req.emr_out_buf = payload;
753 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
755 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
756 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
758 efx_mcdi_execute(enp, &req);
760 if (req.emr_rc != 0) {
768 EFSYS_PROBE1(fail1, efx_rc_t, rc);
773 static __checkReturn efx_rc_t
774 efx_mcdi_unlink_piobuf(
776 __in uint32_t vi_index)
779 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
780 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
783 (void) memset(payload, 0, sizeof (payload));
784 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
785 req.emr_in_buf = payload;
786 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
787 req.emr_out_buf = payload;
788 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
790 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
792 efx_mcdi_execute_quiet(enp, &req);
794 if (req.emr_rc != 0) {
802 EFSYS_PROBE1(fail1, efx_rc_t, rc);
808 ef10_nic_alloc_piobufs(
810 __in uint32_t max_piobuf_count)
812 efx_piobuf_handle_t *handlep;
815 EFSYS_ASSERT3U(max_piobuf_count, <=,
816 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
818 enp->en_arch.ef10.ena_piobuf_count = 0;
820 for (i = 0; i < max_piobuf_count; i++) {
821 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
823 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
826 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
827 enp->en_arch.ef10.ena_piobuf_count++;
833 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
834 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
836 efx_mcdi_free_piobuf(enp, *handlep);
837 *handlep = EFX_PIOBUF_HANDLE_INVALID;
839 enp->en_arch.ef10.ena_piobuf_count = 0;
844 ef10_nic_free_piobufs(
847 efx_piobuf_handle_t *handlep;
850 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
851 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
853 efx_mcdi_free_piobuf(enp, *handlep);
854 *handlep = EFX_PIOBUF_HANDLE_INVALID;
856 enp->en_arch.ef10.ena_piobuf_count = 0;
859 /* Sub-allocate a block from a piobuf */
860 __checkReturn efx_rc_t
862 __inout efx_nic_t *enp,
863 __out uint32_t *bufnump,
864 __out efx_piobuf_handle_t *handlep,
865 __out uint32_t *blknump,
866 __out uint32_t *offsetp,
869 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
870 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
871 uint32_t blk_per_buf;
875 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
876 enp->en_family == EFX_FAMILY_MEDFORD ||
877 enp->en_family == EFX_FAMILY_MEDFORD2);
878 EFSYS_ASSERT(bufnump);
879 EFSYS_ASSERT(handlep);
880 EFSYS_ASSERT(blknump);
881 EFSYS_ASSERT(offsetp);
884 if ((edcp->edc_pio_alloc_size == 0) ||
885 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
889 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
891 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
892 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
897 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
898 for (blk = 0; blk < blk_per_buf; blk++) {
899 if ((*map & (1u << blk)) == 0) {
909 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
912 *sizep = edcp->edc_pio_alloc_size;
913 *offsetp = blk * (*sizep);
920 EFSYS_PROBE1(fail1, efx_rc_t, rc);
925 /* Free a piobuf sub-allocated block */
926 __checkReturn efx_rc_t
928 __inout efx_nic_t *enp,
929 __in uint32_t bufnum,
930 __in uint32_t blknum)
935 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
936 (blknum >= (8 * sizeof (*map)))) {
941 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
942 if ((*map & (1u << blknum)) == 0) {
946 *map &= ~(1u << blknum);
953 EFSYS_PROBE1(fail1, efx_rc_t, rc);
958 __checkReturn efx_rc_t
960 __inout efx_nic_t *enp,
961 __in uint32_t vi_index,
962 __in efx_piobuf_handle_t handle)
964 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
967 __checkReturn efx_rc_t
969 __inout efx_nic_t *enp,
970 __in uint32_t vi_index)
972 return (efx_mcdi_unlink_piobuf(enp, vi_index));
975 static __checkReturn efx_rc_t
976 ef10_mcdi_get_pf_count(
978 __out uint32_t *pf_countp)
981 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
982 MC_CMD_GET_PF_COUNT_OUT_LEN)];
985 (void) memset(payload, 0, sizeof (payload));
986 req.emr_cmd = MC_CMD_GET_PF_COUNT;
987 req.emr_in_buf = payload;
988 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
989 req.emr_out_buf = payload;
990 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
992 efx_mcdi_execute(enp, &req);
994 if (req.emr_rc != 0) {
999 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1004 *pf_countp = *MCDI_OUT(req, uint8_t,
1005 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1007 EFSYS_ASSERT(*pf_countp != 0);
1014 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1019 static __checkReturn efx_rc_t
1020 ef10_get_datapath_caps(
1021 __in efx_nic_t *enp)
1023 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1025 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
1026 MC_CMD_GET_CAPABILITIES_V4_OUT_LEN)];
1029 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1033 (void) memset(payload, 0, sizeof (payload));
1034 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1035 req.emr_in_buf = payload;
1036 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1037 req.emr_out_buf = payload;
1038 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V4_OUT_LEN;
1040 efx_mcdi_execute_quiet(enp, &req);
1042 if (req.emr_rc != 0) {
1047 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1052 #define CAP_FLAGS1(_req, _flag) \
1053 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1054 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1056 #define CAP_FLAGS2(_req, _flag) \
1057 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1058 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1059 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1062 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1063 * We only support the 14 byte prefix here.
1065 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1069 encp->enc_rx_prefix_size = 14;
1071 /* Check if the firmware supports TSO */
1072 if (CAP_FLAGS1(req, TX_TSO))
1073 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1075 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1077 /* Check if the firmware supports FATSOv2 */
1078 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1079 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1080 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1081 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1083 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1084 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1087 /* Check if the firmware has vadapter/vport/vswitch support */
1088 if (CAP_FLAGS1(req, EVB))
1089 encp->enc_datapath_cap_evb = B_TRUE;
1091 encp->enc_datapath_cap_evb = B_FALSE;
1093 /* Check if the firmware supports VLAN insertion */
1094 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1095 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1097 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1099 /* Check if the firmware supports RX event batching */
1100 if (CAP_FLAGS1(req, RX_BATCHING))
1101 encp->enc_rx_batching_enabled = B_TRUE;
1103 encp->enc_rx_batching_enabled = B_FALSE;
1106 * Even if batching isn't reported as supported, we may still get
1109 encp->enc_rx_batch_max = 16;
1111 /* Check if the firmware supports disabling scatter on RXQs */
1112 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1113 encp->enc_rx_disable_scatter_supported = B_TRUE;
1115 encp->enc_rx_disable_scatter_supported = B_FALSE;
1117 /* Check if the firmware supports packed stream mode */
1118 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1119 encp->enc_rx_packed_stream_supported = B_TRUE;
1121 encp->enc_rx_packed_stream_supported = B_FALSE;
1124 * Check if the firmware supports configurable buffer sizes
1125 * for packed stream mode (otherwise buffer size is 1Mbyte)
1127 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1128 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1130 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1132 /* Check if the firmware supports set mac with running filters */
1133 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1134 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1136 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1139 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1140 * specifying which parameters to configure.
1142 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1143 encp->enc_enhanced_set_mac_supported = B_TRUE;
1145 encp->enc_enhanced_set_mac_supported = B_FALSE;
1148 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1149 * us to let the firmware choose the settings to use on an EVQ.
1151 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1152 encp->enc_init_evq_v2_supported = B_TRUE;
1154 encp->enc_init_evq_v2_supported = B_FALSE;
1157 * Check if firmware-verified NVRAM updates must be used.
1159 * The firmware trusted installer requires all NVRAM updates to use
1160 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1161 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1162 * partition and report the result).
1164 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1165 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1167 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1170 * Check if firmware provides packet memory and Rx datapath
1173 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1174 encp->enc_pm_and_rxdp_counters = B_TRUE;
1176 encp->enc_pm_and_rxdp_counters = B_FALSE;
1179 * Check if the 40G MAC hardware is capable of reporting
1180 * statistics for Tx size bins.
1182 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1183 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1185 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1188 * Check if firmware supports VXLAN and NVGRE tunnels.
1189 * The capability indicates Geneve protocol support as well.
1191 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1192 encp->enc_tunnel_encapsulations_supported =
1193 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1194 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1195 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1197 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1198 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1199 encp->enc_tunnel_config_udp_entries_max =
1200 EFX_TUNNEL_MAXNENTRIES;
1202 encp->enc_tunnel_config_udp_entries_max = 0;
1205 /* Check if firmware supports extended MAC stats. */
1206 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1207 /* Extended stats buffer supported */
1208 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1209 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1211 /* Use Siena-compatible legacy MAC stats */
1212 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1215 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1216 encp->enc_fec_counters = B_TRUE;
1218 encp->enc_fec_counters = B_FALSE;
1232 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1237 __checkReturn efx_rc_t
1238 ef10_get_vi_window_shift(
1239 __in efx_nic_t *enp,
1240 __out uint32_t *vi_window_shiftp)
1243 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
1244 MC_CMD_GET_CAPABILITIES_V3_OUT_LEN)];
1248 (void) memset(payload, 0, sizeof (payload));
1249 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1250 req.emr_in_buf = payload;
1251 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1252 req.emr_out_buf = payload;
1253 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V3_OUT_LEN;
1255 efx_mcdi_execute_quiet(enp, &req);
1257 if (req.emr_rc != 0) {
1262 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1266 mode = MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1269 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1270 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8 * 1024);
1271 *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_8K;
1274 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1275 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_16K == 16 * 1024);
1276 *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_16K;
1279 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1280 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_64K == 64 * 1024);
1281 *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_64K;
1285 *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_INVALID;
1297 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1303 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1304 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1305 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1306 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1307 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1308 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1309 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1310 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1311 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1312 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1313 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1314 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1316 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1319 __checkReturn efx_rc_t
1320 ef10_get_privilege_mask(
1321 __in efx_nic_t *enp,
1322 __out uint32_t *maskp)
1324 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1328 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1333 /* Fallback for old firmware without privilege mask support */
1334 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1335 /* Assume PF has admin privilege */
1336 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1338 /* VF is always unprivileged by default */
1339 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1348 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1355 * Table of mapping schemes from port number to external number.
1357 * Each port number ultimately corresponds to a connector: either as part of
1358 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1359 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1360 * "Salina"). In general:
1362 * Port number (0-based)
1364 * port mapping (n:1)
1367 * External port number (normally 1-based)
1369 * fixed (1:1) or cable assembly (1:m)
1374 * The external numbering refers to the cages or magjacks on the board,
1375 * as visibly annotated on the board or back panel. This table describes
1376 * how to determine which external cage/magjack corresponds to the port
1377 * numbers used by the driver.
1379 * The count of adjacent port numbers that map to each external number,
1380 * and the offset in the numbering, is determined by the chip family and
1381 * current port mode.
1383 * For the Huntington family, the current port mode cannot be discovered,
1384 * but a single mapping is used by all modes for a given chip variant,
1385 * so the mapping used is instead the last match in the table to the full
1386 * set of port modes to which the NIC can be configured. Therefore the
1387 * ordering of entries in the mapping table is significant.
1389 static struct ef10_external_port_map_s {
1390 efx_family_t family;
1391 uint32_t modes_mask;
1394 } __ef10_external_port_mappings[] = {
1396 * Modes used by Huntington family controllers where each port
1397 * number maps to a separate cage.
1398 * SFN7x22F (Torino):
1408 EFX_FAMILY_HUNTINGTON,
1409 (1 << TLV_PORT_MODE_10G) |
1410 (1 << TLV_PORT_MODE_10G_10G) |
1411 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1416 * Modes that on Medford allocate each port number to a separate
1425 (1 << TLV_PORT_MODE_10G) |
1426 (1 << TLV_PORT_MODE_10G_10G),
1431 * Modes which for Huntington identify a chip variant where 2
1432 * adjacent port numbers map to each cage.
1440 EFX_FAMILY_HUNTINGTON,
1441 (1 << TLV_PORT_MODE_40G) |
1442 (1 << TLV_PORT_MODE_40G_40G) |
1443 (1 << TLV_PORT_MODE_40G_10G_10G) |
1444 (1 << TLV_PORT_MODE_10G_10G_40G),
1449 * Modes that on Medford allocate 2 adjacent port numbers to each
1458 (1 << TLV_PORT_MODE_40G) |
1459 (1 << TLV_PORT_MODE_40G_40G) |
1460 (1 << TLV_PORT_MODE_40G_10G_10G) |
1461 (1 << TLV_PORT_MODE_10G_10G_40G) |
1462 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1467 * Modes that on Medford allocate 4 adjacent port numbers to each
1468 * connector, starting on cage 1.
1476 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1477 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1482 * Modes that on Medford allocate 4 adjacent port numbers to each
1483 * connector, starting on cage 2.
1491 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1497 static __checkReturn efx_rc_t
1498 ef10_external_port_mapping(
1499 __in efx_nic_t *enp,
1501 __out uint8_t *external_portp)
1505 uint32_t port_modes;
1508 int32_t count = 1; /* Default 1-1 mapping */
1509 int32_t offset = 1; /* Default starting external port number */
1511 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1513 * No current port mode information (i.e. Huntington)
1514 * - infer mapping from available modes
1516 if ((rc = efx_mcdi_get_port_modes(enp,
1517 &port_modes, NULL)) != 0) {
1519 * No port mode information available
1520 * - use default mapping
1525 /* Only need to scan the current mode */
1526 port_modes = 1 << current;
1530 * Infer the internal port -> external number mapping from
1531 * the possible port modes for this NIC.
1533 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1534 struct ef10_external_port_map_s *eepmp =
1535 &__ef10_external_port_mappings[i];
1536 if (eepmp->family != enp->en_family)
1538 matches = (eepmp->modes_mask & port_modes);
1541 * Some modes match. For some Huntington boards
1542 * there will be multiple matches. The mapping on the
1543 * last match is used.
1545 count = eepmp->count;
1546 offset = eepmp->offset;
1547 port_modes &= ~matches;
1551 if (port_modes != 0) {
1552 /* Some advertised modes are not supported */
1559 * Scale as required by last matched mode and then convert to
1560 * correctly offset numbering
1562 *external_portp = (uint8_t)((port / count) + offset);
1566 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1571 static __checkReturn efx_rc_t
1573 __in efx_nic_t *enp)
1575 const efx_nic_ops_t *enop = enp->en_enop;
1576 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1577 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1578 ef10_link_state_t els;
1579 efx_port_t *epp = &(enp->en_port);
1580 uint32_t board_type = 0;
1581 uint32_t base, nvec;
1585 uint8_t mac_addr[6] = { 0 };
1588 /* Get the (zero-based) MCDI port number */
1589 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1592 /* EFX MCDI interface uses one-based port numbers */
1593 emip->emi_port = port + 1;
1595 if ((rc = ef10_external_port_mapping(enp, port,
1596 &encp->enc_external_port)) != 0)
1600 * Get PCIe function number from firmware (used for
1601 * per-function privilege and dynamic config info).
1602 * - PCIe PF: pf = PF number, vf = 0xffff.
1603 * - PCIe VF: pf = parent PF, vf = VF number.
1605 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1611 /* MAC address for this function */
1612 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1613 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1614 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1616 * Disable static config checking, ONLY for manufacturing test
1617 * and setup at the factory, to allow the static config to be
1620 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1621 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1623 * If the static config does not include a global MAC
1624 * address pool then the board may return a locally
1625 * administered MAC address (this should only happen on
1626 * incorrectly programmed boards).
1630 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1632 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1637 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1639 /* Board configuration (legacy) */
1640 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1642 /* Unprivileged functions may not be able to read board cfg */
1649 encp->enc_board_type = board_type;
1650 encp->enc_clk_mult = 1; /* not used for EF10 */
1652 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1653 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1656 /* Obtain the default PHY advertised capabilities */
1657 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1659 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
1660 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
1662 /* Check capabilities of running datapath firmware */
1663 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1666 /* Alignment for WPTR updates */
1667 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1670 * Maximum number of exclusive RSS contexts. EF10 hardware supports 64
1671 * in total, but 6 are reserved for shared contexts. They are a global
1672 * resource so not all may be available.
1674 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1676 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1677 /* No boundary crossing limits */
1678 encp->enc_tx_dma_desc_boundary = 0;
1681 * Maximum number of bytes into the frame the TCP header can start for
1682 * firmware assisted TSO to work.
1684 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1687 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1688 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1689 * resources (allocated to this PCIe function), which is zero until
1690 * after we have allocated VIs.
1692 encp->enc_evq_limit = 1024;
1693 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1694 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1696 encp->enc_buftbl_limit = 0xFFFFFFFF;
1698 /* Get interrupt vector limits */
1699 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1700 if (EFX_PCI_FUNCTION_IS_PF(encp))
1703 /* Ignore error (cannot query vector limits from a VF). */
1707 encp->enc_intr_vec_base = base;
1708 encp->enc_intr_limit = nvec;
1710 /* Get remaining controller-specific board config */
1711 if ((rc = enop->eno_board_cfg(enp)) != 0)
1718 EFSYS_PROBE(fail10);
1736 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1741 __checkReturn efx_rc_t
1743 __in efx_nic_t *enp)
1745 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1746 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1749 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1750 enp->en_family == EFX_FAMILY_MEDFORD ||
1751 enp->en_family == EFX_FAMILY_MEDFORD2);
1753 /* Read and clear any assertion state */
1754 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1757 /* Exit the assertion handler */
1758 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1762 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1765 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1769 * Set default driver config limits (based on board config).
1771 * FIXME: For now allocate a fixed number of VIs which is likely to be
1772 * sufficient and small enough to allow multiple functions on the same
1775 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1776 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1778 /* The client driver must configure and enable PIO buffer support */
1779 edcp->edc_max_piobuf_count = 0;
1780 edcp->edc_pio_alloc_size = 0;
1782 #if EFSYS_OPT_MAC_STATS
1783 /* Wipe the MAC statistics */
1784 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1788 #if EFSYS_OPT_LOOPBACK
1789 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1793 #if EFSYS_OPT_MON_STATS
1794 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1795 /* Unprivileged functions do not have access to sensors */
1801 encp->enc_features = enp->en_features;
1805 #if EFSYS_OPT_MON_STATS
1809 #if EFSYS_OPT_LOOPBACK
1813 #if EFSYS_OPT_MAC_STATS
1824 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1829 __checkReturn efx_rc_t
1830 ef10_nic_set_drv_limits(
1831 __inout efx_nic_t *enp,
1832 __in efx_drv_limits_t *edlp)
1834 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1835 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1836 uint32_t min_evq_count, max_evq_count;
1837 uint32_t min_rxq_count, max_rxq_count;
1838 uint32_t min_txq_count, max_txq_count;
1846 /* Get minimum required and maximum usable VI limits */
1847 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1848 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1849 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1851 edcp->edc_min_vi_count =
1852 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1854 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1855 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1856 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1858 edcp->edc_max_vi_count =
1859 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1862 * Check limits for sub-allocated piobuf blocks.
1863 * PIO is optional, so don't fail if the limits are incorrect.
1865 if ((encp->enc_piobuf_size == 0) ||
1866 (encp->enc_piobuf_limit == 0) ||
1867 (edlp->edl_min_pio_alloc_size == 0) ||
1868 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1870 edcp->edc_max_piobuf_count = 0;
1871 edcp->edc_pio_alloc_size = 0;
1873 uint32_t blk_size, blk_count, blks_per_piobuf;
1876 MAX(edlp->edl_min_pio_alloc_size,
1877 encp->enc_piobuf_min_alloc_size);
1879 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1880 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1882 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1884 /* A zero max pio alloc count means unlimited */
1885 if ((edlp->edl_max_pio_alloc_count > 0) &&
1886 (edlp->edl_max_pio_alloc_count < blk_count)) {
1887 blk_count = edlp->edl_max_pio_alloc_count;
1890 edcp->edc_pio_alloc_size = blk_size;
1891 edcp->edc_max_piobuf_count =
1892 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1898 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1904 __checkReturn efx_rc_t
1906 __in efx_nic_t *enp)
1909 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1910 MC_CMD_ENTITY_RESET_OUT_LEN)];
1913 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1914 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1916 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1919 (void) memset(payload, 0, sizeof (payload));
1920 req.emr_cmd = MC_CMD_ENTITY_RESET;
1921 req.emr_in_buf = payload;
1922 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1923 req.emr_out_buf = payload;
1924 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1926 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1927 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1929 efx_mcdi_execute(enp, &req);
1931 if (req.emr_rc != 0) {
1936 /* Clear RX/TX DMA queue errors */
1937 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1946 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1951 __checkReturn efx_rc_t
1953 __in efx_nic_t *enp)
1955 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1956 uint32_t min_vi_count, max_vi_count;
1957 uint32_t vi_count, vi_base, vi_shift;
1961 uint32_t vi_window_size;
1964 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1965 enp->en_family == EFX_FAMILY_MEDFORD ||
1966 enp->en_family == EFX_FAMILY_MEDFORD2);
1968 /* Enable reporting of some events (e.g. link change) */
1969 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1972 /* Allocate (optional) on-chip PIO buffers */
1973 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1976 * For best performance, PIO writes should use a write-combined
1977 * (WC) memory mapping. Using a separate WC mapping for the PIO
1978 * aperture of each VI would be a burden to drivers (and not
1979 * possible if the host page size is >4Kbyte).
1981 * To avoid this we use a single uncached (UC) mapping for VI
1982 * register access, and a single WC mapping for extra VIs used
1985 * Each piobuf must be linked to a VI in the WC mapping, and to
1986 * each VI that is using a sub-allocated block from the piobuf.
1988 min_vi_count = edcp->edc_min_vi_count;
1990 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1992 /* Ensure that the previously attached driver's VIs are freed */
1993 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1997 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1998 * fails then retrying the request for fewer VI resources may succeed.
2001 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2002 &vi_base, &vi_count, &vi_shift)) != 0)
2005 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2007 if (vi_count < min_vi_count) {
2012 enp->en_arch.ef10.ena_vi_base = vi_base;
2013 enp->en_arch.ef10.ena_vi_count = vi_count;
2014 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2016 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2017 /* Not enough extra VIs to map piobufs */
2018 ef10_nic_free_piobufs(enp);
2021 enp->en_arch.ef10.ena_pio_write_vi_base =
2022 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2024 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2025 EFX_VI_WINDOW_SHIFT_INVALID);
2026 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2027 EFX_VI_WINDOW_SHIFT_64K);
2028 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2030 /* Save UC memory mapping details */
2031 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2032 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2033 enp->en_arch.ef10.ena_uc_mem_map_size =
2035 enp->en_arch.ef10.ena_pio_write_vi_base);
2037 enp->en_arch.ef10.ena_uc_mem_map_size =
2039 enp->en_arch.ef10.ena_vi_count);
2042 /* Save WC memory mapping details */
2043 enp->en_arch.ef10.ena_wc_mem_map_offset =
2044 enp->en_arch.ef10.ena_uc_mem_map_offset +
2045 enp->en_arch.ef10.ena_uc_mem_map_size;
2047 enp->en_arch.ef10.ena_wc_mem_map_size =
2049 enp->en_arch.ef10.ena_piobuf_count);
2051 /* Link piobufs to extra VIs in WC mapping */
2052 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2053 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2054 rc = efx_mcdi_link_piobuf(enp,
2055 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2056 enp->en_arch.ef10.ena_piobuf_handle[i]);
2063 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2065 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2066 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2067 * retry the request several times after waiting a while. The wait time
2068 * between retries starts small (10ms) and exponentially increases.
2069 * Total wait time is a little over two seconds. Retry logic in the
2070 * client driver may mean this whole loop is repeated if it continues to
2075 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2076 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2079 * Do not retry alloc for PF, or for other errors on
2085 /* VF startup before PF is ready. Retry allocation. */
2087 /* Too many attempts */
2091 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2092 EFSYS_SLEEP(delay_us);
2094 if (delay_us < 500000)
2098 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2099 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2114 ef10_nic_free_piobufs(enp);
2117 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2122 __checkReturn efx_rc_t
2123 ef10_nic_get_vi_pool(
2124 __in efx_nic_t *enp,
2125 __out uint32_t *vi_countp)
2127 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2128 enp->en_family == EFX_FAMILY_MEDFORD ||
2129 enp->en_family == EFX_FAMILY_MEDFORD2);
2132 * Report VIs that the client driver can use.
2133 * Do not include VIs used for PIO buffer writes.
2135 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2140 __checkReturn efx_rc_t
2141 ef10_nic_get_bar_region(
2142 __in efx_nic_t *enp,
2143 __in efx_nic_region_t region,
2144 __out uint32_t *offsetp,
2145 __out size_t *sizep)
2149 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2150 enp->en_family == EFX_FAMILY_MEDFORD ||
2151 enp->en_family == EFX_FAMILY_MEDFORD2);
2154 * TODO: Specify host memory mapping alignment and granularity
2155 * in efx_drv_limits_t so that they can be taken into account
2156 * when allocating extra VIs for PIO writes.
2160 /* UC mapped memory BAR region for VI registers */
2161 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2162 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2165 case EFX_REGION_PIO_WRITE_VI:
2166 /* WC mapped memory BAR region for piobuf writes */
2167 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2168 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2179 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2186 __in efx_nic_t *enp)
2191 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2192 enp->en_vport_id = 0;
2194 /* Unlink piobufs from extra VIs in WC mapping */
2195 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2196 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2197 rc = efx_mcdi_unlink_piobuf(enp,
2198 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2204 ef10_nic_free_piobufs(enp);
2206 (void) efx_mcdi_free_vis(enp);
2207 enp->en_arch.ef10.ena_vi_count = 0;
2212 __in efx_nic_t *enp)
2214 #if EFSYS_OPT_MON_STATS
2215 mcdi_mon_cfg_free(enp);
2216 #endif /* EFSYS_OPT_MON_STATS */
2217 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2222 __checkReturn efx_rc_t
2223 ef10_nic_register_test(
2224 __in efx_nic_t *enp)
2229 _NOTE(ARGUNUSED(enp))
2230 _NOTE(CONSTANTCONDITION)
2240 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2245 #endif /* EFSYS_OPT_DIAG */
2248 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */