2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD ||
56 enp->en_family == EFX_FAMILY_MEDFORD2);
58 (void) memset(payload, 0, sizeof (payload));
59 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
60 req.emr_in_buf = payload;
61 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
62 req.emr_out_buf = payload;
63 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
65 efx_mcdi_execute(enp, &req);
67 if (req.emr_rc != 0) {
72 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
77 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
84 EFSYS_PROBE1(fail1, efx_rc_t, rc);
89 __checkReturn efx_rc_t
90 efx_mcdi_get_port_modes(
92 __out uint32_t *modesp,
93 __out_opt uint32_t *current_modep,
94 __out_opt uint32_t *default_modep)
97 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
98 MC_CMD_GET_PORT_MODES_OUT_LEN)];
101 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
102 enp->en_family == EFX_FAMILY_MEDFORD ||
103 enp->en_family == EFX_FAMILY_MEDFORD2);
105 (void) memset(payload, 0, sizeof (payload));
106 req.emr_cmd = MC_CMD_GET_PORT_MODES;
107 req.emr_in_buf = payload;
108 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
109 req.emr_out_buf = payload;
110 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
112 efx_mcdi_execute(enp, &req);
114 if (req.emr_rc != 0) {
120 * Require only Modes and DefaultMode fields, unless the current mode
121 * was requested (CurrentMode field was added for Medford).
123 if (req.emr_out_length_used <
124 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
128 if ((current_modep != NULL) && (req.emr_out_length_used <
129 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
134 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
136 if (current_modep != NULL) {
137 *current_modep = MCDI_OUT_DWORD(req,
138 GET_PORT_MODES_OUT_CURRENT_MODE);
141 if (default_modep != NULL) {
142 *default_modep = MCDI_OUT_DWORD(req,
143 GET_PORT_MODES_OUT_DEFAULT_MODE);
153 EFSYS_PROBE1(fail1, efx_rc_t, rc);
158 __checkReturn efx_rc_t
159 ef10_nic_get_port_mode_bandwidth(
160 __in uint32_t port_mode,
161 __out uint32_t *bandwidth_mbpsp)
167 case TLV_PORT_MODE_10G:
170 case TLV_PORT_MODE_10G_10G:
171 bandwidth = 10000 * 2;
173 case TLV_PORT_MODE_10G_10G_10G_10G:
174 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
175 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
176 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
177 bandwidth = 10000 * 4;
179 case TLV_PORT_MODE_40G:
182 case TLV_PORT_MODE_40G_40G:
183 bandwidth = 40000 * 2;
185 case TLV_PORT_MODE_40G_10G_10G:
186 case TLV_PORT_MODE_10G_10G_40G:
187 bandwidth = 40000 + (10000 * 2);
194 *bandwidth_mbpsp = bandwidth;
199 EFSYS_PROBE1(fail1, efx_rc_t, rc);
204 static __checkReturn efx_rc_t
205 efx_mcdi_vadaptor_alloc(
207 __in uint32_t port_id)
210 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
211 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
214 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
216 (void) memset(payload, 0, sizeof (payload));
217 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
218 req.emr_in_buf = payload;
219 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
220 req.emr_out_buf = payload;
221 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
223 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
224 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
225 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
226 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
228 efx_mcdi_execute(enp, &req);
230 if (req.emr_rc != 0) {
238 EFSYS_PROBE1(fail1, efx_rc_t, rc);
243 static __checkReturn efx_rc_t
244 efx_mcdi_vadaptor_free(
246 __in uint32_t port_id)
249 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
250 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
253 (void) memset(payload, 0, sizeof (payload));
254 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
255 req.emr_in_buf = payload;
256 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
257 req.emr_out_buf = payload;
258 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
260 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
262 efx_mcdi_execute(enp, &req);
264 if (req.emr_rc != 0) {
272 EFSYS_PROBE1(fail1, efx_rc_t, rc);
277 __checkReturn efx_rc_t
278 efx_mcdi_get_mac_address_pf(
280 __out_ecount_opt(6) uint8_t mac_addrp[6])
283 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
284 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
287 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
288 enp->en_family == EFX_FAMILY_MEDFORD ||
289 enp->en_family == EFX_FAMILY_MEDFORD2);
291 (void) memset(payload, 0, sizeof (payload));
292 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
293 req.emr_in_buf = payload;
294 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
295 req.emr_out_buf = payload;
296 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
298 efx_mcdi_execute(enp, &req);
300 if (req.emr_rc != 0) {
305 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
310 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
315 if (mac_addrp != NULL) {
318 addrp = MCDI_OUT2(req, uint8_t,
319 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
321 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
331 EFSYS_PROBE1(fail1, efx_rc_t, rc);
336 __checkReturn efx_rc_t
337 efx_mcdi_get_mac_address_vf(
339 __out_ecount_opt(6) uint8_t mac_addrp[6])
342 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
343 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
346 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
347 enp->en_family == EFX_FAMILY_MEDFORD ||
348 enp->en_family == EFX_FAMILY_MEDFORD2);
350 (void) memset(payload, 0, sizeof (payload));
351 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
352 req.emr_in_buf = payload;
353 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
354 req.emr_out_buf = payload;
355 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
357 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
358 EVB_PORT_ID_ASSIGNED);
360 efx_mcdi_execute(enp, &req);
362 if (req.emr_rc != 0) {
367 if (req.emr_out_length_used <
368 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
373 if (MCDI_OUT_DWORD(req,
374 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
379 if (mac_addrp != NULL) {
382 addrp = MCDI_OUT2(req, uint8_t,
383 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
385 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
395 EFSYS_PROBE1(fail1, efx_rc_t, rc);
400 __checkReturn efx_rc_t
403 __out uint32_t *sys_freqp,
404 __out uint32_t *dpcpu_freqp)
407 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
408 MC_CMD_GET_CLOCK_OUT_LEN)];
411 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
412 enp->en_family == EFX_FAMILY_MEDFORD ||
413 enp->en_family == EFX_FAMILY_MEDFORD2);
415 (void) memset(payload, 0, sizeof (payload));
416 req.emr_cmd = MC_CMD_GET_CLOCK;
417 req.emr_in_buf = payload;
418 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
419 req.emr_out_buf = payload;
420 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
422 efx_mcdi_execute(enp, &req);
424 if (req.emr_rc != 0) {
429 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
434 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
435 if (*sys_freqp == 0) {
439 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
440 if (*dpcpu_freqp == 0) {
454 EFSYS_PROBE1(fail1, efx_rc_t, rc);
459 __checkReturn efx_rc_t
460 efx_mcdi_get_rxdp_config(
462 __out uint32_t *end_paddingp)
465 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
466 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
467 uint32_t end_padding;
470 memset(payload, 0, sizeof (payload));
471 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
472 req.emr_in_buf = payload;
473 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
474 req.emr_out_buf = payload;
475 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
477 efx_mcdi_execute(enp, &req);
478 if (req.emr_rc != 0) {
483 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
484 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
485 /* RX DMA end padding is disabled */
488 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
489 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
490 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
493 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
496 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
505 *end_paddingp = end_padding;
512 EFSYS_PROBE1(fail1, efx_rc_t, rc);
517 __checkReturn efx_rc_t
518 efx_mcdi_get_vector_cfg(
520 __out_opt uint32_t *vec_basep,
521 __out_opt uint32_t *pf_nvecp,
522 __out_opt uint32_t *vf_nvecp)
525 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
526 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
529 (void) memset(payload, 0, sizeof (payload));
530 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
531 req.emr_in_buf = payload;
532 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
533 req.emr_out_buf = payload;
534 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
536 efx_mcdi_execute(enp, &req);
538 if (req.emr_rc != 0) {
543 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
548 if (vec_basep != NULL)
549 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
550 if (pf_nvecp != NULL)
551 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
552 if (vf_nvecp != NULL)
553 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
560 EFSYS_PROBE1(fail1, efx_rc_t, rc);
565 static __checkReturn efx_rc_t
568 __in uint32_t min_vi_count,
569 __in uint32_t max_vi_count,
570 __out uint32_t *vi_basep,
571 __out uint32_t *vi_countp,
572 __out uint32_t *vi_shiftp)
575 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
576 MC_CMD_ALLOC_VIS_EXT_OUT_LEN)];
579 if (vi_countp == NULL) {
584 (void) memset(payload, 0, sizeof (payload));
585 req.emr_cmd = MC_CMD_ALLOC_VIS;
586 req.emr_in_buf = payload;
587 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
588 req.emr_out_buf = payload;
589 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
591 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
592 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
594 efx_mcdi_execute(enp, &req);
596 if (req.emr_rc != 0) {
601 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
606 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
607 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
609 /* Report VI_SHIFT if available (always zero for Huntington) */
610 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
613 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
622 EFSYS_PROBE1(fail1, efx_rc_t, rc);
628 static __checkReturn efx_rc_t
635 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
636 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
638 req.emr_cmd = MC_CMD_FREE_VIS;
639 req.emr_in_buf = NULL;
640 req.emr_in_length = 0;
641 req.emr_out_buf = NULL;
642 req.emr_out_length = 0;
644 efx_mcdi_execute_quiet(enp, &req);
646 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
647 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
655 EFSYS_PROBE1(fail1, efx_rc_t, rc);
661 static __checkReturn efx_rc_t
662 efx_mcdi_alloc_piobuf(
664 __out efx_piobuf_handle_t *handlep)
667 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
668 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
671 if (handlep == NULL) {
676 (void) memset(payload, 0, sizeof (payload));
677 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
678 req.emr_in_buf = payload;
679 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
680 req.emr_out_buf = payload;
681 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
683 efx_mcdi_execute_quiet(enp, &req);
685 if (req.emr_rc != 0) {
690 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
695 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
704 EFSYS_PROBE1(fail1, efx_rc_t, rc);
709 static __checkReturn efx_rc_t
710 efx_mcdi_free_piobuf(
712 __in efx_piobuf_handle_t handle)
715 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
716 MC_CMD_FREE_PIOBUF_OUT_LEN)];
719 (void) memset(payload, 0, sizeof (payload));
720 req.emr_cmd = MC_CMD_FREE_PIOBUF;
721 req.emr_in_buf = payload;
722 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
723 req.emr_out_buf = payload;
724 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
726 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
728 efx_mcdi_execute_quiet(enp, &req);
730 if (req.emr_rc != 0) {
738 EFSYS_PROBE1(fail1, efx_rc_t, rc);
743 static __checkReturn efx_rc_t
744 efx_mcdi_link_piobuf(
746 __in uint32_t vi_index,
747 __in efx_piobuf_handle_t handle)
750 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
751 MC_CMD_LINK_PIOBUF_OUT_LEN)];
754 (void) memset(payload, 0, sizeof (payload));
755 req.emr_cmd = MC_CMD_LINK_PIOBUF;
756 req.emr_in_buf = payload;
757 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
758 req.emr_out_buf = payload;
759 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
761 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
762 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
764 efx_mcdi_execute(enp, &req);
766 if (req.emr_rc != 0) {
774 EFSYS_PROBE1(fail1, efx_rc_t, rc);
779 static __checkReturn efx_rc_t
780 efx_mcdi_unlink_piobuf(
782 __in uint32_t vi_index)
785 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
786 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
789 (void) memset(payload, 0, sizeof (payload));
790 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
791 req.emr_in_buf = payload;
792 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
793 req.emr_out_buf = payload;
794 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
796 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
798 efx_mcdi_execute_quiet(enp, &req);
800 if (req.emr_rc != 0) {
808 EFSYS_PROBE1(fail1, efx_rc_t, rc);
814 ef10_nic_alloc_piobufs(
816 __in uint32_t max_piobuf_count)
818 efx_piobuf_handle_t *handlep;
821 EFSYS_ASSERT3U(max_piobuf_count, <=,
822 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
824 enp->en_arch.ef10.ena_piobuf_count = 0;
826 for (i = 0; i < max_piobuf_count; i++) {
827 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
829 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
832 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
833 enp->en_arch.ef10.ena_piobuf_count++;
839 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
840 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
842 (void) efx_mcdi_free_piobuf(enp, *handlep);
843 *handlep = EFX_PIOBUF_HANDLE_INVALID;
845 enp->en_arch.ef10.ena_piobuf_count = 0;
850 ef10_nic_free_piobufs(
853 efx_piobuf_handle_t *handlep;
856 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
857 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
859 (void) efx_mcdi_free_piobuf(enp, *handlep);
860 *handlep = EFX_PIOBUF_HANDLE_INVALID;
862 enp->en_arch.ef10.ena_piobuf_count = 0;
865 /* Sub-allocate a block from a piobuf */
866 __checkReturn efx_rc_t
868 __inout efx_nic_t *enp,
869 __out uint32_t *bufnump,
870 __out efx_piobuf_handle_t *handlep,
871 __out uint32_t *blknump,
872 __out uint32_t *offsetp,
875 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
876 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
877 uint32_t blk_per_buf;
881 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
882 enp->en_family == EFX_FAMILY_MEDFORD ||
883 enp->en_family == EFX_FAMILY_MEDFORD2);
884 EFSYS_ASSERT(bufnump);
885 EFSYS_ASSERT(handlep);
886 EFSYS_ASSERT(blknump);
887 EFSYS_ASSERT(offsetp);
890 if ((edcp->edc_pio_alloc_size == 0) ||
891 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
895 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
897 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
898 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
903 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
904 for (blk = 0; blk < blk_per_buf; blk++) {
905 if ((*map & (1u << blk)) == 0) {
915 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
918 *sizep = edcp->edc_pio_alloc_size;
919 *offsetp = blk * (*sizep);
926 EFSYS_PROBE1(fail1, efx_rc_t, rc);
931 /* Free a piobuf sub-allocated block */
932 __checkReturn efx_rc_t
934 __inout efx_nic_t *enp,
935 __in uint32_t bufnum,
936 __in uint32_t blknum)
941 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
942 (blknum >= (8 * sizeof (*map)))) {
947 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
948 if ((*map & (1u << blknum)) == 0) {
952 *map &= ~(1u << blknum);
959 EFSYS_PROBE1(fail1, efx_rc_t, rc);
964 __checkReturn efx_rc_t
966 __inout efx_nic_t *enp,
967 __in uint32_t vi_index,
968 __in efx_piobuf_handle_t handle)
970 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
973 __checkReturn efx_rc_t
975 __inout efx_nic_t *enp,
976 __in uint32_t vi_index)
978 return (efx_mcdi_unlink_piobuf(enp, vi_index));
981 static __checkReturn efx_rc_t
982 ef10_mcdi_get_pf_count(
984 __out uint32_t *pf_countp)
987 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
988 MC_CMD_GET_PF_COUNT_OUT_LEN)];
991 (void) memset(payload, 0, sizeof (payload));
992 req.emr_cmd = MC_CMD_GET_PF_COUNT;
993 req.emr_in_buf = payload;
994 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
995 req.emr_out_buf = payload;
996 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
998 efx_mcdi_execute(enp, &req);
1000 if (req.emr_rc != 0) {
1005 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1010 *pf_countp = *MCDI_OUT(req, uint8_t,
1011 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1013 EFSYS_ASSERT(*pf_countp != 0);
1020 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1025 static __checkReturn efx_rc_t
1026 ef10_get_datapath_caps(
1027 __in efx_nic_t *enp)
1029 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1031 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
1032 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)];
1035 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1039 (void) memset(payload, 0, sizeof (payload));
1040 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1041 req.emr_in_buf = payload;
1042 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1043 req.emr_out_buf = payload;
1044 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1046 efx_mcdi_execute_quiet(enp, &req);
1048 if (req.emr_rc != 0) {
1053 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1058 #define CAP_FLAGS1(_req, _flag) \
1059 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1060 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1062 #define CAP_FLAGS2(_req, _flag) \
1063 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1064 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1065 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1068 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1069 * We only support the 14 byte prefix here.
1071 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1075 encp->enc_rx_prefix_size = 14;
1077 /* Check if the firmware supports additional RSS modes */
1078 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1079 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1081 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1083 /* Check if the firmware supports TSO */
1084 if (CAP_FLAGS1(req, TX_TSO))
1085 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1087 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1089 /* Check if the firmware supports FATSOv2 */
1090 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1091 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1092 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1093 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1095 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1096 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1099 /* Check if the firmware supports FATSOv2 encap */
1100 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1101 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1103 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1105 /* Check if the firmware has vadapter/vport/vswitch support */
1106 if (CAP_FLAGS1(req, EVB))
1107 encp->enc_datapath_cap_evb = B_TRUE;
1109 encp->enc_datapath_cap_evb = B_FALSE;
1111 /* Check if the firmware supports VLAN insertion */
1112 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1113 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1115 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1117 /* Check if the firmware supports RX event batching */
1118 if (CAP_FLAGS1(req, RX_BATCHING))
1119 encp->enc_rx_batching_enabled = B_TRUE;
1121 encp->enc_rx_batching_enabled = B_FALSE;
1124 * Even if batching isn't reported as supported, we may still get
1127 encp->enc_rx_batch_max = 16;
1129 /* Check if the firmware supports disabling scatter on RXQs */
1130 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1131 encp->enc_rx_disable_scatter_supported = B_TRUE;
1133 encp->enc_rx_disable_scatter_supported = B_FALSE;
1135 /* Check if the firmware supports packed stream mode */
1136 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1137 encp->enc_rx_packed_stream_supported = B_TRUE;
1139 encp->enc_rx_packed_stream_supported = B_FALSE;
1142 * Check if the firmware supports configurable buffer sizes
1143 * for packed stream mode (otherwise buffer size is 1Mbyte)
1145 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1146 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1148 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1150 /* Check if the firmware supports equal stride super-buffer mode */
1151 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1152 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1154 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1156 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1157 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1158 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1160 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1162 /* Check if the firmware supports set mac with running filters */
1163 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1164 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1166 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1169 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1170 * specifying which parameters to configure.
1172 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1173 encp->enc_enhanced_set_mac_supported = B_TRUE;
1175 encp->enc_enhanced_set_mac_supported = B_FALSE;
1178 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1179 * us to let the firmware choose the settings to use on an EVQ.
1181 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1182 encp->enc_init_evq_v2_supported = B_TRUE;
1184 encp->enc_init_evq_v2_supported = B_FALSE;
1187 * Check if firmware-verified NVRAM updates must be used.
1189 * The firmware trusted installer requires all NVRAM updates to use
1190 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1191 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1192 * partition and report the result).
1194 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1195 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1197 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1200 * Check if firmware provides packet memory and Rx datapath
1203 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1204 encp->enc_pm_and_rxdp_counters = B_TRUE;
1206 encp->enc_pm_and_rxdp_counters = B_FALSE;
1209 * Check if the 40G MAC hardware is capable of reporting
1210 * statistics for Tx size bins.
1212 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1213 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1215 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1218 * Check if firmware supports VXLAN and NVGRE tunnels.
1219 * The capability indicates Geneve protocol support as well.
1221 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1222 encp->enc_tunnel_encapsulations_supported =
1223 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1224 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1225 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1227 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1228 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1229 encp->enc_tunnel_config_udp_entries_max =
1230 EFX_TUNNEL_MAXNENTRIES;
1232 encp->enc_tunnel_config_udp_entries_max = 0;
1236 * Check if firmware reports the VI window mode.
1237 * Medford2 has a variable VI window size (8K, 16K or 64K).
1238 * Medford and Huntington have a fixed 8K VI window size.
1240 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1242 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1245 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1246 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1248 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1249 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1251 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1252 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1255 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1258 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1259 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1260 /* Huntington and Medford have fixed 8K window size */
1261 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1263 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1266 /* Check if firmware supports extended MAC stats. */
1267 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1268 /* Extended stats buffer supported */
1269 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1270 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1272 /* Use Siena-compatible legacy MAC stats */
1273 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1276 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1277 encp->enc_fec_counters = B_TRUE;
1279 encp->enc_fec_counters = B_FALSE;
1281 /* Check if the firmware provides head-of-line blocking counters */
1282 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1283 encp->enc_hlb_counters = B_TRUE;
1285 encp->enc_hlb_counters = B_FALSE;
1287 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1288 /* Only one exclusive RSS context is available per port. */
1289 encp->enc_rx_scale_max_exclusive_contexts = 1;
1291 switch (enp->en_family) {
1292 case EFX_FAMILY_MEDFORD2:
1293 encp->enc_rx_scale_hash_alg_mask =
1294 (1U << EFX_RX_HASHALG_TOEPLITZ);
1297 case EFX_FAMILY_MEDFORD:
1298 case EFX_FAMILY_HUNTINGTON:
1300 * Packed stream firmware variant maintains a
1301 * non-standard algorithm for hash computation.
1302 * It implies explicit XORing together
1303 * source + destination IP addresses (or last
1304 * four bytes in the case of IPv6) and using the
1305 * resulting value as the input to a Toeplitz hash.
1307 encp->enc_rx_scale_hash_alg_mask =
1308 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1316 /* Port numbers cannot contribute to the hash value */
1317 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1320 * Maximum number of exclusive RSS contexts.
1321 * EF10 hardware supports 64 in total, but 6 are reserved
1322 * for shared contexts. They are a global resource so
1323 * not all may be available.
1325 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1327 encp->enc_rx_scale_hash_alg_mask =
1328 (1U << EFX_RX_HASHALG_TOEPLITZ);
1331 * It is possible to use port numbers as
1332 * the input data for hash computation.
1334 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1336 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1337 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1338 encp->enc_filter_action_flag_supported = B_TRUE;
1340 encp->enc_filter_action_flag_supported = B_FALSE;
1342 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1343 encp->enc_filter_action_mark_supported = B_TRUE;
1345 encp->enc_filter_action_mark_supported = B_FALSE;
1347 /* Get maximum supported value for "MARK" filter action */
1348 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1349 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1350 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1352 encp->enc_filter_action_mark_max = 0;
1368 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1374 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1375 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1376 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1377 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1378 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1379 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1380 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1381 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1382 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1383 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1384 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1385 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1387 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1390 __checkReturn efx_rc_t
1391 ef10_get_privilege_mask(
1392 __in efx_nic_t *enp,
1393 __out uint32_t *maskp)
1395 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1399 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1404 /* Fallback for old firmware without privilege mask support */
1405 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1406 /* Assume PF has admin privilege */
1407 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1409 /* VF is always unprivileged by default */
1410 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1419 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1426 * Table of mapping schemes from port number to external number.
1428 * Each port number ultimately corresponds to a connector: either as part of
1429 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1430 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1431 * "Salina"). In general:
1433 * Port number (0-based)
1435 * port mapping (n:1)
1438 * External port number (normally 1-based)
1440 * fixed (1:1) or cable assembly (1:m)
1445 * The external numbering refers to the cages or magjacks on the board,
1446 * as visibly annotated on the board or back panel. This table describes
1447 * how to determine which external cage/magjack corresponds to the port
1448 * numbers used by the driver.
1450 * The count of adjacent port numbers that map to each external number,
1451 * and the offset in the numbering, is determined by the chip family and
1452 * current port mode.
1454 * For the Huntington family, the current port mode cannot be discovered,
1455 * but a single mapping is used by all modes for a given chip variant,
1456 * so the mapping used is instead the last match in the table to the full
1457 * set of port modes to which the NIC can be configured. Therefore the
1458 * ordering of entries in the mapping table is significant.
1460 static struct ef10_external_port_map_s {
1461 efx_family_t family;
1462 uint32_t modes_mask;
1465 } __ef10_external_port_mappings[] = {
1467 * Modes used by Huntington family controllers where each port
1468 * number maps to a separate cage.
1469 * SFN7x22F (Torino):
1479 EFX_FAMILY_HUNTINGTON,
1480 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1481 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1482 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1483 1, /* ports per cage */
1487 * Modes which for Huntington identify a chip variant where 2
1488 * adjacent port numbers map to each cage.
1496 EFX_FAMILY_HUNTINGTON,
1497 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1498 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1499 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1500 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1501 2, /* ports per cage */
1505 * Modes that on Medford allocate each port number to a separate
1514 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1515 (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
1516 1, /* ports per cage */
1520 * Modes that on Medford allocate 2 adjacent port numbers to each
1529 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1530 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1531 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1532 (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */
1533 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1534 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1535 2, /* ports per cage */
1539 * Modes that on Medford allocate 4 adjacent port numbers to each
1540 * connector, starting on cage 1.
1548 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */
1549 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1550 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */
1551 4, /* ports per cage */
1555 * Modes that on Medford allocate 4 adjacent port numbers to each
1556 * connector, starting on cage 2.
1564 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */
1565 4, /* ports per cage */
1569 * Modes that on Medford2 allocate each port number to a separate
1577 EFX_FAMILY_MEDFORD2,
1578 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1579 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1580 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1581 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1582 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1583 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1584 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1585 1, /* ports per cage */
1589 * FIXME: Some port modes are not representable in this mapping:
1590 * - TLV_PORT_MODE_1x2_2x1 (mode 17):
1596 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1597 * cage, starting on cage 1.
1604 EFX_FAMILY_MEDFORD2,
1605 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1606 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1607 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1608 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1609 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1610 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1611 2, /* ports per cage */
1615 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1616 * cage, starting on cage 2.
1621 EFX_FAMILY_MEDFORD2,
1622 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1623 2, /* ports per cage */
1627 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1628 * connector, starting on cage 1.
1635 EFX_FAMILY_MEDFORD2,
1636 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1637 4, /* ports per cage */
1641 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1642 * connector, starting on cage 2.
1649 EFX_FAMILY_MEDFORD2,
1650 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1651 (1U << TLV_PORT_MODE_NA_1x2), /* mode 11 */
1652 4, /* ports per cage */
1657 static __checkReturn efx_rc_t
1658 ef10_external_port_mapping(
1659 __in efx_nic_t *enp,
1661 __out uint8_t *external_portp)
1665 uint32_t port_modes;
1668 int32_t count = 1; /* Default 1-1 mapping */
1669 int32_t offset = 1; /* Default starting external port number */
1671 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1674 * No current port mode information (i.e. Huntington)
1675 * - infer mapping from available modes
1677 if ((rc = efx_mcdi_get_port_modes(enp,
1678 &port_modes, NULL, NULL)) != 0) {
1680 * No port mode information available
1681 * - use default mapping
1686 /* Only need to scan the current mode */
1687 port_modes = 1 << current;
1691 * Infer the internal port -> external number mapping from
1692 * the possible port modes for this NIC.
1694 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1695 struct ef10_external_port_map_s *eepmp =
1696 &__ef10_external_port_mappings[i];
1697 if (eepmp->family != enp->en_family)
1699 matches = (eepmp->modes_mask & port_modes);
1702 * Some modes match. For some Huntington boards
1703 * there will be multiple matches. The mapping on the
1704 * last match is used.
1706 count = eepmp->count;
1707 offset = eepmp->offset;
1708 port_modes &= ~matches;
1712 if (port_modes != 0) {
1713 /* Some advertised modes are not supported */
1720 * Scale as required by last matched mode and then convert to
1721 * correctly offset numbering
1723 *external_portp = (uint8_t)((port / count) + offset);
1727 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1732 static __checkReturn efx_rc_t
1734 __in efx_nic_t *enp)
1736 const efx_nic_ops_t *enop = enp->en_enop;
1737 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1738 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1739 ef10_link_state_t els;
1740 efx_port_t *epp = &(enp->en_port);
1741 uint32_t board_type = 0;
1742 uint32_t base, nvec;
1747 uint8_t mac_addr[6] = { 0 };
1750 /* Get the (zero-based) MCDI port number */
1751 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1754 /* EFX MCDI interface uses one-based port numbers */
1755 emip->emi_port = port + 1;
1757 if ((rc = ef10_external_port_mapping(enp, port,
1758 &encp->enc_external_port)) != 0)
1762 * Get PCIe function number from firmware (used for
1763 * per-function privilege and dynamic config info).
1764 * - PCIe PF: pf = PF number, vf = 0xffff.
1765 * - PCIe VF: pf = parent PF, vf = VF number.
1767 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1773 /* MAC address for this function */
1774 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1775 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1776 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1778 * Disable static config checking, ONLY for manufacturing test
1779 * and setup at the factory, to allow the static config to be
1782 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1783 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1785 * If the static config does not include a global MAC
1786 * address pool then the board may return a locally
1787 * administered MAC address (this should only happen on
1788 * incorrectly programmed boards).
1792 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1794 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1799 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1801 /* Board configuration (legacy) */
1802 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1804 /* Unprivileged functions may not be able to read board cfg */
1811 encp->enc_board_type = board_type;
1812 encp->enc_clk_mult = 1; /* not used for EF10 */
1814 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1815 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1818 /* Obtain the default PHY advertised capabilities */
1819 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1821 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
1822 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
1824 /* Check capabilities of running datapath firmware */
1825 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1828 /* Alignment for WPTR updates */
1829 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1831 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1832 /* No boundary crossing limits */
1833 encp->enc_tx_dma_desc_boundary = 0;
1836 * Maximum number of bytes into the frame the TCP header can start for
1837 * firmware assisted TSO to work.
1839 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1842 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1843 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1844 * resources (allocated to this PCIe function), which is zero until
1845 * after we have allocated VIs.
1847 encp->enc_evq_limit = 1024;
1848 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1849 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1851 encp->enc_buftbl_limit = 0xFFFFFFFF;
1853 /* Get interrupt vector limits */
1854 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1855 if (EFX_PCI_FUNCTION_IS_PF(encp))
1858 /* Ignore error (cannot query vector limits from a VF). */
1862 encp->enc_intr_vec_base = base;
1863 encp->enc_intr_limit = nvec;
1866 * Get the current privilege mask. Note that this may be modified
1867 * dynamically, so this value is informational only. DO NOT use
1868 * the privilege mask to check for sufficient privileges, as that
1869 * can result in time-of-check/time-of-use bugs.
1871 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1873 encp->enc_privilege_mask = mask;
1875 /* Get remaining controller-specific board config */
1876 if ((rc = enop->eno_board_cfg(enp)) != 0)
1883 EFSYS_PROBE(fail11);
1885 EFSYS_PROBE(fail10);
1903 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1908 __checkReturn efx_rc_t
1910 __in efx_nic_t *enp)
1912 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1913 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1916 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1917 enp->en_family == EFX_FAMILY_MEDFORD ||
1918 enp->en_family == EFX_FAMILY_MEDFORD2);
1920 /* Read and clear any assertion state */
1921 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1924 /* Exit the assertion handler */
1925 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1929 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1932 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1936 * Set default driver config limits (based on board config).
1938 * FIXME: For now allocate a fixed number of VIs which is likely to be
1939 * sufficient and small enough to allow multiple functions on the same
1942 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1943 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1945 /* The client driver must configure and enable PIO buffer support */
1946 edcp->edc_max_piobuf_count = 0;
1947 edcp->edc_pio_alloc_size = 0;
1949 #if EFSYS_OPT_MAC_STATS
1950 /* Wipe the MAC statistics */
1951 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1955 #if EFSYS_OPT_LOOPBACK
1956 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1960 #if EFSYS_OPT_MON_STATS
1961 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1962 /* Unprivileged functions do not have access to sensors */
1968 encp->enc_features = enp->en_features;
1972 #if EFSYS_OPT_MON_STATS
1976 #if EFSYS_OPT_LOOPBACK
1980 #if EFSYS_OPT_MAC_STATS
1991 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1996 __checkReturn efx_rc_t
1997 ef10_nic_set_drv_limits(
1998 __inout efx_nic_t *enp,
1999 __in efx_drv_limits_t *edlp)
2001 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2002 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2003 uint32_t min_evq_count, max_evq_count;
2004 uint32_t min_rxq_count, max_rxq_count;
2005 uint32_t min_txq_count, max_txq_count;
2013 /* Get minimum required and maximum usable VI limits */
2014 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2015 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2016 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2018 edcp->edc_min_vi_count =
2019 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2021 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2022 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2023 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2025 edcp->edc_max_vi_count =
2026 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2029 * Check limits for sub-allocated piobuf blocks.
2030 * PIO is optional, so don't fail if the limits are incorrect.
2032 if ((encp->enc_piobuf_size == 0) ||
2033 (encp->enc_piobuf_limit == 0) ||
2034 (edlp->edl_min_pio_alloc_size == 0) ||
2035 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2037 edcp->edc_max_piobuf_count = 0;
2038 edcp->edc_pio_alloc_size = 0;
2040 uint32_t blk_size, blk_count, blks_per_piobuf;
2043 MAX(edlp->edl_min_pio_alloc_size,
2044 encp->enc_piobuf_min_alloc_size);
2046 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2047 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2049 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2051 /* A zero max pio alloc count means unlimited */
2052 if ((edlp->edl_max_pio_alloc_count > 0) &&
2053 (edlp->edl_max_pio_alloc_count < blk_count)) {
2054 blk_count = edlp->edl_max_pio_alloc_count;
2057 edcp->edc_pio_alloc_size = blk_size;
2058 edcp->edc_max_piobuf_count =
2059 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2065 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2071 __checkReturn efx_rc_t
2073 __in efx_nic_t *enp)
2076 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
2077 MC_CMD_ENTITY_RESET_OUT_LEN)];
2080 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2081 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2083 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2086 (void) memset(payload, 0, sizeof (payload));
2087 req.emr_cmd = MC_CMD_ENTITY_RESET;
2088 req.emr_in_buf = payload;
2089 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2090 req.emr_out_buf = payload;
2091 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2093 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2094 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2096 efx_mcdi_execute(enp, &req);
2098 if (req.emr_rc != 0) {
2103 /* Clear RX/TX DMA queue errors */
2104 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2113 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2118 __checkReturn efx_rc_t
2120 __in efx_nic_t *enp)
2122 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2123 uint32_t min_vi_count, max_vi_count;
2124 uint32_t vi_count, vi_base, vi_shift;
2128 uint32_t vi_window_size;
2131 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2132 enp->en_family == EFX_FAMILY_MEDFORD ||
2133 enp->en_family == EFX_FAMILY_MEDFORD2);
2135 /* Enable reporting of some events (e.g. link change) */
2136 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2139 /* Allocate (optional) on-chip PIO buffers */
2140 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2143 * For best performance, PIO writes should use a write-combined
2144 * (WC) memory mapping. Using a separate WC mapping for the PIO
2145 * aperture of each VI would be a burden to drivers (and not
2146 * possible if the host page size is >4Kbyte).
2148 * To avoid this we use a single uncached (UC) mapping for VI
2149 * register access, and a single WC mapping for extra VIs used
2152 * Each piobuf must be linked to a VI in the WC mapping, and to
2153 * each VI that is using a sub-allocated block from the piobuf.
2155 min_vi_count = edcp->edc_min_vi_count;
2157 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2159 /* Ensure that the previously attached driver's VIs are freed */
2160 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2164 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2165 * fails then retrying the request for fewer VI resources may succeed.
2168 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2169 &vi_base, &vi_count, &vi_shift)) != 0)
2172 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2174 if (vi_count < min_vi_count) {
2179 enp->en_arch.ef10.ena_vi_base = vi_base;
2180 enp->en_arch.ef10.ena_vi_count = vi_count;
2181 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2183 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2184 /* Not enough extra VIs to map piobufs */
2185 ef10_nic_free_piobufs(enp);
2188 enp->en_arch.ef10.ena_pio_write_vi_base =
2189 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2191 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2192 EFX_VI_WINDOW_SHIFT_INVALID);
2193 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2194 EFX_VI_WINDOW_SHIFT_64K);
2195 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2197 /* Save UC memory mapping details */
2198 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2199 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2200 enp->en_arch.ef10.ena_uc_mem_map_size =
2202 enp->en_arch.ef10.ena_pio_write_vi_base);
2204 enp->en_arch.ef10.ena_uc_mem_map_size =
2206 enp->en_arch.ef10.ena_vi_count);
2209 /* Save WC memory mapping details */
2210 enp->en_arch.ef10.ena_wc_mem_map_offset =
2211 enp->en_arch.ef10.ena_uc_mem_map_offset +
2212 enp->en_arch.ef10.ena_uc_mem_map_size;
2214 enp->en_arch.ef10.ena_wc_mem_map_size =
2216 enp->en_arch.ef10.ena_piobuf_count);
2218 /* Link piobufs to extra VIs in WC mapping */
2219 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2220 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2221 rc = efx_mcdi_link_piobuf(enp,
2222 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2223 enp->en_arch.ef10.ena_piobuf_handle[i]);
2230 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2232 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2233 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2234 * retry the request several times after waiting a while. The wait time
2235 * between retries starts small (10ms) and exponentially increases.
2236 * Total wait time is a little over two seconds. Retry logic in the
2237 * client driver may mean this whole loop is repeated if it continues to
2242 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2243 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2246 * Do not retry alloc for PF, or for other errors on
2252 /* VF startup before PF is ready. Retry allocation. */
2254 /* Too many attempts */
2258 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2259 EFSYS_SLEEP(delay_us);
2261 if (delay_us < 500000)
2265 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2266 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2281 ef10_nic_free_piobufs(enp);
2284 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2289 __checkReturn efx_rc_t
2290 ef10_nic_get_vi_pool(
2291 __in efx_nic_t *enp,
2292 __out uint32_t *vi_countp)
2294 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2295 enp->en_family == EFX_FAMILY_MEDFORD ||
2296 enp->en_family == EFX_FAMILY_MEDFORD2);
2299 * Report VIs that the client driver can use.
2300 * Do not include VIs used for PIO buffer writes.
2302 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2307 __checkReturn efx_rc_t
2308 ef10_nic_get_bar_region(
2309 __in efx_nic_t *enp,
2310 __in efx_nic_region_t region,
2311 __out uint32_t *offsetp,
2312 __out size_t *sizep)
2316 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2317 enp->en_family == EFX_FAMILY_MEDFORD ||
2318 enp->en_family == EFX_FAMILY_MEDFORD2);
2321 * TODO: Specify host memory mapping alignment and granularity
2322 * in efx_drv_limits_t so that they can be taken into account
2323 * when allocating extra VIs for PIO writes.
2327 /* UC mapped memory BAR region for VI registers */
2328 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2329 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2332 case EFX_REGION_PIO_WRITE_VI:
2333 /* WC mapped memory BAR region for piobuf writes */
2334 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2335 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2346 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2353 __in efx_nic_t *enp)
2358 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2359 enp->en_vport_id = 0;
2361 /* Unlink piobufs from extra VIs in WC mapping */
2362 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2363 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2364 rc = efx_mcdi_unlink_piobuf(enp,
2365 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2371 ef10_nic_free_piobufs(enp);
2373 (void) efx_mcdi_free_vis(enp);
2374 enp->en_arch.ef10.ena_vi_count = 0;
2379 __in efx_nic_t *enp)
2381 #if EFSYS_OPT_MON_STATS
2382 mcdi_mon_cfg_free(enp);
2383 #endif /* EFSYS_OPT_MON_STATS */
2384 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2389 __checkReturn efx_rc_t
2390 ef10_nic_register_test(
2391 __in efx_nic_t *enp)
2396 _NOTE(ARGUNUSED(enp))
2397 _NOTE(CONSTANTCONDITION)
2407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2412 #endif /* EFSYS_OPT_DIAG */
2414 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2416 __checkReturn efx_rc_t
2417 efx_mcdi_get_nic_global(
2418 __in efx_nic_t *enp,
2420 __out uint32_t *valuep)
2423 uint8_t payload[MAX(MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2424 MC_CMD_GET_NIC_GLOBAL_OUT_LEN)];
2427 (void) memset(payload, 0, sizeof (payload));
2428 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2429 req.emr_in_buf = payload;
2430 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2431 req.emr_out_buf = payload;
2432 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2434 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2436 efx_mcdi_execute(enp, &req);
2438 if (req.emr_rc != 0) {
2443 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2448 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2455 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2460 __checkReturn efx_rc_t
2461 efx_mcdi_set_nic_global(
2462 __in efx_nic_t *enp,
2464 __in uint32_t value)
2467 uint8_t payload[MC_CMD_SET_NIC_GLOBAL_IN_LEN];
2470 (void) memset(payload, 0, sizeof (payload));
2471 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2472 req.emr_in_buf = payload;
2473 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2474 req.emr_out_buf = NULL;
2475 req.emr_out_length = 0;
2477 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2478 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2480 efx_mcdi_execute(enp, &req);
2482 if (req.emr_rc != 0) {
2490 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2495 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2497 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */