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33 /* These structures define the layouts for the TLV items stored in static and
34 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
36 * They contain the same sort of information that was kept in the
37 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
38 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
41 * These are used directly by the MC and should also be usable directly on host
42 * systems which are little-endian and do not do strange things with structure
43 * padding. (Big-endian host systems will require some byte-swapping.)
47 * Please refer to SF-108797-SW for a general overview of the TLV partition
52 * The current tag IDs have a general structure: with the exception of the
53 * special values defined in the document, they are of the form 0xLTTTNNNN,
56 * - L is a location, indicating where this tag is expected to be found:
57 * 0: static configuration
58 * 1: dynamic configuration
59 * 2: firmware internal use
60 * 3: license partition
62 * - TTT is a type, which is just a unique value. The same type value
63 * might appear in both locations, indicating a relationship between
64 * the items (e.g. static and dynamic VPD below).
66 * - NNNN is an index of some form. Some item types are per-port, some
67 * are per-PF, some are per-partition-type.
71 * As with the previous Siena structures, each structure here is laid out
72 * carefully: values are aligned to their natural boundary, with explicit
73 * padding fields added where necessary. (No, technically this does not
74 * absolutely guarantee portability. But, in practice, compilers are generally
75 * sensible enough not to introduce completely pointless padding, and it works
80 #ifndef CI_MGMT_TLV_LAYOUT_H
81 #define CI_MGMT_TLV_LAYOUT_H
84 /* ----------------------------------------------------------------------------
85 * General structure (defined by SF-108797-SW)
86 * ----------------------------------------------------------------------------
92 * (Note that this is *not* followed by length or value fields: anything after
93 * the tag itself is irrelevant.)
96 #define TLV_TAG_END (0xEEEEEEEE)
99 /* Other special reserved tag values.
102 #define TLV_TAG_SKIP (0x00000000)
103 #define TLV_TAG_INVALID (0xFFFFFFFF)
106 /* TLV partition header.
108 * In a TLV partition, this must be the first item in the sequence, at offset
112 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
114 struct tlv_partition_header {
118 /* 0 indicates the default segment (always located at offset 0), while other values
119 * are for RFID-selectable presets that should immediately follow the default segment.
120 * The default segment may also have preset > 0, which means that it is a preset
121 * selected through an RFID command and copied by FW to the location at offset 0. */
124 uint32_t total_length;
128 /* TLV partition trailer.
130 * In a TLV partition, this must be the last item in the sequence, immediately
131 * preceding the TLV_TAG_END word.
134 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
136 struct tlv_partition_trailer {
144 /* Appendable TLV partition header.
146 * In an appendable TLV partition, this must be the first item in the sequence,
147 * at offset 0. (Note that, unlike the configuration partitions, there is no
148 * trailer before the TLV_TAG_END word.)
151 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
153 struct tlv_appendable_partition_header {
161 /* ----------------------------------------------------------------------------
162 * Configuration items
163 * ----------------------------------------------------------------------------
167 /* NIC global capabilities.
170 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
172 struct tlv_global_capabilities {
179 /* Siena-style per-port MAC address allocation.
181 * There are <count> addresses, starting at <base_address> and incrementing
182 * by adding <stride> to the low-order byte(s).
184 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
185 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
188 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
190 struct tlv_port_mac {
193 uint8_t base_address[6];
202 * This is the portion of VPD which is set at manufacturing time and not
203 * expected to change. It is formatted as a standard PCI VPD block. There are
204 * global and per-pf TLVs for this, the global TLV is new for Medford and is
205 * used in preference to the per-pf TLV.
208 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
210 struct tlv_pf_static_vpd {
216 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
218 struct tlv_global_static_vpd {
227 * This is the portion of VPD which may be changed (e.g. by firmware updates).
228 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
229 * for this, the global TLV is new for Medford and is used in preference to the
233 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
235 struct tlv_pf_dynamic_vpd {
241 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
243 struct tlv_global_dynamic_vpd {
250 /* "DBI" PCI config space changes.
252 * This is a set of edits made to the default PCI config space values before
253 * the device is allowed to enumerate. There are global and per-pf TLVs for
254 * this, the global TLV is new for Medford and is used in preference to the
258 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
265 uint16_t byte_enables;
271 #define TLV_TAG_GLOBAL_DBI (0x00210000)
273 struct tlv_global_dbi {
278 uint16_t byte_enables;
284 /* Partition subtype codes.
286 * A subtype may optionally be stored for each type of partition present in
287 * the NVRAM. For example, this may be used to allow a generic firmware update
288 * utility to select a specific variant of firmware for a specific variant of
291 * The description[] field is an optional string which is returned in the
292 * MC_CMD_NVRAM_METADATA response if present.
295 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
297 struct tlv_partition_subtype {
301 uint8_t description[];
305 /* Partition version codes.
307 * A version may optionally be stored for each type of partition present in
308 * the NVRAM. This provides a standard way of tracking the currently stored
309 * version of each of the various component images.
312 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
314 struct tlv_partition_version {
323 /* Global PCIe configuration */
325 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
327 struct tlv_pcie_config {
330 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
331 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
332 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
333 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
334 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
335 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
338 /* Per-PF configuration. Note that not all these fields are necessarily useful
339 * as the apertures are constrained by the BIU settings (the one case we do
340 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
341 * tidy things up later */
343 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
345 struct tlv_per_pf_pcie_config {
349 uint8_t port_allocation;
350 uint16_t vectors_per_pf;
351 uint16_t vectors_per_vf;
352 uint8_t pf_bar0_aperture;
353 uint8_t pf_bar2_aperture;
354 uint8_t vf_bar0_aperture;
356 uint16_t supp_pagesz;
357 uint16_t msix_vec_base;
361 /* Development ONLY. This is a single TLV tag for all the gubbins
362 * that can be set through the MC command-line other than the PCIe
363 * settings. This is a temporary measure. */
364 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
365 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
367 struct tlv_tmp_gubbins {
370 /* Consumed by dpcpu.c */
371 uint64_t tx0_tags; /* Bitmap */
372 uint64_t tx1_tags; /* Bitmap */
373 uint64_t dl_tags; /* Bitmap */
375 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
376 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
377 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
378 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
379 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
380 /* Consumed by features.c */
381 uint32_t dut_features; /* All 1s -> leave alone */
382 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
383 /* Consumed by clocks_hunt.c */
384 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
385 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
386 int8_t rx_dc_size; /* -1 -> leave alone */
388 int16_t num_q_allocs;
391 /* Global port configuration
393 * This is now deprecated in favour of a platform-provided default
394 * and dynamic config override via tlv_global_port_options.
396 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
398 struct tlv_global_port_config {
401 uint32_t ports_per_core;
402 uint32_t max_port_speed;
408 * This is intended for user-configurable selection of optional firmware
409 * features and variants.
411 * Initially, this consists only of the satellite CPU firmware variant
412 * selection, but this tag could be extended in the future (using the
413 * tag length to determine whether additional fields are present).
416 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
418 struct tlv_firmware_options {
421 uint32_t firmware_variant;
422 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
424 /* These are the values for overriding the driver's choice; the definitions
425 * are taken from MCDI so that they don't get out of step. Include
426 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
427 * you need to use these constants.
429 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
430 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
431 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
432 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
433 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
434 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
435 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
440 * Intended for boards with A0 silicon where the core voltage may
441 * need tweaking. Most likely set once when the pass voltage is
444 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
446 struct tlv_0v9_settings {
449 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
450 #define TLV_TAG_0V9_REQUIRES_FAN (1)
451 uint16_t target_voltage; /* In millivolts */
452 /* Since the limits are meant to be centred to the target (and must at least
453 * contain it) they need setting as well. */
454 uint16_t warn_low; /* In millivolts */
455 uint16_t warn_high; /* In millivolts */
456 uint16_t panic_low; /* In millivolts */
457 uint16_t panic_high; /* In millivolts */
461 /* Clock configuration */
463 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
464 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
466 struct tlv_clock_config {
469 uint16_t clk_sys; /* MHz */
470 uint16_t clk_dpcpu; /* MHz */
471 uint16_t clk_icore; /* MHz */
472 uint16_t clk_pcs; /* MHz */
475 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
477 struct tlv_clock_config_medford {
480 uint16_t clk_sys; /* MHz */
481 uint16_t clk_mc; /* MHz */
482 uint16_t clk_rmon; /* MHz */
483 uint16_t clk_vswitch; /* MHz */
484 uint16_t clk_dpcpu; /* MHz */
485 uint16_t clk_pcs; /* MHz */
489 /* EF10-style global pool of MAC addresses.
491 * There are <count> addresses, starting at <base_address>, which are
492 * contiguous. Firmware is responsible for allocating addresses from this
493 * pool to ports / PFs as appropriate.
496 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
498 struct tlv_global_mac {
501 uint8_t base_address[6];
507 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
508 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
510 /* The target value for the 0v9 power rail measured on-chip at the
511 * analogue test bus */
512 struct tlv_0v9_atb_target {
519 /* Global PCIe configuration, second revision. This represents the visible PFs
520 * by a bitmap rather than having the number of the highest visible one. As such
521 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
522 * can and it should be used in place of that tag in future (but compatibility with
523 * the old tag will be left in the firmware indefinitely). */
525 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
527 struct tlv_pcie_config_r2 {
530 uint16_t visible_pfs; /**< Bitmap of visible PFs */
531 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
532 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
533 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
536 /* Dynamic port mode.
538 * Allows selecting alternate port configuration for platforms that support it
539 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
540 * number of externally visible ports (and, hence, PF to port mapping), so must
541 * be done at boot time.
543 * This tag supercedes tlv_global_port_config.
546 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
548 struct tlv_global_port_mode {
552 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
553 #define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */
554 #define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */
555 #define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
556 #define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
557 #define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport) */
558 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) /* 4x10G, single QSFP, cage 0 (Medford) */
559 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) OBSOLETE DO NOT USE */
560 #define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
561 #define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
562 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */
563 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) /* 2x10G + 2x10G, dual QSFP (Medford) */
564 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2
567 /* Type of the v-switch created implicitly by the firmware */
569 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
571 struct tlv_vswitch_type {
574 uint32_t vswitch_type;
575 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
576 #define TLV_VSWITCH_TYPE_NONE (0)
577 #define TLV_VSWITCH_TYPE_VLAN (1)
578 #define TLV_VSWITCH_TYPE_VEB (2)
579 #define TLV_VSWITCH_TYPE_VEPA (3)
580 #define TLV_VSWITCH_TYPE_MUX (4)
581 #define TLV_VSWITCH_TYPE_TEST (5)
584 /* A VLAN tag for the v-port created implicitly by the firmware */
586 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
588 struct tlv_vport_vlan_tag {
592 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
595 /* Offset to be applied to the 0v9 setting, wherever it came from */
597 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
599 struct tlv_0v9_atb_offset {
602 int16_t offset_millivolts;
606 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
607 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
608 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
609 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
610 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
612 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
614 struct tlv_privilege_mask { /* legacy structure - do not use */
617 uint32_t privilege_mask;
620 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
622 struct tlv_privilege_mask_add {
625 uint32_t privilege_mask_add;
628 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
630 struct tlv_privilege_mask_rem {
633 uint32_t privilege_mask_rem;
636 /* Additional privileges given to all PFs.
637 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
639 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
641 struct tlv_privilege_mask_add_all_pfs {
644 uint32_t privilege_mask_add;
647 /* Additional privileges given to a selected PF.
648 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
650 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
652 struct tlv_privilege_mask_add_single_pf {
655 uint32_t privilege_mask_add;
658 /* Turning on/off the PFIOV mode.
659 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
661 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
667 #define TLV_PFIOV_OFF (0) /* Default */
668 #define TLV_PFIOV_ON (1)
671 /* Multicast filter chaining mode selection.
673 * When enabled, multicast packets are delivered to all recipients of all
674 * matching multicast filters, with the exception that IP multicast filters
675 * will steal traffic from MAC multicast filters on a per-function basis.
678 * When disabled, multicast packets will always be delivered only to the
679 * recipients of the highest priority matching multicast filter.
680 * (Legacy behaviour.)
682 * The DEFAULT mode (which is the same as the tag not being present at all)
683 * is equivalent to ENABLED in production builds, and DISABLED in eftest
686 * This option is intended to provide run-time control over this feature
687 * while it is being stabilised and may be withdrawn at some point in the
688 * future; the new behaviour is intended to become the standard behaviour.
691 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
693 struct tlv_mcast_filter_chaining {
697 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
698 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
699 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
702 /* Pacer rate limit per PF */
703 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
705 struct tlv_rate_limit {
711 /* OCSD Enable/Disable
713 * This setting allows OCSD to be disabled. This is a requirement for HP
714 * servers to support PCI passthrough for virtualization.
716 * The DEFAULT mode (which is the same as the tag not being present) is
717 * equivalent to ENABLED.
719 * This option is not used by the MCFW, and is entirely handled by the various
720 * drivers that support OCSD, by reading the setting before they attempt
723 * bit0: OCSD Disabled/Enabled
726 #define TLV_TAG_OCSD (0x101C0000)
732 #define TLV_OCSD_DISABLED 0
733 #define TLV_OCSD_ENABLED 1 /* Default */
736 /* Descriptor cache config.
738 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
739 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
740 * away from the highest numbered port first, so a vi_count of 1024 means 1024
741 * VIs on the first port and 0 on the second (on a Torino).
744 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
746 struct tlv_descriptor_cache_config {
749 uint8_t rx_desc_cache_size;
750 uint8_t tx_desc_cache_size;
753 #define TLV_DESC_CACHE_DEFAULT (0xff)
754 #define TLV_VI_COUNT_DEFAULT (0xffff)
756 /* RX event merging config (read batching).
758 * Sets the global maximum number of events for the merging bins, and the
759 * global timeout configuration for the bins.
762 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
764 struct tlv_rx_event_merging_config {
768 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
771 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
772 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
774 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
775 struct tlv_pcie_link_settings {
778 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
779 uint16_t width; /* Number of lanes */
782 /* TX event merging config.
784 * Sets the global maximum number of events for the merging bins, and the
785 * global timeout configuration for the bins, and the global timeout for
788 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
789 struct tlv_tx_event_merging_config {
793 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
795 uint32_t qempty_timeout_ns; /* Medford only */
797 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
798 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
799 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
803 * Medford2 tag for selecting VI window decode (see values below)
805 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
806 struct tlv_biu_vi_window_mode {
810 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
811 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
812 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
815 #define TLV_TAG_LICENSE (0x30800000)
817 typedef struct tlv_license {
823 /* TSA NIC IP address configuration
825 * Sets the TSA NIC IP address statically via configuration tool or dynamically
826 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
828 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
829 * be moved to a private partition during TSA development. It is not used in any
833 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000)
835 #define TLV_TSAN_IP_MODE_STATIC (0)
836 #define TLV_TSAN_IP_MODE_DHCP (1)
837 #define TLV_TSAN_IP_MODE_SNOOP (2)
838 typedef struct tlv_tsan_config {
846 uint32_t bind_retry; /* DEPRECATED */
847 uint32_t bind_bkout; /* DEPRECATED */
850 /* TSA Controller IP address configuration
852 * Sets the TSA Controller IP address statically via configuration tool
854 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
855 * be moved to a private partition during TSA development. It is not used in any
859 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000)
861 #define TLV_MAX_TSACS (4)
862 typedef struct tlv_tsac_config {
866 uint32_t ip[TLV_MAX_TSACS];
867 uint32_t port[TLV_MAX_TSACS];
872 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
873 * and the TSA Controller
875 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
876 * be moved to a private partition during TSA development. It is not used in any
880 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000)
882 typedef struct tlv_binding_ticket {
886 } tlv_binding_ticket_t;
888 /* Solarflare private key (DEPRECATED)
890 * Sets the Solareflare private key used for signing during the binding process
892 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
893 * be moved to a private partition during TSA development. It is not used in any
897 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
899 typedef struct tlv_pik_sf {
905 /* CA root certificate
907 * Sets the CA root certificate used for TSA Controller verfication during
908 * TLS connection setup between the TSA NIC and the TSA Controller
910 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
911 * be moved to a private partition during TSA development. It is not used in any
915 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000)
917 typedef struct tlv_ca_root_cert {
921 } tlv_ca_root_cert_t;
923 /* Tx vFIFO Low latency configuration
925 * To keep the desired booting behaviour for the switch, it just requires to
926 * know if the low latency mode is enabled.
929 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
930 struct tlv_tx_vfifo_ull_mode {
934 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
937 #endif /* CI_MGMT_TLV_LAYOUT_H */