2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
34 * This is NOT the original source file. Do NOT edit it.
35 * To update the tlv layout, please edit the copy in
36 * the sfregistry repo and then, in that repo,
37 * "make tlv_headers" or "make export" to
38 * regenerate and export all types of headers.
41 /* These structures define the layouts for the TLV items stored in static and
42 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
44 * They contain the same sort of information that was kept in the
45 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
46 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
49 * These are used directly by the MC and should also be usable directly on host
50 * systems which are little-endian and do not do strange things with structure
51 * padding. (Big-endian host systems will require some byte-swapping.)
55 * Please refer to SF-108797-SW for a general overview of the TLV partition
60 * The current tag IDs have a general structure: with the exception of the
61 * special values defined in the document, they are of the form 0xLTTTNNNN,
64 * - L is a location, indicating where this tag is expected to be found:
65 * 0: static configuration
66 * 1: dynamic configuration
67 * 2: firmware internal use
68 * 3: license partition
69 * 4: tsa configuration
71 * - TTT is a type, which is just a unique value. The same type value
72 * might appear in both locations, indicating a relationship between
73 * the items (e.g. static and dynamic VPD below).
75 * - NNNN is an index of some form. Some item types are per-port, some
76 * are per-PF, some are per-partition-type.
80 * As with the previous Siena structures, each structure here is laid out
81 * carefully: values are aligned to their natural boundary, with explicit
82 * padding fields added where necessary. (No, technically this does not
83 * absolutely guarantee portability. But, in practice, compilers are generally
84 * sensible enough not to introduce completely pointless padding, and it works
89 #ifndef CI_MGMT_TLV_LAYOUT_H
90 #define CI_MGMT_TLV_LAYOUT_H
93 /* ----------------------------------------------------------------------------
94 * General structure (defined by SF-108797-SW)
95 * ----------------------------------------------------------------------------
101 * (Note that this is *not* followed by length or value fields: anything after
102 * the tag itself is irrelevant.)
105 #define TLV_TAG_END (0xEEEEEEEE)
108 /* Other special reserved tag values.
111 #define TLV_TAG_SKIP (0x00000000)
112 #define TLV_TAG_INVALID (0xFFFFFFFF)
115 /* TLV partition header.
117 * In a TLV partition, this must be the first item in the sequence, at offset
121 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
123 struct tlv_partition_header {
127 /* 0 indicates the default segment (always located at offset 0), while other values
128 * are for RFID-selectable presets that should immediately follow the default segment.
129 * The default segment may also have preset > 0, which means that it is a preset
130 * selected through an RFID command and copied by FW to the location at offset 0. */
133 uint32_t total_length;
137 /* TLV partition trailer.
139 * In a TLV partition, this must be the last item in the sequence, immediately
140 * preceding the TLV_TAG_END word.
143 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
145 struct tlv_partition_trailer {
153 /* Appendable TLV partition header.
155 * In an appendable TLV partition, this must be the first item in the sequence,
156 * at offset 0. (Note that, unlike the configuration partitions, there is no
157 * trailer before the TLV_TAG_END word.)
160 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
162 struct tlv_appendable_partition_header {
170 /* ----------------------------------------------------------------------------
171 * Configuration items
172 * ----------------------------------------------------------------------------
176 /* NIC global capabilities.
179 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
181 struct tlv_global_capabilities {
188 /* Siena-style per-port MAC address allocation.
190 * There are <count> addresses, starting at <base_address> and incrementing
191 * by adding <stride> to the low-order byte(s).
193 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
194 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
197 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
199 struct tlv_port_mac {
202 uint8_t base_address[6];
211 * This is the portion of VPD which is set at manufacturing time and not
212 * expected to change. It is formatted as a standard PCI VPD block. There are
213 * global and per-pf TLVs for this, the global TLV is new for Medford and is
214 * used in preference to the per-pf TLV.
217 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
219 struct tlv_pf_static_vpd {
225 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
227 struct tlv_global_static_vpd {
236 * This is the portion of VPD which may be changed (e.g. by firmware updates).
237 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
238 * for this, the global TLV is new for Medford and is used in preference to the
242 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
244 struct tlv_pf_dynamic_vpd {
250 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
252 struct tlv_global_dynamic_vpd {
259 /* "DBI" PCI config space changes.
261 * This is a set of edits made to the default PCI config space values before
262 * the device is allowed to enumerate. There are global and per-pf TLVs for
263 * this, the global TLV is new for Medford and is used in preference to the
267 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
274 uint16_t byte_enables;
280 #define TLV_TAG_GLOBAL_DBI (0x00210000)
282 struct tlv_global_dbi {
287 uint16_t byte_enables;
293 /* Partition subtype codes.
295 * A subtype may optionally be stored for each type of partition present in
296 * the NVRAM. For example, this may be used to allow a generic firmware update
297 * utility to select a specific variant of firmware for a specific variant of
300 * The description[] field is an optional string which is returned in the
301 * MC_CMD_NVRAM_METADATA response if present.
304 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
306 struct tlv_partition_subtype {
310 uint8_t description[];
314 /* Partition version codes.
316 * A version may optionally be stored for each type of partition present in
317 * the NVRAM. This provides a standard way of tracking the currently stored
318 * version of each of the various component images.
321 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
323 struct tlv_partition_version {
332 /* Global PCIe configuration */
334 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
336 struct tlv_pcie_config {
339 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
340 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
341 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
342 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
343 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
344 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
347 /* Per-PF configuration. Note that not all these fields are necessarily useful
348 * as the apertures are constrained by the BIU settings (the one case we do
349 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
350 * tidy things up later */
352 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
354 struct tlv_per_pf_pcie_config {
358 uint8_t port_allocation;
359 uint16_t vectors_per_pf;
360 uint16_t vectors_per_vf;
361 uint8_t pf_bar0_aperture;
362 uint8_t pf_bar2_aperture;
363 uint8_t vf_bar0_aperture;
365 uint16_t supp_pagesz;
366 uint16_t msix_vec_base;
370 /* Development ONLY. This is a single TLV tag for all the gubbins
371 * that can be set through the MC command-line other than the PCIe
372 * settings. This is a temporary measure. */
373 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
374 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
376 struct tlv_tmp_gubbins {
379 /* Consumed by dpcpu.c */
380 uint64_t tx0_tags; /* Bitmap */
381 uint64_t tx1_tags; /* Bitmap */
382 uint64_t dl_tags; /* Bitmap */
384 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
385 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
386 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
387 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
388 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
389 /* Consumed by features.c */
390 uint32_t dut_features; /* All 1s -> leave alone */
391 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
392 /* Consumed by clocks_hunt.c */
393 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
394 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
395 int8_t rx_dc_size; /* -1 -> leave alone */
397 int16_t num_q_allocs;
400 /* Global port configuration
402 * This is now deprecated in favour of a platform-provided default
403 * and dynamic config override via tlv_global_port_options.
405 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
407 struct tlv_global_port_config {
410 uint32_t ports_per_core;
411 uint32_t max_port_speed;
417 * This is intended for user-configurable selection of optional firmware
418 * features and variants.
420 * Initially, this consists only of the satellite CPU firmware variant
421 * selection, but this tag could be extended in the future (using the
422 * tag length to determine whether additional fields are present).
425 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
427 struct tlv_firmware_options {
430 uint32_t firmware_variant;
431 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
433 /* These are the values for overriding the driver's choice; the definitions
434 * are taken from MCDI so that they don't get out of step. Include
435 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
436 * you need to use these constants.
438 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
439 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
440 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
441 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
442 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
443 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
444 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
445 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
446 #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP
451 * Intended for boards with A0 silicon where the core voltage may
452 * need tweaking. Most likely set once when the pass voltage is
455 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
457 struct tlv_0v9_settings {
460 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
461 #define TLV_TAG_0V9_REQUIRES_FAN (1)
462 uint16_t target_voltage; /* In millivolts */
463 /* Since the limits are meant to be centred to the target (and must at least
464 * contain it) they need setting as well. */
465 uint16_t warn_low; /* In millivolts */
466 uint16_t warn_high; /* In millivolts */
467 uint16_t panic_low; /* In millivolts */
468 uint16_t panic_high; /* In millivolts */
472 /* Clock configuration */
474 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
475 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
477 struct tlv_clock_config {
480 uint16_t clk_sys; /* MHz */
481 uint16_t clk_dpcpu; /* MHz */
482 uint16_t clk_icore; /* MHz */
483 uint16_t clk_pcs; /* MHz */
486 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
488 struct tlv_clock_config_medford {
491 uint16_t clk_sys; /* MHz */
492 uint16_t clk_mc; /* MHz */
493 uint16_t clk_rmon; /* MHz */
494 uint16_t clk_vswitch; /* MHz */
495 uint16_t clk_dpcpu; /* MHz */
496 uint16_t clk_pcs; /* MHz */
500 /* EF10-style global pool of MAC addresses.
502 * There are <count> addresses, starting at <base_address>, which are
503 * contiguous. Firmware is responsible for allocating addresses from this
504 * pool to ports / PFs as appropriate.
507 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
509 struct tlv_global_mac {
512 uint8_t base_address[6];
518 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
519 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
521 /* The target value for the 0v9 power rail measured on-chip at the
522 * analogue test bus */
523 struct tlv_0v9_atb_target {
530 /* Factory settings for amplitude calibration of the PCIE TX serdes */
531 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
532 struct tlv_pcie_tx_amp_config {
535 uint8_t quad_tx_imp2k[4];
536 uint8_t quad_tx_imp50[4];
537 uint8_t lane_amp[16];
541 /* Global PCIe configuration, second revision. This represents the visible PFs
542 * by a bitmap rather than having the number of the highest visible one. As such
543 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
544 * can and it should be used in place of that tag in future (but compatibility with
545 * the old tag will be left in the firmware indefinitely). */
547 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
549 struct tlv_pcie_config_r2 {
552 uint16_t visible_pfs; /**< Bitmap of visible PFs */
553 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
554 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
555 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
558 /* Dynamic port mode.
560 * Allows selecting alternate port configuration for platforms that support it
561 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
562 * number of externally visible ports (and, hence, PF to port mapping), so must
563 * be done at boot time.
565 * Port mode naming convention is
567 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
569 * Port lane width determines the capabilities (speeds) of the ports, subject
570 * to architecture capabilities (e.g. 25G support) and switch bandwidth
572 * - single lane ports can do 25G/10G/1G
573 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
574 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
576 * This tag supercedes tlv_global_port_config.
579 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
581 struct tlv_global_port_mode {
585 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
587 /* Huntington port modes */
588 #define TLV_PORT_MODE_10G (0)
589 #define TLV_PORT_MODE_40G (1)
590 #define TLV_PORT_MODE_10G_10G (2)
591 #define TLV_PORT_MODE_40G_40G (3)
592 #define TLV_PORT_MODE_10G_10G_10G_10G (4)
593 #define TLV_PORT_MODE_40G_10G_10G (6)
594 #define TLV_PORT_MODE_10G_10G_40G (7)
596 /* Medford (and later) port modes */
597 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
598 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
599 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
600 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
601 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
602 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
603 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
604 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
605 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
606 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
607 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
608 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
609 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
610 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
611 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
612 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
613 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
614 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
615 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
617 /* Snapper-only Medford2 port modes.
618 * These modes are eftest only, to allow snapper explicit
619 * selection between multi-channel and LLPCS. In production,
620 * this selection is automatic and outside world should not
623 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
624 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
625 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
626 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
627 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
628 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
629 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
631 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
632 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
633 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
634 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
635 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
637 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
640 /* Type of the v-switch created implicitly by the firmware */
642 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
644 struct tlv_vswitch_type {
647 uint32_t vswitch_type;
648 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
649 #define TLV_VSWITCH_TYPE_NONE (0)
650 #define TLV_VSWITCH_TYPE_VLAN (1)
651 #define TLV_VSWITCH_TYPE_VEB (2)
652 #define TLV_VSWITCH_TYPE_VEPA (3)
653 #define TLV_VSWITCH_TYPE_MUX (4)
654 #define TLV_VSWITCH_TYPE_TEST (5)
657 /* A VLAN tag for the v-port created implicitly by the firmware */
659 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
661 struct tlv_vport_vlan_tag {
665 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
668 /* Offset to be applied to the 0v9 setting, wherever it came from */
670 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
672 struct tlv_0v9_atb_offset {
675 int16_t offset_millivolts;
679 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
680 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
681 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
682 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
683 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
685 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
687 struct tlv_privilege_mask { /* legacy structure - do not use */
690 uint32_t privilege_mask;
693 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
695 struct tlv_privilege_mask_add {
698 uint32_t privilege_mask_add;
701 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
703 struct tlv_privilege_mask_rem {
706 uint32_t privilege_mask_rem;
709 /* Additional privileges given to all PFs.
710 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
712 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
714 struct tlv_privilege_mask_add_all_pfs {
717 uint32_t privilege_mask_add;
720 /* Additional privileges given to a selected PF.
721 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
723 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
725 struct tlv_privilege_mask_add_single_pf {
728 uint32_t privilege_mask_add;
731 /* Turning on/off the PFIOV mode.
732 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
734 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
740 #define TLV_PFIOV_OFF (0) /* Default */
741 #define TLV_PFIOV_ON (1)
744 /* Multicast filter chaining mode selection.
746 * When enabled, multicast packets are delivered to all recipients of all
747 * matching multicast filters, with the exception that IP multicast filters
748 * will steal traffic from MAC multicast filters on a per-function basis.
751 * When disabled, multicast packets will always be delivered only to the
752 * recipients of the highest priority matching multicast filter.
753 * (Legacy behaviour.)
755 * The DEFAULT mode (which is the same as the tag not being present at all)
756 * is equivalent to ENABLED in production builds, and DISABLED in eftest
759 * This option is intended to provide run-time control over this feature
760 * while it is being stabilised and may be withdrawn at some point in the
761 * future; the new behaviour is intended to become the standard behaviour.
764 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
766 struct tlv_mcast_filter_chaining {
770 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
771 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
772 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
775 /* Pacer rate limit per PF */
776 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
778 struct tlv_rate_limit {
784 /* OCSD Enable/Disable
786 * This setting allows OCSD to be disabled. This is a requirement for HP
787 * servers to support PCI passthrough for virtualization.
789 * The DEFAULT mode (which is the same as the tag not being present) is
790 * equivalent to ENABLED.
792 * This option is not used by the MCFW, and is entirely handled by the various
793 * drivers that support OCSD, by reading the setting before they attempt
796 * bit0: OCSD Disabled/Enabled
799 #define TLV_TAG_OCSD (0x101C0000)
805 #define TLV_OCSD_DISABLED 0
806 #define TLV_OCSD_ENABLED 1 /* Default */
809 /* Descriptor cache config.
811 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
812 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
813 * away from the highest numbered port first, so a vi_count of 1024 means 1024
814 * VIs on the first port and 0 on the second (on a Torino).
817 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
819 struct tlv_descriptor_cache_config {
822 uint8_t rx_desc_cache_size;
823 uint8_t tx_desc_cache_size;
826 #define TLV_DESC_CACHE_DEFAULT (0xff)
827 #define TLV_VI_COUNT_DEFAULT (0xffff)
829 /* RX event merging config (read batching).
831 * Sets the global maximum number of events for the merging bins, and the
832 * global timeout configuration for the bins.
835 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
837 struct tlv_rx_event_merging_config {
841 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
844 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
845 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
847 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
848 struct tlv_pcie_link_settings {
851 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
852 uint16_t width; /* Number of lanes */
855 /* TX event merging config.
857 * Sets the global maximum number of events for the merging bins, and the
858 * global timeout configuration for the bins, and the global timeout for
861 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
862 struct tlv_tx_event_merging_config {
866 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
868 uint32_t qempty_timeout_ns; /* Medford only */
870 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
871 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
872 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
874 #define TLV_TAG_LICENSE (0x30800000)
876 typedef struct tlv_license {
882 /* TSA NIC IP address configuration (DEPRECATED)
884 * Sets the TSA NIC IP address statically via configuration tool or dynamically
885 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
887 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
888 * be moved to a private partition during TSA development. It is not used in any
892 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
894 #define TLV_TSAN_IP_MODE_STATIC (0)
895 #define TLV_TSAN_IP_MODE_DHCP (1)
896 #define TLV_TSAN_IP_MODE_SNOOP (2)
897 typedef struct tlv_tsan_config {
905 uint32_t bind_retry; /* DEPRECATED */
906 uint32_t bind_bkout; /* DEPRECATED */
909 /* TSA Controller IP address configuration (DEPRECATED)
911 * Sets the TSA Controller IP address statically via configuration tool
913 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
914 * be moved to a private partition during TSA development. It is not used in any
918 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
920 #define TLV_MAX_TSACS (4)
921 typedef struct tlv_tsac_config {
925 uint32_t ip[TLV_MAX_TSACS];
926 uint32_t port[TLV_MAX_TSACS];
929 /* Binding ticket (DEPRECATED)
931 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
932 * and the TSA Controller
934 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
935 * be moved to a private partition during TSA development. It is not used in any
939 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
941 typedef struct tlv_binding_ticket {
945 } tlv_binding_ticket_t;
947 /* Solarflare private key (DEPRECATED)
949 * Sets the Solareflare private key used for signing during the binding process
951 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
952 * be moved to a private partition during TSA development. It is not used in any
956 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
958 typedef struct tlv_pik_sf {
964 /* CA root certificate (DEPRECATED)
966 * Sets the CA root certificate used for TSA Controller verfication during
967 * TLS connection setup between the TSA NIC and the TSA Controller
969 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
970 * be moved to a private partition during TSA development. It is not used in any
974 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
976 typedef struct tlv_ca_root_cert {
980 } tlv_ca_root_cert_t;
982 /* Tx vFIFO Low latency configuration
984 * To keep the desired booting behaviour for the switch, it just requires to
985 * know if the low latency mode is enabled.
988 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
989 struct tlv_tx_vfifo_ull_mode {
993 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
998 * Medford2 tag for selecting VI window decode (see values below)
1000 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
1001 struct tlv_biu_vi_window_mode {
1005 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
1006 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
1007 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
1012 * Medford2 tag for configuring the FastPD mode (see values below)
1014 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
1015 struct tlv_fastpd_mode {
1019 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
1020 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
1021 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
1024 /* L3xUDP datapath firmware UDP port configuration
1026 * Sets the list of UDP ports on which the encapsulation will be handled.
1027 * The number of ports in the list is implied by the length of the TLV item.
1029 #define TLV_TAG_L3XUDP_PORTS (0x102a0000)
1030 struct tlv_l3xudp_ports {
1034 #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16
1037 #endif /* CI_MGMT_TLV_LAYOUT_H */