2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
34 * This is NOT the original source file. Do NOT edit it.
35 * To update the tlv layout, please edit the copy in
36 * the sfregistry repo and then, in that repo,
37 * "make tlv_headers" or "make export" to
38 * regenerate and export all types of headers.
41 /* These structures define the layouts for the TLV items stored in static and
42 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
44 * They contain the same sort of information that was kept in the
45 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
46 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
49 * These are used directly by the MC and should also be usable directly on host
50 * systems which are little-endian and do not do strange things with structure
51 * padding. (Big-endian host systems will require some byte-swapping.)
55 * Please refer to SF-108797-SW for a general overview of the TLV partition
60 * The current tag IDs have a general structure: with the exception of the
61 * special values defined in the document, they are of the form 0xLTTTNNNN,
64 * - L is a location, indicating where this tag is expected to be found:
65 * 0: static configuration
66 * 1: dynamic configuration
67 * 2: firmware internal use
68 * 3: license partition
69 * 4: tsa configuration
71 * - TTT is a type, which is just a unique value. The same type value
72 * might appear in both locations, indicating a relationship between
73 * the items (e.g. static and dynamic VPD below).
75 * - NNNN is an index of some form. Some item types are per-port, some
76 * are per-PF, some are per-partition-type.
80 * As with the previous Siena structures, each structure here is laid out
81 * carefully: values are aligned to their natural boundary, with explicit
82 * padding fields added where necessary. (No, technically this does not
83 * absolutely guarantee portability. But, in practice, compilers are generally
84 * sensible enough not to introduce completely pointless padding, and it works
88 #ifndef CI_MGMT_TLV_LAYOUT_H
89 #define CI_MGMT_TLV_LAYOUT_H
91 /* ----------------------------------------------------------------------------
92 * General structure (defined by SF-108797-SW)
93 * ----------------------------------------------------------------------------
98 * (Note that this is *not* followed by length or value fields: anything after
99 * the tag itself is irrelevant.)
102 #define TLV_TAG_END (0xEEEEEEEE)
104 /* Other special reserved tag values.
107 #define TLV_TAG_SKIP (0x00000000)
108 #define TLV_TAG_INVALID (0xFFFFFFFF)
110 /* TLV partition header.
112 * In a TLV partition, this must be the first item in the sequence, at offset
116 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
118 struct tlv_partition_header {
122 /* 0 indicates the default segment (always located at offset 0), while other values
123 * are for RFID-selectable presets that should immediately follow the default segment.
124 * The default segment may also have preset > 0, which means that it is a preset
125 * selected through an RFID command and copied by FW to the location at offset 0. */
128 uint32_t total_length;
131 /* TLV partition trailer.
133 * In a TLV partition, this must be the last item in the sequence, immediately
134 * preceding the TLV_TAG_END word.
137 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
139 struct tlv_partition_trailer {
146 /* Appendable TLV partition header.
148 * In an appendable TLV partition, this must be the first item in the sequence,
149 * at offset 0. (Note that, unlike the configuration partitions, there is no
150 * trailer before the TLV_TAG_END word.)
153 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
155 struct tlv_appendable_partition_header {
162 /* ----------------------------------------------------------------------------
163 * Configuration items
164 * ----------------------------------------------------------------------------
167 /* NIC global capabilities.
170 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
172 struct tlv_global_capabilities {
178 /* Siena-style per-port MAC address allocation.
180 * There are <count> addresses, starting at <base_address> and incrementing
181 * by adding <stride> to the low-order byte(s).
183 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
184 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
187 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
189 struct tlv_port_mac {
192 uint8_t base_address[6];
200 * This is the portion of VPD which is set at manufacturing time and not
201 * expected to change. It is formatted as a standard PCI VPD block. There are
202 * global and per-pf TLVs for this, the global TLV is new for Medford and is
203 * used in preference to the per-pf TLV.
206 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
208 struct tlv_pf_static_vpd {
214 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
216 struct tlv_global_static_vpd {
224 * This is the portion of VPD which may be changed (e.g. by firmware updates).
225 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
226 * for this, the global TLV is new for Medford and is used in preference to the
230 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
232 struct tlv_pf_dynamic_vpd {
238 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
240 struct tlv_global_dynamic_vpd {
246 /* "DBI" PCI config space changes.
248 * This is a set of edits made to the default PCI config space values before
249 * the device is allowed to enumerate. There are global and per-pf TLVs for
250 * this, the global TLV is new for Medford and is used in preference to the
254 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
261 uint16_t byte_enables;
266 #define TLV_TAG_GLOBAL_DBI (0x00210000)
268 struct tlv_global_dbi {
273 uint16_t byte_enables;
278 /* Partition subtype codes.
280 * A subtype may optionally be stored for each type of partition present in
281 * the NVRAM. For example, this may be used to allow a generic firmware update
282 * utility to select a specific variant of firmware for a specific variant of
285 * The description[] field is an optional string which is returned in the
286 * MC_CMD_NVRAM_METADATA response if present.
289 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
291 struct tlv_partition_subtype {
295 uint8_t description[];
298 /* Partition version codes.
300 * A version may optionally be stored for each type of partition present in
301 * the NVRAM. This provides a standard way of tracking the currently stored
302 * version of each of the various component images.
305 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
307 struct tlv_partition_version {
316 /* Global PCIe configuration */
318 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
320 struct tlv_pcie_config {
323 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
324 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
325 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
326 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
327 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
328 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
331 /* Per-PF configuration. Note that not all these fields are necessarily useful
332 * as the apertures are constrained by the BIU settings (the one case we do
333 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
334 * tidy things up later */
336 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
338 struct tlv_per_pf_pcie_config {
342 uint8_t port_allocation;
343 uint16_t vectors_per_pf;
344 uint16_t vectors_per_vf;
345 uint8_t pf_bar0_aperture;
346 uint8_t pf_bar2_aperture;
347 uint8_t vf_bar0_aperture;
349 uint16_t supp_pagesz;
350 uint16_t msix_vec_base;
353 /* Development ONLY. This is a single TLV tag for all the gubbins
354 * that can be set through the MC command-line other than the PCIe
355 * settings. This is a temporary measure. */
356 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
357 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
359 struct tlv_tmp_gubbins {
362 /* Consumed by dpcpu.c */
363 uint64_t tx0_tags; /* Bitmap */
364 uint64_t tx1_tags; /* Bitmap */
365 uint64_t dl_tags; /* Bitmap */
367 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
368 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
369 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
370 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
371 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
372 /* Consumed by features.c */
373 uint32_t dut_features; /* All 1s -> leave alone */
374 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
375 /* Consumed by clocks_hunt.c */
376 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
377 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
378 int8_t rx_dc_size; /* -1 -> leave alone */
380 int16_t num_q_allocs;
383 /* Global port configuration
385 * This is now deprecated in favour of a platform-provided default
386 * and dynamic config override via tlv_global_port_options.
388 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
390 struct tlv_global_port_config {
393 uint32_t ports_per_core;
394 uint32_t max_port_speed;
399 * This is intended for user-configurable selection of optional firmware
400 * features and variants.
402 * Initially, this consists only of the satellite CPU firmware variant
403 * selection, but this tag could be extended in the future (using the
404 * tag length to determine whether additional fields are present).
407 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
409 struct tlv_firmware_options {
412 uint32_t firmware_variant;
413 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
415 /* These are the values for overriding the driver's choice; the definitions
416 * are taken from MCDI so that they don't get out of step. Include
417 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
418 * you need to use these constants.
420 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
421 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
422 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
423 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
424 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
425 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
426 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
427 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
428 #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP
433 * Intended for boards with A0 silicon where the core voltage may
434 * need tweaking. Most likely set once when the pass voltage is
437 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
439 struct tlv_0v9_settings {
442 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
443 #define TLV_TAG_0V9_REQUIRES_FAN (1)
444 uint16_t target_voltage; /* In millivolts */
445 /* Since the limits are meant to be centred to the target (and must at least
446 * contain it) they need setting as well. */
447 uint16_t warn_low; /* In millivolts */
448 uint16_t warn_high; /* In millivolts */
449 uint16_t panic_low; /* In millivolts */
450 uint16_t panic_high; /* In millivolts */
453 /* Clock configuration */
455 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
456 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
458 struct tlv_clock_config {
461 uint16_t clk_sys; /* MHz */
462 uint16_t clk_dpcpu; /* MHz */
463 uint16_t clk_icore; /* MHz */
464 uint16_t clk_pcs; /* MHz */
467 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
469 struct tlv_clock_config_medford {
472 uint16_t clk_sys; /* MHz */
473 uint16_t clk_mc; /* MHz */
474 uint16_t clk_rmon; /* MHz */
475 uint16_t clk_vswitch; /* MHz */
476 uint16_t clk_dpcpu; /* MHz */
477 uint16_t clk_pcs; /* MHz */
480 /* EF10-style global pool of MAC addresses.
482 * There are <count> addresses, starting at <base_address>, which are
483 * contiguous. Firmware is responsible for allocating addresses from this
484 * pool to ports / PFs as appropriate.
487 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
489 struct tlv_global_mac {
492 uint8_t base_address[6];
498 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
499 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
501 /* The target value for the 0v9 power rail measured on-chip at the
502 * analogue test bus */
503 struct tlv_0v9_atb_target {
510 /* Factory settings for amplitude calibration of the PCIE TX serdes */
511 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
512 struct tlv_pcie_tx_amp_config {
515 uint8_t quad_tx_imp2k[4];
516 uint8_t quad_tx_imp50[4];
517 uint8_t lane_amp[16];
520 /* Global PCIe configuration, second revision. This represents the visible PFs
521 * by a bitmap rather than having the number of the highest visible one. As such
522 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
523 * can and it should be used in place of that tag in future (but compatibility with
524 * the old tag will be left in the firmware indefinitely). */
526 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
528 struct tlv_pcie_config_r2 {
531 uint16_t visible_pfs; /**< Bitmap of visible PFs */
532 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
533 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
534 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
537 /* Dynamic port mode.
539 * Allows selecting alternate port configuration for platforms that support it
540 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
541 * number of externally visible ports (and, hence, PF to port mapping), so must
542 * be done at boot time.
544 * Port mode naming convention is
546 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
548 * Port lane width determines the capabilities (speeds) of the ports, subject
549 * to architecture capabilities (e.g. 25G support) and switch bandwidth
551 * - single lane ports can do 25G/10G/1G
552 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
553 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
555 * This tag supercedes tlv_global_port_config.
558 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
560 struct tlv_global_port_mode {
564 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
566 /* Huntington port modes */
567 #define TLV_PORT_MODE_10G (0)
568 #define TLV_PORT_MODE_40G (1)
569 #define TLV_PORT_MODE_10G_10G (2)
570 #define TLV_PORT_MODE_40G_40G (3)
571 #define TLV_PORT_MODE_10G_10G_10G_10G (4)
572 #define TLV_PORT_MODE_40G_10G_10G (6)
573 #define TLV_PORT_MODE_10G_10G_40G (7)
575 /* Medford (and later) port modes */
576 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
577 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
578 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
579 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
580 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
581 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
582 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
583 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
584 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
585 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
586 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
587 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
588 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
589 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
590 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
591 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
592 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
593 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
594 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
596 /* Snapper-only Medford2 port modes.
597 * These modes are eftest only, to allow snapper explicit
598 * selection between multi-channel and LLPCS. In production,
599 * this selection is automatic and outside world should not
602 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
603 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
604 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
605 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
606 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
607 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
608 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
610 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
611 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
612 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
613 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
614 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
616 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
619 /* Type of the v-switch created implicitly by the firmware */
621 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
623 struct tlv_vswitch_type {
626 uint32_t vswitch_type;
627 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
628 #define TLV_VSWITCH_TYPE_NONE (0)
629 #define TLV_VSWITCH_TYPE_VLAN (1)
630 #define TLV_VSWITCH_TYPE_VEB (2)
631 #define TLV_VSWITCH_TYPE_VEPA (3)
632 #define TLV_VSWITCH_TYPE_MUX (4)
633 #define TLV_VSWITCH_TYPE_TEST (5)
636 /* A VLAN tag for the v-port created implicitly by the firmware */
638 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
640 struct tlv_vport_vlan_tag {
644 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
647 /* Offset to be applied to the 0v9 setting, wherever it came from */
649 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
651 struct tlv_0v9_atb_offset {
654 int16_t offset_millivolts;
658 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
659 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
660 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
661 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
662 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
664 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
666 struct tlv_privilege_mask { /* legacy structure - do not use */
669 uint32_t privilege_mask;
672 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
674 struct tlv_privilege_mask_add {
677 uint32_t privilege_mask_add;
680 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
682 struct tlv_privilege_mask_rem {
685 uint32_t privilege_mask_rem;
688 /* Additional privileges given to all PFs.
689 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
691 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
693 struct tlv_privilege_mask_add_all_pfs {
696 uint32_t privilege_mask_add;
699 /* Additional privileges given to a selected PF.
700 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
702 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
704 struct tlv_privilege_mask_add_single_pf {
707 uint32_t privilege_mask_add;
710 /* Turning on/off the PFIOV mode.
711 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
713 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
719 #define TLV_PFIOV_OFF (0) /* Default */
720 #define TLV_PFIOV_ON (1)
723 /* Multicast filter chaining mode selection.
725 * When enabled, multicast packets are delivered to all recipients of all
726 * matching multicast filters, with the exception that IP multicast filters
727 * will steal traffic from MAC multicast filters on a per-function basis.
730 * When disabled, multicast packets will always be delivered only to the
731 * recipients of the highest priority matching multicast filter.
732 * (Legacy behaviour.)
734 * The DEFAULT mode (which is the same as the tag not being present at all)
735 * is equivalent to ENABLED in production builds, and DISABLED in eftest
738 * This option is intended to provide run-time control over this feature
739 * while it is being stabilised and may be withdrawn at some point in the
740 * future; the new behaviour is intended to become the standard behaviour.
743 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
745 struct tlv_mcast_filter_chaining {
749 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
750 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
751 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
754 /* Pacer rate limit per PF */
755 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
757 struct tlv_rate_limit {
763 /* OCSD Enable/Disable
765 * This setting allows OCSD to be disabled. This is a requirement for HP
766 * servers to support PCI passthrough for virtualization.
768 * The DEFAULT mode (which is the same as the tag not being present) is
769 * equivalent to ENABLED.
771 * This option is not used by the MCFW, and is entirely handled by the various
772 * drivers that support OCSD, by reading the setting before they attempt
775 * bit0: OCSD Disabled/Enabled
778 #define TLV_TAG_OCSD (0x101C0000)
784 #define TLV_OCSD_DISABLED 0
785 #define TLV_OCSD_ENABLED 1 /* Default */
788 /* Descriptor cache config.
790 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
791 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
792 * away from the highest numbered port first, so a vi_count of 1024 means 1024
793 * VIs on the first port and 0 on the second (on a Torino).
796 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
798 struct tlv_descriptor_cache_config {
801 uint8_t rx_desc_cache_size;
802 uint8_t tx_desc_cache_size;
805 #define TLV_DESC_CACHE_DEFAULT (0xff)
806 #define TLV_VI_COUNT_DEFAULT (0xffff)
808 /* RX event merging config (read batching).
810 * Sets the global maximum number of events for the merging bins, and the
811 * global timeout configuration for the bins.
814 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
816 struct tlv_rx_event_merging_config {
820 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
823 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
824 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
826 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
827 struct tlv_pcie_link_settings {
830 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
831 uint16_t width; /* Number of lanes */
834 /* TX event merging config.
836 * Sets the global maximum number of events for the merging bins, and the
837 * global timeout configuration for the bins, and the global timeout for
840 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
841 struct tlv_tx_event_merging_config {
845 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
847 uint32_t qempty_timeout_ns; /* Medford only */
849 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
850 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
851 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
853 #define TLV_TAG_LICENSE (0x30800000)
855 typedef struct tlv_license {
861 /* TSA NIC IP address configuration (DEPRECATED)
863 * Sets the TSA NIC IP address statically via configuration tool or dynamically
864 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
866 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
867 * be moved to a private partition during TSA development. It is not used in any
871 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
873 #define TLV_TSAN_IP_MODE_STATIC (0)
874 #define TLV_TSAN_IP_MODE_DHCP (1)
875 #define TLV_TSAN_IP_MODE_SNOOP (2)
876 typedef struct tlv_tsan_config {
884 uint32_t bind_retry; /* DEPRECATED */
885 uint32_t bind_bkout; /* DEPRECATED */
888 /* TSA Controller IP address configuration (DEPRECATED)
890 * Sets the TSA Controller IP address statically via configuration tool
892 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
893 * be moved to a private partition during TSA development. It is not used in any
897 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
899 #define TLV_MAX_TSACS (4)
900 typedef struct tlv_tsac_config {
904 uint32_t ip[TLV_MAX_TSACS];
905 uint32_t port[TLV_MAX_TSACS];
908 /* Binding ticket (DEPRECATED)
910 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
911 * and the TSA Controller
913 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
914 * be moved to a private partition during TSA development. It is not used in any
918 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
920 typedef struct tlv_binding_ticket {
924 } tlv_binding_ticket_t;
926 /* Solarflare private key (DEPRECATED)
928 * Sets the Solareflare private key used for signing during the binding process
930 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
931 * be moved to a private partition during TSA development. It is not used in any
935 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
937 typedef struct tlv_pik_sf {
943 /* CA root certificate (DEPRECATED)
945 * Sets the CA root certificate used for TSA Controller verfication during
946 * TLS connection setup between the TSA NIC and the TSA Controller
948 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
949 * be moved to a private partition during TSA development. It is not used in any
953 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
955 typedef struct tlv_ca_root_cert {
959 } tlv_ca_root_cert_t;
961 /* Tx vFIFO Low latency configuration
963 * To keep the desired booting behaviour for the switch, it just requires to
964 * know if the low latency mode is enabled.
967 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
968 struct tlv_tx_vfifo_ull_mode {
972 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
977 * Medford2 tag for selecting VI window decode (see values below)
979 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
980 struct tlv_biu_vi_window_mode {
984 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
985 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
986 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
991 * Medford2 tag for configuring the FastPD mode (see values below)
993 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
994 struct tlv_fastpd_mode {
998 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
999 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
1000 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
1003 /* L3xUDP datapath firmware UDP port configuration
1005 * Sets the list of UDP ports on which the encapsulation will be handled.
1006 * The number of ports in the list is implied by the length of the TLV item.
1008 #define TLV_TAG_L3XUDP_PORTS (0x102a0000)
1009 struct tlv_l3xudp_ports {
1013 #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16
1016 #endif /* CI_MGMT_TLV_LAYOUT_H */