2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
38 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
41 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
43 (_etp)->et_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
47 #define EFX_TX_QSTAT_INCR(_etp, _stat)
50 static __checkReturn efx_rc_t
54 __in uint32_t target_evq,
56 __in uint32_t instance,
58 __in efsys_mem_t *esmp)
61 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
62 MC_CMD_INIT_TXQ_OUT_LEN)];
63 efx_qword_t *dma_addr;
69 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
70 EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg)));
72 npages = EFX_TXQ_NBUFS(size);
73 if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
78 (void) memset(payload, 0, sizeof (payload));
79 req.emr_cmd = MC_CMD_INIT_TXQ;
80 req.emr_in_buf = payload;
81 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
82 req.emr_out_buf = payload;
83 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
86 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
87 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
88 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
90 MCDI_IN_POPULATE_DWORD_7(req, INIT_TXQ_IN_FLAGS,
91 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
92 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
93 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
94 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
95 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
96 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
97 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
98 INIT_TXQ_IN_CRC_MODE, 0,
99 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
101 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
102 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
104 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
105 addr = EFSYS_MEM_ADDR(esmp);
107 for (i = 0; i < npages; i++) {
108 EFX_POPULATE_QWORD_2(*dma_addr,
109 EFX_DWORD_1, (uint32_t)(addr >> 32),
110 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
113 addr += EFX_BUF_SIZE;
116 efx_mcdi_execute(enp, &req);
118 if (req.emr_rc != 0) {
128 EFSYS_PROBE1(fail1, efx_rc_t, rc);
133 static __checkReturn efx_rc_t
136 __in uint32_t instance)
139 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
140 MC_CMD_FINI_TXQ_OUT_LEN)];
143 (void) memset(payload, 0, sizeof (payload));
144 req.emr_cmd = MC_CMD_FINI_TXQ;
145 req.emr_in_buf = payload;
146 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
147 req.emr_out_buf = payload;
148 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
150 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
152 efx_mcdi_execute_quiet(enp, &req);
154 if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) {
162 EFSYS_PROBE1(fail1, efx_rc_t, rc);
167 __checkReturn efx_rc_t
171 _NOTE(ARGUNUSED(enp))
179 _NOTE(ARGUNUSED(enp))
182 __checkReturn efx_rc_t
185 __in unsigned int index,
186 __in unsigned int label,
187 __in efsys_mem_t *esmp,
193 __out unsigned int *addedp)
200 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
205 * A previous user of this TX queue may have written a descriptor to the
206 * TX push collector, but not pushed the doorbell (e.g. after a crash).
207 * The next doorbell write would then push the stale descriptor.
209 * Ensure the (per network port) TX push collector is cleared by writing
210 * a no-op TX option descriptor. See bug29981 for details.
213 EFX_POPULATE_QWORD_4(desc,
214 ESF_DZ_TX_DESC_IS_OPT, 1,
215 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
216 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
217 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
218 ESF_DZ_TX_OPTION_IP_CSUM,
219 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
221 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
222 ef10_tx_qpush(etp, *addedp, 0);
227 EFSYS_PROBE1(fail1, efx_rc_t, rc);
237 _NOTE(ARGUNUSED(etp))
241 __checkReturn efx_rc_t
245 efx_nic_t *enp = etp->et_enp;
246 efx_piobuf_handle_t handle;
249 if (etp->et_pio_size != 0) {
254 /* Sub-allocate a PIO block from a piobuf */
255 if ((rc = ef10_nic_pio_alloc(enp,
260 &etp->et_pio_size)) != 0) {
263 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
265 /* Link the piobuf to this TXQ */
266 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
271 * et_pio_offset is the offset of the sub-allocated block within the
272 * hardware PIO buffer. It is used as the buffer address in the PIO
275 * et_pio_write_offset is the offset of the sub-allocated block from the
276 * start of the write-combined memory mapping, and is used for writing
277 * data into the PIO buffer.
279 etp->et_pio_write_offset =
280 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
281 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
287 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
288 etp->et_pio_size = 0;
292 EFSYS_PROBE1(fail1, efx_rc_t, rc);
298 ef10_tx_qpio_disable(
301 efx_nic_t *enp = etp->et_enp;
303 if (etp->et_pio_size != 0) {
304 /* Unlink the piobuf from this TXQ */
305 ef10_nic_pio_unlink(enp, etp->et_index);
307 /* Free the sub-allocated PIO block */
308 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
309 etp->et_pio_size = 0;
310 etp->et_pio_write_offset = 0;
314 __checkReturn efx_rc_t
317 __in_ecount(length) uint8_t *buffer,
321 efx_nic_t *enp = etp->et_enp;
322 efsys_bar_t *esbp = enp->en_esbp;
323 uint32_t write_offset;
324 uint32_t write_offset_limit;
328 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
330 if (etp->et_pio_size == 0) {
334 if (offset + length > etp->et_pio_size) {
340 * Writes to PIO buffers must be 64 bit aligned, and multiples of
343 write_offset = etp->et_pio_write_offset + offset;
344 write_offset_limit = write_offset + length;
345 eqp = (efx_qword_t *)buffer;
346 while (write_offset < write_offset_limit) {
347 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
349 write_offset += sizeof (efx_qword_t);
357 EFSYS_PROBE1(fail1, efx_rc_t, rc);
362 __checkReturn efx_rc_t
365 __in size_t pkt_length,
366 __in unsigned int completed,
367 __inout unsigned int *addedp)
369 efx_qword_t pio_desc;
372 unsigned int added = *addedp;
376 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
381 if (etp->et_pio_size == 0) {
386 id = added++ & etp->et_mask;
387 offset = id * sizeof (efx_qword_t);
389 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
390 unsigned int, id, uint32_t, etp->et_pio_offset,
393 EFX_POPULATE_QWORD_5(pio_desc,
394 ESF_DZ_TX_DESC_IS_OPT, 1,
395 ESF_DZ_TX_OPTION_TYPE, 1,
396 ESF_DZ_TX_PIO_CONT, 0,
397 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
398 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
400 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
402 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
415 __checkReturn efx_rc_t
418 __in_ecount(n) efx_buffer_t *eb,
420 __in unsigned int completed,
421 __inout unsigned int *addedp)
423 unsigned int added = *addedp;
427 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
432 for (i = 0; i < n; i++) {
433 efx_buffer_t *ebp = &eb[i];
434 efsys_dma_addr_t addr = ebp->eb_addr;
435 size_t size = ebp->eb_size;
436 boolean_t eop = ebp->eb_eop;
441 /* No limitations on boundary crossing */
443 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
445 id = added++ & etp->et_mask;
446 offset = id * sizeof (efx_qword_t);
448 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
449 unsigned int, id, efsys_dma_addr_t, addr,
450 size_t, size, boolean_t, eop);
452 EFX_POPULATE_QWORD_5(qword,
453 ESF_DZ_TX_KER_TYPE, 0,
454 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
455 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
456 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
457 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
459 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
462 EFX_TX_QSTAT_INCR(etp, TX_POST);
468 EFSYS_PROBE1(fail1, efx_rc_t, rc);
474 * This improves performance by, when possible, pushing a TX descriptor at the
475 * same time as the doorbell. The descriptor must be added to the TXQ, so that
476 * can be used if the hardware decides not to use the pushed descriptor.
481 __in unsigned int added,
482 __in unsigned int pushed)
484 efx_nic_t *enp = etp->et_enp;
491 wptr = added & etp->et_mask;
492 id = pushed & etp->et_mask;
493 offset = id * sizeof (efx_qword_t);
495 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
498 * SF Bug 65776: TSO option descriptors cannot be pushed if pacer bypass
499 * is enabled on the event queue this transmit queue is attached to.
501 * To ensure the code is safe, it is easiest to simply test the type of
502 * the descriptor to push, and only push it is if it not a TSO option
505 if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
506 (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
507 ESE_DZ_TX_OPTION_DESC_TSO)) {
508 /* Push the descriptor and update the wptr. */
509 EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
510 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
511 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
513 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
514 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
516 EFSYS_PIO_WRITE_BARRIER();
517 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
518 etp->et_index, &oword);
523 * Only update the wptr. This is signalled to the hardware by
524 * only writing one DWORD of the doorbell register.
526 EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
527 dword = oword.eo_dword[2];
529 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
530 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
532 EFSYS_PIO_WRITE_BARRIER();
533 EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
534 etp->et_index, &dword, B_FALSE);
538 __checkReturn efx_rc_t
541 __in_ecount(n) efx_desc_t *ed,
543 __in unsigned int completed,
544 __inout unsigned int *addedp)
546 unsigned int added = *addedp;
550 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
555 for (i = 0; i < n; i++) {
556 efx_desc_t *edp = &ed[i];
560 id = added++ & etp->et_mask;
561 offset = id * sizeof (efx_desc_t);
563 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
566 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
567 unsigned int, added, unsigned int, n);
569 EFX_TX_QSTAT_INCR(etp, TX_POST);
575 EFSYS_PROBE1(fail1, efx_rc_t, rc);
581 ef10_tx_qdesc_dma_create(
583 __in efsys_dma_addr_t addr,
586 __out efx_desc_t *edp)
588 /* No limitations on boundary crossing */
589 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
591 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
592 efsys_dma_addr_t, addr,
593 size_t, size, boolean_t, eop);
595 EFX_POPULATE_QWORD_5(edp->ed_eq,
596 ESF_DZ_TX_KER_TYPE, 0,
597 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
598 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
599 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
600 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
604 ef10_tx_qdesc_tso_create(
606 __in uint16_t ipv4_id,
607 __in uint32_t tcp_seq,
608 __in uint8_t tcp_flags,
609 __out efx_desc_t *edp)
611 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
612 uint16_t, ipv4_id, uint32_t, tcp_seq,
615 EFX_POPULATE_QWORD_5(edp->ed_eq,
616 ESF_DZ_TX_DESC_IS_OPT, 1,
617 ESF_DZ_TX_OPTION_TYPE,
618 ESE_DZ_TX_OPTION_DESC_TSO,
619 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
620 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
621 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
625 ef10_tx_qdesc_tso2_create(
627 __in uint16_t ipv4_id,
628 __in uint32_t tcp_seq,
629 __in uint16_t tcp_mss,
630 __out_ecount(count) efx_desc_t *edp,
633 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
634 uint16_t, ipv4_id, uint32_t, tcp_seq,
637 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
639 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
640 ESF_DZ_TX_DESC_IS_OPT, 1,
641 ESF_DZ_TX_OPTION_TYPE,
642 ESE_DZ_TX_OPTION_DESC_TSO,
643 ESF_DZ_TX_TSO_OPTION_TYPE,
644 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
645 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
646 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
647 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
648 ESF_DZ_TX_DESC_IS_OPT, 1,
649 ESF_DZ_TX_OPTION_TYPE,
650 ESE_DZ_TX_OPTION_DESC_TSO,
651 ESF_DZ_TX_TSO_OPTION_TYPE,
652 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
653 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
657 ef10_tx_qdesc_vlantci_create(
660 __out efx_desc_t *edp)
662 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
665 EFX_POPULATE_QWORD_4(edp->ed_eq,
666 ESF_DZ_TX_DESC_IS_OPT, 1,
667 ESF_DZ_TX_OPTION_TYPE,
668 ESE_DZ_TX_OPTION_DESC_VLAN,
669 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
670 ESF_DZ_TX_VLAN_TAG1, tci);
674 __checkReturn efx_rc_t
677 __in unsigned int ns)
682 _NOTE(ARGUNUSED(etp, ns))
683 _NOTE(CONSTANTCONDITION)
693 EFSYS_PROBE1(fail1, efx_rc_t, rc);
698 __checkReturn efx_rc_t
702 efx_nic_t *enp = etp->et_enp;
705 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
711 EFSYS_PROBE1(fail1, efx_rc_t, rc);
721 _NOTE(ARGUNUSED(etp))
727 ef10_tx_qstats_update(
729 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
733 for (id = 0; id < TX_NQSTATS; id++) {
734 efsys_stat_t *essp = &stat[id];
736 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
737 etp->et_stat[id] = 0;
741 #endif /* EFSYS_OPT_QSTATS */
743 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */