2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
38 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
41 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
43 (_etp)->et_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
47 #define EFX_TX_QSTAT_INCR(_etp, _stat)
50 static __checkReturn efx_rc_t
54 __in uint32_t target_evq,
56 __in uint32_t instance,
58 __in efsys_mem_t *esmp)
61 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
62 MC_CMD_INIT_TXQ_OUT_LEN);
63 efx_qword_t *dma_addr;
69 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
70 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
72 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_TXQ_SIZE(ndescs))) {
77 npages = EFX_TXQ_NBUFS(ndescs);
78 if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
83 req.emr_cmd = MC_CMD_INIT_TXQ;
84 req.emr_in_buf = payload;
85 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
86 req.emr_out_buf = payload;
87 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
89 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, ndescs);
90 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
91 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
92 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
94 MCDI_IN_POPULATE_DWORD_9(req, INIT_TXQ_IN_FLAGS,
95 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
96 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
97 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
98 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
99 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
100 INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN,
101 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0,
102 INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN,
103 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
104 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
105 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
106 INIT_TXQ_IN_CRC_MODE, 0,
107 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
109 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
110 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
112 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
113 addr = EFSYS_MEM_ADDR(esmp);
115 for (i = 0; i < npages; i++) {
116 EFX_POPULATE_QWORD_2(*dma_addr,
117 EFX_DWORD_1, (uint32_t)(addr >> 32),
118 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
121 addr += EFX_BUF_SIZE;
124 efx_mcdi_execute(enp, &req);
126 if (req.emr_rc != 0) {
138 EFSYS_PROBE1(fail1, efx_rc_t, rc);
143 static __checkReturn efx_rc_t
146 __in uint32_t instance)
149 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_TXQ_IN_LEN,
150 MC_CMD_FINI_TXQ_OUT_LEN);
153 req.emr_cmd = MC_CMD_FINI_TXQ;
154 req.emr_in_buf = payload;
155 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
156 req.emr_out_buf = payload;
157 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
159 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
161 efx_mcdi_execute_quiet(enp, &req);
163 if (req.emr_rc != 0) {
172 * EALREADY is not an error, but indicates that the MC has rebooted and
173 * that the TXQ has already been destroyed.
176 EFSYS_PROBE1(fail1, efx_rc_t, rc);
181 __checkReturn efx_rc_t
185 _NOTE(ARGUNUSED(enp))
193 _NOTE(ARGUNUSED(enp))
196 __checkReturn efx_rc_t
199 __in unsigned int index,
200 __in unsigned int label,
201 __in efsys_mem_t *esmp,
207 __out unsigned int *addedp)
209 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
216 inner_csum = EFX_TXQ_CKSUM_INNER_IPV4 | EFX_TXQ_CKSUM_INNER_TCPUDP;
217 if (((flags & inner_csum) != 0) &&
218 (encp->enc_tunnel_encapsulations_supported == 0)) {
223 if ((rc = efx_mcdi_init_txq(enp, ndescs, eep->ee_index, label, index,
228 * A previous user of this TX queue may have written a descriptor to the
229 * TX push collector, but not pushed the doorbell (e.g. after a crash).
230 * The next doorbell write would then push the stale descriptor.
232 * Ensure the (per network port) TX push collector is cleared by writing
233 * a no-op TX option descriptor. See bug29981 for details.
236 ef10_tx_qdesc_checksum_create(etp, flags, &desc);
238 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc.ed_eq);
239 ef10_tx_qpush(etp, *addedp, 0);
246 EFSYS_PROBE1(fail1, efx_rc_t, rc);
256 _NOTE(ARGUNUSED(etp))
260 __checkReturn efx_rc_t
264 efx_nic_t *enp = etp->et_enp;
265 efx_piobuf_handle_t handle;
268 if (etp->et_pio_size != 0) {
273 /* Sub-allocate a PIO block from a piobuf */
274 if ((rc = ef10_nic_pio_alloc(enp,
279 &etp->et_pio_size)) != 0) {
282 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
284 /* Link the piobuf to this TXQ */
285 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
290 * et_pio_offset is the offset of the sub-allocated block within the
291 * hardware PIO buffer. It is used as the buffer address in the PIO
294 * et_pio_write_offset is the offset of the sub-allocated block from the
295 * start of the write-combined memory mapping, and is used for writing
296 * data into the PIO buffer.
298 etp->et_pio_write_offset =
299 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
300 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
306 (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
309 etp->et_pio_size = 0;
311 EFSYS_PROBE1(fail1, efx_rc_t, rc);
317 ef10_tx_qpio_disable(
320 efx_nic_t *enp = etp->et_enp;
322 if (etp->et_pio_size != 0) {
323 /* Unlink the piobuf from this TXQ */
324 if (ef10_nic_pio_unlink(enp, etp->et_index) != 0)
327 /* Free the sub-allocated PIO block */
328 (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum,
330 etp->et_pio_size = 0;
331 etp->et_pio_write_offset = 0;
335 __checkReturn efx_rc_t
338 __in_ecount(length) uint8_t *buffer,
342 efx_nic_t *enp = etp->et_enp;
343 efsys_bar_t *esbp = enp->en_esbp;
344 uint32_t write_offset;
345 uint32_t write_offset_limit;
349 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
351 if (etp->et_pio_size == 0) {
355 if (offset + length > etp->et_pio_size) {
361 * Writes to PIO buffers must be 64 bit aligned, and multiples of
364 write_offset = etp->et_pio_write_offset + offset;
365 write_offset_limit = write_offset + length;
366 eqp = (efx_qword_t *)buffer;
367 while (write_offset < write_offset_limit) {
368 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
370 write_offset += sizeof (efx_qword_t);
378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
383 __checkReturn efx_rc_t
386 __in size_t pkt_length,
387 __in unsigned int completed,
388 __inout unsigned int *addedp)
390 efx_qword_t pio_desc;
393 unsigned int added = *addedp;
397 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
402 if (etp->et_pio_size == 0) {
407 id = added++ & etp->et_mask;
408 offset = id * sizeof (efx_qword_t);
410 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
411 unsigned int, id, uint32_t, etp->et_pio_offset,
414 EFX_POPULATE_QWORD_5(pio_desc,
415 ESF_DZ_TX_DESC_IS_OPT, 1,
416 ESF_DZ_TX_OPTION_TYPE, 1,
417 ESF_DZ_TX_PIO_CONT, 0,
418 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
419 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
421 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
423 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
431 EFSYS_PROBE1(fail1, efx_rc_t, rc);
436 __checkReturn efx_rc_t
439 __in_ecount(ndescs) efx_buffer_t *eb,
440 __in unsigned int ndescs,
441 __in unsigned int completed,
442 __inout unsigned int *addedp)
444 unsigned int added = *addedp;
448 if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
453 for (i = 0; i < ndescs; i++) {
454 efx_buffer_t *ebp = &eb[i];
455 efsys_dma_addr_t addr = ebp->eb_addr;
456 size_t size = ebp->eb_size;
457 boolean_t eop = ebp->eb_eop;
462 /* No limitations on boundary crossing */
464 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
466 id = added++ & etp->et_mask;
467 offset = id * sizeof (efx_qword_t);
469 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
470 unsigned int, id, efsys_dma_addr_t, addr,
471 size_t, size, boolean_t, eop);
473 EFX_POPULATE_QWORD_5(qword,
474 ESF_DZ_TX_KER_TYPE, 0,
475 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
476 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
477 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
478 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
480 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
483 EFX_TX_QSTAT_INCR(etp, TX_POST);
489 EFSYS_PROBE1(fail1, efx_rc_t, rc);
495 * This improves performance by, when possible, pushing a TX descriptor at the
496 * same time as the doorbell. The descriptor must be added to the TXQ, so that
497 * can be used if the hardware decides not to use the pushed descriptor.
502 __in unsigned int added,
503 __in unsigned int pushed)
505 efx_nic_t *enp = etp->et_enp;
512 wptr = added & etp->et_mask;
513 id = pushed & etp->et_mask;
514 offset = id * sizeof (efx_qword_t);
516 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
519 * SF Bug 65776: TSO option descriptors cannot be pushed if pacer bypass
520 * is enabled on the event queue this transmit queue is attached to.
522 * To ensure the code is safe, it is easiest to simply test the type of
523 * the descriptor to push, and only push it is if it not a TSO option
526 if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
527 (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
528 ESE_DZ_TX_OPTION_DESC_TSO)) {
529 /* Push the descriptor and update the wptr. */
530 EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
531 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
532 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
534 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
535 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
537 EFSYS_PIO_WRITE_BARRIER();
538 EFX_BAR_VI_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
539 etp->et_index, &oword);
544 * Only update the wptr. This is signalled to the hardware by
545 * only writing one DWORD of the doorbell register.
547 EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
548 dword = oword.eo_dword[2];
550 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
551 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
553 EFSYS_PIO_WRITE_BARRIER();
554 EFX_BAR_VI_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
555 etp->et_index, &dword, B_FALSE);
559 __checkReturn efx_rc_t
562 __in_ecount(ndescs) efx_desc_t *ed,
563 __in unsigned int ndescs,
564 __in unsigned int completed,
565 __inout unsigned int *addedp)
567 unsigned int added = *addedp;
570 if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1))
573 for (i = 0; i < ndescs; i++) {
574 efx_desc_t *edp = &ed[i];
578 id = added++ & etp->et_mask;
579 offset = id * sizeof (efx_desc_t);
581 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
584 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
585 unsigned int, added, unsigned int, ndescs);
587 EFX_TX_QSTAT_INCR(etp, TX_POST);
594 ef10_tx_qdesc_dma_create(
596 __in efsys_dma_addr_t addr,
599 __out efx_desc_t *edp)
601 _NOTE(ARGUNUSED(etp))
603 /* No limitations on boundary crossing */
604 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
606 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
607 efsys_dma_addr_t, addr,
608 size_t, size, boolean_t, eop);
610 EFX_POPULATE_QWORD_5(edp->ed_eq,
611 ESF_DZ_TX_KER_TYPE, 0,
612 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
613 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
614 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
615 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
619 ef10_tx_qdesc_tso_create(
621 __in uint16_t ipv4_id,
622 __in uint32_t tcp_seq,
623 __in uint8_t tcp_flags,
624 __out efx_desc_t *edp)
626 _NOTE(ARGUNUSED(etp))
628 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
629 uint16_t, ipv4_id, uint32_t, tcp_seq,
632 EFX_POPULATE_QWORD_5(edp->ed_eq,
633 ESF_DZ_TX_DESC_IS_OPT, 1,
634 ESF_DZ_TX_OPTION_TYPE,
635 ESE_DZ_TX_OPTION_DESC_TSO,
636 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
637 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
638 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
642 ef10_tx_qdesc_tso2_create(
644 __in uint16_t ipv4_id,
645 __in uint16_t outer_ipv4_id,
646 __in uint32_t tcp_seq,
647 __in uint16_t tcp_mss,
648 __out_ecount(count) efx_desc_t *edp,
651 _NOTE(ARGUNUSED(etp, count))
653 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
654 uint16_t, ipv4_id, uint32_t, tcp_seq,
657 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
659 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
660 ESF_DZ_TX_DESC_IS_OPT, 1,
661 ESF_DZ_TX_OPTION_TYPE,
662 ESE_DZ_TX_OPTION_DESC_TSO,
663 ESF_DZ_TX_TSO_OPTION_TYPE,
664 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
665 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
666 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
667 EFX_POPULATE_QWORD_5(edp[1].ed_eq,
668 ESF_DZ_TX_DESC_IS_OPT, 1,
669 ESF_DZ_TX_OPTION_TYPE,
670 ESE_DZ_TX_OPTION_DESC_TSO,
671 ESF_DZ_TX_TSO_OPTION_TYPE,
672 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
673 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss,
674 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id);
678 ef10_tx_qdesc_vlantci_create(
681 __out efx_desc_t *edp)
683 _NOTE(ARGUNUSED(etp))
685 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
688 EFX_POPULATE_QWORD_4(edp->ed_eq,
689 ESF_DZ_TX_DESC_IS_OPT, 1,
690 ESF_DZ_TX_OPTION_TYPE,
691 ESE_DZ_TX_OPTION_DESC_VLAN,
692 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
693 ESF_DZ_TX_VLAN_TAG1, tci);
697 ef10_tx_qdesc_checksum_create(
700 __out efx_desc_t *edp)
702 _NOTE(ARGUNUSED(etp));
704 EFSYS_PROBE2(tx_desc_checksum_create, unsigned int, etp->et_index,
707 EFX_POPULATE_QWORD_6(edp->ed_eq,
708 ESF_DZ_TX_DESC_IS_OPT, 1,
709 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
710 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
711 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
712 ESF_DZ_TX_OPTION_IP_CSUM,
713 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
714 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
715 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
716 ESF_DZ_TX_OPTION_INNER_IP_CSUM,
717 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
721 __checkReturn efx_rc_t
724 __in unsigned int ns)
729 _NOTE(ARGUNUSED(etp, ns))
730 _NOTE(CONSTANTCONDITION)
741 * EALREADY is not an error, but indicates that the MC has rebooted and
742 * that the TXQ has already been destroyed. Callers need to know that
743 * the TXQ flush has completed to avoid waiting until timeout for a
744 * flush done event that will not be delivered.
747 EFSYS_PROBE1(fail1, efx_rc_t, rc);
752 __checkReturn efx_rc_t
756 efx_nic_t *enp = etp->et_enp;
759 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
765 EFSYS_PROBE1(fail1, efx_rc_t, rc);
775 _NOTE(ARGUNUSED(etp))
781 ef10_tx_qstats_update(
783 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
787 for (id = 0; id < TX_NQSTATS; id++) {
788 efsys_stat_t *essp = &stat[id];
790 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
791 etp->et_stat[id] = 0;
795 #endif /* EFSYS_OPT_QSTATS */
797 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */