2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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39 #include "efx_check.h"
40 #include "efx_phy_ids.h"
46 #define EFX_STATIC_ASSERT(_cond) \
47 ((void)sizeof (char[(_cond) ? 1 : -1]))
49 #define EFX_ARRAY_SIZE(_array) \
50 (sizeof (_array) / sizeof ((_array)[0]))
52 #define EFX_FIELD_OFFSET(_type, _field) \
53 ((size_t)&(((_type *)0)->_field))
55 /* The macro expands divider twice */
56 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
60 typedef __success(return == 0) int efx_rc_t;
65 typedef enum efx_family_e {
67 EFX_FAMILY_FALCON, /* Obsolete and not supported */
69 EFX_FAMILY_HUNTINGTON,
74 extern __checkReturn efx_rc_t
78 __out efx_family_t *efp);
81 #define EFX_PCI_VENID_SFC 0x1924
83 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
85 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
86 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
87 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
89 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
90 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
91 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
93 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
94 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
96 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
97 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
98 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 #define EFX_MEM_BAR 2
107 EFX_ERR_BUFID_DC_OOB,
120 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
121 extern __checkReturn uint32_t
123 __in uint32_t crc_init,
124 __in_ecount(length) uint8_t const *input,
128 /* Type prototypes */
130 typedef struct efx_rxq_s efx_rxq_t;
134 typedef struct efx_nic_s efx_nic_t;
136 extern __checkReturn efx_rc_t
138 __in efx_family_t family,
139 __in efsys_identifier_t *esip,
140 __in efsys_bar_t *esbp,
141 __in efsys_lock_t *eslp,
142 __deref_out efx_nic_t **enpp);
144 extern __checkReturn efx_rc_t
146 __in efx_nic_t *enp);
148 extern __checkReturn efx_rc_t
150 __in efx_nic_t *enp);
152 extern __checkReturn efx_rc_t
154 __in efx_nic_t *enp);
158 extern __checkReturn efx_rc_t
159 efx_nic_register_test(
160 __in efx_nic_t *enp);
162 #endif /* EFSYS_OPT_DIAG */
166 __in efx_nic_t *enp);
170 __in efx_nic_t *enp);
174 __in efx_nic_t *enp);
176 #define EFX_PCIE_LINK_SPEED_GEN1 1
177 #define EFX_PCIE_LINK_SPEED_GEN2 2
178 #define EFX_PCIE_LINK_SPEED_GEN3 3
180 typedef enum efx_pcie_link_performance_e {
181 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
182 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
184 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
185 } efx_pcie_link_performance_t;
187 extern __checkReturn efx_rc_t
188 efx_nic_calculate_pcie_link_bandwidth(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out uint32_t *bandwidth_mbpsp);
193 extern __checkReturn efx_rc_t
194 efx_nic_check_pcie_link_speed(
196 __in uint32_t pcie_link_width,
197 __in uint32_t pcie_link_gen,
198 __out efx_pcie_link_performance_t *resultp);
202 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
203 /* Huntington and Medford require MCDIv2 commands */
204 #define WITH_MCDI_V2 1
207 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
209 typedef enum efx_mcdi_exception_e {
210 EFX_MCDI_EXCEPTION_MC_REBOOT,
211 EFX_MCDI_EXCEPTION_MC_BADASSERT,
212 } efx_mcdi_exception_t;
214 #if EFSYS_OPT_MCDI_LOGGING
215 typedef enum efx_log_msg_e {
217 EFX_LOG_MCDI_REQUEST,
218 EFX_LOG_MCDI_RESPONSE,
220 #endif /* EFSYS_OPT_MCDI_LOGGING */
222 typedef struct efx_mcdi_transport_s {
224 efsys_mem_t *emt_dma_mem;
225 void (*emt_execute)(void *, efx_mcdi_req_t *);
226 void (*emt_ev_cpl)(void *);
227 void (*emt_exception)(void *, efx_mcdi_exception_t);
228 #if EFSYS_OPT_MCDI_LOGGING
229 void (*emt_logger)(void *, efx_log_msg_t,
230 void *, size_t, void *, size_t);
231 #endif /* EFSYS_OPT_MCDI_LOGGING */
232 #if EFSYS_OPT_MCDI_PROXY_AUTH
233 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
234 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
235 } efx_mcdi_transport_t;
237 extern __checkReturn efx_rc_t
240 __in const efx_mcdi_transport_t *mtp);
242 extern __checkReturn efx_rc_t
244 __in efx_nic_t *enp);
248 __in efx_nic_t *enp);
251 efx_mcdi_get_timeout(
253 __in efx_mcdi_req_t *emrp,
254 __out uint32_t *usec_timeoutp);
257 efx_mcdi_request_start(
259 __in efx_mcdi_req_t *emrp,
260 __in boolean_t ev_cpl);
262 extern __checkReturn boolean_t
263 efx_mcdi_request_poll(
264 __in efx_nic_t *enp);
266 extern __checkReturn boolean_t
267 efx_mcdi_request_abort(
268 __in efx_nic_t *enp);
272 __in efx_nic_t *enp);
274 #endif /* EFSYS_OPT_MCDI */
278 #define EFX_NINTR_SIENA 1024
280 typedef enum efx_intr_type_e {
281 EFX_INTR_INVALID = 0,
287 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
289 extern __checkReturn efx_rc_t
292 __in efx_intr_type_t type,
293 __in efsys_mem_t *esmp);
297 __in efx_nic_t *enp);
301 __in efx_nic_t *enp);
304 efx_intr_disable_unlocked(
305 __in efx_nic_t *enp);
307 #define EFX_INTR_NEVQS 32
309 extern __checkReturn efx_rc_t
312 __in unsigned int level);
315 efx_intr_status_line(
317 __out boolean_t *fatalp,
318 __out uint32_t *maskp);
321 efx_intr_status_message(
323 __in unsigned int message,
324 __out boolean_t *fatalp);
328 __in efx_nic_t *enp);
332 __in efx_nic_t *enp);
336 #if EFSYS_OPT_MAC_STATS
338 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
339 typedef enum efx_mac_stat_e {
342 EFX_MAC_RX_UNICST_PKTS,
343 EFX_MAC_RX_MULTICST_PKTS,
344 EFX_MAC_RX_BRDCST_PKTS,
345 EFX_MAC_RX_PAUSE_PKTS,
346 EFX_MAC_RX_LE_64_PKTS,
347 EFX_MAC_RX_65_TO_127_PKTS,
348 EFX_MAC_RX_128_TO_255_PKTS,
349 EFX_MAC_RX_256_TO_511_PKTS,
350 EFX_MAC_RX_512_TO_1023_PKTS,
351 EFX_MAC_RX_1024_TO_15XX_PKTS,
352 EFX_MAC_RX_GE_15XX_PKTS,
354 EFX_MAC_RX_FCS_ERRORS,
355 EFX_MAC_RX_DROP_EVENTS,
356 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
357 EFX_MAC_RX_SYMBOL_ERRORS,
358 EFX_MAC_RX_ALIGN_ERRORS,
359 EFX_MAC_RX_INTERNAL_ERRORS,
360 EFX_MAC_RX_JABBER_PKTS,
361 EFX_MAC_RX_LANE0_CHAR_ERR,
362 EFX_MAC_RX_LANE1_CHAR_ERR,
363 EFX_MAC_RX_LANE2_CHAR_ERR,
364 EFX_MAC_RX_LANE3_CHAR_ERR,
365 EFX_MAC_RX_LANE0_DISP_ERR,
366 EFX_MAC_RX_LANE1_DISP_ERR,
367 EFX_MAC_RX_LANE2_DISP_ERR,
368 EFX_MAC_RX_LANE3_DISP_ERR,
369 EFX_MAC_RX_MATCH_FAULT,
370 EFX_MAC_RX_NODESC_DROP_CNT,
373 EFX_MAC_TX_UNICST_PKTS,
374 EFX_MAC_TX_MULTICST_PKTS,
375 EFX_MAC_TX_BRDCST_PKTS,
376 EFX_MAC_TX_PAUSE_PKTS,
377 EFX_MAC_TX_LE_64_PKTS,
378 EFX_MAC_TX_65_TO_127_PKTS,
379 EFX_MAC_TX_128_TO_255_PKTS,
380 EFX_MAC_TX_256_TO_511_PKTS,
381 EFX_MAC_TX_512_TO_1023_PKTS,
382 EFX_MAC_TX_1024_TO_15XX_PKTS,
383 EFX_MAC_TX_GE_15XX_PKTS,
385 EFX_MAC_TX_SGL_COL_PKTS,
386 EFX_MAC_TX_MULT_COL_PKTS,
387 EFX_MAC_TX_EX_COL_PKTS,
388 EFX_MAC_TX_LATE_COL_PKTS,
390 EFX_MAC_TX_EX_DEF_PKTS,
391 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
392 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
393 EFX_MAC_PM_TRUNC_VFIFO_FULL,
394 EFX_MAC_PM_DISCARD_VFIFO_FULL,
395 EFX_MAC_PM_TRUNC_QBB,
396 EFX_MAC_PM_DISCARD_QBB,
397 EFX_MAC_PM_DISCARD_MAPPING,
398 EFX_MAC_RXDP_Q_DISABLED_PKTS,
399 EFX_MAC_RXDP_DI_DROPPED_PKTS,
400 EFX_MAC_RXDP_STREAMING_PKTS,
401 EFX_MAC_RXDP_HLB_FETCH,
402 EFX_MAC_RXDP_HLB_WAIT,
403 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
404 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
405 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
406 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
407 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
408 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
409 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
410 EFX_MAC_VADAPTER_RX_BAD_BYTES,
411 EFX_MAC_VADAPTER_RX_OVERFLOW,
412 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
413 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
414 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
415 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
416 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
417 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
418 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
419 EFX_MAC_VADAPTER_TX_BAD_BYTES,
420 EFX_MAC_VADAPTER_TX_OVERFLOW,
424 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
426 #endif /* EFSYS_OPT_MAC_STATS */
428 typedef enum efx_link_mode_e {
429 EFX_LINK_UNKNOWN = 0,
442 #define EFX_MAC_ADDR_LEN 6
444 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
446 #define EFX_MAC_MULTICAST_LIST_MAX 256
448 #define EFX_MAC_SDU_MAX 9202
450 #define EFX_MAC_PDU_ADJUSTMENT \
454 + /* bug16011 */ 16) \
456 #define EFX_MAC_PDU(_sdu) \
457 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
460 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
461 * the SDU rounded up slightly.
463 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
465 #define EFX_MAC_PDU_MIN 60
466 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
468 extern __checkReturn efx_rc_t
473 extern __checkReturn efx_rc_t
478 extern __checkReturn efx_rc_t
483 extern __checkReturn efx_rc_t
486 __in boolean_t all_unicst,
487 __in boolean_t mulcst,
488 __in boolean_t all_mulcst,
489 __in boolean_t brdcst);
491 extern __checkReturn efx_rc_t
492 efx_mac_multicast_list_set(
494 __in_ecount(6*count) uint8_t const *addrs,
497 extern __checkReturn efx_rc_t
498 efx_mac_filter_default_rxq_set(
501 __in boolean_t using_rss);
504 efx_mac_filter_default_rxq_clear(
505 __in efx_nic_t *enp);
507 extern __checkReturn efx_rc_t
510 __in boolean_t enabled);
512 extern __checkReturn efx_rc_t
515 __out boolean_t *mac_upp);
517 #define EFX_FCNTL_RESPOND 0x00000001
518 #define EFX_FCNTL_GENERATE 0x00000002
520 extern __checkReturn efx_rc_t
523 __in unsigned int fcntl,
524 __in boolean_t autoneg);
529 __out unsigned int *fcntl_wantedp,
530 __out unsigned int *fcntl_linkp);
533 #if EFSYS_OPT_MAC_STATS
537 extern __checkReturn const char *
540 __in unsigned int id);
542 #endif /* EFSYS_OPT_NAMES */
544 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
546 #define EFX_MAC_STATS_MASK_NPAGES \
547 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
548 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
551 * Get mask of MAC statistics supported by the hardware.
553 * If mask_size is insufficient to return the mask, EINVAL error is
554 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
555 * (which is sizeof (uint32_t)) is sufficient.
557 extern __checkReturn efx_rc_t
558 efx_mac_stats_get_mask(
560 __out_bcount(mask_size) uint32_t *maskp,
561 __in size_t mask_size);
563 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
564 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
565 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
567 #define EFX_MAC_STATS_SIZE 0x400
569 extern __checkReturn efx_rc_t
571 __in efx_nic_t *enp);
574 * Upload mac statistics supported by the hardware into the given buffer.
576 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
579 * The hardware will only DMA statistics that it understands (of course).
580 * Drivers should not make any assumptions about which statistics are
581 * supported, especially when the statistics are generated by firmware.
583 * Thus, drivers should zero this buffer before use, so that not-understood
584 * statistics read back as zero.
586 extern __checkReturn efx_rc_t
587 efx_mac_stats_upload(
589 __in efsys_mem_t *esmp);
591 extern __checkReturn efx_rc_t
592 efx_mac_stats_periodic(
594 __in efsys_mem_t *esmp,
595 __in uint16_t period_ms,
596 __in boolean_t events);
598 extern __checkReturn efx_rc_t
599 efx_mac_stats_update(
601 __in efsys_mem_t *esmp,
602 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
603 __inout_opt uint32_t *generationp);
605 #endif /* EFSYS_OPT_MAC_STATS */
609 typedef enum efx_mon_type_e {
621 __in efx_nic_t *enp);
623 #endif /* EFSYS_OPT_NAMES */
625 extern __checkReturn efx_rc_t
627 __in efx_nic_t *enp);
629 #if EFSYS_OPT_MON_STATS
631 #define EFX_MON_STATS_PAGE_SIZE 0x100
632 #define EFX_MON_MASK_ELEMENT_SIZE 32
634 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock aa0233c80156308e */
635 typedef enum efx_mon_stat_e {
642 EFX_MON_STAT_EXT_TEMP,
643 EFX_MON_STAT_INT_TEMP,
646 EFX_MON_STAT_INT_COOLING,
647 EFX_MON_STAT_EXT_COOLING,
655 EFX_MON_STAT_AOE_TEMP,
656 EFX_MON_STAT_PSU_AOE_TEMP,
657 EFX_MON_STAT_PSU_TEMP,
663 EFX_MON_STAT_VAOE_IN,
665 EFX_MON_STAT_IAOE_IN,
666 EFX_MON_STAT_NIC_POWER,
670 EFX_MON_STAT_0_9V_ADC,
671 EFX_MON_STAT_INT_TEMP2,
672 EFX_MON_STAT_VREG_TEMP,
673 EFX_MON_STAT_VREG_0_9V_TEMP,
674 EFX_MON_STAT_VREG_1_2V_TEMP,
675 EFX_MON_STAT_INT_VPTAT,
676 EFX_MON_STAT_INT_ADC_TEMP,
677 EFX_MON_STAT_EXT_VPTAT,
678 EFX_MON_STAT_EXT_ADC_TEMP,
679 EFX_MON_STAT_AMBIENT_TEMP,
680 EFX_MON_STAT_AIRFLOW,
681 EFX_MON_STAT_VDD08D_VSS08D_CSR,
682 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
683 EFX_MON_STAT_HOTPOINT_TEMP,
684 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
685 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
686 EFX_MON_STAT_MUM_VCC,
689 EFX_MON_STAT_0V9_A_TEMP,
692 EFX_MON_STAT_0V9_B_TEMP,
693 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
694 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
695 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
696 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
697 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
698 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
699 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
700 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
701 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
702 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
703 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
704 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
705 EFX_MON_STAT_SODIMM_VOUT,
706 EFX_MON_STAT_SODIMM_0_TEMP,
707 EFX_MON_STAT_SODIMM_1_TEMP,
708 EFX_MON_STAT_PHY0_VCC,
709 EFX_MON_STAT_PHY1_VCC,
710 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
711 EFX_MON_STAT_BOARD_FRONT_TEMP,
712 EFX_MON_STAT_BOARD_BACK_TEMP,
718 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
720 typedef enum efx_mon_stat_state_e {
721 EFX_MON_STAT_STATE_OK = 0,
722 EFX_MON_STAT_STATE_WARNING = 1,
723 EFX_MON_STAT_STATE_FATAL = 2,
724 EFX_MON_STAT_STATE_BROKEN = 3,
725 EFX_MON_STAT_STATE_NO_READING = 4,
726 } efx_mon_stat_state_t;
728 typedef struct efx_mon_stat_value_s {
731 } efx_mon_stat_value_t;
738 __in efx_mon_stat_t id);
740 #endif /* EFSYS_OPT_NAMES */
742 extern __checkReturn efx_rc_t
743 efx_mon_stats_update(
745 __in efsys_mem_t *esmp,
746 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
748 #endif /* EFSYS_OPT_MON_STATS */
752 __in efx_nic_t *enp);
756 extern __checkReturn efx_rc_t
758 __in efx_nic_t *enp);
760 #if EFSYS_OPT_PHY_LED_CONTROL
762 typedef enum efx_phy_led_mode_e {
763 EFX_PHY_LED_DEFAULT = 0,
768 } efx_phy_led_mode_t;
770 extern __checkReturn efx_rc_t
773 __in efx_phy_led_mode_t mode);
775 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
777 extern __checkReturn efx_rc_t
779 __in efx_nic_t *enp);
781 #if EFSYS_OPT_LOOPBACK
783 typedef enum efx_loopback_type_e {
784 EFX_LOOPBACK_OFF = 0,
785 EFX_LOOPBACK_DATA = 1,
786 EFX_LOOPBACK_GMAC = 2,
787 EFX_LOOPBACK_XGMII = 3,
788 EFX_LOOPBACK_XGXS = 4,
789 EFX_LOOPBACK_XAUI = 5,
790 EFX_LOOPBACK_GMII = 6,
791 EFX_LOOPBACK_SGMII = 7,
792 EFX_LOOPBACK_XGBR = 8,
793 EFX_LOOPBACK_XFI = 9,
794 EFX_LOOPBACK_XAUI_FAR = 10,
795 EFX_LOOPBACK_GMII_FAR = 11,
796 EFX_LOOPBACK_SGMII_FAR = 12,
797 EFX_LOOPBACK_XFI_FAR = 13,
798 EFX_LOOPBACK_GPHY = 14,
799 EFX_LOOPBACK_PHY_XS = 15,
800 EFX_LOOPBACK_PCS = 16,
801 EFX_LOOPBACK_PMA_PMD = 17,
802 EFX_LOOPBACK_XPORT = 18,
803 EFX_LOOPBACK_XGMII_WS = 19,
804 EFX_LOOPBACK_XAUI_WS = 20,
805 EFX_LOOPBACK_XAUI_WS_FAR = 21,
806 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
807 EFX_LOOPBACK_GMII_WS = 23,
808 EFX_LOOPBACK_XFI_WS = 24,
809 EFX_LOOPBACK_XFI_WS_FAR = 25,
810 EFX_LOOPBACK_PHYXS_WS = 26,
811 EFX_LOOPBACK_PMA_INT = 27,
812 EFX_LOOPBACK_SD_NEAR = 28,
813 EFX_LOOPBACK_SD_FAR = 29,
814 EFX_LOOPBACK_PMA_INT_WS = 30,
815 EFX_LOOPBACK_SD_FEP2_WS = 31,
816 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
817 EFX_LOOPBACK_SD_FEP_WS = 33,
818 EFX_LOOPBACK_SD_FES_WS = 34,
820 } efx_loopback_type_t;
822 typedef enum efx_loopback_kind_e {
823 EFX_LOOPBACK_KIND_OFF = 0,
824 EFX_LOOPBACK_KIND_ALL,
825 EFX_LOOPBACK_KIND_MAC,
826 EFX_LOOPBACK_KIND_PHY,
828 } efx_loopback_kind_t;
832 __in efx_loopback_kind_t loopback_kind,
833 __out efx_qword_t *maskp);
835 extern __checkReturn efx_rc_t
836 efx_port_loopback_set(
838 __in efx_link_mode_t link_mode,
839 __in efx_loopback_type_t type);
843 extern __checkReturn const char *
844 efx_loopback_type_name(
846 __in efx_loopback_type_t type);
848 #endif /* EFSYS_OPT_NAMES */
850 #endif /* EFSYS_OPT_LOOPBACK */
852 extern __checkReturn efx_rc_t
855 __out_opt efx_link_mode_t *link_modep);
859 __in efx_nic_t *enp);
861 typedef enum efx_phy_cap_type_e {
862 EFX_PHY_CAP_INVALID = 0,
869 EFX_PHY_CAP_10000FDX,
873 EFX_PHY_CAP_40000FDX,
875 } efx_phy_cap_type_t;
878 #define EFX_PHY_CAP_CURRENT 0x00000000
879 #define EFX_PHY_CAP_DEFAULT 0x00000001
880 #define EFX_PHY_CAP_PERM 0x00000002
886 __out uint32_t *maskp);
888 extern __checkReturn efx_rc_t
896 __out uint32_t *maskp);
898 extern __checkReturn efx_rc_t
901 __out uint32_t *ouip);
903 typedef enum efx_phy_media_type_e {
904 EFX_PHY_MEDIA_INVALID = 0,
909 EFX_PHY_MEDIA_SFP_PLUS,
910 EFX_PHY_MEDIA_BASE_T,
911 EFX_PHY_MEDIA_QSFP_PLUS,
913 } efx_phy_media_type_t;
916 * Get the type of medium currently used. If the board has ports for
917 * modules, a module is present, and we recognise the media type of
918 * the module, then this will be the media type of the module.
919 * Otherwise it will be the media type of the port.
922 efx_phy_media_type_get(
924 __out efx_phy_media_type_t *typep);
926 extern __checkReturn efx_rc_t
927 efx_phy_module_get_info(
929 __in uint8_t dev_addr,
932 __out_bcount(len) uint8_t *data);
934 #if EFSYS_OPT_PHY_STATS
936 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
937 typedef enum efx_phy_stat_e {
939 EFX_PHY_STAT_PMA_PMD_LINK_UP,
940 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
941 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
942 EFX_PHY_STAT_PMA_PMD_REV_A,
943 EFX_PHY_STAT_PMA_PMD_REV_B,
944 EFX_PHY_STAT_PMA_PMD_REV_C,
945 EFX_PHY_STAT_PMA_PMD_REV_D,
946 EFX_PHY_STAT_PCS_LINK_UP,
947 EFX_PHY_STAT_PCS_RX_FAULT,
948 EFX_PHY_STAT_PCS_TX_FAULT,
949 EFX_PHY_STAT_PCS_BER,
950 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
951 EFX_PHY_STAT_PHY_XS_LINK_UP,
952 EFX_PHY_STAT_PHY_XS_RX_FAULT,
953 EFX_PHY_STAT_PHY_XS_TX_FAULT,
954 EFX_PHY_STAT_PHY_XS_ALIGN,
955 EFX_PHY_STAT_PHY_XS_SYNC_A,
956 EFX_PHY_STAT_PHY_XS_SYNC_B,
957 EFX_PHY_STAT_PHY_XS_SYNC_C,
958 EFX_PHY_STAT_PHY_XS_SYNC_D,
959 EFX_PHY_STAT_AN_LINK_UP,
960 EFX_PHY_STAT_AN_MASTER,
961 EFX_PHY_STAT_AN_LOCAL_RX_OK,
962 EFX_PHY_STAT_AN_REMOTE_RX_OK,
963 EFX_PHY_STAT_CL22EXT_LINK_UP,
968 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
969 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
970 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
971 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
972 EFX_PHY_STAT_AN_COMPLETE,
973 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
974 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
975 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
976 EFX_PHY_STAT_PCS_FW_VERSION_0,
977 EFX_PHY_STAT_PCS_FW_VERSION_1,
978 EFX_PHY_STAT_PCS_FW_VERSION_2,
979 EFX_PHY_STAT_PCS_FW_VERSION_3,
980 EFX_PHY_STAT_PCS_FW_BUILD_YY,
981 EFX_PHY_STAT_PCS_FW_BUILD_MM,
982 EFX_PHY_STAT_PCS_FW_BUILD_DD,
983 EFX_PHY_STAT_PCS_OP_MODE,
987 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
994 __in efx_phy_stat_t stat);
996 #endif /* EFSYS_OPT_NAMES */
998 #define EFX_PHY_STATS_SIZE 0x100
1000 extern __checkReturn efx_rc_t
1001 efx_phy_stats_update(
1002 __in efx_nic_t *enp,
1003 __in efsys_mem_t *esmp,
1004 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1006 #endif /* EFSYS_OPT_PHY_STATS */
1011 typedef enum efx_bist_type_e {
1012 EFX_BIST_TYPE_UNKNOWN,
1013 EFX_BIST_TYPE_PHY_NORMAL,
1014 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1015 EFX_BIST_TYPE_PHY_CABLE_LONG,
1016 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1017 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1018 EFX_BIST_TYPE_REG, /* Test the register memories */
1019 EFX_BIST_TYPE_NTYPES,
1022 typedef enum efx_bist_result_e {
1023 EFX_BIST_RESULT_UNKNOWN,
1024 EFX_BIST_RESULT_RUNNING,
1025 EFX_BIST_RESULT_PASSED,
1026 EFX_BIST_RESULT_FAILED,
1027 } efx_bist_result_t;
1029 typedef enum efx_phy_cable_status_e {
1030 EFX_PHY_CABLE_STATUS_OK,
1031 EFX_PHY_CABLE_STATUS_INVALID,
1032 EFX_PHY_CABLE_STATUS_OPEN,
1033 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1034 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1035 EFX_PHY_CABLE_STATUS_BUSY,
1036 } efx_phy_cable_status_t;
1038 typedef enum efx_bist_value_e {
1039 EFX_BIST_PHY_CABLE_LENGTH_A,
1040 EFX_BIST_PHY_CABLE_LENGTH_B,
1041 EFX_BIST_PHY_CABLE_LENGTH_C,
1042 EFX_BIST_PHY_CABLE_LENGTH_D,
1043 EFX_BIST_PHY_CABLE_STATUS_A,
1044 EFX_BIST_PHY_CABLE_STATUS_B,
1045 EFX_BIST_PHY_CABLE_STATUS_C,
1046 EFX_BIST_PHY_CABLE_STATUS_D,
1047 EFX_BIST_FAULT_CODE,
1049 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1055 EFX_BIST_MEM_EXPECT,
1056 EFX_BIST_MEM_ACTUAL,
1058 EFX_BIST_MEM_ECC_PARITY,
1059 EFX_BIST_MEM_ECC_FATAL,
1063 extern __checkReturn efx_rc_t
1064 efx_bist_enable_offline(
1065 __in efx_nic_t *enp);
1067 extern __checkReturn efx_rc_t
1069 __in efx_nic_t *enp,
1070 __in efx_bist_type_t type);
1072 extern __checkReturn efx_rc_t
1074 __in efx_nic_t *enp,
1075 __in efx_bist_type_t type,
1076 __out efx_bist_result_t *resultp,
1077 __out_opt uint32_t *value_maskp,
1078 __out_ecount_opt(count) unsigned long *valuesp,
1083 __in efx_nic_t *enp,
1084 __in efx_bist_type_t type);
1086 #endif /* EFSYS_OPT_BIST */
1088 #define EFX_FEATURE_IPV6 0x00000001
1089 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1090 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1091 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1092 #define EFX_FEATURE_MCDI 0x00000020
1093 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1094 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1095 #define EFX_FEATURE_TURBO 0x00000100
1096 #define EFX_FEATURE_MCDI_DMA 0x00000200
1097 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1098 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1099 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1100 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1101 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1103 typedef enum efx_tunnel_protocol_e {
1104 EFX_TUNNEL_PROTOCOL_NONE = 0,
1105 EFX_TUNNEL_PROTOCOL_VXLAN,
1106 EFX_TUNNEL_PROTOCOL_GENEVE,
1107 EFX_TUNNEL_PROTOCOL_NVGRE,
1109 } efx_tunnel_protocol_t;
1111 typedef struct efx_nic_cfg_s {
1112 uint32_t enc_board_type;
1113 uint32_t enc_phy_type;
1115 char enc_phy_name[21];
1117 char enc_phy_revision[21];
1118 efx_mon_type_t enc_mon_type;
1119 #if EFSYS_OPT_MON_STATS
1120 uint32_t enc_mon_stat_dma_buf_size;
1121 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1123 unsigned int enc_features;
1124 uint8_t enc_mac_addr[6];
1125 uint8_t enc_port; /* PHY port number */
1126 uint32_t enc_intr_vec_base;
1127 uint32_t enc_intr_limit;
1128 uint32_t enc_evq_limit;
1129 uint32_t enc_txq_limit;
1130 uint32_t enc_rxq_limit;
1131 uint32_t enc_txq_max_ndescs;
1132 uint32_t enc_buftbl_limit;
1133 uint32_t enc_piobuf_limit;
1134 uint32_t enc_piobuf_size;
1135 uint32_t enc_piobuf_min_alloc_size;
1136 uint32_t enc_evq_timer_quantum_ns;
1137 uint32_t enc_evq_timer_max_us;
1138 uint32_t enc_clk_mult;
1139 uint32_t enc_rx_prefix_size;
1140 uint32_t enc_rx_buf_align_start;
1141 uint32_t enc_rx_buf_align_end;
1142 uint32_t enc_rx_scale_max_exclusive_contexts;
1143 #if EFSYS_OPT_LOOPBACK
1144 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1145 #endif /* EFSYS_OPT_LOOPBACK */
1146 #if EFSYS_OPT_PHY_FLAGS
1147 uint32_t enc_phy_flags_mask;
1148 #endif /* EFSYS_OPT_PHY_FLAGS */
1149 #if EFSYS_OPT_PHY_LED_CONTROL
1150 uint32_t enc_led_mask;
1151 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1152 #if EFSYS_OPT_PHY_STATS
1153 uint64_t enc_phy_stat_mask;
1154 #endif /* EFSYS_OPT_PHY_STATS */
1156 uint8_t enc_mcdi_mdio_channel;
1157 #if EFSYS_OPT_PHY_STATS
1158 uint32_t enc_mcdi_phy_stat_mask;
1159 #endif /* EFSYS_OPT_PHY_STATS */
1160 #if EFSYS_OPT_MON_STATS
1161 uint32_t *enc_mcdi_sensor_maskp;
1162 uint32_t enc_mcdi_sensor_mask_size;
1163 #endif /* EFSYS_OPT_MON_STATS */
1164 #endif /* EFSYS_OPT_MCDI */
1166 uint32_t enc_bist_mask;
1167 #endif /* EFSYS_OPT_BIST */
1168 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1171 uint32_t enc_privilege_mask;
1172 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1173 boolean_t enc_bug26807_workaround;
1174 boolean_t enc_bug35388_workaround;
1175 boolean_t enc_bug41750_workaround;
1176 boolean_t enc_bug61265_workaround;
1177 boolean_t enc_rx_batching_enabled;
1178 /* Maximum number of descriptors completed in an rx event. */
1179 uint32_t enc_rx_batch_max;
1180 /* Number of rx descriptors the hardware requires for a push. */
1181 uint32_t enc_rx_push_align;
1182 /* Maximum amount of data in DMA descriptor */
1183 uint32_t enc_tx_dma_desc_size_max;
1185 * Boundary which DMA descriptor data must not cross or 0 if no
1188 uint32_t enc_tx_dma_desc_boundary;
1190 * Maximum number of bytes into the packet the TCP header can start for
1191 * the hardware to apply TSO packet edits.
1193 uint32_t enc_tx_tso_tcp_header_offset_limit;
1194 boolean_t enc_fw_assisted_tso_enabled;
1195 boolean_t enc_fw_assisted_tso_v2_enabled;
1196 /* Number of TSO contexts on the NIC (FATSOv2) */
1197 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1198 boolean_t enc_hw_tx_insert_vlan_enabled;
1199 /* Number of PFs on the NIC */
1200 uint32_t enc_hw_pf_count;
1201 /* Datapath firmware vadapter/vport/vswitch support */
1202 boolean_t enc_datapath_cap_evb;
1203 boolean_t enc_rx_disable_scatter_supported;
1204 boolean_t enc_allow_set_mac_with_installed_filters;
1205 boolean_t enc_enhanced_set_mac_supported;
1206 boolean_t enc_init_evq_v2_supported;
1207 boolean_t enc_rx_packed_stream_supported;
1208 boolean_t enc_rx_var_packed_stream_supported;
1209 boolean_t enc_pm_and_rxdp_counters;
1210 boolean_t enc_mac_stats_40g_tx_size_bins;
1211 uint32_t enc_tunnel_encapsulations_supported;
1212 /* External port identifier */
1213 uint8_t enc_external_port;
1214 uint32_t enc_mcdi_max_payload_length;
1215 /* VPD may be per-PF or global */
1216 boolean_t enc_vpd_is_global;
1217 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1218 uint32_t enc_required_pcie_bandwidth_mbps;
1219 uint32_t enc_max_pcie_link_gen;
1220 /* Firmware verifies integrity of NVRAM updates */
1221 uint32_t enc_nvram_update_verify_result_supported;
1224 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1225 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1227 #define EFX_PCI_FUNCTION(_encp) \
1228 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1230 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1232 extern const efx_nic_cfg_t *
1234 __in efx_nic_t *enp);
1236 typedef struct efx_nic_fw_info_s {
1237 /* Basic FW version information */
1238 uint16_t enfi_mc_fw_version[4];
1240 * If datapath capabilities can be detected,
1241 * additional FW information is to be shown
1243 boolean_t enfi_dpcpu_fw_ids_valid;
1244 /* Rx and Tx datapath CPU FW IDs */
1245 uint16_t enfi_rx_dpcpu_fw_id;
1246 uint16_t enfi_tx_dpcpu_fw_id;
1247 } efx_nic_fw_info_t;
1249 extern __checkReturn efx_rc_t
1250 efx_nic_get_fw_version(
1251 __in efx_nic_t *enp,
1252 __out efx_nic_fw_info_t *enfip);
1254 /* Driver resource limits (minimum required/maximum usable). */
1255 typedef struct efx_drv_limits_s {
1256 uint32_t edl_min_evq_count;
1257 uint32_t edl_max_evq_count;
1259 uint32_t edl_min_rxq_count;
1260 uint32_t edl_max_rxq_count;
1262 uint32_t edl_min_txq_count;
1263 uint32_t edl_max_txq_count;
1265 /* PIO blocks (sub-allocated from piobuf) */
1266 uint32_t edl_min_pio_alloc_size;
1267 uint32_t edl_max_pio_alloc_count;
1270 extern __checkReturn efx_rc_t
1271 efx_nic_set_drv_limits(
1272 __inout efx_nic_t *enp,
1273 __in efx_drv_limits_t *edlp);
1275 typedef enum efx_nic_region_e {
1276 EFX_REGION_VI, /* Memory BAR UC mapping */
1277 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1280 extern __checkReturn efx_rc_t
1281 efx_nic_get_bar_region(
1282 __in efx_nic_t *enp,
1283 __in efx_nic_region_t region,
1284 __out uint32_t *offsetp,
1285 __out size_t *sizep);
1287 extern __checkReturn efx_rc_t
1288 efx_nic_get_vi_pool(
1289 __in efx_nic_t *enp,
1290 __out uint32_t *evq_countp,
1291 __out uint32_t *rxq_countp,
1292 __out uint32_t *txq_countp);
1297 typedef enum efx_vpd_tag_e {
1304 typedef uint16_t efx_vpd_keyword_t;
1306 typedef struct efx_vpd_value_s {
1307 efx_vpd_tag_t evv_tag;
1308 efx_vpd_keyword_t evv_keyword;
1310 uint8_t evv_value[0x100];
1314 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1316 extern __checkReturn efx_rc_t
1318 __in efx_nic_t *enp);
1320 extern __checkReturn efx_rc_t
1322 __in efx_nic_t *enp,
1323 __out size_t *sizep);
1325 extern __checkReturn efx_rc_t
1327 __in efx_nic_t *enp,
1328 __out_bcount(size) caddr_t data,
1331 extern __checkReturn efx_rc_t
1333 __in efx_nic_t *enp,
1334 __in_bcount(size) caddr_t data,
1337 extern __checkReturn efx_rc_t
1339 __in efx_nic_t *enp,
1340 __in_bcount(size) caddr_t data,
1343 extern __checkReturn efx_rc_t
1345 __in efx_nic_t *enp,
1346 __in_bcount(size) caddr_t data,
1348 __inout efx_vpd_value_t *evvp);
1350 extern __checkReturn efx_rc_t
1352 __in efx_nic_t *enp,
1353 __inout_bcount(size) caddr_t data,
1355 __in efx_vpd_value_t *evvp);
1357 extern __checkReturn efx_rc_t
1359 __in efx_nic_t *enp,
1360 __inout_bcount(size) caddr_t data,
1362 __out efx_vpd_value_t *evvp,
1363 __inout unsigned int *contp);
1365 extern __checkReturn efx_rc_t
1367 __in efx_nic_t *enp,
1368 __in_bcount(size) caddr_t data,
1373 __in efx_nic_t *enp);
1375 #endif /* EFSYS_OPT_VPD */
1381 typedef enum efx_nvram_type_e {
1382 EFX_NVRAM_INVALID = 0,
1384 EFX_NVRAM_BOOTROM_CFG,
1385 EFX_NVRAM_MC_FIRMWARE,
1386 EFX_NVRAM_MC_GOLDEN,
1392 EFX_NVRAM_FPGA_BACKUP,
1393 EFX_NVRAM_DYNAMIC_CFG,
1396 EFX_NVRAM_MUM_FIRMWARE,
1400 extern __checkReturn efx_rc_t
1402 __in efx_nic_t *enp);
1406 extern __checkReturn efx_rc_t
1408 __in efx_nic_t *enp);
1410 #endif /* EFSYS_OPT_DIAG */
1412 extern __checkReturn efx_rc_t
1414 __in efx_nic_t *enp,
1415 __in efx_nvram_type_t type,
1416 __out size_t *sizep);
1418 extern __checkReturn efx_rc_t
1420 __in efx_nic_t *enp,
1421 __in efx_nvram_type_t type,
1422 __out_opt size_t *pref_chunkp);
1424 extern __checkReturn efx_rc_t
1425 efx_nvram_rw_finish(
1426 __in efx_nic_t *enp,
1427 __in efx_nvram_type_t type,
1428 __out_opt uint32_t *verify_resultp);
1430 extern __checkReturn efx_rc_t
1431 efx_nvram_get_version(
1432 __in efx_nic_t *enp,
1433 __in efx_nvram_type_t type,
1434 __out uint32_t *subtypep,
1435 __out_ecount(4) uint16_t version[4]);
1437 extern __checkReturn efx_rc_t
1438 efx_nvram_read_chunk(
1439 __in efx_nic_t *enp,
1440 __in efx_nvram_type_t type,
1441 __in unsigned int offset,
1442 __out_bcount(size) caddr_t data,
1445 extern __checkReturn efx_rc_t
1446 efx_nvram_read_backup(
1447 __in efx_nic_t *enp,
1448 __in efx_nvram_type_t type,
1449 __in unsigned int offset,
1450 __out_bcount(size) caddr_t data,
1453 extern __checkReturn efx_rc_t
1454 efx_nvram_set_version(
1455 __in efx_nic_t *enp,
1456 __in efx_nvram_type_t type,
1457 __in_ecount(4) uint16_t version[4]);
1459 extern __checkReturn efx_rc_t
1461 __in efx_nic_t *enp,
1462 __in efx_nvram_type_t type,
1463 __in_bcount(partn_size) caddr_t partn_data,
1464 __in size_t partn_size);
1466 extern __checkReturn efx_rc_t
1468 __in efx_nic_t *enp,
1469 __in efx_nvram_type_t type);
1471 extern __checkReturn efx_rc_t
1472 efx_nvram_write_chunk(
1473 __in efx_nic_t *enp,
1474 __in efx_nvram_type_t type,
1475 __in unsigned int offset,
1476 __in_bcount(size) caddr_t data,
1481 __in efx_nic_t *enp);
1483 #endif /* EFSYS_OPT_NVRAM */
1485 #if EFSYS_OPT_BOOTCFG
1487 /* Report size and offset of bootcfg sector in NVRAM partition. */
1488 extern __checkReturn efx_rc_t
1489 efx_bootcfg_sector_info(
1490 __in efx_nic_t *enp,
1492 __out_opt uint32_t *sector_countp,
1493 __out size_t *offsetp,
1494 __out size_t *max_sizep);
1497 * Copy bootcfg sector data to a target buffer which may differ in size.
1498 * Optionally corrects format errors in source buffer.
1501 efx_bootcfg_copy_sector(
1502 __in efx_nic_t *enp,
1503 __inout_bcount(sector_length)
1505 __in size_t sector_length,
1506 __out_bcount(data_size) uint8_t *data,
1507 __in size_t data_size,
1508 __in boolean_t handle_format_errors);
1512 __in efx_nic_t *enp,
1513 __out_bcount(size) uint8_t *data,
1518 __in efx_nic_t *enp,
1519 __in_bcount(size) uint8_t *data,
1522 #endif /* EFSYS_OPT_BOOTCFG */
1526 typedef enum efx_pattern_type_t {
1527 EFX_PATTERN_BYTE_INCREMENT = 0,
1528 EFX_PATTERN_ALL_THE_SAME,
1529 EFX_PATTERN_BIT_ALTERNATE,
1530 EFX_PATTERN_BYTE_ALTERNATE,
1531 EFX_PATTERN_BYTE_CHANGING,
1532 EFX_PATTERN_BIT_SWEEP,
1534 } efx_pattern_type_t;
1537 (*efx_sram_pattern_fn_t)(
1539 __in boolean_t negate,
1540 __out efx_qword_t *eqp);
1542 extern __checkReturn efx_rc_t
1544 __in efx_nic_t *enp,
1545 __in efx_pattern_type_t type);
1547 #endif /* EFSYS_OPT_DIAG */
1549 extern __checkReturn efx_rc_t
1550 efx_sram_buf_tbl_set(
1551 __in efx_nic_t *enp,
1553 __in efsys_mem_t *esmp,
1557 efx_sram_buf_tbl_clear(
1558 __in efx_nic_t *enp,
1562 #define EFX_BUF_TBL_SIZE 0x20000
1564 #define EFX_BUF_SIZE 4096
1568 typedef struct efx_evq_s efx_evq_t;
1570 #if EFSYS_OPT_QSTATS
1572 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1573 typedef enum efx_ev_qstat_e {
1579 EV_RX_PAUSE_FRM_ERR,
1580 EV_RX_BUF_OWNER_ID_ERR,
1581 EV_RX_IPV4_HDR_CHKSUM_ERR,
1582 EV_RX_TCP_UDP_CHKSUM_ERR,
1586 EV_RX_MCAST_HASH_MATCH,
1603 EV_DRIVER_SRM_UPD_DONE,
1604 EV_DRIVER_TX_DESCQ_FLS_DONE,
1605 EV_DRIVER_RX_DESCQ_FLS_DONE,
1606 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1607 EV_DRIVER_RX_DSC_ERROR,
1608 EV_DRIVER_TX_DSC_ERROR,
1614 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1616 #endif /* EFSYS_OPT_QSTATS */
1618 extern __checkReturn efx_rc_t
1620 __in efx_nic_t *enp);
1624 __in efx_nic_t *enp);
1626 #define EFX_EVQ_MAXNEVS 32768
1627 #define EFX_EVQ_MINNEVS 512
1629 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1630 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1632 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1633 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1634 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1635 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1637 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1638 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1639 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1641 extern __checkReturn efx_rc_t
1643 __in efx_nic_t *enp,
1644 __in unsigned int index,
1645 __in efsys_mem_t *esmp,
1649 __in uint32_t flags,
1650 __deref_out efx_evq_t **eepp);
1654 __in efx_evq_t *eep,
1655 __in uint16_t data);
1657 typedef __checkReturn boolean_t
1658 (*efx_initialized_ev_t)(
1659 __in_opt void *arg);
1661 #define EFX_PKT_UNICAST 0x0004
1662 #define EFX_PKT_START 0x0008
1664 #define EFX_PKT_VLAN_TAGGED 0x0010
1665 #define EFX_CKSUM_TCPUDP 0x0020
1666 #define EFX_CKSUM_IPV4 0x0040
1667 #define EFX_PKT_CONT 0x0080
1669 #define EFX_CHECK_VLAN 0x0100
1670 #define EFX_PKT_TCP 0x0200
1671 #define EFX_PKT_UDP 0x0400
1672 #define EFX_PKT_IPV4 0x0800
1674 #define EFX_PKT_IPV6 0x1000
1675 #define EFX_PKT_PREFIX_LEN 0x2000
1676 #define EFX_ADDR_MISMATCH 0x4000
1677 #define EFX_DISCARD 0x8000
1680 * The following flags are used only for packed stream
1681 * mode. The values for the flags are reused to fit into 16 bit,
1682 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1683 * packed stream mode
1685 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1686 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1689 #define EFX_EV_RX_NLABELS 32
1690 #define EFX_EV_TX_NLABELS 32
1692 typedef __checkReturn boolean_t
1695 __in uint32_t label,
1698 __in uint16_t flags);
1700 #if EFSYS_OPT_RX_PACKED_STREAM
1703 * Packed stream mode is documented in SF-112241-TC.
1704 * The general idea is that, instead of putting each incoming
1705 * packet into a separate buffer which is specified in a RX
1706 * descriptor, a large buffer is provided to the hardware and
1707 * packets are put there in a continuous stream.
1708 * The main advantage of such an approach is that RX queue refilling
1709 * happens much less frequently.
1712 typedef __checkReturn boolean_t
1715 __in uint32_t label,
1717 __in uint32_t pkt_count,
1718 __in uint16_t flags);
1722 typedef __checkReturn boolean_t
1725 __in uint32_t label,
1728 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1729 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1730 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1731 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1732 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1733 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1734 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1735 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1736 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1738 typedef __checkReturn boolean_t
1739 (*efx_exception_ev_t)(
1741 __in uint32_t label,
1742 __in uint32_t data);
1744 typedef __checkReturn boolean_t
1745 (*efx_rxq_flush_done_ev_t)(
1747 __in uint32_t rxq_index);
1749 typedef __checkReturn boolean_t
1750 (*efx_rxq_flush_failed_ev_t)(
1752 __in uint32_t rxq_index);
1754 typedef __checkReturn boolean_t
1755 (*efx_txq_flush_done_ev_t)(
1757 __in uint32_t txq_index);
1759 typedef __checkReturn boolean_t
1760 (*efx_software_ev_t)(
1762 __in uint16_t magic);
1764 typedef __checkReturn boolean_t
1767 __in uint32_t code);
1769 #define EFX_SRAM_CLEAR 0
1770 #define EFX_SRAM_UPDATE 1
1771 #define EFX_SRAM_ILLEGAL_CLEAR 2
1773 typedef __checkReturn boolean_t
1774 (*efx_wake_up_ev_t)(
1776 __in uint32_t label);
1778 typedef __checkReturn boolean_t
1781 __in uint32_t label);
1783 typedef __checkReturn boolean_t
1784 (*efx_link_change_ev_t)(
1786 __in efx_link_mode_t link_mode);
1788 #if EFSYS_OPT_MON_STATS
1790 typedef __checkReturn boolean_t
1791 (*efx_monitor_ev_t)(
1793 __in efx_mon_stat_t id,
1794 __in efx_mon_stat_value_t value);
1796 #endif /* EFSYS_OPT_MON_STATS */
1798 #if EFSYS_OPT_MAC_STATS
1800 typedef __checkReturn boolean_t
1801 (*efx_mac_stats_ev_t)(
1803 __in uint32_t generation);
1805 #endif /* EFSYS_OPT_MAC_STATS */
1807 typedef struct efx_ev_callbacks_s {
1808 efx_initialized_ev_t eec_initialized;
1810 #if EFSYS_OPT_RX_PACKED_STREAM
1811 efx_rx_ps_ev_t eec_rx_ps;
1814 efx_exception_ev_t eec_exception;
1815 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1816 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1817 efx_txq_flush_done_ev_t eec_txq_flush_done;
1818 efx_software_ev_t eec_software;
1819 efx_sram_ev_t eec_sram;
1820 efx_wake_up_ev_t eec_wake_up;
1821 efx_timer_ev_t eec_timer;
1822 efx_link_change_ev_t eec_link_change;
1823 #if EFSYS_OPT_MON_STATS
1824 efx_monitor_ev_t eec_monitor;
1825 #endif /* EFSYS_OPT_MON_STATS */
1826 #if EFSYS_OPT_MAC_STATS
1827 efx_mac_stats_ev_t eec_mac_stats;
1828 #endif /* EFSYS_OPT_MAC_STATS */
1829 } efx_ev_callbacks_t;
1831 extern __checkReturn boolean_t
1833 __in efx_evq_t *eep,
1834 __in unsigned int count);
1836 #if EFSYS_OPT_EV_PREFETCH
1840 __in efx_evq_t *eep,
1841 __in unsigned int count);
1843 #endif /* EFSYS_OPT_EV_PREFETCH */
1847 __in efx_evq_t *eep,
1848 __inout unsigned int *countp,
1849 __in const efx_ev_callbacks_t *eecp,
1850 __in_opt void *arg);
1852 extern __checkReturn efx_rc_t
1853 efx_ev_usecs_to_ticks(
1854 __in efx_nic_t *enp,
1855 __in unsigned int usecs,
1856 __out unsigned int *ticksp);
1858 extern __checkReturn efx_rc_t
1860 __in efx_evq_t *eep,
1861 __in unsigned int us);
1863 extern __checkReturn efx_rc_t
1865 __in efx_evq_t *eep,
1866 __in unsigned int count);
1868 #if EFSYS_OPT_QSTATS
1874 __in efx_nic_t *enp,
1875 __in unsigned int id);
1877 #endif /* EFSYS_OPT_NAMES */
1880 efx_ev_qstats_update(
1881 __in efx_evq_t *eep,
1882 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1884 #endif /* EFSYS_OPT_QSTATS */
1888 __in efx_evq_t *eep);
1892 extern __checkReturn efx_rc_t
1894 __inout efx_nic_t *enp);
1898 __in efx_nic_t *enp);
1900 #if EFSYS_OPT_RX_SCATTER
1901 __checkReturn efx_rc_t
1902 efx_rx_scatter_enable(
1903 __in efx_nic_t *enp,
1904 __in unsigned int buf_size);
1905 #endif /* EFSYS_OPT_RX_SCATTER */
1907 /* Handle to represent use of the default RSS context. */
1908 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1910 #if EFSYS_OPT_RX_SCALE
1912 typedef enum efx_rx_hash_alg_e {
1913 EFX_RX_HASHALG_LFSR = 0,
1914 EFX_RX_HASHALG_TOEPLITZ
1915 } efx_rx_hash_alg_t;
1917 #define EFX_RX_HASH_IPV4 (1U << 0)
1918 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1919 #define EFX_RX_HASH_IPV6 (1U << 2)
1920 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1922 typedef unsigned int efx_rx_hash_type_t;
1924 typedef enum efx_rx_hash_support_e {
1925 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1926 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1927 } efx_rx_hash_support_t;
1929 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1930 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1931 #define EFX_MAXRSS 64 /* RX indirection entry range */
1932 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1934 typedef enum efx_rx_scale_context_type_e {
1935 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1936 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1937 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1938 } efx_rx_scale_context_type_t;
1940 extern __checkReturn efx_rc_t
1941 efx_rx_hash_default_support_get(
1942 __in efx_nic_t *enp,
1943 __out efx_rx_hash_support_t *supportp);
1946 extern __checkReturn efx_rc_t
1947 efx_rx_scale_default_support_get(
1948 __in efx_nic_t *enp,
1949 __out efx_rx_scale_context_type_t *typep);
1951 extern __checkReturn efx_rc_t
1952 efx_rx_scale_context_alloc(
1953 __in efx_nic_t *enp,
1954 __in efx_rx_scale_context_type_t type,
1955 __in uint32_t num_queues,
1956 __out uint32_t *rss_contextp);
1958 extern __checkReturn efx_rc_t
1959 efx_rx_scale_context_free(
1960 __in efx_nic_t *enp,
1961 __in uint32_t rss_context);
1963 extern __checkReturn efx_rc_t
1964 efx_rx_scale_mode_set(
1965 __in efx_nic_t *enp,
1966 __in uint32_t rss_context,
1967 __in efx_rx_hash_alg_t alg,
1968 __in efx_rx_hash_type_t type,
1969 __in boolean_t insert);
1971 extern __checkReturn efx_rc_t
1972 efx_rx_scale_tbl_set(
1973 __in efx_nic_t *enp,
1974 __in uint32_t rss_context,
1975 __in_ecount(n) unsigned int *table,
1978 extern __checkReturn efx_rc_t
1979 efx_rx_scale_key_set(
1980 __in efx_nic_t *enp,
1981 __in uint32_t rss_context,
1982 __in_ecount(n) uint8_t *key,
1985 extern __checkReturn uint32_t
1986 efx_pseudo_hdr_hash_get(
1987 __in efx_rxq_t *erp,
1988 __in efx_rx_hash_alg_t func,
1989 __in uint8_t *buffer);
1991 #endif /* EFSYS_OPT_RX_SCALE */
1993 extern __checkReturn efx_rc_t
1994 efx_pseudo_hdr_pkt_length_get(
1995 __in efx_rxq_t *erp,
1996 __in uint8_t *buffer,
1997 __out uint16_t *pkt_lengthp);
1999 #define EFX_RXQ_MAXNDESCS 4096
2000 #define EFX_RXQ_MINNDESCS 512
2002 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2003 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2004 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2005 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2007 typedef enum efx_rxq_type_e {
2008 EFX_RXQ_TYPE_DEFAULT,
2009 EFX_RXQ_TYPE_SCATTER,
2010 EFX_RXQ_TYPE_PACKED_STREAM_1M,
2011 EFX_RXQ_TYPE_PACKED_STREAM_512K,
2012 EFX_RXQ_TYPE_PACKED_STREAM_256K,
2013 EFX_RXQ_TYPE_PACKED_STREAM_128K,
2014 EFX_RXQ_TYPE_PACKED_STREAM_64K,
2018 extern __checkReturn efx_rc_t
2020 __in efx_nic_t *enp,
2021 __in unsigned int index,
2022 __in unsigned int label,
2023 __in efx_rxq_type_t type,
2024 __in efsys_mem_t *esmp,
2027 __in efx_evq_t *eep,
2028 __deref_out efx_rxq_t **erpp);
2030 typedef struct efx_buffer_s {
2031 efsys_dma_addr_t eb_addr;
2036 typedef struct efx_desc_s {
2042 __in efx_rxq_t *erp,
2043 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2045 __in unsigned int ndescs,
2046 __in unsigned int completed,
2047 __in unsigned int added);
2051 __in efx_rxq_t *erp,
2052 __in unsigned int added,
2053 __inout unsigned int *pushedp);
2055 #if EFSYS_OPT_RX_PACKED_STREAM
2058 efx_rx_qpush_ps_credits(
2059 __in efx_rxq_t *erp);
2061 extern __checkReturn uint8_t *
2062 efx_rx_qps_packet_info(
2063 __in efx_rxq_t *erp,
2064 __in uint8_t *buffer,
2065 __in uint32_t buffer_length,
2066 __in uint32_t current_offset,
2067 __out uint16_t *lengthp,
2068 __out uint32_t *next_offsetp,
2069 __out uint32_t *timestamp);
2072 extern __checkReturn efx_rc_t
2074 __in efx_rxq_t *erp);
2078 __in efx_rxq_t *erp);
2082 __in efx_rxq_t *erp);
2086 typedef struct efx_txq_s efx_txq_t;
2088 #if EFSYS_OPT_QSTATS
2090 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2091 typedef enum efx_tx_qstat_e {
2097 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2099 #endif /* EFSYS_OPT_QSTATS */
2101 extern __checkReturn efx_rc_t
2103 __in efx_nic_t *enp);
2107 __in efx_nic_t *enp);
2109 #define EFX_TXQ_MINNDESCS 512
2111 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2112 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2113 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2115 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2117 #define EFX_TXQ_CKSUM_IPV4 0x0001
2118 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2119 #define EFX_TXQ_FATSOV2 0x0004
2120 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2121 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2123 extern __checkReturn efx_rc_t
2125 __in efx_nic_t *enp,
2126 __in unsigned int index,
2127 __in unsigned int label,
2128 __in efsys_mem_t *esmp,
2131 __in uint16_t flags,
2132 __in efx_evq_t *eep,
2133 __deref_out efx_txq_t **etpp,
2134 __out unsigned int *addedp);
2136 extern __checkReturn efx_rc_t
2138 __in efx_txq_t *etp,
2139 __in_ecount(ndescs) efx_buffer_t *eb,
2140 __in unsigned int ndescs,
2141 __in unsigned int completed,
2142 __inout unsigned int *addedp);
2144 extern __checkReturn efx_rc_t
2146 __in efx_txq_t *etp,
2147 __in unsigned int ns);
2151 __in efx_txq_t *etp,
2152 __in unsigned int added,
2153 __in unsigned int pushed);
2155 extern __checkReturn efx_rc_t
2157 __in efx_txq_t *etp);
2161 __in efx_txq_t *etp);
2163 extern __checkReturn efx_rc_t
2165 __in efx_txq_t *etp);
2168 efx_tx_qpio_disable(
2169 __in efx_txq_t *etp);
2171 extern __checkReturn efx_rc_t
2173 __in efx_txq_t *etp,
2174 __in_ecount(buf_length) uint8_t *buffer,
2175 __in size_t buf_length,
2176 __in size_t pio_buf_offset);
2178 extern __checkReturn efx_rc_t
2180 __in efx_txq_t *etp,
2181 __in size_t pkt_length,
2182 __in unsigned int completed,
2183 __inout unsigned int *addedp);
2185 extern __checkReturn efx_rc_t
2187 __in efx_txq_t *etp,
2188 __in_ecount(n) efx_desc_t *ed,
2189 __in unsigned int n,
2190 __in unsigned int completed,
2191 __inout unsigned int *addedp);
2194 efx_tx_qdesc_dma_create(
2195 __in efx_txq_t *etp,
2196 __in efsys_dma_addr_t addr,
2199 __out efx_desc_t *edp);
2202 efx_tx_qdesc_tso_create(
2203 __in efx_txq_t *etp,
2204 __in uint16_t ipv4_id,
2205 __in uint32_t tcp_seq,
2206 __in uint8_t tcp_flags,
2207 __out efx_desc_t *edp);
2209 /* Number of FATSOv2 option descriptors */
2210 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2212 /* Maximum number of DMA segments per TSO packet (not superframe) */
2213 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2216 efx_tx_qdesc_tso2_create(
2217 __in efx_txq_t *etp,
2218 __in uint16_t ipv4_id,
2219 __in uint32_t tcp_seq,
2220 __in uint16_t tcp_mss,
2221 __out_ecount(count) efx_desc_t *edp,
2225 efx_tx_qdesc_vlantci_create(
2226 __in efx_txq_t *etp,
2228 __out efx_desc_t *edp);
2230 #if EFSYS_OPT_QSTATS
2236 __in efx_nic_t *etp,
2237 __in unsigned int id);
2239 #endif /* EFSYS_OPT_NAMES */
2242 efx_tx_qstats_update(
2243 __in efx_txq_t *etp,
2244 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2246 #endif /* EFSYS_OPT_QSTATS */
2250 __in efx_txq_t *etp);
2255 #if EFSYS_OPT_FILTER
2257 #define EFX_ETHER_TYPE_IPV4 0x0800
2258 #define EFX_ETHER_TYPE_IPV6 0x86DD
2260 #define EFX_IPPROTO_TCP 6
2261 #define EFX_IPPROTO_UDP 17
2262 #define EFX_IPPROTO_GRE 47
2264 /* Use RSS to spread across multiple queues */
2265 #define EFX_FILTER_FLAG_RX_RSS 0x01
2266 /* Enable RX scatter */
2267 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2269 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2270 * May only be set by the filter implementation for each type.
2271 * A removal request will restore the automatic filter in its place.
2273 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2274 /* Filter is for RX */
2275 #define EFX_FILTER_FLAG_RX 0x08
2276 /* Filter is for TX */
2277 #define EFX_FILTER_FLAG_TX 0x10
2279 typedef unsigned int efx_filter_flags_t;
2282 * Flags which specify the fields to match on. The values are the same as in the
2283 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2286 /* Match by remote IP host address */
2287 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2288 /* Match by local IP host address */
2289 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2290 /* Match by remote MAC address */
2291 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2292 /* Match by remote TCP/UDP port */
2293 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2294 /* Match by remote TCP/UDP port */
2295 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2296 /* Match by local TCP/UDP port */
2297 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2298 /* Match by Ether-type */
2299 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2300 /* Match by inner VLAN ID */
2301 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2302 /* Match by outer VLAN ID */
2303 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2304 /* Match by IP transport protocol */
2305 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2306 /* For encapsulated packets, match all multicast inner frames */
2307 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2308 /* For encapsulated packets, match all unicast inner frames */
2309 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2310 /* Match otherwise-unmatched multicast and broadcast packets */
2311 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2312 /* Match otherwise-unmatched unicast packets */
2313 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2315 typedef uint32_t efx_filter_match_flags_t;
2317 typedef enum efx_filter_priority_s {
2318 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2319 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2320 * address list or hardware
2321 * requirements. This may only be used
2322 * by the filter implementation for
2324 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2325 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2326 * client (e.g. SR-IOV, HyperV VMQ etc.)
2328 } efx_filter_priority_t;
2331 * FIXME: All these fields are assumed to be in little-endian byte order.
2332 * It may be better for some to be big-endian. See bug42804.
2335 typedef struct efx_filter_spec_s {
2336 uint32_t efs_match_flags;
2337 uint32_t efs_priority:2;
2338 uint32_t efs_flags:6;
2339 uint32_t efs_dmaq_id:12;
2340 uint32_t efs_rss_context;
2341 uint16_t efs_outer_vid;
2342 uint16_t efs_inner_vid;
2343 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2344 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2345 uint16_t efs_ether_type;
2346 uint8_t efs_ip_proto;
2347 efx_tunnel_protocol_t efs_encap_type;
2348 uint16_t efs_loc_port;
2349 uint16_t efs_rem_port;
2350 efx_oword_t efs_rem_host;
2351 efx_oword_t efs_loc_host;
2352 } efx_filter_spec_t;
2355 /* Default values for use in filter specifications */
2356 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2357 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2359 extern __checkReturn efx_rc_t
2361 __in efx_nic_t *enp);
2365 __in efx_nic_t *enp);
2367 extern __checkReturn efx_rc_t
2369 __in efx_nic_t *enp,
2370 __inout efx_filter_spec_t *spec);
2372 extern __checkReturn efx_rc_t
2374 __in efx_nic_t *enp,
2375 __inout efx_filter_spec_t *spec);
2377 extern __checkReturn efx_rc_t
2379 __in efx_nic_t *enp);
2381 extern __checkReturn efx_rc_t
2382 efx_filter_supported_filters(
2383 __in efx_nic_t *enp,
2384 __out_ecount(buffer_length) uint32_t *buffer,
2385 __in size_t buffer_length,
2386 __out size_t *list_lengthp);
2389 efx_filter_spec_init_rx(
2390 __out efx_filter_spec_t *spec,
2391 __in efx_filter_priority_t priority,
2392 __in efx_filter_flags_t flags,
2393 __in efx_rxq_t *erp);
2396 efx_filter_spec_init_tx(
2397 __out efx_filter_spec_t *spec,
2398 __in efx_txq_t *etp);
2400 extern __checkReturn efx_rc_t
2401 efx_filter_spec_set_ipv4_local(
2402 __inout efx_filter_spec_t *spec,
2405 __in uint16_t port);
2407 extern __checkReturn efx_rc_t
2408 efx_filter_spec_set_ipv4_full(
2409 __inout efx_filter_spec_t *spec,
2411 __in uint32_t lhost,
2412 __in uint16_t lport,
2413 __in uint32_t rhost,
2414 __in uint16_t rport);
2416 extern __checkReturn efx_rc_t
2417 efx_filter_spec_set_eth_local(
2418 __inout efx_filter_spec_t *spec,
2420 __in const uint8_t *addr);
2423 efx_filter_spec_set_ether_type(
2424 __inout efx_filter_spec_t *spec,
2425 __in uint16_t ether_type);
2427 extern __checkReturn efx_rc_t
2428 efx_filter_spec_set_uc_def(
2429 __inout efx_filter_spec_t *spec);
2431 extern __checkReturn efx_rc_t
2432 efx_filter_spec_set_mc_def(
2433 __inout efx_filter_spec_t *spec);
2435 typedef enum efx_filter_inner_frame_match_e {
2436 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2437 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2438 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2439 } efx_filter_inner_frame_match_t;
2441 extern __checkReturn efx_rc_t
2442 efx_filter_spec_set_encap_type(
2443 __inout efx_filter_spec_t *spec,
2444 __in efx_tunnel_protocol_t encap_type,
2445 __in efx_filter_inner_frame_match_t inner_frame_match);
2447 #if EFSYS_OPT_RX_SCALE
2448 extern __checkReturn efx_rc_t
2449 efx_filter_spec_set_rss_context(
2450 __inout efx_filter_spec_t *spec,
2451 __in uint32_t rss_context);
2453 #endif /* EFSYS_OPT_FILTER */
2457 extern __checkReturn uint32_t
2459 __in_ecount(count) uint32_t const *input,
2461 __in uint32_t init);
2463 extern __checkReturn uint32_t
2465 __in_ecount(length) uint8_t const *input,
2467 __in uint32_t init);
2469 #if EFSYS_OPT_LICENSING
2473 typedef struct efx_key_stats_s {
2475 uint32_t eks_invalid;
2476 uint32_t eks_blacklisted;
2477 uint32_t eks_unverifiable;
2478 uint32_t eks_wrong_node;
2479 uint32_t eks_licensed_apps_lo;
2480 uint32_t eks_licensed_apps_hi;
2481 uint32_t eks_licensed_features_lo;
2482 uint32_t eks_licensed_features_hi;
2485 extern __checkReturn efx_rc_t
2487 __in efx_nic_t *enp);
2491 __in efx_nic_t *enp);
2493 extern __checkReturn boolean_t
2494 efx_lic_check_support(
2495 __in efx_nic_t *enp);
2497 extern __checkReturn efx_rc_t
2498 efx_lic_update_licenses(
2499 __in efx_nic_t *enp);
2501 extern __checkReturn efx_rc_t
2502 efx_lic_get_key_stats(
2503 __in efx_nic_t *enp,
2504 __out efx_key_stats_t *ksp);
2506 extern __checkReturn efx_rc_t
2508 __in efx_nic_t *enp,
2509 __in uint64_t app_id,
2510 __out boolean_t *licensedp);
2512 extern __checkReturn efx_rc_t
2514 __in efx_nic_t *enp,
2515 __in size_t buffer_size,
2516 __out uint32_t *typep,
2517 __out size_t *lengthp,
2518 __out_opt uint8_t *bufferp);
2521 extern __checkReturn efx_rc_t
2523 __in efx_nic_t *enp,
2524 __in_bcount(buffer_size)
2526 __in size_t buffer_size,
2527 __out uint32_t *startp);
2529 extern __checkReturn efx_rc_t
2531 __in efx_nic_t *enp,
2532 __in_bcount(buffer_size)
2534 __in size_t buffer_size,
2535 __in uint32_t offset,
2536 __out uint32_t *endp);
2538 extern __checkReturn __success(return != B_FALSE) boolean_t
2540 __in efx_nic_t *enp,
2541 __in_bcount(buffer_size)
2543 __in size_t buffer_size,
2544 __in uint32_t offset,
2545 __out uint32_t *startp,
2546 __out uint32_t *lengthp);
2548 extern __checkReturn __success(return != B_FALSE) boolean_t
2549 efx_lic_validate_key(
2550 __in efx_nic_t *enp,
2551 __in_bcount(length) caddr_t keyp,
2552 __in uint32_t length);
2554 extern __checkReturn efx_rc_t
2556 __in efx_nic_t *enp,
2557 __in_bcount(buffer_size)
2559 __in size_t buffer_size,
2560 __in uint32_t offset,
2561 __in uint32_t length,
2562 __out_bcount_part(key_max_size, *lengthp)
2564 __in size_t key_max_size,
2565 __out uint32_t *lengthp);
2567 extern __checkReturn efx_rc_t
2569 __in efx_nic_t *enp,
2570 __in_bcount(buffer_size)
2572 __in size_t buffer_size,
2573 __in uint32_t offset,
2574 __in_bcount(length) caddr_t keyp,
2575 __in uint32_t length,
2576 __out uint32_t *lengthp);
2578 __checkReturn efx_rc_t
2580 __in efx_nic_t *enp,
2581 __in_bcount(buffer_size)
2583 __in size_t buffer_size,
2584 __in uint32_t offset,
2585 __in uint32_t length,
2587 __out uint32_t *deltap);
2589 extern __checkReturn efx_rc_t
2590 efx_lic_create_partition(
2591 __in efx_nic_t *enp,
2592 __in_bcount(buffer_size)
2594 __in size_t buffer_size);
2596 extern __checkReturn efx_rc_t
2597 efx_lic_finish_partition(
2598 __in efx_nic_t *enp,
2599 __in_bcount(buffer_size)
2601 __in size_t buffer_size);
2603 #endif /* EFSYS_OPT_LICENSING */
2611 #endif /* _SYS_EFX_H */