2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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39 #include "efx_check.h"
40 #include "efx_phy_ids.h"
46 #define EFX_STATIC_ASSERT(_cond) \
47 ((void)sizeof (char[(_cond) ? 1 : -1]))
49 #define EFX_ARRAY_SIZE(_array) \
50 (sizeof (_array) / sizeof ((_array)[0]))
52 #define EFX_FIELD_OFFSET(_type, _field) \
53 ((size_t)&(((_type *)0)->_field))
55 /* The macro expands divider twice */
56 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
60 typedef __success(return == 0) int efx_rc_t;
65 typedef enum efx_family_e {
67 EFX_FAMILY_FALCON, /* Obsolete and not supported */
69 EFX_FAMILY_HUNTINGTON,
75 extern __checkReturn efx_rc_t
79 __out efx_family_t *efp,
80 __out unsigned int *membarp);
83 #define EFX_PCI_VENID_SFC 0x1924
85 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
87 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
88 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
89 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
91 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
92 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
93 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
95 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
96 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
98 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
99 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
100 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
103 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
104 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
107 #define EFX_MEM_BAR_SIENA 2
109 #define EFX_MEM_BAR_HUNTINGTON_PF 2
110 #define EFX_MEM_BAR_HUNTINGTON_VF 0
112 #define EFX_MEM_BAR_MEDFORD_PF 2
113 #define EFX_MEM_BAR_MEDFORD_VF 0
115 #define EFX_MEM_BAR_MEDFORD2 0
123 EFX_ERR_BUFID_DC_OOB,
136 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
137 extern __checkReturn uint32_t
139 __in uint32_t crc_init,
140 __in_ecount(length) uint8_t const *input,
144 /* Type prototypes */
146 typedef struct efx_rxq_s efx_rxq_t;
150 typedef struct efx_nic_s efx_nic_t;
152 extern __checkReturn efx_rc_t
154 __in efx_family_t family,
155 __in efsys_identifier_t *esip,
156 __in efsys_bar_t *esbp,
157 __in efsys_lock_t *eslp,
158 __deref_out efx_nic_t **enpp);
160 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
161 typedef enum efx_fw_variant_e {
162 EFX_FW_VARIANT_FULL_FEATURED,
163 EFX_FW_VARIANT_LOW_LATENCY,
164 EFX_FW_VARIANT_PACKED_STREAM,
165 EFX_FW_VARIANT_HIGH_TX_RATE,
166 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
167 EFX_FW_VARIANT_RULES_ENGINE,
169 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
172 extern __checkReturn efx_rc_t
175 __in efx_fw_variant_t efv);
177 extern __checkReturn efx_rc_t
179 __in efx_nic_t *enp);
181 extern __checkReturn efx_rc_t
183 __in efx_nic_t *enp);
187 extern __checkReturn efx_rc_t
188 efx_nic_register_test(
189 __in efx_nic_t *enp);
191 #endif /* EFSYS_OPT_DIAG */
195 __in efx_nic_t *enp);
199 __in efx_nic_t *enp);
203 __in efx_nic_t *enp);
205 #define EFX_PCIE_LINK_SPEED_GEN1 1
206 #define EFX_PCIE_LINK_SPEED_GEN2 2
207 #define EFX_PCIE_LINK_SPEED_GEN3 3
209 typedef enum efx_pcie_link_performance_e {
210 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
211 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
212 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
213 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
214 } efx_pcie_link_performance_t;
216 extern __checkReturn efx_rc_t
217 efx_nic_calculate_pcie_link_bandwidth(
218 __in uint32_t pcie_link_width,
219 __in uint32_t pcie_link_gen,
220 __out uint32_t *bandwidth_mbpsp);
222 extern __checkReturn efx_rc_t
223 efx_nic_check_pcie_link_speed(
225 __in uint32_t pcie_link_width,
226 __in uint32_t pcie_link_gen,
227 __out efx_pcie_link_performance_t *resultp);
231 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
232 /* Huntington and Medford require MCDIv2 commands */
233 #define WITH_MCDI_V2 1
236 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
238 typedef enum efx_mcdi_exception_e {
239 EFX_MCDI_EXCEPTION_MC_REBOOT,
240 EFX_MCDI_EXCEPTION_MC_BADASSERT,
241 } efx_mcdi_exception_t;
243 #if EFSYS_OPT_MCDI_LOGGING
244 typedef enum efx_log_msg_e {
246 EFX_LOG_MCDI_REQUEST,
247 EFX_LOG_MCDI_RESPONSE,
249 #endif /* EFSYS_OPT_MCDI_LOGGING */
251 typedef struct efx_mcdi_transport_s {
253 efsys_mem_t *emt_dma_mem;
254 void (*emt_execute)(void *, efx_mcdi_req_t *);
255 void (*emt_ev_cpl)(void *);
256 void (*emt_exception)(void *, efx_mcdi_exception_t);
257 #if EFSYS_OPT_MCDI_LOGGING
258 void (*emt_logger)(void *, efx_log_msg_t,
259 void *, size_t, void *, size_t);
260 #endif /* EFSYS_OPT_MCDI_LOGGING */
261 #if EFSYS_OPT_MCDI_PROXY_AUTH
262 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
263 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
264 } efx_mcdi_transport_t;
266 extern __checkReturn efx_rc_t
269 __in const efx_mcdi_transport_t *mtp);
271 extern __checkReturn efx_rc_t
273 __in efx_nic_t *enp);
277 __in efx_nic_t *enp);
280 efx_mcdi_get_timeout(
282 __in efx_mcdi_req_t *emrp,
283 __out uint32_t *usec_timeoutp);
286 efx_mcdi_request_start(
288 __in efx_mcdi_req_t *emrp,
289 __in boolean_t ev_cpl);
291 extern __checkReturn boolean_t
292 efx_mcdi_request_poll(
293 __in efx_nic_t *enp);
295 extern __checkReturn boolean_t
296 efx_mcdi_request_abort(
297 __in efx_nic_t *enp);
301 __in efx_nic_t *enp);
303 #endif /* EFSYS_OPT_MCDI */
307 #define EFX_NINTR_SIENA 1024
309 typedef enum efx_intr_type_e {
310 EFX_INTR_INVALID = 0,
316 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
318 extern __checkReturn efx_rc_t
321 __in efx_intr_type_t type,
322 __in efsys_mem_t *esmp);
326 __in efx_nic_t *enp);
330 __in efx_nic_t *enp);
333 efx_intr_disable_unlocked(
334 __in efx_nic_t *enp);
336 #define EFX_INTR_NEVQS 32
338 extern __checkReturn efx_rc_t
341 __in unsigned int level);
344 efx_intr_status_line(
346 __out boolean_t *fatalp,
347 __out uint32_t *maskp);
350 efx_intr_status_message(
352 __in unsigned int message,
353 __out boolean_t *fatalp);
357 __in efx_nic_t *enp);
361 __in efx_nic_t *enp);
365 #if EFSYS_OPT_MAC_STATS
367 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
368 typedef enum efx_mac_stat_e {
371 EFX_MAC_RX_UNICST_PKTS,
372 EFX_MAC_RX_MULTICST_PKTS,
373 EFX_MAC_RX_BRDCST_PKTS,
374 EFX_MAC_RX_PAUSE_PKTS,
375 EFX_MAC_RX_LE_64_PKTS,
376 EFX_MAC_RX_65_TO_127_PKTS,
377 EFX_MAC_RX_128_TO_255_PKTS,
378 EFX_MAC_RX_256_TO_511_PKTS,
379 EFX_MAC_RX_512_TO_1023_PKTS,
380 EFX_MAC_RX_1024_TO_15XX_PKTS,
381 EFX_MAC_RX_GE_15XX_PKTS,
383 EFX_MAC_RX_FCS_ERRORS,
384 EFX_MAC_RX_DROP_EVENTS,
385 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
386 EFX_MAC_RX_SYMBOL_ERRORS,
387 EFX_MAC_RX_ALIGN_ERRORS,
388 EFX_MAC_RX_INTERNAL_ERRORS,
389 EFX_MAC_RX_JABBER_PKTS,
390 EFX_MAC_RX_LANE0_CHAR_ERR,
391 EFX_MAC_RX_LANE1_CHAR_ERR,
392 EFX_MAC_RX_LANE2_CHAR_ERR,
393 EFX_MAC_RX_LANE3_CHAR_ERR,
394 EFX_MAC_RX_LANE0_DISP_ERR,
395 EFX_MAC_RX_LANE1_DISP_ERR,
396 EFX_MAC_RX_LANE2_DISP_ERR,
397 EFX_MAC_RX_LANE3_DISP_ERR,
398 EFX_MAC_RX_MATCH_FAULT,
399 EFX_MAC_RX_NODESC_DROP_CNT,
402 EFX_MAC_TX_UNICST_PKTS,
403 EFX_MAC_TX_MULTICST_PKTS,
404 EFX_MAC_TX_BRDCST_PKTS,
405 EFX_MAC_TX_PAUSE_PKTS,
406 EFX_MAC_TX_LE_64_PKTS,
407 EFX_MAC_TX_65_TO_127_PKTS,
408 EFX_MAC_TX_128_TO_255_PKTS,
409 EFX_MAC_TX_256_TO_511_PKTS,
410 EFX_MAC_TX_512_TO_1023_PKTS,
411 EFX_MAC_TX_1024_TO_15XX_PKTS,
412 EFX_MAC_TX_GE_15XX_PKTS,
414 EFX_MAC_TX_SGL_COL_PKTS,
415 EFX_MAC_TX_MULT_COL_PKTS,
416 EFX_MAC_TX_EX_COL_PKTS,
417 EFX_MAC_TX_LATE_COL_PKTS,
419 EFX_MAC_TX_EX_DEF_PKTS,
420 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
421 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
422 EFX_MAC_PM_TRUNC_VFIFO_FULL,
423 EFX_MAC_PM_DISCARD_VFIFO_FULL,
424 EFX_MAC_PM_TRUNC_QBB,
425 EFX_MAC_PM_DISCARD_QBB,
426 EFX_MAC_PM_DISCARD_MAPPING,
427 EFX_MAC_RXDP_Q_DISABLED_PKTS,
428 EFX_MAC_RXDP_DI_DROPPED_PKTS,
429 EFX_MAC_RXDP_STREAMING_PKTS,
430 EFX_MAC_RXDP_HLB_FETCH,
431 EFX_MAC_RXDP_HLB_WAIT,
432 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
433 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
434 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
435 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
436 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
437 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
438 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
439 EFX_MAC_VADAPTER_RX_BAD_BYTES,
440 EFX_MAC_VADAPTER_RX_OVERFLOW,
441 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
442 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
443 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
444 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
445 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
446 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
447 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
448 EFX_MAC_VADAPTER_TX_BAD_BYTES,
449 EFX_MAC_VADAPTER_TX_OVERFLOW,
450 EFX_MAC_FEC_UNCORRECTED_ERRORS,
451 EFX_MAC_FEC_CORRECTED_ERRORS,
452 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
453 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
454 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
455 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
456 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
457 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
458 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
459 EFX_MAC_CTPIO_OVERFLOW_FAIL,
460 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
461 EFX_MAC_CTPIO_TIMEOUT_FAIL,
462 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
463 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
464 EFX_MAC_CTPIO_INVALID_WR_FAIL,
465 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
466 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
467 EFX_MAC_CTPIO_RUNT_FALLBACK,
468 EFX_MAC_CTPIO_SUCCESS,
469 EFX_MAC_CTPIO_FALLBACK,
470 EFX_MAC_CTPIO_POISON,
472 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
473 EFX_MAC_RXDP_HLB_IDLE,
474 EFX_MAC_RXDP_HLB_TIMEOUT,
478 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
480 #endif /* EFSYS_OPT_MAC_STATS */
482 typedef enum efx_link_mode_e {
483 EFX_LINK_UNKNOWN = 0,
499 #define EFX_MAC_ADDR_LEN 6
501 #define EFX_VNI_OR_VSID_LEN 3
503 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
505 #define EFX_MAC_MULTICAST_LIST_MAX 256
507 #define EFX_MAC_SDU_MAX 9202
509 #define EFX_MAC_PDU_ADJUSTMENT \
513 + /* bug16011 */ 16) \
515 #define EFX_MAC_PDU(_sdu) \
516 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
519 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
520 * the SDU rounded up slightly.
522 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
524 #define EFX_MAC_PDU_MIN 60
525 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
527 extern __checkReturn efx_rc_t
532 extern __checkReturn efx_rc_t
537 extern __checkReturn efx_rc_t
542 extern __checkReturn efx_rc_t
545 __in boolean_t all_unicst,
546 __in boolean_t mulcst,
547 __in boolean_t all_mulcst,
548 __in boolean_t brdcst);
550 extern __checkReturn efx_rc_t
551 efx_mac_multicast_list_set(
553 __in_ecount(6*count) uint8_t const *addrs,
556 extern __checkReturn efx_rc_t
557 efx_mac_filter_default_rxq_set(
560 __in boolean_t using_rss);
563 efx_mac_filter_default_rxq_clear(
564 __in efx_nic_t *enp);
566 extern __checkReturn efx_rc_t
569 __in boolean_t enabled);
571 extern __checkReturn efx_rc_t
574 __out boolean_t *mac_upp);
576 #define EFX_FCNTL_RESPOND 0x00000001
577 #define EFX_FCNTL_GENERATE 0x00000002
579 extern __checkReturn efx_rc_t
582 __in unsigned int fcntl,
583 __in boolean_t autoneg);
588 __out unsigned int *fcntl_wantedp,
589 __out unsigned int *fcntl_linkp);
592 #if EFSYS_OPT_MAC_STATS
596 extern __checkReturn const char *
599 __in unsigned int id);
601 #endif /* EFSYS_OPT_NAMES */
603 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
605 #define EFX_MAC_STATS_MASK_NPAGES \
606 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
607 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
610 * Get mask of MAC statistics supported by the hardware.
612 * If mask_size is insufficient to return the mask, EINVAL error is
613 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
614 * (which is sizeof (uint32_t)) is sufficient.
616 extern __checkReturn efx_rc_t
617 efx_mac_stats_get_mask(
619 __out_bcount(mask_size) uint32_t *maskp,
620 __in size_t mask_size);
622 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
623 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
624 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
627 extern __checkReturn efx_rc_t
629 __in efx_nic_t *enp);
632 * Upload mac statistics supported by the hardware into the given buffer.
634 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
635 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
637 * The hardware will only DMA statistics that it understands (of course).
638 * Drivers should not make any assumptions about which statistics are
639 * supported, especially when the statistics are generated by firmware.
641 * Thus, drivers should zero this buffer before use, so that not-understood
642 * statistics read back as zero.
644 extern __checkReturn efx_rc_t
645 efx_mac_stats_upload(
647 __in efsys_mem_t *esmp);
649 extern __checkReturn efx_rc_t
650 efx_mac_stats_periodic(
652 __in efsys_mem_t *esmp,
653 __in uint16_t period_ms,
654 __in boolean_t events);
656 extern __checkReturn efx_rc_t
657 efx_mac_stats_update(
659 __in efsys_mem_t *esmp,
660 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
661 __inout_opt uint32_t *generationp);
663 #endif /* EFSYS_OPT_MAC_STATS */
667 typedef enum efx_mon_type_e {
679 __in efx_nic_t *enp);
681 #endif /* EFSYS_OPT_NAMES */
683 extern __checkReturn efx_rc_t
685 __in efx_nic_t *enp);
687 #if EFSYS_OPT_MON_STATS
689 #define EFX_MON_STATS_PAGE_SIZE 0x100
690 #define EFX_MON_MASK_ELEMENT_SIZE 32
692 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
693 typedef enum efx_mon_stat_e {
700 EFX_MON_STAT_EXT_TEMP,
701 EFX_MON_STAT_INT_TEMP,
704 EFX_MON_STAT_INT_COOLING,
705 EFX_MON_STAT_EXT_COOLING,
713 EFX_MON_STAT_AOE_TEMP,
714 EFX_MON_STAT_PSU_AOE_TEMP,
715 EFX_MON_STAT_PSU_TEMP,
721 EFX_MON_STAT_VAOE_IN,
723 EFX_MON_STAT_IAOE_IN,
724 EFX_MON_STAT_NIC_POWER,
728 EFX_MON_STAT_0_9V_ADC,
729 EFX_MON_STAT_INT_TEMP2,
730 EFX_MON_STAT_VREG_TEMP,
731 EFX_MON_STAT_VREG_0_9V_TEMP,
732 EFX_MON_STAT_VREG_1_2V_TEMP,
733 EFX_MON_STAT_INT_VPTAT,
734 EFX_MON_STAT_INT_ADC_TEMP,
735 EFX_MON_STAT_EXT_VPTAT,
736 EFX_MON_STAT_EXT_ADC_TEMP,
737 EFX_MON_STAT_AMBIENT_TEMP,
738 EFX_MON_STAT_AIRFLOW,
739 EFX_MON_STAT_VDD08D_VSS08D_CSR,
740 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
741 EFX_MON_STAT_HOTPOINT_TEMP,
742 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
743 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
744 EFX_MON_STAT_MUM_VCC,
747 EFX_MON_STAT_0V9_A_TEMP,
750 EFX_MON_STAT_0V9_B_TEMP,
751 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
752 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
753 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
754 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
755 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
756 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
757 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
758 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
759 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
760 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
761 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
762 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
763 EFX_MON_STAT_SODIMM_VOUT,
764 EFX_MON_STAT_SODIMM_0_TEMP,
765 EFX_MON_STAT_SODIMM_1_TEMP,
766 EFX_MON_STAT_PHY0_VCC,
767 EFX_MON_STAT_PHY1_VCC,
768 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
769 EFX_MON_STAT_BOARD_FRONT_TEMP,
770 EFX_MON_STAT_BOARD_BACK_TEMP,
780 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
782 typedef enum efx_mon_stat_state_e {
783 EFX_MON_STAT_STATE_OK = 0,
784 EFX_MON_STAT_STATE_WARNING = 1,
785 EFX_MON_STAT_STATE_FATAL = 2,
786 EFX_MON_STAT_STATE_BROKEN = 3,
787 EFX_MON_STAT_STATE_NO_READING = 4,
788 } efx_mon_stat_state_t;
790 typedef struct efx_mon_stat_value_s {
793 } efx_mon_stat_value_t;
800 __in efx_mon_stat_t id);
802 #endif /* EFSYS_OPT_NAMES */
804 extern __checkReturn efx_rc_t
805 efx_mon_stats_update(
807 __in efsys_mem_t *esmp,
808 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
810 #endif /* EFSYS_OPT_MON_STATS */
814 __in efx_nic_t *enp);
818 extern __checkReturn efx_rc_t
820 __in efx_nic_t *enp);
822 #if EFSYS_OPT_PHY_LED_CONTROL
824 typedef enum efx_phy_led_mode_e {
825 EFX_PHY_LED_DEFAULT = 0,
830 } efx_phy_led_mode_t;
832 extern __checkReturn efx_rc_t
835 __in efx_phy_led_mode_t mode);
837 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
839 extern __checkReturn efx_rc_t
841 __in efx_nic_t *enp);
843 #if EFSYS_OPT_LOOPBACK
845 typedef enum efx_loopback_type_e {
846 EFX_LOOPBACK_OFF = 0,
847 EFX_LOOPBACK_DATA = 1,
848 EFX_LOOPBACK_GMAC = 2,
849 EFX_LOOPBACK_XGMII = 3,
850 EFX_LOOPBACK_XGXS = 4,
851 EFX_LOOPBACK_XAUI = 5,
852 EFX_LOOPBACK_GMII = 6,
853 EFX_LOOPBACK_SGMII = 7,
854 EFX_LOOPBACK_XGBR = 8,
855 EFX_LOOPBACK_XFI = 9,
856 EFX_LOOPBACK_XAUI_FAR = 10,
857 EFX_LOOPBACK_GMII_FAR = 11,
858 EFX_LOOPBACK_SGMII_FAR = 12,
859 EFX_LOOPBACK_XFI_FAR = 13,
860 EFX_LOOPBACK_GPHY = 14,
861 EFX_LOOPBACK_PHY_XS = 15,
862 EFX_LOOPBACK_PCS = 16,
863 EFX_LOOPBACK_PMA_PMD = 17,
864 EFX_LOOPBACK_XPORT = 18,
865 EFX_LOOPBACK_XGMII_WS = 19,
866 EFX_LOOPBACK_XAUI_WS = 20,
867 EFX_LOOPBACK_XAUI_WS_FAR = 21,
868 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
869 EFX_LOOPBACK_GMII_WS = 23,
870 EFX_LOOPBACK_XFI_WS = 24,
871 EFX_LOOPBACK_XFI_WS_FAR = 25,
872 EFX_LOOPBACK_PHYXS_WS = 26,
873 EFX_LOOPBACK_PMA_INT = 27,
874 EFX_LOOPBACK_SD_NEAR = 28,
875 EFX_LOOPBACK_SD_FAR = 29,
876 EFX_LOOPBACK_PMA_INT_WS = 30,
877 EFX_LOOPBACK_SD_FEP2_WS = 31,
878 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
879 EFX_LOOPBACK_SD_FEP_WS = 33,
880 EFX_LOOPBACK_SD_FES_WS = 34,
881 EFX_LOOPBACK_AOE_INT_NEAR = 35,
882 EFX_LOOPBACK_DATA_WS = 36,
883 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
885 } efx_loopback_type_t;
887 typedef enum efx_loopback_kind_e {
888 EFX_LOOPBACK_KIND_OFF = 0,
889 EFX_LOOPBACK_KIND_ALL,
890 EFX_LOOPBACK_KIND_MAC,
891 EFX_LOOPBACK_KIND_PHY,
893 } efx_loopback_kind_t;
897 __in efx_loopback_kind_t loopback_kind,
898 __out efx_qword_t *maskp);
900 extern __checkReturn efx_rc_t
901 efx_port_loopback_set(
903 __in efx_link_mode_t link_mode,
904 __in efx_loopback_type_t type);
908 extern __checkReturn const char *
909 efx_loopback_type_name(
911 __in efx_loopback_type_t type);
913 #endif /* EFSYS_OPT_NAMES */
915 #endif /* EFSYS_OPT_LOOPBACK */
917 extern __checkReturn efx_rc_t
920 __out_opt efx_link_mode_t *link_modep);
924 __in efx_nic_t *enp);
926 typedef enum efx_phy_cap_type_e {
927 EFX_PHY_CAP_INVALID = 0,
934 EFX_PHY_CAP_10000FDX,
938 EFX_PHY_CAP_40000FDX,
940 EFX_PHY_CAP_100000FDX,
941 EFX_PHY_CAP_25000FDX,
942 EFX_PHY_CAP_50000FDX,
943 EFX_PHY_CAP_BASER_FEC,
944 EFX_PHY_CAP_BASER_FEC_REQUESTED,
946 EFX_PHY_CAP_RS_FEC_REQUESTED,
947 EFX_PHY_CAP_25G_BASER_FEC,
948 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
950 } efx_phy_cap_type_t;
953 #define EFX_PHY_CAP_CURRENT 0x00000000
954 #define EFX_PHY_CAP_DEFAULT 0x00000001
955 #define EFX_PHY_CAP_PERM 0x00000002
961 __out uint32_t *maskp);
963 extern __checkReturn efx_rc_t
971 __out uint32_t *maskp);
973 extern __checkReturn efx_rc_t
976 __out uint32_t *ouip);
978 typedef enum efx_phy_media_type_e {
979 EFX_PHY_MEDIA_INVALID = 0,
984 EFX_PHY_MEDIA_SFP_PLUS,
985 EFX_PHY_MEDIA_BASE_T,
986 EFX_PHY_MEDIA_QSFP_PLUS,
988 } efx_phy_media_type_t;
991 * Get the type of medium currently used. If the board has ports for
992 * modules, a module is present, and we recognise the media type of
993 * the module, then this will be the media type of the module.
994 * Otherwise it will be the media type of the port.
997 efx_phy_media_type_get(
999 __out efx_phy_media_type_t *typep);
1001 extern __checkReturn efx_rc_t
1002 efx_phy_module_get_info(
1003 __in efx_nic_t *enp,
1004 __in uint8_t dev_addr,
1005 __in uint8_t offset,
1007 __out_bcount(len) uint8_t *data);
1009 #if EFSYS_OPT_PHY_STATS
1011 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1012 typedef enum efx_phy_stat_e {
1014 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1015 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1016 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1017 EFX_PHY_STAT_PMA_PMD_REV_A,
1018 EFX_PHY_STAT_PMA_PMD_REV_B,
1019 EFX_PHY_STAT_PMA_PMD_REV_C,
1020 EFX_PHY_STAT_PMA_PMD_REV_D,
1021 EFX_PHY_STAT_PCS_LINK_UP,
1022 EFX_PHY_STAT_PCS_RX_FAULT,
1023 EFX_PHY_STAT_PCS_TX_FAULT,
1024 EFX_PHY_STAT_PCS_BER,
1025 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1026 EFX_PHY_STAT_PHY_XS_LINK_UP,
1027 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1028 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1029 EFX_PHY_STAT_PHY_XS_ALIGN,
1030 EFX_PHY_STAT_PHY_XS_SYNC_A,
1031 EFX_PHY_STAT_PHY_XS_SYNC_B,
1032 EFX_PHY_STAT_PHY_XS_SYNC_C,
1033 EFX_PHY_STAT_PHY_XS_SYNC_D,
1034 EFX_PHY_STAT_AN_LINK_UP,
1035 EFX_PHY_STAT_AN_MASTER,
1036 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1037 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1038 EFX_PHY_STAT_CL22EXT_LINK_UP,
1043 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1044 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1045 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1046 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1047 EFX_PHY_STAT_AN_COMPLETE,
1048 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1049 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1050 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1051 EFX_PHY_STAT_PCS_FW_VERSION_0,
1052 EFX_PHY_STAT_PCS_FW_VERSION_1,
1053 EFX_PHY_STAT_PCS_FW_VERSION_2,
1054 EFX_PHY_STAT_PCS_FW_VERSION_3,
1055 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1056 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1057 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1058 EFX_PHY_STAT_PCS_OP_MODE,
1062 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1068 __in efx_nic_t *enp,
1069 __in efx_phy_stat_t stat);
1071 #endif /* EFSYS_OPT_NAMES */
1073 #define EFX_PHY_STATS_SIZE 0x100
1075 extern __checkReturn efx_rc_t
1076 efx_phy_stats_update(
1077 __in efx_nic_t *enp,
1078 __in efsys_mem_t *esmp,
1079 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1081 #endif /* EFSYS_OPT_PHY_STATS */
1086 typedef enum efx_bist_type_e {
1087 EFX_BIST_TYPE_UNKNOWN,
1088 EFX_BIST_TYPE_PHY_NORMAL,
1089 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1090 EFX_BIST_TYPE_PHY_CABLE_LONG,
1091 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1092 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1093 EFX_BIST_TYPE_REG, /* Test the register memories */
1094 EFX_BIST_TYPE_NTYPES,
1097 typedef enum efx_bist_result_e {
1098 EFX_BIST_RESULT_UNKNOWN,
1099 EFX_BIST_RESULT_RUNNING,
1100 EFX_BIST_RESULT_PASSED,
1101 EFX_BIST_RESULT_FAILED,
1102 } efx_bist_result_t;
1104 typedef enum efx_phy_cable_status_e {
1105 EFX_PHY_CABLE_STATUS_OK,
1106 EFX_PHY_CABLE_STATUS_INVALID,
1107 EFX_PHY_CABLE_STATUS_OPEN,
1108 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1109 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1110 EFX_PHY_CABLE_STATUS_BUSY,
1111 } efx_phy_cable_status_t;
1113 typedef enum efx_bist_value_e {
1114 EFX_BIST_PHY_CABLE_LENGTH_A,
1115 EFX_BIST_PHY_CABLE_LENGTH_B,
1116 EFX_BIST_PHY_CABLE_LENGTH_C,
1117 EFX_BIST_PHY_CABLE_LENGTH_D,
1118 EFX_BIST_PHY_CABLE_STATUS_A,
1119 EFX_BIST_PHY_CABLE_STATUS_B,
1120 EFX_BIST_PHY_CABLE_STATUS_C,
1121 EFX_BIST_PHY_CABLE_STATUS_D,
1122 EFX_BIST_FAULT_CODE,
1124 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1130 EFX_BIST_MEM_EXPECT,
1131 EFX_BIST_MEM_ACTUAL,
1133 EFX_BIST_MEM_ECC_PARITY,
1134 EFX_BIST_MEM_ECC_FATAL,
1138 extern __checkReturn efx_rc_t
1139 efx_bist_enable_offline(
1140 __in efx_nic_t *enp);
1142 extern __checkReturn efx_rc_t
1144 __in efx_nic_t *enp,
1145 __in efx_bist_type_t type);
1147 extern __checkReturn efx_rc_t
1149 __in efx_nic_t *enp,
1150 __in efx_bist_type_t type,
1151 __out efx_bist_result_t *resultp,
1152 __out_opt uint32_t *value_maskp,
1153 __out_ecount_opt(count) unsigned long *valuesp,
1158 __in efx_nic_t *enp,
1159 __in efx_bist_type_t type);
1161 #endif /* EFSYS_OPT_BIST */
1163 #define EFX_FEATURE_IPV6 0x00000001
1164 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1165 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1166 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1167 #define EFX_FEATURE_MCDI 0x00000020
1168 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1169 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1170 #define EFX_FEATURE_TURBO 0x00000100
1171 #define EFX_FEATURE_MCDI_DMA 0x00000200
1172 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1173 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1174 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1175 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1176 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1178 typedef enum efx_tunnel_protocol_e {
1179 EFX_TUNNEL_PROTOCOL_NONE = 0,
1180 EFX_TUNNEL_PROTOCOL_VXLAN,
1181 EFX_TUNNEL_PROTOCOL_GENEVE,
1182 EFX_TUNNEL_PROTOCOL_NVGRE,
1184 } efx_tunnel_protocol_t;
1186 typedef enum efx_vi_window_shift_e {
1187 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1188 EFX_VI_WINDOW_SHIFT_8K = 13,
1189 EFX_VI_WINDOW_SHIFT_16K = 14,
1190 EFX_VI_WINDOW_SHIFT_64K = 16,
1191 } efx_vi_window_shift_t;
1193 typedef struct efx_nic_cfg_s {
1194 uint32_t enc_board_type;
1195 uint32_t enc_phy_type;
1197 char enc_phy_name[21];
1199 char enc_phy_revision[21];
1200 efx_mon_type_t enc_mon_type;
1201 #if EFSYS_OPT_MON_STATS
1202 uint32_t enc_mon_stat_dma_buf_size;
1203 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1205 unsigned int enc_features;
1206 efx_vi_window_shift_t enc_vi_window_shift;
1207 uint8_t enc_mac_addr[6];
1208 uint8_t enc_port; /* PHY port number */
1209 uint32_t enc_intr_vec_base;
1210 uint32_t enc_intr_limit;
1211 uint32_t enc_evq_limit;
1212 uint32_t enc_txq_limit;
1213 uint32_t enc_rxq_limit;
1214 uint32_t enc_txq_max_ndescs;
1215 uint32_t enc_buftbl_limit;
1216 uint32_t enc_piobuf_limit;
1217 uint32_t enc_piobuf_size;
1218 uint32_t enc_piobuf_min_alloc_size;
1219 uint32_t enc_evq_timer_quantum_ns;
1220 uint32_t enc_evq_timer_max_us;
1221 uint32_t enc_clk_mult;
1222 uint32_t enc_rx_prefix_size;
1223 uint32_t enc_rx_buf_align_start;
1224 uint32_t enc_rx_buf_align_end;
1225 uint32_t enc_rx_scale_max_exclusive_contexts;
1227 * Mask of supported hash algorithms.
1228 * Hash algorithm types are used as the bit indices.
1230 uint32_t enc_rx_scale_hash_alg_mask;
1232 * Indicates whether port numbers can be included to the
1233 * input data for hash computation.
1235 boolean_t enc_rx_scale_l4_hash_supported;
1236 boolean_t enc_rx_scale_additional_modes_supported;
1237 #if EFSYS_OPT_LOOPBACK
1238 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1239 #endif /* EFSYS_OPT_LOOPBACK */
1240 #if EFSYS_OPT_PHY_FLAGS
1241 uint32_t enc_phy_flags_mask;
1242 #endif /* EFSYS_OPT_PHY_FLAGS */
1243 #if EFSYS_OPT_PHY_LED_CONTROL
1244 uint32_t enc_led_mask;
1245 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1246 #if EFSYS_OPT_PHY_STATS
1247 uint64_t enc_phy_stat_mask;
1248 #endif /* EFSYS_OPT_PHY_STATS */
1250 uint8_t enc_mcdi_mdio_channel;
1251 #if EFSYS_OPT_PHY_STATS
1252 uint32_t enc_mcdi_phy_stat_mask;
1253 #endif /* EFSYS_OPT_PHY_STATS */
1254 #if EFSYS_OPT_MON_STATS
1255 uint32_t *enc_mcdi_sensor_maskp;
1256 uint32_t enc_mcdi_sensor_mask_size;
1257 #endif /* EFSYS_OPT_MON_STATS */
1258 #endif /* EFSYS_OPT_MCDI */
1260 uint32_t enc_bist_mask;
1261 #endif /* EFSYS_OPT_BIST */
1262 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1265 uint32_t enc_privilege_mask;
1266 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1267 boolean_t enc_bug26807_workaround;
1268 boolean_t enc_bug35388_workaround;
1269 boolean_t enc_bug41750_workaround;
1270 boolean_t enc_bug61265_workaround;
1271 boolean_t enc_rx_batching_enabled;
1272 /* Maximum number of descriptors completed in an rx event. */
1273 uint32_t enc_rx_batch_max;
1274 /* Number of rx descriptors the hardware requires for a push. */
1275 uint32_t enc_rx_push_align;
1276 /* Maximum amount of data in DMA descriptor */
1277 uint32_t enc_tx_dma_desc_size_max;
1279 * Boundary which DMA descriptor data must not cross or 0 if no
1282 uint32_t enc_tx_dma_desc_boundary;
1284 * Maximum number of bytes into the packet the TCP header can start for
1285 * the hardware to apply TSO packet edits.
1287 uint32_t enc_tx_tso_tcp_header_offset_limit;
1288 boolean_t enc_fw_assisted_tso_enabled;
1289 boolean_t enc_fw_assisted_tso_v2_enabled;
1290 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1291 /* Number of TSO contexts on the NIC (FATSOv2) */
1292 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1293 boolean_t enc_hw_tx_insert_vlan_enabled;
1294 /* Number of PFs on the NIC */
1295 uint32_t enc_hw_pf_count;
1296 /* Datapath firmware vadapter/vport/vswitch support */
1297 boolean_t enc_datapath_cap_evb;
1298 boolean_t enc_rx_disable_scatter_supported;
1299 boolean_t enc_allow_set_mac_with_installed_filters;
1300 boolean_t enc_enhanced_set_mac_supported;
1301 boolean_t enc_init_evq_v2_supported;
1302 boolean_t enc_rx_packed_stream_supported;
1303 boolean_t enc_rx_var_packed_stream_supported;
1304 boolean_t enc_rx_es_super_buffer_supported;
1305 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1306 boolean_t enc_pm_and_rxdp_counters;
1307 boolean_t enc_mac_stats_40g_tx_size_bins;
1308 uint32_t enc_tunnel_encapsulations_supported;
1310 * NIC global maximum for unique UDP tunnel ports shared by all
1313 uint32_t enc_tunnel_config_udp_entries_max;
1314 /* External port identifier */
1315 uint8_t enc_external_port;
1316 uint32_t enc_mcdi_max_payload_length;
1317 /* VPD may be per-PF or global */
1318 boolean_t enc_vpd_is_global;
1319 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1320 uint32_t enc_required_pcie_bandwidth_mbps;
1321 uint32_t enc_max_pcie_link_gen;
1322 /* Firmware verifies integrity of NVRAM updates */
1323 uint32_t enc_nvram_update_verify_result_supported;
1324 /* Firmware support for extended MAC_STATS buffer */
1325 uint32_t enc_mac_stats_nstats;
1326 boolean_t enc_fec_counters;
1327 boolean_t enc_hlb_counters;
1328 /* Firmware support for "FLAG" and "MARK" filter actions */
1329 boolean_t enc_filter_action_flag_supported;
1330 boolean_t enc_filter_action_mark_supported;
1331 uint32_t enc_filter_action_mark_max;
1334 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1335 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1337 #define EFX_PCI_FUNCTION(_encp) \
1338 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1340 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1342 extern const efx_nic_cfg_t *
1344 __in efx_nic_t *enp);
1346 /* RxDPCPU firmware id values by which FW variant can be identified */
1347 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1348 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1349 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1350 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1351 #define EFX_RXDP_DPDK_FW_ID 0x6
1353 typedef struct efx_nic_fw_info_s {
1354 /* Basic FW version information */
1355 uint16_t enfi_mc_fw_version[4];
1357 * If datapath capabilities can be detected,
1358 * additional FW information is to be shown
1360 boolean_t enfi_dpcpu_fw_ids_valid;
1361 /* Rx and Tx datapath CPU FW IDs */
1362 uint16_t enfi_rx_dpcpu_fw_id;
1363 uint16_t enfi_tx_dpcpu_fw_id;
1364 } efx_nic_fw_info_t;
1366 extern __checkReturn efx_rc_t
1367 efx_nic_get_fw_version(
1368 __in efx_nic_t *enp,
1369 __out efx_nic_fw_info_t *enfip);
1371 /* Driver resource limits (minimum required/maximum usable). */
1372 typedef struct efx_drv_limits_s {
1373 uint32_t edl_min_evq_count;
1374 uint32_t edl_max_evq_count;
1376 uint32_t edl_min_rxq_count;
1377 uint32_t edl_max_rxq_count;
1379 uint32_t edl_min_txq_count;
1380 uint32_t edl_max_txq_count;
1382 /* PIO blocks (sub-allocated from piobuf) */
1383 uint32_t edl_min_pio_alloc_size;
1384 uint32_t edl_max_pio_alloc_count;
1387 extern __checkReturn efx_rc_t
1388 efx_nic_set_drv_limits(
1389 __inout efx_nic_t *enp,
1390 __in efx_drv_limits_t *edlp);
1392 typedef enum efx_nic_region_e {
1393 EFX_REGION_VI, /* Memory BAR UC mapping */
1394 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1397 extern __checkReturn efx_rc_t
1398 efx_nic_get_bar_region(
1399 __in efx_nic_t *enp,
1400 __in efx_nic_region_t region,
1401 __out uint32_t *offsetp,
1402 __out size_t *sizep);
1404 extern __checkReturn efx_rc_t
1405 efx_nic_get_vi_pool(
1406 __in efx_nic_t *enp,
1407 __out uint32_t *evq_countp,
1408 __out uint32_t *rxq_countp,
1409 __out uint32_t *txq_countp);
1414 typedef enum efx_vpd_tag_e {
1421 typedef uint16_t efx_vpd_keyword_t;
1423 typedef struct efx_vpd_value_s {
1424 efx_vpd_tag_t evv_tag;
1425 efx_vpd_keyword_t evv_keyword;
1427 uint8_t evv_value[0x100];
1431 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1433 extern __checkReturn efx_rc_t
1435 __in efx_nic_t *enp);
1437 extern __checkReturn efx_rc_t
1439 __in efx_nic_t *enp,
1440 __out size_t *sizep);
1442 extern __checkReturn efx_rc_t
1444 __in efx_nic_t *enp,
1445 __out_bcount(size) caddr_t data,
1448 extern __checkReturn efx_rc_t
1450 __in efx_nic_t *enp,
1451 __in_bcount(size) caddr_t data,
1454 extern __checkReturn efx_rc_t
1456 __in efx_nic_t *enp,
1457 __in_bcount(size) caddr_t data,
1460 extern __checkReturn efx_rc_t
1462 __in efx_nic_t *enp,
1463 __in_bcount(size) caddr_t data,
1465 __inout efx_vpd_value_t *evvp);
1467 extern __checkReturn efx_rc_t
1469 __in efx_nic_t *enp,
1470 __inout_bcount(size) caddr_t data,
1472 __in efx_vpd_value_t *evvp);
1474 extern __checkReturn efx_rc_t
1476 __in efx_nic_t *enp,
1477 __inout_bcount(size) caddr_t data,
1479 __out efx_vpd_value_t *evvp,
1480 __inout unsigned int *contp);
1482 extern __checkReturn efx_rc_t
1484 __in efx_nic_t *enp,
1485 __in_bcount(size) caddr_t data,
1490 __in efx_nic_t *enp);
1492 #endif /* EFSYS_OPT_VPD */
1498 typedef enum efx_nvram_type_e {
1499 EFX_NVRAM_INVALID = 0,
1501 EFX_NVRAM_BOOTROM_CFG,
1502 EFX_NVRAM_MC_FIRMWARE,
1503 EFX_NVRAM_MC_GOLDEN,
1509 EFX_NVRAM_FPGA_BACKUP,
1510 EFX_NVRAM_DYNAMIC_CFG,
1513 EFX_NVRAM_MUM_FIRMWARE,
1517 extern __checkReturn efx_rc_t
1519 __in efx_nic_t *enp);
1523 extern __checkReturn efx_rc_t
1525 __in efx_nic_t *enp);
1527 #endif /* EFSYS_OPT_DIAG */
1529 extern __checkReturn efx_rc_t
1531 __in efx_nic_t *enp,
1532 __in efx_nvram_type_t type,
1533 __out size_t *sizep);
1535 extern __checkReturn efx_rc_t
1537 __in efx_nic_t *enp,
1538 __in efx_nvram_type_t type,
1539 __out_opt size_t *pref_chunkp);
1541 extern __checkReturn efx_rc_t
1542 efx_nvram_rw_finish(
1543 __in efx_nic_t *enp,
1544 __in efx_nvram_type_t type,
1545 __out_opt uint32_t *verify_resultp);
1547 extern __checkReturn efx_rc_t
1548 efx_nvram_get_version(
1549 __in efx_nic_t *enp,
1550 __in efx_nvram_type_t type,
1551 __out uint32_t *subtypep,
1552 __out_ecount(4) uint16_t version[4]);
1554 extern __checkReturn efx_rc_t
1555 efx_nvram_read_chunk(
1556 __in efx_nic_t *enp,
1557 __in efx_nvram_type_t type,
1558 __in unsigned int offset,
1559 __out_bcount(size) caddr_t data,
1562 extern __checkReturn efx_rc_t
1563 efx_nvram_read_backup(
1564 __in efx_nic_t *enp,
1565 __in efx_nvram_type_t type,
1566 __in unsigned int offset,
1567 __out_bcount(size) caddr_t data,
1570 extern __checkReturn efx_rc_t
1571 efx_nvram_set_version(
1572 __in efx_nic_t *enp,
1573 __in efx_nvram_type_t type,
1574 __in_ecount(4) uint16_t version[4]);
1576 extern __checkReturn efx_rc_t
1578 __in efx_nic_t *enp,
1579 __in efx_nvram_type_t type,
1580 __in_bcount(partn_size) caddr_t partn_data,
1581 __in size_t partn_size);
1583 extern __checkReturn efx_rc_t
1585 __in efx_nic_t *enp,
1586 __in efx_nvram_type_t type);
1588 extern __checkReturn efx_rc_t
1589 efx_nvram_write_chunk(
1590 __in efx_nic_t *enp,
1591 __in efx_nvram_type_t type,
1592 __in unsigned int offset,
1593 __in_bcount(size) caddr_t data,
1598 __in efx_nic_t *enp);
1600 #endif /* EFSYS_OPT_NVRAM */
1602 #if EFSYS_OPT_BOOTCFG
1604 /* Report size and offset of bootcfg sector in NVRAM partition. */
1605 extern __checkReturn efx_rc_t
1606 efx_bootcfg_sector_info(
1607 __in efx_nic_t *enp,
1609 __out_opt uint32_t *sector_countp,
1610 __out size_t *offsetp,
1611 __out size_t *max_sizep);
1614 * Copy bootcfg sector data to a target buffer which may differ in size.
1615 * Optionally corrects format errors in source buffer.
1618 efx_bootcfg_copy_sector(
1619 __in efx_nic_t *enp,
1620 __inout_bcount(sector_length)
1622 __in size_t sector_length,
1623 __out_bcount(data_size) uint8_t *data,
1624 __in size_t data_size,
1625 __in boolean_t handle_format_errors);
1629 __in efx_nic_t *enp,
1630 __out_bcount(size) uint8_t *data,
1635 __in efx_nic_t *enp,
1636 __in_bcount(size) uint8_t *data,
1639 #endif /* EFSYS_OPT_BOOTCFG */
1641 #if EFSYS_OPT_IMAGE_LAYOUT
1643 #include "ef10_signed_image_layout.h"
1646 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1649 * The image header format is extensible. However, older drivers require an
1650 * exact match of image header version and header length when validating and
1651 * writing firmware images.
1653 * To avoid breaking backward compatibility, we use the upper bits of the
1654 * controller version fields to contain an extra version number used for
1655 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1656 * version). See bug39254 and SF-102785-PS for details.
1658 typedef struct efx_image_header_s {
1660 uint32_t eih_version;
1662 uint32_t eih_subtype;
1663 uint32_t eih_code_size;
1666 uint32_t eih_controller_version_min;
1668 uint16_t eih_controller_version_min_short;
1669 uint8_t eih_extra_version_a;
1670 uint8_t eih_extra_version_b;
1674 uint32_t eih_controller_version_max;
1676 uint16_t eih_controller_version_max_short;
1677 uint8_t eih_extra_version_c;
1678 uint8_t eih_extra_version_d;
1681 uint16_t eih_code_version_a;
1682 uint16_t eih_code_version_b;
1683 uint16_t eih_code_version_c;
1684 uint16_t eih_code_version_d;
1685 } efx_image_header_t;
1687 #define EFX_IMAGE_HEADER_SIZE (40)
1688 #define EFX_IMAGE_HEADER_VERSION (4)
1689 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1692 typedef struct efx_image_trailer_s {
1694 } efx_image_trailer_t;
1696 #define EFX_IMAGE_TRAILER_SIZE (4)
1698 typedef enum efx_image_format_e {
1699 EFX_IMAGE_FORMAT_NO_IMAGE,
1700 EFX_IMAGE_FORMAT_INVALID,
1701 EFX_IMAGE_FORMAT_UNSIGNED,
1702 EFX_IMAGE_FORMAT_SIGNED,
1703 } efx_image_format_t;
1705 typedef struct efx_image_info_s {
1706 efx_image_format_t eii_format;
1707 uint8_t * eii_imagep;
1708 size_t eii_image_size;
1709 efx_image_header_t * eii_headerp;
1712 extern __checkReturn efx_rc_t
1713 efx_check_reflash_image(
1715 __in uint32_t buffer_size,
1716 __out efx_image_info_t *infop);
1718 extern __checkReturn efx_rc_t
1719 efx_build_signed_image_write_buffer(
1720 __out_bcount(buffer_size)
1722 __in uint32_t buffer_size,
1723 __in efx_image_info_t *infop,
1724 __out efx_image_header_t **headerpp);
1726 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1730 typedef enum efx_pattern_type_t {
1731 EFX_PATTERN_BYTE_INCREMENT = 0,
1732 EFX_PATTERN_ALL_THE_SAME,
1733 EFX_PATTERN_BIT_ALTERNATE,
1734 EFX_PATTERN_BYTE_ALTERNATE,
1735 EFX_PATTERN_BYTE_CHANGING,
1736 EFX_PATTERN_BIT_SWEEP,
1738 } efx_pattern_type_t;
1741 (*efx_sram_pattern_fn_t)(
1743 __in boolean_t negate,
1744 __out efx_qword_t *eqp);
1746 extern __checkReturn efx_rc_t
1748 __in efx_nic_t *enp,
1749 __in efx_pattern_type_t type);
1751 #endif /* EFSYS_OPT_DIAG */
1753 extern __checkReturn efx_rc_t
1754 efx_sram_buf_tbl_set(
1755 __in efx_nic_t *enp,
1757 __in efsys_mem_t *esmp,
1761 efx_sram_buf_tbl_clear(
1762 __in efx_nic_t *enp,
1766 #define EFX_BUF_TBL_SIZE 0x20000
1768 #define EFX_BUF_SIZE 4096
1772 typedef struct efx_evq_s efx_evq_t;
1774 #if EFSYS_OPT_QSTATS
1776 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1777 typedef enum efx_ev_qstat_e {
1783 EV_RX_PAUSE_FRM_ERR,
1784 EV_RX_BUF_OWNER_ID_ERR,
1785 EV_RX_IPV4_HDR_CHKSUM_ERR,
1786 EV_RX_TCP_UDP_CHKSUM_ERR,
1790 EV_RX_MCAST_HASH_MATCH,
1807 EV_DRIVER_SRM_UPD_DONE,
1808 EV_DRIVER_TX_DESCQ_FLS_DONE,
1809 EV_DRIVER_RX_DESCQ_FLS_DONE,
1810 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1811 EV_DRIVER_RX_DSC_ERROR,
1812 EV_DRIVER_TX_DSC_ERROR,
1818 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1820 #endif /* EFSYS_OPT_QSTATS */
1822 extern __checkReturn efx_rc_t
1824 __in efx_nic_t *enp);
1828 __in efx_nic_t *enp);
1830 #define EFX_EVQ_MAXNEVS 32768
1831 #define EFX_EVQ_MINNEVS 512
1833 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1834 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1836 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1837 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1838 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1839 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1841 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1842 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1843 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1845 extern __checkReturn efx_rc_t
1847 __in efx_nic_t *enp,
1848 __in unsigned int index,
1849 __in efsys_mem_t *esmp,
1853 __in uint32_t flags,
1854 __deref_out efx_evq_t **eepp);
1858 __in efx_evq_t *eep,
1859 __in uint16_t data);
1861 typedef __checkReturn boolean_t
1862 (*efx_initialized_ev_t)(
1863 __in_opt void *arg);
1865 #define EFX_PKT_UNICAST 0x0004
1866 #define EFX_PKT_START 0x0008
1868 #define EFX_PKT_VLAN_TAGGED 0x0010
1869 #define EFX_CKSUM_TCPUDP 0x0020
1870 #define EFX_CKSUM_IPV4 0x0040
1871 #define EFX_PKT_CONT 0x0080
1873 #define EFX_CHECK_VLAN 0x0100
1874 #define EFX_PKT_TCP 0x0200
1875 #define EFX_PKT_UDP 0x0400
1876 #define EFX_PKT_IPV4 0x0800
1878 #define EFX_PKT_IPV6 0x1000
1879 #define EFX_PKT_PREFIX_LEN 0x2000
1880 #define EFX_ADDR_MISMATCH 0x4000
1881 #define EFX_DISCARD 0x8000
1884 * The following flags are used only for packed stream
1885 * mode. The values for the flags are reused to fit into 16 bit,
1886 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1887 * packed stream mode
1889 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1890 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1893 #define EFX_EV_RX_NLABELS 32
1894 #define EFX_EV_TX_NLABELS 32
1896 typedef __checkReturn boolean_t
1899 __in uint32_t label,
1902 __in uint16_t flags);
1904 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1907 * Packed stream mode is documented in SF-112241-TC.
1908 * The general idea is that, instead of putting each incoming
1909 * packet into a separate buffer which is specified in a RX
1910 * descriptor, a large buffer is provided to the hardware and
1911 * packets are put there in a continuous stream.
1912 * The main advantage of such an approach is that RX queue refilling
1913 * happens much less frequently.
1915 * Equal stride packed stream mode is documented in SF-119419-TC.
1916 * The general idea is to utilize advantages of the packed stream,
1917 * but avoid indirection in packets representation.
1918 * The main advantage of such an approach is that RX queue refilling
1919 * happens much less frequently and packets buffers are independent
1920 * from upper layers point of view.
1923 typedef __checkReturn boolean_t
1926 __in uint32_t label,
1928 __in uint32_t pkt_count,
1929 __in uint16_t flags);
1933 typedef __checkReturn boolean_t
1936 __in uint32_t label,
1939 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1940 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1941 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1942 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1943 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1944 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1945 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1946 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1947 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1949 typedef __checkReturn boolean_t
1950 (*efx_exception_ev_t)(
1952 __in uint32_t label,
1953 __in uint32_t data);
1955 typedef __checkReturn boolean_t
1956 (*efx_rxq_flush_done_ev_t)(
1958 __in uint32_t rxq_index);
1960 typedef __checkReturn boolean_t
1961 (*efx_rxq_flush_failed_ev_t)(
1963 __in uint32_t rxq_index);
1965 typedef __checkReturn boolean_t
1966 (*efx_txq_flush_done_ev_t)(
1968 __in uint32_t txq_index);
1970 typedef __checkReturn boolean_t
1971 (*efx_software_ev_t)(
1973 __in uint16_t magic);
1975 typedef __checkReturn boolean_t
1978 __in uint32_t code);
1980 #define EFX_SRAM_CLEAR 0
1981 #define EFX_SRAM_UPDATE 1
1982 #define EFX_SRAM_ILLEGAL_CLEAR 2
1984 typedef __checkReturn boolean_t
1985 (*efx_wake_up_ev_t)(
1987 __in uint32_t label);
1989 typedef __checkReturn boolean_t
1992 __in uint32_t label);
1994 typedef __checkReturn boolean_t
1995 (*efx_link_change_ev_t)(
1997 __in efx_link_mode_t link_mode);
1999 #if EFSYS_OPT_MON_STATS
2001 typedef __checkReturn boolean_t
2002 (*efx_monitor_ev_t)(
2004 __in efx_mon_stat_t id,
2005 __in efx_mon_stat_value_t value);
2007 #endif /* EFSYS_OPT_MON_STATS */
2009 #if EFSYS_OPT_MAC_STATS
2011 typedef __checkReturn boolean_t
2012 (*efx_mac_stats_ev_t)(
2014 __in uint32_t generation);
2016 #endif /* EFSYS_OPT_MAC_STATS */
2018 typedef struct efx_ev_callbacks_s {
2019 efx_initialized_ev_t eec_initialized;
2021 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2022 efx_rx_ps_ev_t eec_rx_ps;
2025 efx_exception_ev_t eec_exception;
2026 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2027 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2028 efx_txq_flush_done_ev_t eec_txq_flush_done;
2029 efx_software_ev_t eec_software;
2030 efx_sram_ev_t eec_sram;
2031 efx_wake_up_ev_t eec_wake_up;
2032 efx_timer_ev_t eec_timer;
2033 efx_link_change_ev_t eec_link_change;
2034 #if EFSYS_OPT_MON_STATS
2035 efx_monitor_ev_t eec_monitor;
2036 #endif /* EFSYS_OPT_MON_STATS */
2037 #if EFSYS_OPT_MAC_STATS
2038 efx_mac_stats_ev_t eec_mac_stats;
2039 #endif /* EFSYS_OPT_MAC_STATS */
2040 } efx_ev_callbacks_t;
2042 extern __checkReturn boolean_t
2044 __in efx_evq_t *eep,
2045 __in unsigned int count);
2047 #if EFSYS_OPT_EV_PREFETCH
2051 __in efx_evq_t *eep,
2052 __in unsigned int count);
2054 #endif /* EFSYS_OPT_EV_PREFETCH */
2058 __in efx_evq_t *eep,
2059 __inout unsigned int *countp,
2060 __in const efx_ev_callbacks_t *eecp,
2061 __in_opt void *arg);
2063 extern __checkReturn efx_rc_t
2064 efx_ev_usecs_to_ticks(
2065 __in efx_nic_t *enp,
2066 __in unsigned int usecs,
2067 __out unsigned int *ticksp);
2069 extern __checkReturn efx_rc_t
2071 __in efx_evq_t *eep,
2072 __in unsigned int us);
2074 extern __checkReturn efx_rc_t
2076 __in efx_evq_t *eep,
2077 __in unsigned int count);
2079 #if EFSYS_OPT_QSTATS
2085 __in efx_nic_t *enp,
2086 __in unsigned int id);
2088 #endif /* EFSYS_OPT_NAMES */
2091 efx_ev_qstats_update(
2092 __in efx_evq_t *eep,
2093 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2095 #endif /* EFSYS_OPT_QSTATS */
2099 __in efx_evq_t *eep);
2103 extern __checkReturn efx_rc_t
2105 __inout efx_nic_t *enp);
2109 __in efx_nic_t *enp);
2111 #if EFSYS_OPT_RX_SCATTER
2112 __checkReturn efx_rc_t
2113 efx_rx_scatter_enable(
2114 __in efx_nic_t *enp,
2115 __in unsigned int buf_size);
2116 #endif /* EFSYS_OPT_RX_SCATTER */
2118 /* Handle to represent use of the default RSS context. */
2119 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2121 #if EFSYS_OPT_RX_SCALE
2123 typedef enum efx_rx_hash_alg_e {
2124 EFX_RX_HASHALG_LFSR = 0,
2125 EFX_RX_HASHALG_TOEPLITZ,
2126 EFX_RX_HASHALG_PACKED_STREAM,
2128 } efx_rx_hash_alg_t;
2131 * Legacy hash type flags.
2133 * They represent standard tuples for distinct traffic classes.
2135 #define EFX_RX_HASH_IPV4 (1U << 0)
2136 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2137 #define EFX_RX_HASH_IPV6 (1U << 2)
2138 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2140 #define EFX_RX_HASH_LEGACY_MASK \
2141 (EFX_RX_HASH_IPV4 | \
2142 EFX_RX_HASH_TCPIPV4 | \
2143 EFX_RX_HASH_IPV6 | \
2144 EFX_RX_HASH_TCPIPV6)
2147 * The type of the argument used by efx_rx_scale_mode_set() to
2148 * provide a means for the client drivers to configure hashing.
2150 * A properly constructed value can either be:
2151 * - a combination of legacy flags
2152 * - a combination of EFX_RX_HASH() flags
2154 typedef unsigned int efx_rx_hash_type_t;
2156 typedef enum efx_rx_hash_support_e {
2157 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2158 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2159 } efx_rx_hash_support_t;
2161 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2162 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2163 #define EFX_MAXRSS 64 /* RX indirection entry range */
2164 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2166 typedef enum efx_rx_scale_context_type_e {
2167 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2168 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2169 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2170 } efx_rx_scale_context_type_t;
2173 * Traffic classes eligible for hash computation.
2175 * Select packet headers used in computing the receive hash.
2176 * This uses the same encoding as the RSS_MODES field of
2177 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2179 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2180 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2181 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2182 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2183 #define EFX_RX_CLASS_IPV4_LBN 16
2184 #define EFX_RX_CLASS_IPV4_WIDTH 4
2185 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2186 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2187 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2188 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2189 #define EFX_RX_CLASS_IPV6_LBN 28
2190 #define EFX_RX_CLASS_IPV6_WIDTH 4
2192 #define EFX_RX_NCLASSES 6
2195 * Ancillary flags used to construct generic hash tuples.
2196 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2198 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2199 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2200 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2201 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2204 * Generic hash tuples.
2206 * They express combinations of packet fields
2207 * which can contribute to the hash value for
2208 * a particular traffic class.
2210 #define EFX_RX_CLASS_HASH_DISABLE 0
2212 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2213 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2215 #define EFX_RX_CLASS_HASH_2TUPLE \
2216 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2217 EFX_RX_CLASS_HASH_DST_ADDR)
2219 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2220 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2221 EFX_RX_CLASS_HASH_SRC_PORT)
2223 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2224 (EFX_RX_CLASS_HASH_DST_ADDR | \
2225 EFX_RX_CLASS_HASH_DST_PORT)
2227 #define EFX_RX_CLASS_HASH_4TUPLE \
2228 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2229 EFX_RX_CLASS_HASH_DST_ADDR | \
2230 EFX_RX_CLASS_HASH_SRC_PORT | \
2231 EFX_RX_CLASS_HASH_DST_PORT)
2233 #define EFX_RX_CLASS_HASH_NTUPLES 7
2236 * Hash flag constructor.
2238 * Resulting flags encode hash tuples for specific traffic classes.
2239 * The client drivers are encouraged to use these flags to form
2240 * a hash type value.
2242 #define EFX_RX_HASH(_class, _tuple) \
2243 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2244 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2247 * The maximum number of EFX_RX_HASH() flags.
2249 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2251 extern __checkReturn efx_rc_t
2252 efx_rx_scale_hash_flags_get(
2253 __in efx_nic_t *enp,
2254 __in efx_rx_hash_alg_t hash_alg,
2255 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flagsp,
2256 __out unsigned int *nflagsp);
2258 extern __checkReturn efx_rc_t
2259 efx_rx_hash_default_support_get(
2260 __in efx_nic_t *enp,
2261 __out efx_rx_hash_support_t *supportp);
2264 extern __checkReturn efx_rc_t
2265 efx_rx_scale_default_support_get(
2266 __in efx_nic_t *enp,
2267 __out efx_rx_scale_context_type_t *typep);
2269 extern __checkReturn efx_rc_t
2270 efx_rx_scale_context_alloc(
2271 __in efx_nic_t *enp,
2272 __in efx_rx_scale_context_type_t type,
2273 __in uint32_t num_queues,
2274 __out uint32_t *rss_contextp);
2276 extern __checkReturn efx_rc_t
2277 efx_rx_scale_context_free(
2278 __in efx_nic_t *enp,
2279 __in uint32_t rss_context);
2281 extern __checkReturn efx_rc_t
2282 efx_rx_scale_mode_set(
2283 __in efx_nic_t *enp,
2284 __in uint32_t rss_context,
2285 __in efx_rx_hash_alg_t alg,
2286 __in efx_rx_hash_type_t type,
2287 __in boolean_t insert);
2289 extern __checkReturn efx_rc_t
2290 efx_rx_scale_tbl_set(
2291 __in efx_nic_t *enp,
2292 __in uint32_t rss_context,
2293 __in_ecount(n) unsigned int *table,
2296 extern __checkReturn efx_rc_t
2297 efx_rx_scale_key_set(
2298 __in efx_nic_t *enp,
2299 __in uint32_t rss_context,
2300 __in_ecount(n) uint8_t *key,
2303 extern __checkReturn uint32_t
2304 efx_pseudo_hdr_hash_get(
2305 __in efx_rxq_t *erp,
2306 __in efx_rx_hash_alg_t func,
2307 __in uint8_t *buffer);
2309 #endif /* EFSYS_OPT_RX_SCALE */
2311 extern __checkReturn efx_rc_t
2312 efx_pseudo_hdr_pkt_length_get(
2313 __in efx_rxq_t *erp,
2314 __in uint8_t *buffer,
2315 __out uint16_t *pkt_lengthp);
2317 #define EFX_RXQ_MAXNDESCS 4096
2318 #define EFX_RXQ_MINNDESCS 512
2320 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2321 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2322 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2323 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2325 typedef enum efx_rxq_type_e {
2326 EFX_RXQ_TYPE_DEFAULT,
2327 EFX_RXQ_TYPE_PACKED_STREAM,
2328 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2333 * Dummy flag to be used instead of 0 to make it clear that the argument
2334 * is receive queue flags.
2336 #define EFX_RXQ_FLAG_NONE 0x0
2337 #define EFX_RXQ_FLAG_SCATTER 0x1
2339 * If tunnels are supported and Rx event can provide information about
2340 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2341 * full-feature firmware variant running), outer classes are requested by
2342 * default. However, if the driver supports tunnels, the flag allows to
2343 * request inner classes which are required to be able to interpret inner
2344 * Rx checksum offload results.
2346 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2348 extern __checkReturn efx_rc_t
2350 __in efx_nic_t *enp,
2351 __in unsigned int index,
2352 __in unsigned int label,
2353 __in efx_rxq_type_t type,
2354 __in efsys_mem_t *esmp,
2357 __in unsigned int flags,
2358 __in efx_evq_t *eep,
2359 __deref_out efx_rxq_t **erpp);
2361 #if EFSYS_OPT_RX_PACKED_STREAM
2363 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2364 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2365 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2366 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2367 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2369 extern __checkReturn efx_rc_t
2370 efx_rx_qcreate_packed_stream(
2371 __in efx_nic_t *enp,
2372 __in unsigned int index,
2373 __in unsigned int label,
2374 __in uint32_t ps_buf_size,
2375 __in efsys_mem_t *esmp,
2377 __in efx_evq_t *eep,
2378 __deref_out efx_rxq_t **erpp);
2382 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2384 /* Maximum head-of-line block timeout in nanoseconds */
2385 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2387 extern __checkReturn efx_rc_t
2388 efx_rx_qcreate_es_super_buffer(
2389 __in efx_nic_t *enp,
2390 __in unsigned int index,
2391 __in unsigned int label,
2392 __in uint32_t n_bufs_per_desc,
2393 __in uint32_t max_dma_len,
2394 __in uint32_t buf_stride,
2395 __in uint32_t hol_block_timeout,
2396 __in efsys_mem_t *esmp,
2398 __in unsigned int flags,
2399 __in efx_evq_t *eep,
2400 __deref_out efx_rxq_t **erpp);
2404 typedef struct efx_buffer_s {
2405 efsys_dma_addr_t eb_addr;
2410 typedef struct efx_desc_s {
2416 __in efx_rxq_t *erp,
2417 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2419 __in unsigned int ndescs,
2420 __in unsigned int completed,
2421 __in unsigned int added);
2425 __in efx_rxq_t *erp,
2426 __in unsigned int added,
2427 __inout unsigned int *pushedp);
2429 #if EFSYS_OPT_RX_PACKED_STREAM
2432 efx_rx_qpush_ps_credits(
2433 __in efx_rxq_t *erp);
2435 extern __checkReturn uint8_t *
2436 efx_rx_qps_packet_info(
2437 __in efx_rxq_t *erp,
2438 __in uint8_t *buffer,
2439 __in uint32_t buffer_length,
2440 __in uint32_t current_offset,
2441 __out uint16_t *lengthp,
2442 __out uint32_t *next_offsetp,
2443 __out uint32_t *timestamp);
2446 extern __checkReturn efx_rc_t
2448 __in efx_rxq_t *erp);
2452 __in efx_rxq_t *erp);
2456 __in efx_rxq_t *erp);
2460 typedef struct efx_txq_s efx_txq_t;
2462 #if EFSYS_OPT_QSTATS
2464 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2465 typedef enum efx_tx_qstat_e {
2471 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2473 #endif /* EFSYS_OPT_QSTATS */
2475 extern __checkReturn efx_rc_t
2477 __in efx_nic_t *enp);
2481 __in efx_nic_t *enp);
2483 #define EFX_TXQ_MINNDESCS 512
2485 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2486 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2487 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2489 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2491 #define EFX_TXQ_CKSUM_IPV4 0x0001
2492 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2493 #define EFX_TXQ_FATSOV2 0x0004
2494 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2495 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2497 extern __checkReturn efx_rc_t
2499 __in efx_nic_t *enp,
2500 __in unsigned int index,
2501 __in unsigned int label,
2502 __in efsys_mem_t *esmp,
2505 __in uint16_t flags,
2506 __in efx_evq_t *eep,
2507 __deref_out efx_txq_t **etpp,
2508 __out unsigned int *addedp);
2510 extern __checkReturn efx_rc_t
2512 __in efx_txq_t *etp,
2513 __in_ecount(ndescs) efx_buffer_t *eb,
2514 __in unsigned int ndescs,
2515 __in unsigned int completed,
2516 __inout unsigned int *addedp);
2518 extern __checkReturn efx_rc_t
2520 __in efx_txq_t *etp,
2521 __in unsigned int ns);
2525 __in efx_txq_t *etp,
2526 __in unsigned int added,
2527 __in unsigned int pushed);
2529 extern __checkReturn efx_rc_t
2531 __in efx_txq_t *etp);
2535 __in efx_txq_t *etp);
2537 extern __checkReturn efx_rc_t
2539 __in efx_txq_t *etp);
2542 efx_tx_qpio_disable(
2543 __in efx_txq_t *etp);
2545 extern __checkReturn efx_rc_t
2547 __in efx_txq_t *etp,
2548 __in_ecount(buf_length) uint8_t *buffer,
2549 __in size_t buf_length,
2550 __in size_t pio_buf_offset);
2552 extern __checkReturn efx_rc_t
2554 __in efx_txq_t *etp,
2555 __in size_t pkt_length,
2556 __in unsigned int completed,
2557 __inout unsigned int *addedp);
2559 extern __checkReturn efx_rc_t
2561 __in efx_txq_t *etp,
2562 __in_ecount(n) efx_desc_t *ed,
2563 __in unsigned int n,
2564 __in unsigned int completed,
2565 __inout unsigned int *addedp);
2568 efx_tx_qdesc_dma_create(
2569 __in efx_txq_t *etp,
2570 __in efsys_dma_addr_t addr,
2573 __out efx_desc_t *edp);
2576 efx_tx_qdesc_tso_create(
2577 __in efx_txq_t *etp,
2578 __in uint16_t ipv4_id,
2579 __in uint32_t tcp_seq,
2580 __in uint8_t tcp_flags,
2581 __out efx_desc_t *edp);
2583 /* Number of FATSOv2 option descriptors */
2584 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2586 /* Maximum number of DMA segments per TSO packet (not superframe) */
2587 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2590 efx_tx_qdesc_tso2_create(
2591 __in efx_txq_t *etp,
2592 __in uint16_t ipv4_id,
2593 __in uint16_t outer_ipv4_id,
2594 __in uint32_t tcp_seq,
2595 __in uint16_t tcp_mss,
2596 __out_ecount(count) efx_desc_t *edp,
2600 efx_tx_qdesc_vlantci_create(
2601 __in efx_txq_t *etp,
2603 __out efx_desc_t *edp);
2606 efx_tx_qdesc_checksum_create(
2607 __in efx_txq_t *etp,
2608 __in uint16_t flags,
2609 __out efx_desc_t *edp);
2611 #if EFSYS_OPT_QSTATS
2617 __in efx_nic_t *etp,
2618 __in unsigned int id);
2620 #endif /* EFSYS_OPT_NAMES */
2623 efx_tx_qstats_update(
2624 __in efx_txq_t *etp,
2625 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2627 #endif /* EFSYS_OPT_QSTATS */
2631 __in efx_txq_t *etp);
2636 #if EFSYS_OPT_FILTER
2638 #define EFX_ETHER_TYPE_IPV4 0x0800
2639 #define EFX_ETHER_TYPE_IPV6 0x86DD
2641 #define EFX_IPPROTO_TCP 6
2642 #define EFX_IPPROTO_UDP 17
2643 #define EFX_IPPROTO_GRE 47
2645 /* Use RSS to spread across multiple queues */
2646 #define EFX_FILTER_FLAG_RX_RSS 0x01
2647 /* Enable RX scatter */
2648 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2650 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2651 * May only be set by the filter implementation for each type.
2652 * A removal request will restore the automatic filter in its place.
2654 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2655 /* Filter is for RX */
2656 #define EFX_FILTER_FLAG_RX 0x08
2657 /* Filter is for TX */
2658 #define EFX_FILTER_FLAG_TX 0x10
2659 /* Set match flag on the received packet */
2660 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2661 /* Set match mark on the received packet */
2662 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2664 typedef uint8_t efx_filter_flags_t;
2667 * Flags which specify the fields to match on. The values are the same as in the
2668 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2671 /* Match by remote IP host address */
2672 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2673 /* Match by local IP host address */
2674 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2675 /* Match by remote MAC address */
2676 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2677 /* Match by remote TCP/UDP port */
2678 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2679 /* Match by remote TCP/UDP port */
2680 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2681 /* Match by local TCP/UDP port */
2682 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2683 /* Match by Ether-type */
2684 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2685 /* Match by inner VLAN ID */
2686 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2687 /* Match by outer VLAN ID */
2688 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2689 /* Match by IP transport protocol */
2690 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2691 /* Match by VNI or VSID */
2692 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2693 /* For encapsulated packets, match by inner frame local MAC address */
2694 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2695 /* For encapsulated packets, match all multicast inner frames */
2696 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2697 /* For encapsulated packets, match all unicast inner frames */
2698 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2700 * Match by encap type, this flag does not correspond to
2701 * the MCDI match flags and any unoccupied value may be used
2703 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2704 /* Match otherwise-unmatched multicast and broadcast packets */
2705 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2706 /* Match otherwise-unmatched unicast packets */
2707 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2709 typedef uint32_t efx_filter_match_flags_t;
2711 typedef enum efx_filter_priority_s {
2712 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2713 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2714 * address list or hardware
2715 * requirements. This may only be used
2716 * by the filter implementation for
2718 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2719 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2720 * client (e.g. SR-IOV, HyperV VMQ etc.)
2722 } efx_filter_priority_t;
2725 * FIXME: All these fields are assumed to be in little-endian byte order.
2726 * It may be better for some to be big-endian. See bug42804.
2729 typedef struct efx_filter_spec_s {
2730 efx_filter_match_flags_t efs_match_flags;
2731 uint8_t efs_priority;
2732 efx_filter_flags_t efs_flags;
2733 uint16_t efs_dmaq_id;
2734 uint32_t efs_rss_context;
2736 /* Fields below here are hashed for software filter lookup */
2737 uint16_t efs_outer_vid;
2738 uint16_t efs_inner_vid;
2739 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2740 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2741 uint16_t efs_ether_type;
2742 uint8_t efs_ip_proto;
2743 efx_tunnel_protocol_t efs_encap_type;
2744 uint16_t efs_loc_port;
2745 uint16_t efs_rem_port;
2746 efx_oword_t efs_rem_host;
2747 efx_oword_t efs_loc_host;
2748 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2749 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2750 } efx_filter_spec_t;
2753 /* Default values for use in filter specifications */
2754 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2755 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2757 extern __checkReturn efx_rc_t
2759 __in efx_nic_t *enp);
2763 __in efx_nic_t *enp);
2765 extern __checkReturn efx_rc_t
2767 __in efx_nic_t *enp,
2768 __inout efx_filter_spec_t *spec);
2770 extern __checkReturn efx_rc_t
2772 __in efx_nic_t *enp,
2773 __inout efx_filter_spec_t *spec);
2775 extern __checkReturn efx_rc_t
2777 __in efx_nic_t *enp);
2779 extern __checkReturn efx_rc_t
2780 efx_filter_supported_filters(
2781 __in efx_nic_t *enp,
2782 __out_ecount(buffer_length) uint32_t *buffer,
2783 __in size_t buffer_length,
2784 __out size_t *list_lengthp);
2787 efx_filter_spec_init_rx(
2788 __out efx_filter_spec_t *spec,
2789 __in efx_filter_priority_t priority,
2790 __in efx_filter_flags_t flags,
2791 __in efx_rxq_t *erp);
2794 efx_filter_spec_init_tx(
2795 __out efx_filter_spec_t *spec,
2796 __in efx_txq_t *etp);
2798 extern __checkReturn efx_rc_t
2799 efx_filter_spec_set_ipv4_local(
2800 __inout efx_filter_spec_t *spec,
2803 __in uint16_t port);
2805 extern __checkReturn efx_rc_t
2806 efx_filter_spec_set_ipv4_full(
2807 __inout efx_filter_spec_t *spec,
2809 __in uint32_t lhost,
2810 __in uint16_t lport,
2811 __in uint32_t rhost,
2812 __in uint16_t rport);
2814 extern __checkReturn efx_rc_t
2815 efx_filter_spec_set_eth_local(
2816 __inout efx_filter_spec_t *spec,
2818 __in const uint8_t *addr);
2821 efx_filter_spec_set_ether_type(
2822 __inout efx_filter_spec_t *spec,
2823 __in uint16_t ether_type);
2825 extern __checkReturn efx_rc_t
2826 efx_filter_spec_set_uc_def(
2827 __inout efx_filter_spec_t *spec);
2829 extern __checkReturn efx_rc_t
2830 efx_filter_spec_set_mc_def(
2831 __inout efx_filter_spec_t *spec);
2833 typedef enum efx_filter_inner_frame_match_e {
2834 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2835 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2836 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2837 } efx_filter_inner_frame_match_t;
2839 extern __checkReturn efx_rc_t
2840 efx_filter_spec_set_encap_type(
2841 __inout efx_filter_spec_t *spec,
2842 __in efx_tunnel_protocol_t encap_type,
2843 __in efx_filter_inner_frame_match_t inner_frame_match);
2845 extern __checkReturn efx_rc_t
2846 efx_filter_spec_set_vxlan_full(
2847 __inout efx_filter_spec_t *spec,
2848 __in const uint8_t *vxlan_id,
2849 __in const uint8_t *inner_addr,
2850 __in const uint8_t *outer_addr);
2852 #if EFSYS_OPT_RX_SCALE
2853 extern __checkReturn efx_rc_t
2854 efx_filter_spec_set_rss_context(
2855 __inout efx_filter_spec_t *spec,
2856 __in uint32_t rss_context);
2858 #endif /* EFSYS_OPT_FILTER */
2862 extern __checkReturn uint32_t
2864 __in_ecount(count) uint32_t const *input,
2866 __in uint32_t init);
2868 extern __checkReturn uint32_t
2870 __in_ecount(length) uint8_t const *input,
2872 __in uint32_t init);
2874 #if EFSYS_OPT_LICENSING
2878 typedef struct efx_key_stats_s {
2880 uint32_t eks_invalid;
2881 uint32_t eks_blacklisted;
2882 uint32_t eks_unverifiable;
2883 uint32_t eks_wrong_node;
2884 uint32_t eks_licensed_apps_lo;
2885 uint32_t eks_licensed_apps_hi;
2886 uint32_t eks_licensed_features_lo;
2887 uint32_t eks_licensed_features_hi;
2890 extern __checkReturn efx_rc_t
2892 __in efx_nic_t *enp);
2896 __in efx_nic_t *enp);
2898 extern __checkReturn boolean_t
2899 efx_lic_check_support(
2900 __in efx_nic_t *enp);
2902 extern __checkReturn efx_rc_t
2903 efx_lic_update_licenses(
2904 __in efx_nic_t *enp);
2906 extern __checkReturn efx_rc_t
2907 efx_lic_get_key_stats(
2908 __in efx_nic_t *enp,
2909 __out efx_key_stats_t *ksp);
2911 extern __checkReturn efx_rc_t
2913 __in efx_nic_t *enp,
2914 __in uint64_t app_id,
2915 __out boolean_t *licensedp);
2917 extern __checkReturn efx_rc_t
2919 __in efx_nic_t *enp,
2920 __in size_t buffer_size,
2921 __out uint32_t *typep,
2922 __out size_t *lengthp,
2923 __out_opt uint8_t *bufferp);
2926 extern __checkReturn efx_rc_t
2928 __in efx_nic_t *enp,
2929 __in_bcount(buffer_size)
2931 __in size_t buffer_size,
2932 __out uint32_t *startp);
2934 extern __checkReturn efx_rc_t
2936 __in efx_nic_t *enp,
2937 __in_bcount(buffer_size)
2939 __in size_t buffer_size,
2940 __in uint32_t offset,
2941 __out uint32_t *endp);
2943 extern __checkReturn __success(return != B_FALSE) boolean_t
2945 __in efx_nic_t *enp,
2946 __in_bcount(buffer_size)
2948 __in size_t buffer_size,
2949 __in uint32_t offset,
2950 __out uint32_t *startp,
2951 __out uint32_t *lengthp);
2953 extern __checkReturn __success(return != B_FALSE) boolean_t
2954 efx_lic_validate_key(
2955 __in efx_nic_t *enp,
2956 __in_bcount(length) caddr_t keyp,
2957 __in uint32_t length);
2959 extern __checkReturn efx_rc_t
2961 __in efx_nic_t *enp,
2962 __in_bcount(buffer_size)
2964 __in size_t buffer_size,
2965 __in uint32_t offset,
2966 __in uint32_t length,
2967 __out_bcount_part(key_max_size, *lengthp)
2969 __in size_t key_max_size,
2970 __out uint32_t *lengthp);
2972 extern __checkReturn efx_rc_t
2974 __in efx_nic_t *enp,
2975 __in_bcount(buffer_size)
2977 __in size_t buffer_size,
2978 __in uint32_t offset,
2979 __in_bcount(length) caddr_t keyp,
2980 __in uint32_t length,
2981 __out uint32_t *lengthp);
2983 __checkReturn efx_rc_t
2985 __in efx_nic_t *enp,
2986 __in_bcount(buffer_size)
2988 __in size_t buffer_size,
2989 __in uint32_t offset,
2990 __in uint32_t length,
2992 __out uint32_t *deltap);
2994 extern __checkReturn efx_rc_t
2995 efx_lic_create_partition(
2996 __in efx_nic_t *enp,
2997 __in_bcount(buffer_size)
2999 __in size_t buffer_size);
3001 extern __checkReturn efx_rc_t
3002 efx_lic_finish_partition(
3003 __in efx_nic_t *enp,
3004 __in_bcount(buffer_size)
3006 __in size_t buffer_size);
3008 #endif /* EFSYS_OPT_LICENSING */
3012 #if EFSYS_OPT_TUNNEL
3014 extern __checkReturn efx_rc_t
3016 __in efx_nic_t *enp);
3020 __in efx_nic_t *enp);
3023 * For overlay network encapsulation using UDP, the firmware needs to know
3024 * the configured UDP port for the overlay so it can decode encapsulated
3026 * The UDP port/protocol list is global.
3029 extern __checkReturn efx_rc_t
3030 efx_tunnel_config_udp_add(
3031 __in efx_nic_t *enp,
3032 __in uint16_t port /* host/cpu-endian */,
3033 __in efx_tunnel_protocol_t protocol);
3035 extern __checkReturn efx_rc_t
3036 efx_tunnel_config_udp_remove(
3037 __in efx_nic_t *enp,
3038 __in uint16_t port /* host/cpu-endian */,
3039 __in efx_tunnel_protocol_t protocol);
3042 efx_tunnel_config_clear(
3043 __in efx_nic_t *enp);
3046 * Apply tunnel UDP ports configuration to hardware.
3048 * EAGAIN is returned if hardware will be reset (datapath and management CPU
3051 extern __checkReturn efx_rc_t
3052 efx_tunnel_reconfigure(
3053 __in efx_nic_t *enp);
3055 #endif /* EFSYS_OPT_TUNNEL */
3057 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3060 * Firmware subvariant choice options.
3062 * It may be switched to no Tx checksum if attached drivers are either
3063 * preboot or firmware subvariant aware and no VIS are allocated.
3064 * If may be always switched to default explicitly using set request or
3065 * implicitly if unaware driver is attaching. If switching is done when
3066 * a driver is attached, it gets MC_REBOOT event and should recreate its
3069 * See SF-119419-TC DPDK Firmware Driver Interface and
3070 * SF-109306-TC EF10 for Driver Writers for details.
3072 typedef enum efx_nic_fw_subvariant_e {
3073 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3074 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3075 EFX_NIC_FW_SUBVARIANT_NTYPES
3076 } efx_nic_fw_subvariant_t;
3078 extern __checkReturn efx_rc_t
3079 efx_nic_get_fw_subvariant(
3080 __in efx_nic_t *enp,
3081 __out efx_nic_fw_subvariant_t *subvariantp);
3083 extern __checkReturn efx_rc_t
3084 efx_nic_set_fw_subvariant(
3085 __in efx_nic_t *enp,
3086 __in efx_nic_fw_subvariant_t subvariant);
3088 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3094 #endif /* _SYS_EFX_H */