2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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30 * policies, either expressed or implied, of the FreeBSD Project.
38 #include "efx_annote.h"
40 #include "efx_check.h"
41 #include "efx_phy_ids.h"
47 #define EFX_STATIC_ASSERT(_cond) \
48 ((void)sizeof (char[(_cond) ? 1 : -1]))
50 #define EFX_ARRAY_SIZE(_array) \
51 (sizeof (_array) / sizeof ((_array)[0]))
53 #define EFX_FIELD_OFFSET(_type, _field) \
54 ((size_t)&(((_type *)0)->_field))
56 /* The macro expands divider twice */
57 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
59 /* Round value up to the nearest power of two. */
60 #define EFX_P2ROUNDUP(_type, _value, _align) \
61 (-(-(_type)(_value) & -(_type)(_align)))
65 typedef __success(return == 0) int efx_rc_t;
70 typedef enum efx_family_e {
72 EFX_FAMILY_FALCON, /* Obsolete and not supported */
74 EFX_FAMILY_HUNTINGTON,
80 extern __checkReturn efx_rc_t
84 __out efx_family_t *efp,
85 __out unsigned int *membarp);
88 #define EFX_PCI_VENID_SFC 0x1924
90 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
92 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
93 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
94 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
96 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
97 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
98 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
100 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
101 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
103 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
104 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
105 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
107 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
108 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
109 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
112 #define EFX_MEM_BAR_SIENA 2
114 #define EFX_MEM_BAR_HUNTINGTON_PF 2
115 #define EFX_MEM_BAR_HUNTINGTON_VF 0
117 #define EFX_MEM_BAR_MEDFORD_PF 2
118 #define EFX_MEM_BAR_MEDFORD_VF 0
120 #define EFX_MEM_BAR_MEDFORD2 0
128 EFX_ERR_BUFID_DC_OOB,
141 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
142 extern __checkReturn uint32_t
144 __in uint32_t crc_init,
145 __in_ecount(length) uint8_t const *input,
149 /* Type prototypes */
151 typedef struct efx_rxq_s efx_rxq_t;
155 typedef struct efx_nic_s efx_nic_t;
157 extern __checkReturn efx_rc_t
159 __in efx_family_t family,
160 __in efsys_identifier_t *esip,
161 __in efsys_bar_t *esbp,
162 __in efsys_lock_t *eslp,
163 __deref_out efx_nic_t **enpp);
165 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
166 typedef enum efx_fw_variant_e {
167 EFX_FW_VARIANT_FULL_FEATURED,
168 EFX_FW_VARIANT_LOW_LATENCY,
169 EFX_FW_VARIANT_PACKED_STREAM,
170 EFX_FW_VARIANT_HIGH_TX_RATE,
171 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
172 EFX_FW_VARIANT_RULES_ENGINE,
174 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
177 extern __checkReturn efx_rc_t
180 __in efx_fw_variant_t efv);
182 extern __checkReturn efx_rc_t
184 __in efx_nic_t *enp);
186 extern __checkReturn efx_rc_t
188 __in efx_nic_t *enp);
190 extern __checkReturn boolean_t
191 efx_nic_hw_unavailable(
192 __in efx_nic_t *enp);
195 efx_nic_set_hw_unavailable(
196 __in efx_nic_t *enp);
200 extern __checkReturn efx_rc_t
201 efx_nic_register_test(
202 __in efx_nic_t *enp);
204 #endif /* EFSYS_OPT_DIAG */
208 __in efx_nic_t *enp);
212 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
218 #define EFX_PCIE_LINK_SPEED_GEN1 1
219 #define EFX_PCIE_LINK_SPEED_GEN2 2
220 #define EFX_PCIE_LINK_SPEED_GEN3 3
222 typedef enum efx_pcie_link_performance_e {
223 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
224 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
225 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
226 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
227 } efx_pcie_link_performance_t;
229 extern __checkReturn efx_rc_t
230 efx_nic_calculate_pcie_link_bandwidth(
231 __in uint32_t pcie_link_width,
232 __in uint32_t pcie_link_gen,
233 __out uint32_t *bandwidth_mbpsp);
235 extern __checkReturn efx_rc_t
236 efx_nic_check_pcie_link_speed(
238 __in uint32_t pcie_link_width,
239 __in uint32_t pcie_link_gen,
240 __out efx_pcie_link_performance_t *resultp);
244 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
245 /* Huntington and Medford require MCDIv2 commands */
246 #define WITH_MCDI_V2 1
249 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
251 typedef enum efx_mcdi_exception_e {
252 EFX_MCDI_EXCEPTION_MC_REBOOT,
253 EFX_MCDI_EXCEPTION_MC_BADASSERT,
254 } efx_mcdi_exception_t;
256 #if EFSYS_OPT_MCDI_LOGGING
257 typedef enum efx_log_msg_e {
259 EFX_LOG_MCDI_REQUEST,
260 EFX_LOG_MCDI_RESPONSE,
262 #endif /* EFSYS_OPT_MCDI_LOGGING */
264 typedef struct efx_mcdi_transport_s {
266 efsys_mem_t *emt_dma_mem;
267 void (*emt_execute)(void *, efx_mcdi_req_t *);
268 void (*emt_ev_cpl)(void *);
269 void (*emt_exception)(void *, efx_mcdi_exception_t);
270 #if EFSYS_OPT_MCDI_LOGGING
271 void (*emt_logger)(void *, efx_log_msg_t,
272 void *, size_t, void *, size_t);
273 #endif /* EFSYS_OPT_MCDI_LOGGING */
274 #if EFSYS_OPT_MCDI_PROXY_AUTH
275 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
276 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
277 } efx_mcdi_transport_t;
279 extern __checkReturn efx_rc_t
282 __in const efx_mcdi_transport_t *mtp);
284 extern __checkReturn efx_rc_t
286 __in efx_nic_t *enp);
290 __in efx_nic_t *enp);
293 efx_mcdi_get_timeout(
295 __in efx_mcdi_req_t *emrp,
296 __out uint32_t *usec_timeoutp);
299 efx_mcdi_request_start(
301 __in efx_mcdi_req_t *emrp,
302 __in boolean_t ev_cpl);
304 extern __checkReturn boolean_t
305 efx_mcdi_request_poll(
306 __in efx_nic_t *enp);
308 extern __checkReturn boolean_t
309 efx_mcdi_request_abort(
310 __in efx_nic_t *enp);
314 __in efx_nic_t *enp);
316 #endif /* EFSYS_OPT_MCDI */
320 #define EFX_NINTR_SIENA 1024
322 typedef enum efx_intr_type_e {
323 EFX_INTR_INVALID = 0,
329 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
331 extern __checkReturn efx_rc_t
334 __in efx_intr_type_t type,
335 __in_opt efsys_mem_t *esmp);
339 __in efx_nic_t *enp);
343 __in efx_nic_t *enp);
346 efx_intr_disable_unlocked(
347 __in efx_nic_t *enp);
349 #define EFX_INTR_NEVQS 32
351 extern __checkReturn efx_rc_t
354 __in unsigned int level);
357 efx_intr_status_line(
359 __out boolean_t *fatalp,
360 __out uint32_t *maskp);
363 efx_intr_status_message(
365 __in unsigned int message,
366 __out boolean_t *fatalp);
370 __in efx_nic_t *enp);
374 __in efx_nic_t *enp);
378 #if EFSYS_OPT_MAC_STATS
380 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
381 typedef enum efx_mac_stat_e {
384 EFX_MAC_RX_UNICST_PKTS,
385 EFX_MAC_RX_MULTICST_PKTS,
386 EFX_MAC_RX_BRDCST_PKTS,
387 EFX_MAC_RX_PAUSE_PKTS,
388 EFX_MAC_RX_LE_64_PKTS,
389 EFX_MAC_RX_65_TO_127_PKTS,
390 EFX_MAC_RX_128_TO_255_PKTS,
391 EFX_MAC_RX_256_TO_511_PKTS,
392 EFX_MAC_RX_512_TO_1023_PKTS,
393 EFX_MAC_RX_1024_TO_15XX_PKTS,
394 EFX_MAC_RX_GE_15XX_PKTS,
396 EFX_MAC_RX_FCS_ERRORS,
397 EFX_MAC_RX_DROP_EVENTS,
398 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
399 EFX_MAC_RX_SYMBOL_ERRORS,
400 EFX_MAC_RX_ALIGN_ERRORS,
401 EFX_MAC_RX_INTERNAL_ERRORS,
402 EFX_MAC_RX_JABBER_PKTS,
403 EFX_MAC_RX_LANE0_CHAR_ERR,
404 EFX_MAC_RX_LANE1_CHAR_ERR,
405 EFX_MAC_RX_LANE2_CHAR_ERR,
406 EFX_MAC_RX_LANE3_CHAR_ERR,
407 EFX_MAC_RX_LANE0_DISP_ERR,
408 EFX_MAC_RX_LANE1_DISP_ERR,
409 EFX_MAC_RX_LANE2_DISP_ERR,
410 EFX_MAC_RX_LANE3_DISP_ERR,
411 EFX_MAC_RX_MATCH_FAULT,
412 EFX_MAC_RX_NODESC_DROP_CNT,
415 EFX_MAC_TX_UNICST_PKTS,
416 EFX_MAC_TX_MULTICST_PKTS,
417 EFX_MAC_TX_BRDCST_PKTS,
418 EFX_MAC_TX_PAUSE_PKTS,
419 EFX_MAC_TX_LE_64_PKTS,
420 EFX_MAC_TX_65_TO_127_PKTS,
421 EFX_MAC_TX_128_TO_255_PKTS,
422 EFX_MAC_TX_256_TO_511_PKTS,
423 EFX_MAC_TX_512_TO_1023_PKTS,
424 EFX_MAC_TX_1024_TO_15XX_PKTS,
425 EFX_MAC_TX_GE_15XX_PKTS,
427 EFX_MAC_TX_SGL_COL_PKTS,
428 EFX_MAC_TX_MULT_COL_PKTS,
429 EFX_MAC_TX_EX_COL_PKTS,
430 EFX_MAC_TX_LATE_COL_PKTS,
432 EFX_MAC_TX_EX_DEF_PKTS,
433 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
434 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
435 EFX_MAC_PM_TRUNC_VFIFO_FULL,
436 EFX_MAC_PM_DISCARD_VFIFO_FULL,
437 EFX_MAC_PM_TRUNC_QBB,
438 EFX_MAC_PM_DISCARD_QBB,
439 EFX_MAC_PM_DISCARD_MAPPING,
440 EFX_MAC_RXDP_Q_DISABLED_PKTS,
441 EFX_MAC_RXDP_DI_DROPPED_PKTS,
442 EFX_MAC_RXDP_STREAMING_PKTS,
443 EFX_MAC_RXDP_HLB_FETCH,
444 EFX_MAC_RXDP_HLB_WAIT,
445 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
446 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
447 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
448 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
449 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
450 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
451 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
452 EFX_MAC_VADAPTER_RX_BAD_BYTES,
453 EFX_MAC_VADAPTER_RX_OVERFLOW,
454 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
455 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
456 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
457 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
458 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
459 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
460 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
461 EFX_MAC_VADAPTER_TX_BAD_BYTES,
462 EFX_MAC_VADAPTER_TX_OVERFLOW,
463 EFX_MAC_FEC_UNCORRECTED_ERRORS,
464 EFX_MAC_FEC_CORRECTED_ERRORS,
465 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
466 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
467 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
468 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
469 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
470 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
471 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
472 EFX_MAC_CTPIO_OVERFLOW_FAIL,
473 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
474 EFX_MAC_CTPIO_TIMEOUT_FAIL,
475 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
476 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
477 EFX_MAC_CTPIO_INVALID_WR_FAIL,
478 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
479 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
480 EFX_MAC_CTPIO_RUNT_FALLBACK,
481 EFX_MAC_CTPIO_SUCCESS,
482 EFX_MAC_CTPIO_FALLBACK,
483 EFX_MAC_CTPIO_POISON,
485 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
486 EFX_MAC_RXDP_HLB_IDLE,
487 EFX_MAC_RXDP_HLB_TIMEOUT,
491 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
493 #endif /* EFSYS_OPT_MAC_STATS */
495 typedef enum efx_link_mode_e {
496 EFX_LINK_UNKNOWN = 0,
512 #define EFX_MAC_ADDR_LEN 6
514 #define EFX_VNI_OR_VSID_LEN 3
516 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
518 #define EFX_MAC_MULTICAST_LIST_MAX 256
520 #define EFX_MAC_SDU_MAX 9202
522 #define EFX_MAC_PDU_ADJUSTMENT \
526 + /* bug16011 */ 16) \
528 #define EFX_MAC_PDU(_sdu) \
529 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
532 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
533 * the SDU rounded up slightly.
535 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
537 #define EFX_MAC_PDU_MIN 60
538 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
540 extern __checkReturn efx_rc_t
545 extern __checkReturn efx_rc_t
550 extern __checkReturn efx_rc_t
555 extern __checkReturn efx_rc_t
558 __in boolean_t all_unicst,
559 __in boolean_t mulcst,
560 __in boolean_t all_mulcst,
561 __in boolean_t brdcst);
563 extern __checkReturn efx_rc_t
564 efx_mac_multicast_list_set(
566 __in_ecount(6*count) uint8_t const *addrs,
569 extern __checkReturn efx_rc_t
570 efx_mac_filter_default_rxq_set(
573 __in boolean_t using_rss);
576 efx_mac_filter_default_rxq_clear(
577 __in efx_nic_t *enp);
579 extern __checkReturn efx_rc_t
582 __in boolean_t enabled);
584 extern __checkReturn efx_rc_t
587 __out boolean_t *mac_upp);
589 #define EFX_FCNTL_RESPOND 0x00000001
590 #define EFX_FCNTL_GENERATE 0x00000002
592 extern __checkReturn efx_rc_t
595 __in unsigned int fcntl,
596 __in boolean_t autoneg);
601 __out unsigned int *fcntl_wantedp,
602 __out unsigned int *fcntl_linkp);
605 #if EFSYS_OPT_MAC_STATS
609 extern __checkReturn const char *
612 __in unsigned int id);
614 #endif /* EFSYS_OPT_NAMES */
616 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
618 #define EFX_MAC_STATS_MASK_NPAGES \
619 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
620 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
621 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
624 * Get mask of MAC statistics supported by the hardware.
626 * If mask_size is insufficient to return the mask, EINVAL error is
627 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
628 * (which is sizeof (uint32_t)) is sufficient.
630 extern __checkReturn efx_rc_t
631 efx_mac_stats_get_mask(
633 __out_bcount(mask_size) uint32_t *maskp,
634 __in size_t mask_size);
636 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
637 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
638 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
641 extern __checkReturn efx_rc_t
643 __in efx_nic_t *enp);
646 * Upload mac statistics supported by the hardware into the given buffer.
648 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
649 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
651 * The hardware will only DMA statistics that it understands (of course).
652 * Drivers should not make any assumptions about which statistics are
653 * supported, especially when the statistics are generated by firmware.
655 * Thus, drivers should zero this buffer before use, so that not-understood
656 * statistics read back as zero.
658 extern __checkReturn efx_rc_t
659 efx_mac_stats_upload(
661 __in efsys_mem_t *esmp);
663 extern __checkReturn efx_rc_t
664 efx_mac_stats_periodic(
666 __in efsys_mem_t *esmp,
667 __in uint16_t period_ms,
668 __in boolean_t events);
670 extern __checkReturn efx_rc_t
671 efx_mac_stats_update(
673 __in efsys_mem_t *esmp,
674 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
675 __inout_opt uint32_t *generationp);
677 #endif /* EFSYS_OPT_MAC_STATS */
681 typedef enum efx_mon_type_e {
693 __in efx_nic_t *enp);
695 #endif /* EFSYS_OPT_NAMES */
697 extern __checkReturn efx_rc_t
699 __in efx_nic_t *enp);
701 #if EFSYS_OPT_MON_STATS
703 #define EFX_MON_STATS_PAGE_SIZE 0x100
704 #define EFX_MON_MASK_ELEMENT_SIZE 32
706 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
707 typedef enum efx_mon_stat_e {
708 EFX_MON_STAT_CONTROLLER_TEMP,
709 EFX_MON_STAT_PHY_COMMON_TEMP,
710 EFX_MON_STAT_CONTROLLER_COOLING,
711 EFX_MON_STAT_PHY0_TEMP,
712 EFX_MON_STAT_PHY0_COOLING,
713 EFX_MON_STAT_PHY1_TEMP,
714 EFX_MON_STAT_PHY1_COOLING,
720 EFX_MON_STAT_IN_12V0,
721 EFX_MON_STAT_IN_1V2A,
722 EFX_MON_STAT_IN_VREF,
723 EFX_MON_STAT_OUT_VAOE,
724 EFX_MON_STAT_AOE_TEMP,
725 EFX_MON_STAT_PSU_AOE_TEMP,
726 EFX_MON_STAT_PSU_TEMP,
732 EFX_MON_STAT_IN_VAOE,
733 EFX_MON_STAT_OUT_IAOE,
734 EFX_MON_STAT_IN_IAOE,
735 EFX_MON_STAT_NIC_POWER,
737 EFX_MON_STAT_IN_I0V9,
738 EFX_MON_STAT_IN_I1V2,
739 EFX_MON_STAT_IN_0V9_ADC,
740 EFX_MON_STAT_CONTROLLER_2_TEMP,
741 EFX_MON_STAT_VREG_INTERNAL_TEMP,
742 EFX_MON_STAT_VREG_0V9_TEMP,
743 EFX_MON_STAT_VREG_1V2_TEMP,
744 EFX_MON_STAT_CONTROLLER_VPTAT,
745 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
746 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
747 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
748 EFX_MON_STAT_AMBIENT_TEMP,
749 EFX_MON_STAT_AIRFLOW,
750 EFX_MON_STAT_VDD08D_VSS08D_CSR,
751 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
752 EFX_MON_STAT_HOTPOINT_TEMP,
753 EFX_MON_STAT_PHY_POWER_PORT0,
754 EFX_MON_STAT_PHY_POWER_PORT1,
755 EFX_MON_STAT_MUM_VCC,
756 EFX_MON_STAT_IN_0V9_A,
757 EFX_MON_STAT_IN_I0V9_A,
758 EFX_MON_STAT_VREG_0V9_A_TEMP,
759 EFX_MON_STAT_IN_0V9_B,
760 EFX_MON_STAT_IN_I0V9_B,
761 EFX_MON_STAT_VREG_0V9_B_TEMP,
762 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
763 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
764 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
765 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
766 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
767 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
768 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
769 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
770 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
771 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
772 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
773 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
774 EFX_MON_STAT_SODIMM_VOUT,
775 EFX_MON_STAT_SODIMM_0_TEMP,
776 EFX_MON_STAT_SODIMM_1_TEMP,
777 EFX_MON_STAT_PHY0_VCC,
778 EFX_MON_STAT_PHY1_VCC,
779 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
780 EFX_MON_STAT_BOARD_FRONT_TEMP,
781 EFX_MON_STAT_BOARD_BACK_TEMP,
782 EFX_MON_STAT_IN_I1V8,
783 EFX_MON_STAT_IN_I2V5,
784 EFX_MON_STAT_IN_I3V3,
785 EFX_MON_STAT_IN_I12V0,
787 EFX_MON_STAT_IN_I1V3,
791 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
793 typedef enum efx_mon_stat_state_e {
794 EFX_MON_STAT_STATE_OK = 0,
795 EFX_MON_STAT_STATE_WARNING = 1,
796 EFX_MON_STAT_STATE_FATAL = 2,
797 EFX_MON_STAT_STATE_BROKEN = 3,
798 EFX_MON_STAT_STATE_NO_READING = 4,
799 } efx_mon_stat_state_t;
801 typedef enum efx_mon_stat_unit_e {
802 EFX_MON_STAT_UNIT_UNKNOWN = 0,
803 EFX_MON_STAT_UNIT_BOOL,
804 EFX_MON_STAT_UNIT_TEMP_C,
805 EFX_MON_STAT_UNIT_VOLTAGE_MV,
806 EFX_MON_STAT_UNIT_CURRENT_MA,
807 EFX_MON_STAT_UNIT_POWER_W,
808 EFX_MON_STAT_UNIT_RPM,
810 } efx_mon_stat_unit_t;
812 typedef struct efx_mon_stat_value_s {
814 efx_mon_stat_state_t emsv_state;
815 efx_mon_stat_unit_t emsv_unit;
816 } efx_mon_stat_value_t;
818 typedef struct efx_mon_limit_value_s {
819 uint16_t emlv_warning_min;
820 uint16_t emlv_warning_max;
821 uint16_t emlv_fatal_min;
822 uint16_t emlv_fatal_max;
823 } efx_mon_stat_limits_t;
825 typedef enum efx_mon_stat_portmask_e {
826 EFX_MON_STAT_PORTMAP_NONE = 0,
827 EFX_MON_STAT_PORTMAP_PORT0 = 1,
828 EFX_MON_STAT_PORTMAP_PORT1 = 2,
829 EFX_MON_STAT_PORTMAP_PORT2 = 3,
830 EFX_MON_STAT_PORTMAP_PORT3 = 4,
831 EFX_MON_STAT_PORTMAP_ALL = (-1),
832 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
833 } efx_mon_stat_portmask_t;
840 __in efx_mon_stat_t id);
843 efx_mon_stat_description(
845 __in efx_mon_stat_t id);
847 #endif /* EFSYS_OPT_NAMES */
849 extern __checkReturn boolean_t
850 efx_mon_mcdi_to_efx_stat(
852 __out efx_mon_stat_t *statp);
854 extern __checkReturn boolean_t
855 efx_mon_get_stat_unit(
856 __in efx_mon_stat_t stat,
857 __out efx_mon_stat_unit_t *unitp);
859 extern __checkReturn boolean_t
860 efx_mon_get_stat_portmap(
861 __in efx_mon_stat_t stat,
862 __out efx_mon_stat_portmask_t *maskp);
864 extern __checkReturn efx_rc_t
865 efx_mon_stats_update(
867 __in efsys_mem_t *esmp,
868 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
870 extern __checkReturn efx_rc_t
871 efx_mon_limits_update(
873 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
875 #endif /* EFSYS_OPT_MON_STATS */
879 __in efx_nic_t *enp);
883 extern __checkReturn efx_rc_t
885 __in efx_nic_t *enp);
887 #if EFSYS_OPT_PHY_LED_CONTROL
889 typedef enum efx_phy_led_mode_e {
890 EFX_PHY_LED_DEFAULT = 0,
895 } efx_phy_led_mode_t;
897 extern __checkReturn efx_rc_t
900 __in efx_phy_led_mode_t mode);
902 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
904 extern __checkReturn efx_rc_t
906 __in efx_nic_t *enp);
908 #if EFSYS_OPT_LOOPBACK
910 typedef enum efx_loopback_type_e {
911 EFX_LOOPBACK_OFF = 0,
912 EFX_LOOPBACK_DATA = 1,
913 EFX_LOOPBACK_GMAC = 2,
914 EFX_LOOPBACK_XGMII = 3,
915 EFX_LOOPBACK_XGXS = 4,
916 EFX_LOOPBACK_XAUI = 5,
917 EFX_LOOPBACK_GMII = 6,
918 EFX_LOOPBACK_SGMII = 7,
919 EFX_LOOPBACK_XGBR = 8,
920 EFX_LOOPBACK_XFI = 9,
921 EFX_LOOPBACK_XAUI_FAR = 10,
922 EFX_LOOPBACK_GMII_FAR = 11,
923 EFX_LOOPBACK_SGMII_FAR = 12,
924 EFX_LOOPBACK_XFI_FAR = 13,
925 EFX_LOOPBACK_GPHY = 14,
926 EFX_LOOPBACK_PHY_XS = 15,
927 EFX_LOOPBACK_PCS = 16,
928 EFX_LOOPBACK_PMA_PMD = 17,
929 EFX_LOOPBACK_XPORT = 18,
930 EFX_LOOPBACK_XGMII_WS = 19,
931 EFX_LOOPBACK_XAUI_WS = 20,
932 EFX_LOOPBACK_XAUI_WS_FAR = 21,
933 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
934 EFX_LOOPBACK_GMII_WS = 23,
935 EFX_LOOPBACK_XFI_WS = 24,
936 EFX_LOOPBACK_XFI_WS_FAR = 25,
937 EFX_LOOPBACK_PHYXS_WS = 26,
938 EFX_LOOPBACK_PMA_INT = 27,
939 EFX_LOOPBACK_SD_NEAR = 28,
940 EFX_LOOPBACK_SD_FAR = 29,
941 EFX_LOOPBACK_PMA_INT_WS = 30,
942 EFX_LOOPBACK_SD_FEP2_WS = 31,
943 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
944 EFX_LOOPBACK_SD_FEP_WS = 33,
945 EFX_LOOPBACK_SD_FES_WS = 34,
946 EFX_LOOPBACK_AOE_INT_NEAR = 35,
947 EFX_LOOPBACK_DATA_WS = 36,
948 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
950 } efx_loopback_type_t;
952 typedef enum efx_loopback_kind_e {
953 EFX_LOOPBACK_KIND_OFF = 0,
954 EFX_LOOPBACK_KIND_ALL,
955 EFX_LOOPBACK_KIND_MAC,
956 EFX_LOOPBACK_KIND_PHY,
958 } efx_loopback_kind_t;
962 __in efx_loopback_kind_t loopback_kind,
963 __out efx_qword_t *maskp);
965 extern __checkReturn efx_rc_t
966 efx_port_loopback_set(
968 __in efx_link_mode_t link_mode,
969 __in efx_loopback_type_t type);
973 extern __checkReturn const char *
974 efx_loopback_type_name(
976 __in efx_loopback_type_t type);
978 #endif /* EFSYS_OPT_NAMES */
980 #endif /* EFSYS_OPT_LOOPBACK */
982 extern __checkReturn efx_rc_t
985 __out_opt efx_link_mode_t *link_modep);
989 __in efx_nic_t *enp);
991 typedef enum efx_phy_cap_type_e {
992 EFX_PHY_CAP_INVALID = 0,
999 EFX_PHY_CAP_10000FDX,
1003 EFX_PHY_CAP_40000FDX,
1005 EFX_PHY_CAP_100000FDX,
1006 EFX_PHY_CAP_25000FDX,
1007 EFX_PHY_CAP_50000FDX,
1008 EFX_PHY_CAP_BASER_FEC,
1009 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1011 EFX_PHY_CAP_RS_FEC_REQUESTED,
1012 EFX_PHY_CAP_25G_BASER_FEC,
1013 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1015 } efx_phy_cap_type_t;
1018 #define EFX_PHY_CAP_CURRENT 0x00000000
1019 #define EFX_PHY_CAP_DEFAULT 0x00000001
1020 #define EFX_PHY_CAP_PERM 0x00000002
1023 efx_phy_adv_cap_get(
1024 __in efx_nic_t *enp,
1026 __out uint32_t *maskp);
1028 extern __checkReturn efx_rc_t
1029 efx_phy_adv_cap_set(
1030 __in efx_nic_t *enp,
1031 __in uint32_t mask);
1035 __in efx_nic_t *enp,
1036 __out uint32_t *maskp);
1038 extern __checkReturn efx_rc_t
1040 __in efx_nic_t *enp,
1041 __out uint32_t *ouip);
1043 typedef enum efx_phy_media_type_e {
1044 EFX_PHY_MEDIA_INVALID = 0,
1049 EFX_PHY_MEDIA_SFP_PLUS,
1050 EFX_PHY_MEDIA_BASE_T,
1051 EFX_PHY_MEDIA_QSFP_PLUS,
1052 EFX_PHY_MEDIA_NTYPES
1053 } efx_phy_media_type_t;
1056 * Get the type of medium currently used. If the board has ports for
1057 * modules, a module is present, and we recognise the media type of
1058 * the module, then this will be the media type of the module.
1059 * Otherwise it will be the media type of the port.
1062 efx_phy_media_type_get(
1063 __in efx_nic_t *enp,
1064 __out efx_phy_media_type_t *typep);
1067 * 2-wire device address of the base information in accordance with SFF-8472
1068 * Diagnostic Monitoring Interface for Optical Transceivers section
1069 * 4 Memory Organization.
1071 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1074 * 2-wire device address of the digital diagnostics monitoring interface
1075 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1076 * Transceivers section 4 Memory Organization.
1078 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1081 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1082 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1085 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1088 * Maximum accessible data offset for PHY module information.
1090 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1093 extern __checkReturn efx_rc_t
1094 efx_phy_module_get_info(
1095 __in efx_nic_t *enp,
1096 __in uint8_t dev_addr,
1099 __out_bcount(len) uint8_t *data);
1101 #if EFSYS_OPT_PHY_STATS
1103 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1104 typedef enum efx_phy_stat_e {
1106 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1107 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1108 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1109 EFX_PHY_STAT_PMA_PMD_REV_A,
1110 EFX_PHY_STAT_PMA_PMD_REV_B,
1111 EFX_PHY_STAT_PMA_PMD_REV_C,
1112 EFX_PHY_STAT_PMA_PMD_REV_D,
1113 EFX_PHY_STAT_PCS_LINK_UP,
1114 EFX_PHY_STAT_PCS_RX_FAULT,
1115 EFX_PHY_STAT_PCS_TX_FAULT,
1116 EFX_PHY_STAT_PCS_BER,
1117 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1118 EFX_PHY_STAT_PHY_XS_LINK_UP,
1119 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1120 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1121 EFX_PHY_STAT_PHY_XS_ALIGN,
1122 EFX_PHY_STAT_PHY_XS_SYNC_A,
1123 EFX_PHY_STAT_PHY_XS_SYNC_B,
1124 EFX_PHY_STAT_PHY_XS_SYNC_C,
1125 EFX_PHY_STAT_PHY_XS_SYNC_D,
1126 EFX_PHY_STAT_AN_LINK_UP,
1127 EFX_PHY_STAT_AN_MASTER,
1128 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1129 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1130 EFX_PHY_STAT_CL22EXT_LINK_UP,
1135 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1136 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1137 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1138 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1139 EFX_PHY_STAT_AN_COMPLETE,
1140 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1141 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1142 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1143 EFX_PHY_STAT_PCS_FW_VERSION_0,
1144 EFX_PHY_STAT_PCS_FW_VERSION_1,
1145 EFX_PHY_STAT_PCS_FW_VERSION_2,
1146 EFX_PHY_STAT_PCS_FW_VERSION_3,
1147 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1148 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1149 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1150 EFX_PHY_STAT_PCS_OP_MODE,
1154 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1160 __in efx_nic_t *enp,
1161 __in efx_phy_stat_t stat);
1163 #endif /* EFSYS_OPT_NAMES */
1165 #define EFX_PHY_STATS_SIZE 0x100
1167 extern __checkReturn efx_rc_t
1168 efx_phy_stats_update(
1169 __in efx_nic_t *enp,
1170 __in efsys_mem_t *esmp,
1171 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1173 #endif /* EFSYS_OPT_PHY_STATS */
1178 typedef enum efx_bist_type_e {
1179 EFX_BIST_TYPE_UNKNOWN,
1180 EFX_BIST_TYPE_PHY_NORMAL,
1181 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1182 EFX_BIST_TYPE_PHY_CABLE_LONG,
1183 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1184 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1185 EFX_BIST_TYPE_REG, /* Test the register memories */
1186 EFX_BIST_TYPE_NTYPES,
1189 typedef enum efx_bist_result_e {
1190 EFX_BIST_RESULT_UNKNOWN,
1191 EFX_BIST_RESULT_RUNNING,
1192 EFX_BIST_RESULT_PASSED,
1193 EFX_BIST_RESULT_FAILED,
1194 } efx_bist_result_t;
1196 typedef enum efx_phy_cable_status_e {
1197 EFX_PHY_CABLE_STATUS_OK,
1198 EFX_PHY_CABLE_STATUS_INVALID,
1199 EFX_PHY_CABLE_STATUS_OPEN,
1200 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1201 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1202 EFX_PHY_CABLE_STATUS_BUSY,
1203 } efx_phy_cable_status_t;
1205 typedef enum efx_bist_value_e {
1206 EFX_BIST_PHY_CABLE_LENGTH_A,
1207 EFX_BIST_PHY_CABLE_LENGTH_B,
1208 EFX_BIST_PHY_CABLE_LENGTH_C,
1209 EFX_BIST_PHY_CABLE_LENGTH_D,
1210 EFX_BIST_PHY_CABLE_STATUS_A,
1211 EFX_BIST_PHY_CABLE_STATUS_B,
1212 EFX_BIST_PHY_CABLE_STATUS_C,
1213 EFX_BIST_PHY_CABLE_STATUS_D,
1214 EFX_BIST_FAULT_CODE,
1216 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1222 EFX_BIST_MEM_EXPECT,
1223 EFX_BIST_MEM_ACTUAL,
1225 EFX_BIST_MEM_ECC_PARITY,
1226 EFX_BIST_MEM_ECC_FATAL,
1230 extern __checkReturn efx_rc_t
1231 efx_bist_enable_offline(
1232 __in efx_nic_t *enp);
1234 extern __checkReturn efx_rc_t
1236 __in efx_nic_t *enp,
1237 __in efx_bist_type_t type);
1239 extern __checkReturn efx_rc_t
1241 __in efx_nic_t *enp,
1242 __in efx_bist_type_t type,
1243 __out efx_bist_result_t *resultp,
1244 __out_opt uint32_t *value_maskp,
1245 __out_ecount_opt(count) unsigned long *valuesp,
1250 __in efx_nic_t *enp,
1251 __in efx_bist_type_t type);
1253 #endif /* EFSYS_OPT_BIST */
1255 #define EFX_FEATURE_IPV6 0x00000001
1256 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1257 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1258 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1259 #define EFX_FEATURE_MCDI 0x00000020
1260 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1261 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1262 #define EFX_FEATURE_TURBO 0x00000100
1263 #define EFX_FEATURE_MCDI_DMA 0x00000200
1264 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1265 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1266 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1267 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1268 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1269 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1271 typedef enum efx_tunnel_protocol_e {
1272 EFX_TUNNEL_PROTOCOL_NONE = 0,
1273 EFX_TUNNEL_PROTOCOL_VXLAN,
1274 EFX_TUNNEL_PROTOCOL_GENEVE,
1275 EFX_TUNNEL_PROTOCOL_NVGRE,
1277 } efx_tunnel_protocol_t;
1279 typedef enum efx_vi_window_shift_e {
1280 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1281 EFX_VI_WINDOW_SHIFT_8K = 13,
1282 EFX_VI_WINDOW_SHIFT_16K = 14,
1283 EFX_VI_WINDOW_SHIFT_64K = 16,
1284 } efx_vi_window_shift_t;
1286 typedef struct efx_nic_cfg_s {
1287 uint32_t enc_board_type;
1288 uint32_t enc_phy_type;
1290 char enc_phy_name[21];
1292 char enc_phy_revision[21];
1293 efx_mon_type_t enc_mon_type;
1294 #if EFSYS_OPT_MON_STATS
1295 uint32_t enc_mon_stat_dma_buf_size;
1296 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1298 unsigned int enc_features;
1299 efx_vi_window_shift_t enc_vi_window_shift;
1300 uint8_t enc_mac_addr[6];
1301 uint8_t enc_port; /* PHY port number */
1302 uint32_t enc_intr_vec_base;
1303 uint32_t enc_intr_limit;
1304 uint32_t enc_evq_limit;
1305 uint32_t enc_txq_limit;
1306 uint32_t enc_rxq_limit;
1307 uint32_t enc_txq_max_ndescs;
1308 uint32_t enc_buftbl_limit;
1309 uint32_t enc_piobuf_limit;
1310 uint32_t enc_piobuf_size;
1311 uint32_t enc_piobuf_min_alloc_size;
1312 uint32_t enc_evq_timer_quantum_ns;
1313 uint32_t enc_evq_timer_max_us;
1314 uint32_t enc_clk_mult;
1315 uint32_t enc_rx_prefix_size;
1316 uint32_t enc_rx_buf_align_start;
1317 uint32_t enc_rx_buf_align_end;
1318 #if EFSYS_OPT_RX_SCALE
1319 uint32_t enc_rx_scale_max_exclusive_contexts;
1321 * Mask of supported hash algorithms.
1322 * Hash algorithm types are used as the bit indices.
1324 uint32_t enc_rx_scale_hash_alg_mask;
1326 * Indicates whether port numbers can be included to the
1327 * input data for hash computation.
1329 boolean_t enc_rx_scale_l4_hash_supported;
1330 boolean_t enc_rx_scale_additional_modes_supported;
1331 #endif /* EFSYS_OPT_RX_SCALE */
1332 #if EFSYS_OPT_LOOPBACK
1333 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1334 #endif /* EFSYS_OPT_LOOPBACK */
1335 #if EFSYS_OPT_PHY_FLAGS
1336 uint32_t enc_phy_flags_mask;
1337 #endif /* EFSYS_OPT_PHY_FLAGS */
1338 #if EFSYS_OPT_PHY_LED_CONTROL
1339 uint32_t enc_led_mask;
1340 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1341 #if EFSYS_OPT_PHY_STATS
1342 uint64_t enc_phy_stat_mask;
1343 #endif /* EFSYS_OPT_PHY_STATS */
1345 uint8_t enc_mcdi_mdio_channel;
1346 #if EFSYS_OPT_PHY_STATS
1347 uint32_t enc_mcdi_phy_stat_mask;
1348 #endif /* EFSYS_OPT_PHY_STATS */
1349 #if EFSYS_OPT_MON_STATS
1350 uint32_t *enc_mcdi_sensor_maskp;
1351 uint32_t enc_mcdi_sensor_mask_size;
1352 #endif /* EFSYS_OPT_MON_STATS */
1353 #endif /* EFSYS_OPT_MCDI */
1355 uint32_t enc_bist_mask;
1356 #endif /* EFSYS_OPT_BIST */
1357 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1360 uint32_t enc_privilege_mask;
1361 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1362 boolean_t enc_bug26807_workaround;
1363 boolean_t enc_bug35388_workaround;
1364 boolean_t enc_bug41750_workaround;
1365 boolean_t enc_bug61265_workaround;
1366 boolean_t enc_bug61297_workaround;
1367 boolean_t enc_rx_batching_enabled;
1368 /* Maximum number of descriptors completed in an rx event. */
1369 uint32_t enc_rx_batch_max;
1370 /* Number of rx descriptors the hardware requires for a push. */
1371 uint32_t enc_rx_push_align;
1372 /* Maximum amount of data in DMA descriptor */
1373 uint32_t enc_tx_dma_desc_size_max;
1375 * Boundary which DMA descriptor data must not cross or 0 if no
1378 uint32_t enc_tx_dma_desc_boundary;
1380 * Maximum number of bytes into the packet the TCP header can start for
1381 * the hardware to apply TSO packet edits.
1383 uint32_t enc_tx_tso_tcp_header_offset_limit;
1384 boolean_t enc_fw_assisted_tso_enabled;
1385 boolean_t enc_fw_assisted_tso_v2_enabled;
1386 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1387 /* Number of TSO contexts on the NIC (FATSOv2) */
1388 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1389 boolean_t enc_hw_tx_insert_vlan_enabled;
1390 /* Number of PFs on the NIC */
1391 uint32_t enc_hw_pf_count;
1392 /* Datapath firmware vadapter/vport/vswitch support */
1393 boolean_t enc_datapath_cap_evb;
1394 boolean_t enc_rx_disable_scatter_supported;
1395 boolean_t enc_allow_set_mac_with_installed_filters;
1396 boolean_t enc_enhanced_set_mac_supported;
1397 boolean_t enc_init_evq_v2_supported;
1398 boolean_t enc_rx_packed_stream_supported;
1399 boolean_t enc_rx_var_packed_stream_supported;
1400 boolean_t enc_rx_es_super_buffer_supported;
1401 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1402 boolean_t enc_pm_and_rxdp_counters;
1403 boolean_t enc_mac_stats_40g_tx_size_bins;
1404 uint32_t enc_tunnel_encapsulations_supported;
1406 * NIC global maximum for unique UDP tunnel ports shared by all
1409 uint32_t enc_tunnel_config_udp_entries_max;
1410 /* External port identifier */
1411 uint8_t enc_external_port;
1412 uint32_t enc_mcdi_max_payload_length;
1413 /* VPD may be per-PF or global */
1414 boolean_t enc_vpd_is_global;
1415 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1416 uint32_t enc_required_pcie_bandwidth_mbps;
1417 uint32_t enc_max_pcie_link_gen;
1418 /* Firmware verifies integrity of NVRAM updates */
1419 uint32_t enc_nvram_update_verify_result_supported;
1420 /* Firmware support for extended MAC_STATS buffer */
1421 uint32_t enc_mac_stats_nstats;
1422 boolean_t enc_fec_counters;
1423 boolean_t enc_hlb_counters;
1424 /* Firmware support for "FLAG" and "MARK" filter actions */
1425 boolean_t enc_filter_action_flag_supported;
1426 boolean_t enc_filter_action_mark_supported;
1427 uint32_t enc_filter_action_mark_max;
1430 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1431 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1433 #define EFX_PCI_FUNCTION(_encp) \
1434 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1436 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1438 extern const efx_nic_cfg_t *
1440 __in efx_nic_t *enp);
1442 /* RxDPCPU firmware id values by which FW variant can be identified */
1443 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1444 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1445 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1446 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1447 #define EFX_RXDP_DPDK_FW_ID 0x6
1449 typedef struct efx_nic_fw_info_s {
1450 /* Basic FW version information */
1451 uint16_t enfi_mc_fw_version[4];
1453 * If datapath capabilities can be detected,
1454 * additional FW information is to be shown
1456 boolean_t enfi_dpcpu_fw_ids_valid;
1457 /* Rx and Tx datapath CPU FW IDs */
1458 uint16_t enfi_rx_dpcpu_fw_id;
1459 uint16_t enfi_tx_dpcpu_fw_id;
1460 } efx_nic_fw_info_t;
1462 extern __checkReturn efx_rc_t
1463 efx_nic_get_fw_version(
1464 __in efx_nic_t *enp,
1465 __out efx_nic_fw_info_t *enfip);
1467 /* Driver resource limits (minimum required/maximum usable). */
1468 typedef struct efx_drv_limits_s {
1469 uint32_t edl_min_evq_count;
1470 uint32_t edl_max_evq_count;
1472 uint32_t edl_min_rxq_count;
1473 uint32_t edl_max_rxq_count;
1475 uint32_t edl_min_txq_count;
1476 uint32_t edl_max_txq_count;
1478 /* PIO blocks (sub-allocated from piobuf) */
1479 uint32_t edl_min_pio_alloc_size;
1480 uint32_t edl_max_pio_alloc_count;
1483 extern __checkReturn efx_rc_t
1484 efx_nic_set_drv_limits(
1485 __inout efx_nic_t *enp,
1486 __in efx_drv_limits_t *edlp);
1488 typedef enum efx_nic_region_e {
1489 EFX_REGION_VI, /* Memory BAR UC mapping */
1490 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1493 extern __checkReturn efx_rc_t
1494 efx_nic_get_bar_region(
1495 __in efx_nic_t *enp,
1496 __in efx_nic_region_t region,
1497 __out uint32_t *offsetp,
1498 __out size_t *sizep);
1500 extern __checkReturn efx_rc_t
1501 efx_nic_get_vi_pool(
1502 __in efx_nic_t *enp,
1503 __out uint32_t *evq_countp,
1504 __out uint32_t *rxq_countp,
1505 __out uint32_t *txq_countp);
1510 typedef enum efx_vpd_tag_e {
1517 typedef uint16_t efx_vpd_keyword_t;
1519 typedef struct efx_vpd_value_s {
1520 efx_vpd_tag_t evv_tag;
1521 efx_vpd_keyword_t evv_keyword;
1523 uint8_t evv_value[0x100];
1527 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1529 extern __checkReturn efx_rc_t
1531 __in efx_nic_t *enp);
1533 extern __checkReturn efx_rc_t
1535 __in efx_nic_t *enp,
1536 __out size_t *sizep);
1538 extern __checkReturn efx_rc_t
1540 __in efx_nic_t *enp,
1541 __out_bcount(size) caddr_t data,
1544 extern __checkReturn efx_rc_t
1546 __in efx_nic_t *enp,
1547 __in_bcount(size) caddr_t data,
1550 extern __checkReturn efx_rc_t
1552 __in efx_nic_t *enp,
1553 __in_bcount(size) caddr_t data,
1556 extern __checkReturn efx_rc_t
1558 __in efx_nic_t *enp,
1559 __in_bcount(size) caddr_t data,
1561 __inout efx_vpd_value_t *evvp);
1563 extern __checkReturn efx_rc_t
1565 __in efx_nic_t *enp,
1566 __inout_bcount(size) caddr_t data,
1568 __in efx_vpd_value_t *evvp);
1570 extern __checkReturn efx_rc_t
1572 __in efx_nic_t *enp,
1573 __inout_bcount(size) caddr_t data,
1575 __out efx_vpd_value_t *evvp,
1576 __inout unsigned int *contp);
1578 extern __checkReturn efx_rc_t
1580 __in efx_nic_t *enp,
1581 __in_bcount(size) caddr_t data,
1586 __in efx_nic_t *enp);
1588 #endif /* EFSYS_OPT_VPD */
1594 typedef enum efx_nvram_type_e {
1595 EFX_NVRAM_INVALID = 0,
1597 EFX_NVRAM_BOOTROM_CFG,
1598 EFX_NVRAM_MC_FIRMWARE,
1599 EFX_NVRAM_MC_GOLDEN,
1605 EFX_NVRAM_FPGA_BACKUP,
1606 EFX_NVRAM_DYNAMIC_CFG,
1609 EFX_NVRAM_MUM_FIRMWARE,
1610 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1611 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1615 extern __checkReturn efx_rc_t
1617 __in efx_nic_t *enp);
1621 extern __checkReturn efx_rc_t
1623 __in efx_nic_t *enp);
1625 #endif /* EFSYS_OPT_DIAG */
1627 extern __checkReturn efx_rc_t
1629 __in efx_nic_t *enp,
1630 __in efx_nvram_type_t type,
1631 __out size_t *sizep);
1633 extern __checkReturn efx_rc_t
1635 __in efx_nic_t *enp,
1636 __in efx_nvram_type_t type,
1637 __out_opt size_t *pref_chunkp);
1639 extern __checkReturn efx_rc_t
1640 efx_nvram_rw_finish(
1641 __in efx_nic_t *enp,
1642 __in efx_nvram_type_t type,
1643 __out_opt uint32_t *verify_resultp);
1645 extern __checkReturn efx_rc_t
1646 efx_nvram_get_version(
1647 __in efx_nic_t *enp,
1648 __in efx_nvram_type_t type,
1649 __out uint32_t *subtypep,
1650 __out_ecount(4) uint16_t version[4]);
1652 extern __checkReturn efx_rc_t
1653 efx_nvram_read_chunk(
1654 __in efx_nic_t *enp,
1655 __in efx_nvram_type_t type,
1656 __in unsigned int offset,
1657 __out_bcount(size) caddr_t data,
1660 extern __checkReturn efx_rc_t
1661 efx_nvram_read_backup(
1662 __in efx_nic_t *enp,
1663 __in efx_nvram_type_t type,
1664 __in unsigned int offset,
1665 __out_bcount(size) caddr_t data,
1668 extern __checkReturn efx_rc_t
1669 efx_nvram_set_version(
1670 __in efx_nic_t *enp,
1671 __in efx_nvram_type_t type,
1672 __in_ecount(4) uint16_t version[4]);
1674 extern __checkReturn efx_rc_t
1676 __in efx_nic_t *enp,
1677 __in efx_nvram_type_t type,
1678 __in_bcount(partn_size) caddr_t partn_data,
1679 __in size_t partn_size);
1681 extern __checkReturn efx_rc_t
1683 __in efx_nic_t *enp,
1684 __in efx_nvram_type_t type);
1686 extern __checkReturn efx_rc_t
1687 efx_nvram_write_chunk(
1688 __in efx_nic_t *enp,
1689 __in efx_nvram_type_t type,
1690 __in unsigned int offset,
1691 __in_bcount(size) caddr_t data,
1696 __in efx_nic_t *enp);
1698 #endif /* EFSYS_OPT_NVRAM */
1700 #if EFSYS_OPT_BOOTCFG
1702 /* Report size and offset of bootcfg sector in NVRAM partition. */
1703 extern __checkReturn efx_rc_t
1704 efx_bootcfg_sector_info(
1705 __in efx_nic_t *enp,
1707 __out_opt uint32_t *sector_countp,
1708 __out size_t *offsetp,
1709 __out size_t *max_sizep);
1712 * Copy bootcfg sector data to a target buffer which may differ in size.
1713 * Optionally corrects format errors in source buffer.
1716 efx_bootcfg_copy_sector(
1717 __in efx_nic_t *enp,
1718 __inout_bcount(sector_length)
1720 __in size_t sector_length,
1721 __out_bcount(data_size) uint8_t *data,
1722 __in size_t data_size,
1723 __in boolean_t handle_format_errors);
1727 __in efx_nic_t *enp,
1728 __out_bcount(size) uint8_t *data,
1733 __in efx_nic_t *enp,
1734 __in_bcount(size) uint8_t *data,
1739 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1740 * (see https://tools.ietf.org/html/rfc1533)
1742 * Summarising the format: the buffer is a sequence of options. All options
1743 * begin with a tag octet, which uniquely identifies the option. Fixed-
1744 * length options without data consist of only a tag octet. Only options PAD
1745 * (0) and END (255) are fixed length. All other options are variable-length
1746 * with a length octet following the tag octet. The value of the length
1747 * octet does not include the two octets specifying the tag and length. The
1748 * length octet is followed by "length" octets of data.
1750 * Option data may be a sequence of sub-options in the same format. The data
1751 * content of the encapsulating option is one or more encapsulated sub-options,
1752 * with no terminating END tag is required.
1754 * To be valid, the top-level sequence of options should be terminated by an
1755 * END tag. The buffer should be padded with the PAD byte.
1757 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1758 * checksum octet. The full buffer (including after the END tag) contributes
1759 * to the checksum, hence the need to fill the buffer to the end with PAD.
1762 #define EFX_DHCP_END ((uint8_t)0xff)
1763 #define EFX_DHCP_PAD ((uint8_t)0)
1765 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1766 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1768 extern __checkReturn uint8_t
1770 __in_bcount(size) uint8_t const *data,
1773 extern __checkReturn efx_rc_t
1775 __in_bcount(size) uint8_t const *data,
1777 __out_opt size_t *usedp);
1779 extern __checkReturn efx_rc_t
1781 __in_bcount(buffer_length) uint8_t *bufferp,
1782 __in size_t buffer_length,
1784 __deref_out uint8_t **valuepp,
1785 __out size_t *value_lengthp);
1787 extern __checkReturn efx_rc_t
1789 __in_bcount(buffer_length) uint8_t *bufferp,
1790 __in size_t buffer_length,
1791 __deref_out uint8_t **endpp);
1794 extern __checkReturn efx_rc_t
1795 efx_dhcp_delete_tag(
1796 __inout_bcount(buffer_length) uint8_t *bufferp,
1797 __in size_t buffer_length,
1800 extern __checkReturn efx_rc_t
1802 __inout_bcount(buffer_length) uint8_t *bufferp,
1803 __in size_t buffer_length,
1805 __in_bcount_opt(value_length) uint8_t *valuep,
1806 __in size_t value_length);
1808 extern __checkReturn efx_rc_t
1809 efx_dhcp_update_tag(
1810 __inout_bcount(buffer_length) uint8_t *bufferp,
1811 __in size_t buffer_length,
1813 __in uint8_t *value_locationp,
1814 __in_bcount_opt(value_length) uint8_t *valuep,
1815 __in size_t value_length);
1818 #endif /* EFSYS_OPT_BOOTCFG */
1820 #if EFSYS_OPT_IMAGE_LAYOUT
1822 #include "ef10_signed_image_layout.h"
1825 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1828 * The image header format is extensible. However, older drivers require an
1829 * exact match of image header version and header length when validating and
1830 * writing firmware images.
1832 * To avoid breaking backward compatibility, we use the upper bits of the
1833 * controller version fields to contain an extra version number used for
1834 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1835 * version). See bug39254 and SF-102785-PS for details.
1837 typedef struct efx_image_header_s {
1839 uint32_t eih_version;
1841 uint32_t eih_subtype;
1842 uint32_t eih_code_size;
1845 uint32_t eih_controller_version_min;
1847 uint16_t eih_controller_version_min_short;
1848 uint8_t eih_extra_version_a;
1849 uint8_t eih_extra_version_b;
1853 uint32_t eih_controller_version_max;
1855 uint16_t eih_controller_version_max_short;
1856 uint8_t eih_extra_version_c;
1857 uint8_t eih_extra_version_d;
1860 uint16_t eih_code_version_a;
1861 uint16_t eih_code_version_b;
1862 uint16_t eih_code_version_c;
1863 uint16_t eih_code_version_d;
1864 } efx_image_header_t;
1866 #define EFX_IMAGE_HEADER_SIZE (40)
1867 #define EFX_IMAGE_HEADER_VERSION (4)
1868 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1871 typedef struct efx_image_trailer_s {
1873 } efx_image_trailer_t;
1875 #define EFX_IMAGE_TRAILER_SIZE (4)
1877 typedef enum efx_image_format_e {
1878 EFX_IMAGE_FORMAT_NO_IMAGE,
1879 EFX_IMAGE_FORMAT_INVALID,
1880 EFX_IMAGE_FORMAT_UNSIGNED,
1881 EFX_IMAGE_FORMAT_SIGNED,
1882 } efx_image_format_t;
1884 typedef struct efx_image_info_s {
1885 efx_image_format_t eii_format;
1886 uint8_t * eii_imagep;
1887 size_t eii_image_size;
1888 efx_image_header_t * eii_headerp;
1891 extern __checkReturn efx_rc_t
1892 efx_check_reflash_image(
1894 __in uint32_t buffer_size,
1895 __out efx_image_info_t *infop);
1897 extern __checkReturn efx_rc_t
1898 efx_build_signed_image_write_buffer(
1899 __out_bcount(buffer_size)
1901 __in uint32_t buffer_size,
1902 __in efx_image_info_t *infop,
1903 __out efx_image_header_t **headerpp);
1905 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1909 typedef enum efx_pattern_type_t {
1910 EFX_PATTERN_BYTE_INCREMENT = 0,
1911 EFX_PATTERN_ALL_THE_SAME,
1912 EFX_PATTERN_BIT_ALTERNATE,
1913 EFX_PATTERN_BYTE_ALTERNATE,
1914 EFX_PATTERN_BYTE_CHANGING,
1915 EFX_PATTERN_BIT_SWEEP,
1917 } efx_pattern_type_t;
1920 (*efx_sram_pattern_fn_t)(
1922 __in boolean_t negate,
1923 __out efx_qword_t *eqp);
1925 extern __checkReturn efx_rc_t
1927 __in efx_nic_t *enp,
1928 __in efx_pattern_type_t type);
1930 #endif /* EFSYS_OPT_DIAG */
1932 extern __checkReturn efx_rc_t
1933 efx_sram_buf_tbl_set(
1934 __in efx_nic_t *enp,
1936 __in efsys_mem_t *esmp,
1940 efx_sram_buf_tbl_clear(
1941 __in efx_nic_t *enp,
1945 #define EFX_BUF_TBL_SIZE 0x20000
1947 #define EFX_BUF_SIZE 4096
1951 typedef struct efx_evq_s efx_evq_t;
1953 #if EFSYS_OPT_QSTATS
1955 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1956 typedef enum efx_ev_qstat_e {
1962 EV_RX_PAUSE_FRM_ERR,
1963 EV_RX_BUF_OWNER_ID_ERR,
1964 EV_RX_IPV4_HDR_CHKSUM_ERR,
1965 EV_RX_TCP_UDP_CHKSUM_ERR,
1969 EV_RX_MCAST_HASH_MATCH,
1986 EV_DRIVER_SRM_UPD_DONE,
1987 EV_DRIVER_TX_DESCQ_FLS_DONE,
1988 EV_DRIVER_RX_DESCQ_FLS_DONE,
1989 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1990 EV_DRIVER_RX_DSC_ERROR,
1991 EV_DRIVER_TX_DSC_ERROR,
1997 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1999 #endif /* EFSYS_OPT_QSTATS */
2001 extern __checkReturn efx_rc_t
2003 __in efx_nic_t *enp);
2007 __in efx_nic_t *enp);
2009 #define EFX_EVQ_MAXNEVS 32768
2010 #define EFX_EVQ_MINNEVS 512
2012 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
2013 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
2015 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2016 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2017 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2018 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2020 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2021 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2022 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2024 extern __checkReturn efx_rc_t
2026 __in efx_nic_t *enp,
2027 __in unsigned int index,
2028 __in efsys_mem_t *esmp,
2032 __in uint32_t flags,
2033 __deref_out efx_evq_t **eepp);
2037 __in efx_evq_t *eep,
2038 __in uint16_t data);
2040 typedef __checkReturn boolean_t
2041 (*efx_initialized_ev_t)(
2042 __in_opt void *arg);
2044 #define EFX_PKT_UNICAST 0x0004
2045 #define EFX_PKT_START 0x0008
2047 #define EFX_PKT_VLAN_TAGGED 0x0010
2048 #define EFX_CKSUM_TCPUDP 0x0020
2049 #define EFX_CKSUM_IPV4 0x0040
2050 #define EFX_PKT_CONT 0x0080
2052 #define EFX_CHECK_VLAN 0x0100
2053 #define EFX_PKT_TCP 0x0200
2054 #define EFX_PKT_UDP 0x0400
2055 #define EFX_PKT_IPV4 0x0800
2057 #define EFX_PKT_IPV6 0x1000
2058 #define EFX_PKT_PREFIX_LEN 0x2000
2059 #define EFX_ADDR_MISMATCH 0x4000
2060 #define EFX_DISCARD 0x8000
2063 * The following flags are used only for packed stream
2064 * mode. The values for the flags are reused to fit into 16 bit,
2065 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2066 * packed stream mode
2068 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2069 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2072 #define EFX_EV_RX_NLABELS 32
2073 #define EFX_EV_TX_NLABELS 32
2075 typedef __checkReturn boolean_t
2078 __in uint32_t label,
2081 __in uint16_t flags);
2083 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2086 * Packed stream mode is documented in SF-112241-TC.
2087 * The general idea is that, instead of putting each incoming
2088 * packet into a separate buffer which is specified in a RX
2089 * descriptor, a large buffer is provided to the hardware and
2090 * packets are put there in a continuous stream.
2091 * The main advantage of such an approach is that RX queue refilling
2092 * happens much less frequently.
2094 * Equal stride packed stream mode is documented in SF-119419-TC.
2095 * The general idea is to utilize advantages of the packed stream,
2096 * but avoid indirection in packets representation.
2097 * The main advantage of such an approach is that RX queue refilling
2098 * happens much less frequently and packets buffers are independent
2099 * from upper layers point of view.
2102 typedef __checkReturn boolean_t
2105 __in uint32_t label,
2107 __in uint32_t pkt_count,
2108 __in uint16_t flags);
2112 typedef __checkReturn boolean_t
2115 __in uint32_t label,
2118 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2119 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2120 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2121 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2122 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2123 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2124 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2125 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2126 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2128 typedef __checkReturn boolean_t
2129 (*efx_exception_ev_t)(
2131 __in uint32_t label,
2132 __in uint32_t data);
2134 typedef __checkReturn boolean_t
2135 (*efx_rxq_flush_done_ev_t)(
2137 __in uint32_t rxq_index);
2139 typedef __checkReturn boolean_t
2140 (*efx_rxq_flush_failed_ev_t)(
2142 __in uint32_t rxq_index);
2144 typedef __checkReturn boolean_t
2145 (*efx_txq_flush_done_ev_t)(
2147 __in uint32_t txq_index);
2149 typedef __checkReturn boolean_t
2150 (*efx_software_ev_t)(
2152 __in uint16_t magic);
2154 typedef __checkReturn boolean_t
2157 __in uint32_t code);
2159 #define EFX_SRAM_CLEAR 0
2160 #define EFX_SRAM_UPDATE 1
2161 #define EFX_SRAM_ILLEGAL_CLEAR 2
2163 typedef __checkReturn boolean_t
2164 (*efx_wake_up_ev_t)(
2166 __in uint32_t label);
2168 typedef __checkReturn boolean_t
2171 __in uint32_t label);
2173 typedef __checkReturn boolean_t
2174 (*efx_link_change_ev_t)(
2176 __in efx_link_mode_t link_mode);
2178 #if EFSYS_OPT_MON_STATS
2180 typedef __checkReturn boolean_t
2181 (*efx_monitor_ev_t)(
2183 __in efx_mon_stat_t id,
2184 __in efx_mon_stat_value_t value);
2186 #endif /* EFSYS_OPT_MON_STATS */
2188 #if EFSYS_OPT_MAC_STATS
2190 typedef __checkReturn boolean_t
2191 (*efx_mac_stats_ev_t)(
2193 __in uint32_t generation);
2195 #endif /* EFSYS_OPT_MAC_STATS */
2197 typedef struct efx_ev_callbacks_s {
2198 efx_initialized_ev_t eec_initialized;
2200 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2201 efx_rx_ps_ev_t eec_rx_ps;
2204 efx_exception_ev_t eec_exception;
2205 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2206 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2207 efx_txq_flush_done_ev_t eec_txq_flush_done;
2208 efx_software_ev_t eec_software;
2209 efx_sram_ev_t eec_sram;
2210 efx_wake_up_ev_t eec_wake_up;
2211 efx_timer_ev_t eec_timer;
2212 efx_link_change_ev_t eec_link_change;
2213 #if EFSYS_OPT_MON_STATS
2214 efx_monitor_ev_t eec_monitor;
2215 #endif /* EFSYS_OPT_MON_STATS */
2216 #if EFSYS_OPT_MAC_STATS
2217 efx_mac_stats_ev_t eec_mac_stats;
2218 #endif /* EFSYS_OPT_MAC_STATS */
2219 } efx_ev_callbacks_t;
2221 extern __checkReturn boolean_t
2223 __in efx_evq_t *eep,
2224 __in unsigned int count);
2226 #if EFSYS_OPT_EV_PREFETCH
2230 __in efx_evq_t *eep,
2231 __in unsigned int count);
2233 #endif /* EFSYS_OPT_EV_PREFETCH */
2237 __in efx_evq_t *eep,
2238 __inout unsigned int *countp,
2239 __in const efx_ev_callbacks_t *eecp,
2240 __in_opt void *arg);
2242 extern __checkReturn efx_rc_t
2243 efx_ev_usecs_to_ticks(
2244 __in efx_nic_t *enp,
2245 __in unsigned int usecs,
2246 __out unsigned int *ticksp);
2248 extern __checkReturn efx_rc_t
2250 __in efx_evq_t *eep,
2251 __in unsigned int us);
2253 extern __checkReturn efx_rc_t
2255 __in efx_evq_t *eep,
2256 __in unsigned int count);
2258 #if EFSYS_OPT_QSTATS
2264 __in efx_nic_t *enp,
2265 __in unsigned int id);
2267 #endif /* EFSYS_OPT_NAMES */
2270 efx_ev_qstats_update(
2271 __in efx_evq_t *eep,
2272 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2274 #endif /* EFSYS_OPT_QSTATS */
2278 __in efx_evq_t *eep);
2282 extern __checkReturn efx_rc_t
2284 __inout efx_nic_t *enp);
2288 __in efx_nic_t *enp);
2290 #if EFSYS_OPT_RX_SCATTER
2291 __checkReturn efx_rc_t
2292 efx_rx_scatter_enable(
2293 __in efx_nic_t *enp,
2294 __in unsigned int buf_size);
2295 #endif /* EFSYS_OPT_RX_SCATTER */
2297 /* Handle to represent use of the default RSS context. */
2298 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2300 #if EFSYS_OPT_RX_SCALE
2302 typedef enum efx_rx_hash_alg_e {
2303 EFX_RX_HASHALG_LFSR = 0,
2304 EFX_RX_HASHALG_TOEPLITZ,
2305 EFX_RX_HASHALG_PACKED_STREAM,
2307 } efx_rx_hash_alg_t;
2310 * Legacy hash type flags.
2312 * They represent standard tuples for distinct traffic classes.
2314 #define EFX_RX_HASH_IPV4 (1U << 0)
2315 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2316 #define EFX_RX_HASH_IPV6 (1U << 2)
2317 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2319 #define EFX_RX_HASH_LEGACY_MASK \
2320 (EFX_RX_HASH_IPV4 | \
2321 EFX_RX_HASH_TCPIPV4 | \
2322 EFX_RX_HASH_IPV6 | \
2323 EFX_RX_HASH_TCPIPV6)
2326 * The type of the argument used by efx_rx_scale_mode_set() to
2327 * provide a means for the client drivers to configure hashing.
2329 * A properly constructed value can either be:
2330 * - a combination of legacy flags
2331 * - a combination of EFX_RX_HASH() flags
2333 typedef uint32_t efx_rx_hash_type_t;
2335 typedef enum efx_rx_hash_support_e {
2336 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2337 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2338 } efx_rx_hash_support_t;
2340 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2341 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2342 #define EFX_MAXRSS 64 /* RX indirection entry range */
2343 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2345 typedef enum efx_rx_scale_context_type_e {
2346 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2347 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2348 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2349 } efx_rx_scale_context_type_t;
2352 * Traffic classes eligible for hash computation.
2354 * Select packet headers used in computing the receive hash.
2355 * This uses the same encoding as the RSS_MODES field of
2356 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2358 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2359 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2360 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2361 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2362 #define EFX_RX_CLASS_IPV4_LBN 16
2363 #define EFX_RX_CLASS_IPV4_WIDTH 4
2364 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2365 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2366 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2367 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2368 #define EFX_RX_CLASS_IPV6_LBN 28
2369 #define EFX_RX_CLASS_IPV6_WIDTH 4
2371 #define EFX_RX_NCLASSES 6
2374 * Ancillary flags used to construct generic hash tuples.
2375 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2377 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2378 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2379 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2380 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2383 * Generic hash tuples.
2385 * They express combinations of packet fields
2386 * which can contribute to the hash value for
2387 * a particular traffic class.
2389 #define EFX_RX_CLASS_HASH_DISABLE 0
2391 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2392 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2394 #define EFX_RX_CLASS_HASH_2TUPLE \
2395 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2396 EFX_RX_CLASS_HASH_DST_ADDR)
2398 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2399 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2400 EFX_RX_CLASS_HASH_SRC_PORT)
2402 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2403 (EFX_RX_CLASS_HASH_DST_ADDR | \
2404 EFX_RX_CLASS_HASH_DST_PORT)
2406 #define EFX_RX_CLASS_HASH_4TUPLE \
2407 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2408 EFX_RX_CLASS_HASH_DST_ADDR | \
2409 EFX_RX_CLASS_HASH_SRC_PORT | \
2410 EFX_RX_CLASS_HASH_DST_PORT)
2412 #define EFX_RX_CLASS_HASH_NTUPLES 7
2415 * Hash flag constructor.
2417 * Resulting flags encode hash tuples for specific traffic classes.
2418 * The client drivers are encouraged to use these flags to form
2419 * a hash type value.
2421 #define EFX_RX_HASH(_class, _tuple) \
2422 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2423 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2426 * The maximum number of EFX_RX_HASH() flags.
2428 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2430 extern __checkReturn efx_rc_t
2431 efx_rx_scale_hash_flags_get(
2432 __in efx_nic_t *enp,
2433 __in efx_rx_hash_alg_t hash_alg,
2434 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2435 __in unsigned int max_nflags,
2436 __out unsigned int *nflagsp);
2438 extern __checkReturn efx_rc_t
2439 efx_rx_hash_default_support_get(
2440 __in efx_nic_t *enp,
2441 __out efx_rx_hash_support_t *supportp);
2444 extern __checkReturn efx_rc_t
2445 efx_rx_scale_default_support_get(
2446 __in efx_nic_t *enp,
2447 __out efx_rx_scale_context_type_t *typep);
2449 extern __checkReturn efx_rc_t
2450 efx_rx_scale_context_alloc(
2451 __in efx_nic_t *enp,
2452 __in efx_rx_scale_context_type_t type,
2453 __in uint32_t num_queues,
2454 __out uint32_t *rss_contextp);
2456 extern __checkReturn efx_rc_t
2457 efx_rx_scale_context_free(
2458 __in efx_nic_t *enp,
2459 __in uint32_t rss_context);
2461 extern __checkReturn efx_rc_t
2462 efx_rx_scale_mode_set(
2463 __in efx_nic_t *enp,
2464 __in uint32_t rss_context,
2465 __in efx_rx_hash_alg_t alg,
2466 __in efx_rx_hash_type_t type,
2467 __in boolean_t insert);
2469 extern __checkReturn efx_rc_t
2470 efx_rx_scale_tbl_set(
2471 __in efx_nic_t *enp,
2472 __in uint32_t rss_context,
2473 __in_ecount(n) unsigned int *table,
2476 extern __checkReturn efx_rc_t
2477 efx_rx_scale_key_set(
2478 __in efx_nic_t *enp,
2479 __in uint32_t rss_context,
2480 __in_ecount(n) uint8_t *key,
2483 extern __checkReturn uint32_t
2484 efx_pseudo_hdr_hash_get(
2485 __in efx_rxq_t *erp,
2486 __in efx_rx_hash_alg_t func,
2487 __in uint8_t *buffer);
2489 #endif /* EFSYS_OPT_RX_SCALE */
2491 extern __checkReturn efx_rc_t
2492 efx_pseudo_hdr_pkt_length_get(
2493 __in efx_rxq_t *erp,
2494 __in uint8_t *buffer,
2495 __out uint16_t *pkt_lengthp);
2497 #define EFX_RXQ_MAXNDESCS 4096
2498 #define EFX_RXQ_MINNDESCS 512
2500 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2501 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2502 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2503 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2505 typedef enum efx_rxq_type_e {
2506 EFX_RXQ_TYPE_DEFAULT,
2507 EFX_RXQ_TYPE_PACKED_STREAM,
2508 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2513 * Dummy flag to be used instead of 0 to make it clear that the argument
2514 * is receive queue flags.
2516 #define EFX_RXQ_FLAG_NONE 0x0
2517 #define EFX_RXQ_FLAG_SCATTER 0x1
2519 * If tunnels are supported and Rx event can provide information about
2520 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2521 * full-feature firmware variant running), outer classes are requested by
2522 * default. However, if the driver supports tunnels, the flag allows to
2523 * request inner classes which are required to be able to interpret inner
2524 * Rx checksum offload results.
2526 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2528 extern __checkReturn efx_rc_t
2530 __in efx_nic_t *enp,
2531 __in unsigned int index,
2532 __in unsigned int label,
2533 __in efx_rxq_type_t type,
2534 __in efsys_mem_t *esmp,
2537 __in unsigned int flags,
2538 __in efx_evq_t *eep,
2539 __deref_out efx_rxq_t **erpp);
2541 #if EFSYS_OPT_RX_PACKED_STREAM
2543 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2544 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2545 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2546 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2547 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2549 extern __checkReturn efx_rc_t
2550 efx_rx_qcreate_packed_stream(
2551 __in efx_nic_t *enp,
2552 __in unsigned int index,
2553 __in unsigned int label,
2554 __in uint32_t ps_buf_size,
2555 __in efsys_mem_t *esmp,
2557 __in efx_evq_t *eep,
2558 __deref_out efx_rxq_t **erpp);
2562 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2564 /* Maximum head-of-line block timeout in nanoseconds */
2565 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2567 extern __checkReturn efx_rc_t
2568 efx_rx_qcreate_es_super_buffer(
2569 __in efx_nic_t *enp,
2570 __in unsigned int index,
2571 __in unsigned int label,
2572 __in uint32_t n_bufs_per_desc,
2573 __in uint32_t max_dma_len,
2574 __in uint32_t buf_stride,
2575 __in uint32_t hol_block_timeout,
2576 __in efsys_mem_t *esmp,
2578 __in unsigned int flags,
2579 __in efx_evq_t *eep,
2580 __deref_out efx_rxq_t **erpp);
2584 typedef struct efx_buffer_s {
2585 efsys_dma_addr_t eb_addr;
2590 typedef struct efx_desc_s {
2596 __in efx_rxq_t *erp,
2597 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2599 __in unsigned int ndescs,
2600 __in unsigned int completed,
2601 __in unsigned int added);
2605 __in efx_rxq_t *erp,
2606 __in unsigned int added,
2607 __inout unsigned int *pushedp);
2609 #if EFSYS_OPT_RX_PACKED_STREAM
2612 efx_rx_qpush_ps_credits(
2613 __in efx_rxq_t *erp);
2615 extern __checkReturn uint8_t *
2616 efx_rx_qps_packet_info(
2617 __in efx_rxq_t *erp,
2618 __in uint8_t *buffer,
2619 __in uint32_t buffer_length,
2620 __in uint32_t current_offset,
2621 __out uint16_t *lengthp,
2622 __out uint32_t *next_offsetp,
2623 __out uint32_t *timestamp);
2626 extern __checkReturn efx_rc_t
2628 __in efx_rxq_t *erp);
2632 __in efx_rxq_t *erp);
2636 __in efx_rxq_t *erp);
2640 typedef struct efx_txq_s efx_txq_t;
2642 #if EFSYS_OPT_QSTATS
2644 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2645 typedef enum efx_tx_qstat_e {
2651 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2653 #endif /* EFSYS_OPT_QSTATS */
2655 extern __checkReturn efx_rc_t
2657 __in efx_nic_t *enp);
2661 __in efx_nic_t *enp);
2663 #define EFX_TXQ_MINNDESCS 512
2665 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2666 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2667 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2669 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2671 #define EFX_TXQ_CKSUM_IPV4 0x0001
2672 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2673 #define EFX_TXQ_FATSOV2 0x0004
2674 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2675 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2677 extern __checkReturn efx_rc_t
2679 __in efx_nic_t *enp,
2680 __in unsigned int index,
2681 __in unsigned int label,
2682 __in efsys_mem_t *esmp,
2685 __in uint16_t flags,
2686 __in efx_evq_t *eep,
2687 __deref_out efx_txq_t **etpp,
2688 __out unsigned int *addedp);
2690 extern __checkReturn efx_rc_t
2692 __in efx_txq_t *etp,
2693 __in_ecount(ndescs) efx_buffer_t *eb,
2694 __in unsigned int ndescs,
2695 __in unsigned int completed,
2696 __inout unsigned int *addedp);
2698 extern __checkReturn efx_rc_t
2700 __in efx_txq_t *etp,
2701 __in unsigned int ns);
2705 __in efx_txq_t *etp,
2706 __in unsigned int added,
2707 __in unsigned int pushed);
2709 extern __checkReturn efx_rc_t
2711 __in efx_txq_t *etp);
2715 __in efx_txq_t *etp);
2717 extern __checkReturn efx_rc_t
2719 __in efx_txq_t *etp);
2722 efx_tx_qpio_disable(
2723 __in efx_txq_t *etp);
2725 extern __checkReturn efx_rc_t
2727 __in efx_txq_t *etp,
2728 __in_ecount(buf_length) uint8_t *buffer,
2729 __in size_t buf_length,
2730 __in size_t pio_buf_offset);
2732 extern __checkReturn efx_rc_t
2734 __in efx_txq_t *etp,
2735 __in size_t pkt_length,
2736 __in unsigned int completed,
2737 __inout unsigned int *addedp);
2739 extern __checkReturn efx_rc_t
2741 __in efx_txq_t *etp,
2742 __in_ecount(n) efx_desc_t *ed,
2743 __in unsigned int n,
2744 __in unsigned int completed,
2745 __inout unsigned int *addedp);
2748 efx_tx_qdesc_dma_create(
2749 __in efx_txq_t *etp,
2750 __in efsys_dma_addr_t addr,
2753 __out efx_desc_t *edp);
2756 efx_tx_qdesc_tso_create(
2757 __in efx_txq_t *etp,
2758 __in uint16_t ipv4_id,
2759 __in uint32_t tcp_seq,
2760 __in uint8_t tcp_flags,
2761 __out efx_desc_t *edp);
2763 /* Number of FATSOv2 option descriptors */
2764 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2766 /* Maximum number of DMA segments per TSO packet (not superframe) */
2767 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2770 efx_tx_qdesc_tso2_create(
2771 __in efx_txq_t *etp,
2772 __in uint16_t ipv4_id,
2773 __in uint16_t outer_ipv4_id,
2774 __in uint32_t tcp_seq,
2775 __in uint16_t tcp_mss,
2776 __out_ecount(count) efx_desc_t *edp,
2780 efx_tx_qdesc_vlantci_create(
2781 __in efx_txq_t *etp,
2783 __out efx_desc_t *edp);
2786 efx_tx_qdesc_checksum_create(
2787 __in efx_txq_t *etp,
2788 __in uint16_t flags,
2789 __out efx_desc_t *edp);
2791 #if EFSYS_OPT_QSTATS
2797 __in efx_nic_t *etp,
2798 __in unsigned int id);
2800 #endif /* EFSYS_OPT_NAMES */
2803 efx_tx_qstats_update(
2804 __in efx_txq_t *etp,
2805 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2807 #endif /* EFSYS_OPT_QSTATS */
2811 __in efx_txq_t *etp);
2816 #if EFSYS_OPT_FILTER
2818 #define EFX_ETHER_TYPE_IPV4 0x0800
2819 #define EFX_ETHER_TYPE_IPV6 0x86DD
2821 #define EFX_IPPROTO_TCP 6
2822 #define EFX_IPPROTO_UDP 17
2823 #define EFX_IPPROTO_GRE 47
2825 /* Use RSS to spread across multiple queues */
2826 #define EFX_FILTER_FLAG_RX_RSS 0x01
2827 /* Enable RX scatter */
2828 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2830 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2831 * May only be set by the filter implementation for each type.
2832 * A removal request will restore the automatic filter in its place.
2834 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2835 /* Filter is for RX */
2836 #define EFX_FILTER_FLAG_RX 0x08
2837 /* Filter is for TX */
2838 #define EFX_FILTER_FLAG_TX 0x10
2839 /* Set match flag on the received packet */
2840 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2841 /* Set match mark on the received packet */
2842 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2844 typedef uint8_t efx_filter_flags_t;
2847 * Flags which specify the fields to match on. The values are the same as in the
2848 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2851 /* Match by remote IP host address */
2852 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2853 /* Match by local IP host address */
2854 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2855 /* Match by remote MAC address */
2856 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2857 /* Match by remote TCP/UDP port */
2858 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2859 /* Match by remote TCP/UDP port */
2860 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2861 /* Match by local TCP/UDP port */
2862 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2863 /* Match by Ether-type */
2864 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2865 /* Match by inner VLAN ID */
2866 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2867 /* Match by outer VLAN ID */
2868 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2869 /* Match by IP transport protocol */
2870 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2871 /* Match by VNI or VSID */
2872 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2873 /* For encapsulated packets, match by inner frame local MAC address */
2874 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2875 /* For encapsulated packets, match all multicast inner frames */
2876 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2877 /* For encapsulated packets, match all unicast inner frames */
2878 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2880 * Match by encap type, this flag does not correspond to
2881 * the MCDI match flags and any unoccupied value may be used
2883 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2884 /* Match otherwise-unmatched multicast and broadcast packets */
2885 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2886 /* Match otherwise-unmatched unicast packets */
2887 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2889 typedef uint32_t efx_filter_match_flags_t;
2891 typedef enum efx_filter_priority_s {
2892 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2893 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2894 * address list or hardware
2895 * requirements. This may only be used
2896 * by the filter implementation for
2898 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2899 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2900 * client (e.g. SR-IOV, HyperV VMQ etc.)
2902 } efx_filter_priority_t;
2905 * FIXME: All these fields are assumed to be in little-endian byte order.
2906 * It may be better for some to be big-endian. See bug42804.
2909 typedef struct efx_filter_spec_s {
2910 efx_filter_match_flags_t efs_match_flags;
2911 uint8_t efs_priority;
2912 efx_filter_flags_t efs_flags;
2913 uint16_t efs_dmaq_id;
2914 uint32_t efs_rss_context;
2916 /* Fields below here are hashed for software filter lookup */
2917 uint16_t efs_outer_vid;
2918 uint16_t efs_inner_vid;
2919 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2920 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2921 uint16_t efs_ether_type;
2922 uint8_t efs_ip_proto;
2923 efx_tunnel_protocol_t efs_encap_type;
2924 uint16_t efs_loc_port;
2925 uint16_t efs_rem_port;
2926 efx_oword_t efs_rem_host;
2927 efx_oword_t efs_loc_host;
2928 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2929 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2930 } efx_filter_spec_t;
2933 /* Default values for use in filter specifications */
2934 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2935 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2937 extern __checkReturn efx_rc_t
2939 __in efx_nic_t *enp);
2943 __in efx_nic_t *enp);
2945 extern __checkReturn efx_rc_t
2947 __in efx_nic_t *enp,
2948 __inout efx_filter_spec_t *spec);
2950 extern __checkReturn efx_rc_t
2952 __in efx_nic_t *enp,
2953 __inout efx_filter_spec_t *spec);
2955 extern __checkReturn efx_rc_t
2957 __in efx_nic_t *enp);
2959 extern __checkReturn efx_rc_t
2960 efx_filter_supported_filters(
2961 __in efx_nic_t *enp,
2962 __out_ecount(buffer_length) uint32_t *buffer,
2963 __in size_t buffer_length,
2964 __out size_t *list_lengthp);
2967 efx_filter_spec_init_rx(
2968 __out efx_filter_spec_t *spec,
2969 __in efx_filter_priority_t priority,
2970 __in efx_filter_flags_t flags,
2971 __in efx_rxq_t *erp);
2974 efx_filter_spec_init_tx(
2975 __out efx_filter_spec_t *spec,
2976 __in efx_txq_t *etp);
2978 extern __checkReturn efx_rc_t
2979 efx_filter_spec_set_ipv4_local(
2980 __inout efx_filter_spec_t *spec,
2983 __in uint16_t port);
2985 extern __checkReturn efx_rc_t
2986 efx_filter_spec_set_ipv4_full(
2987 __inout efx_filter_spec_t *spec,
2989 __in uint32_t lhost,
2990 __in uint16_t lport,
2991 __in uint32_t rhost,
2992 __in uint16_t rport);
2994 extern __checkReturn efx_rc_t
2995 efx_filter_spec_set_eth_local(
2996 __inout efx_filter_spec_t *spec,
2998 __in const uint8_t *addr);
3001 efx_filter_spec_set_ether_type(
3002 __inout efx_filter_spec_t *spec,
3003 __in uint16_t ether_type);
3005 extern __checkReturn efx_rc_t
3006 efx_filter_spec_set_uc_def(
3007 __inout efx_filter_spec_t *spec);
3009 extern __checkReturn efx_rc_t
3010 efx_filter_spec_set_mc_def(
3011 __inout efx_filter_spec_t *spec);
3013 typedef enum efx_filter_inner_frame_match_e {
3014 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3015 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3016 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3017 } efx_filter_inner_frame_match_t;
3019 extern __checkReturn efx_rc_t
3020 efx_filter_spec_set_encap_type(
3021 __inout efx_filter_spec_t *spec,
3022 __in efx_tunnel_protocol_t encap_type,
3023 __in efx_filter_inner_frame_match_t inner_frame_match);
3025 extern __checkReturn efx_rc_t
3026 efx_filter_spec_set_vxlan(
3027 __inout efx_filter_spec_t *spec,
3028 __in const uint8_t *vni,
3029 __in const uint8_t *inner_addr,
3030 __in const uint8_t *outer_addr);
3032 extern __checkReturn efx_rc_t
3033 efx_filter_spec_set_geneve(
3034 __inout efx_filter_spec_t *spec,
3035 __in const uint8_t *vni,
3036 __in const uint8_t *inner_addr,
3037 __in const uint8_t *outer_addr);
3039 extern __checkReturn efx_rc_t
3040 efx_filter_spec_set_nvgre(
3041 __inout efx_filter_spec_t *spec,
3042 __in const uint8_t *vsid,
3043 __in const uint8_t *inner_addr,
3044 __in const uint8_t *outer_addr);
3046 #if EFSYS_OPT_RX_SCALE
3047 extern __checkReturn efx_rc_t
3048 efx_filter_spec_set_rss_context(
3049 __inout efx_filter_spec_t *spec,
3050 __in uint32_t rss_context);
3052 #endif /* EFSYS_OPT_FILTER */
3056 extern __checkReturn uint32_t
3058 __in_ecount(count) uint32_t const *input,
3060 __in uint32_t init);
3062 extern __checkReturn uint32_t
3064 __in_ecount(length) uint8_t const *input,
3066 __in uint32_t init);
3068 #if EFSYS_OPT_LICENSING
3072 typedef struct efx_key_stats_s {
3074 uint32_t eks_invalid;
3075 uint32_t eks_blacklisted;
3076 uint32_t eks_unverifiable;
3077 uint32_t eks_wrong_node;
3078 uint32_t eks_licensed_apps_lo;
3079 uint32_t eks_licensed_apps_hi;
3080 uint32_t eks_licensed_features_lo;
3081 uint32_t eks_licensed_features_hi;
3084 extern __checkReturn efx_rc_t
3086 __in efx_nic_t *enp);
3090 __in efx_nic_t *enp);
3092 extern __checkReturn boolean_t
3093 efx_lic_check_support(
3094 __in efx_nic_t *enp);
3096 extern __checkReturn efx_rc_t
3097 efx_lic_update_licenses(
3098 __in efx_nic_t *enp);
3100 extern __checkReturn efx_rc_t
3101 efx_lic_get_key_stats(
3102 __in efx_nic_t *enp,
3103 __out efx_key_stats_t *ksp);
3105 extern __checkReturn efx_rc_t
3107 __in efx_nic_t *enp,
3108 __in uint64_t app_id,
3109 __out boolean_t *licensedp);
3111 extern __checkReturn efx_rc_t
3113 __in efx_nic_t *enp,
3114 __in size_t buffer_size,
3115 __out uint32_t *typep,
3116 __out size_t *lengthp,
3117 __out_opt uint8_t *bufferp);
3120 extern __checkReturn efx_rc_t
3122 __in efx_nic_t *enp,
3123 __in_bcount(buffer_size)
3125 __in size_t buffer_size,
3126 __out uint32_t *startp);
3128 extern __checkReturn efx_rc_t
3130 __in efx_nic_t *enp,
3131 __in_bcount(buffer_size)
3133 __in size_t buffer_size,
3134 __in uint32_t offset,
3135 __out uint32_t *endp);
3137 extern __checkReturn __success(return != B_FALSE) boolean_t
3139 __in efx_nic_t *enp,
3140 __in_bcount(buffer_size)
3142 __in size_t buffer_size,
3143 __in uint32_t offset,
3144 __out uint32_t *startp,
3145 __out uint32_t *lengthp);
3147 extern __checkReturn __success(return != B_FALSE) boolean_t
3148 efx_lic_validate_key(
3149 __in efx_nic_t *enp,
3150 __in_bcount(length) caddr_t keyp,
3151 __in uint32_t length);
3153 extern __checkReturn efx_rc_t
3155 __in efx_nic_t *enp,
3156 __in_bcount(buffer_size)
3158 __in size_t buffer_size,
3159 __in uint32_t offset,
3160 __in uint32_t length,
3161 __out_bcount_part(key_max_size, *lengthp)
3163 __in size_t key_max_size,
3164 __out uint32_t *lengthp);
3166 extern __checkReturn efx_rc_t
3168 __in efx_nic_t *enp,
3169 __in_bcount(buffer_size)
3171 __in size_t buffer_size,
3172 __in uint32_t offset,
3173 __in_bcount(length) caddr_t keyp,
3174 __in uint32_t length,
3175 __out uint32_t *lengthp);
3177 __checkReturn efx_rc_t
3179 __in efx_nic_t *enp,
3180 __in_bcount(buffer_size)
3182 __in size_t buffer_size,
3183 __in uint32_t offset,
3184 __in uint32_t length,
3186 __out uint32_t *deltap);
3188 extern __checkReturn efx_rc_t
3189 efx_lic_create_partition(
3190 __in efx_nic_t *enp,
3191 __in_bcount(buffer_size)
3193 __in size_t buffer_size);
3195 extern __checkReturn efx_rc_t
3196 efx_lic_finish_partition(
3197 __in efx_nic_t *enp,
3198 __in_bcount(buffer_size)
3200 __in size_t buffer_size);
3202 #endif /* EFSYS_OPT_LICENSING */
3206 #if EFSYS_OPT_TUNNEL
3208 extern __checkReturn efx_rc_t
3210 __in efx_nic_t *enp);
3214 __in efx_nic_t *enp);
3217 * For overlay network encapsulation using UDP, the firmware needs to know
3218 * the configured UDP port for the overlay so it can decode encapsulated
3220 * The UDP port/protocol list is global.
3223 extern __checkReturn efx_rc_t
3224 efx_tunnel_config_udp_add(
3225 __in efx_nic_t *enp,
3226 __in uint16_t port /* host/cpu-endian */,
3227 __in efx_tunnel_protocol_t protocol);
3229 extern __checkReturn efx_rc_t
3230 efx_tunnel_config_udp_remove(
3231 __in efx_nic_t *enp,
3232 __in uint16_t port /* host/cpu-endian */,
3233 __in efx_tunnel_protocol_t protocol);
3236 efx_tunnel_config_clear(
3237 __in efx_nic_t *enp);
3240 * Apply tunnel UDP ports configuration to hardware.
3242 * EAGAIN is returned if hardware will be reset (datapath and management CPU
3245 extern __checkReturn efx_rc_t
3246 efx_tunnel_reconfigure(
3247 __in efx_nic_t *enp);
3249 #endif /* EFSYS_OPT_TUNNEL */
3251 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3254 * Firmware subvariant choice options.
3256 * It may be switched to no Tx checksum if attached drivers are either
3257 * preboot or firmware subvariant aware and no VIS are allocated.
3258 * If may be always switched to default explicitly using set request or
3259 * implicitly if unaware driver is attaching. If switching is done when
3260 * a driver is attached, it gets MC_REBOOT event and should recreate its
3263 * See SF-119419-TC DPDK Firmware Driver Interface and
3264 * SF-109306-TC EF10 for Driver Writers for details.
3266 typedef enum efx_nic_fw_subvariant_e {
3267 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3268 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3269 EFX_NIC_FW_SUBVARIANT_NTYPES
3270 } efx_nic_fw_subvariant_t;
3272 extern __checkReturn efx_rc_t
3273 efx_nic_get_fw_subvariant(
3274 __in efx_nic_t *enp,
3275 __out efx_nic_fw_subvariant_t *subvariantp);
3277 extern __checkReturn efx_rc_t
3278 efx_nic_set_fw_subvariant(
3279 __in efx_nic_t *enp,
3280 __in efx_nic_fw_subvariant_t subvariant);
3282 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3284 typedef enum efx_phy_fec_type_e {
3285 EFX_PHY_FEC_NONE = 0,
3288 } efx_phy_fec_type_t;
3290 extern __checkReturn efx_rc_t
3291 efx_phy_fec_type_get(
3292 __in efx_nic_t *enp,
3293 __out efx_phy_fec_type_t *typep);
3295 typedef struct efx_phy_link_state_s {
3296 uint32_t epls_adv_cap_mask;
3297 uint32_t epls_lp_cap_mask;
3298 uint32_t epls_ld_cap_mask;
3299 unsigned int epls_fcntl;
3300 efx_phy_fec_type_t epls_fec;
3301 efx_link_mode_t epls_link_mode;
3302 } efx_phy_link_state_t;
3304 extern __checkReturn efx_rc_t
3305 efx_phy_link_state_get(
3306 __in efx_nic_t *enp,
3307 __out efx_phy_link_state_t *eplsp);
3314 #endif /* _SYS_EFX_H */