2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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28 * The views and conclusions contained in the software and documentation are
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30 * policies, either expressed or implied, of the FreeBSD Project.
39 #include "efx_check.h"
40 #include "efx_phy_ids.h"
46 #define EFX_STATIC_ASSERT(_cond) \
47 ((void)sizeof (char[(_cond) ? 1 : -1]))
49 #define EFX_ARRAY_SIZE(_array) \
50 (sizeof (_array) / sizeof ((_array)[0]))
52 #define EFX_FIELD_OFFSET(_type, _field) \
53 ((size_t)&(((_type *)0)->_field))
55 /* The macro expands divider twice */
56 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
60 typedef __success(return == 0) int efx_rc_t;
65 typedef enum efx_family_e {
67 EFX_FAMILY_FALCON, /* Obsolete and not supported */
69 EFX_FAMILY_HUNTINGTON,
75 extern __checkReturn efx_rc_t
79 __out efx_family_t *efp,
80 __out unsigned int *membarp);
83 #define EFX_PCI_VENID_SFC 0x1924
85 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
87 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
88 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
89 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
91 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
92 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
93 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
95 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
96 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
98 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
99 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
100 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
103 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
104 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
107 #define EFX_MEM_BAR_SIENA 2
109 #define EFX_MEM_BAR_HUNTINGTON_PF 2
110 #define EFX_MEM_BAR_HUNTINGTON_VF 0
112 #define EFX_MEM_BAR_MEDFORD_PF 2
113 #define EFX_MEM_BAR_MEDFORD_VF 0
115 #define EFX_MEM_BAR_MEDFORD2 0
123 EFX_ERR_BUFID_DC_OOB,
136 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
137 extern __checkReturn uint32_t
139 __in uint32_t crc_init,
140 __in_ecount(length) uint8_t const *input,
144 /* Type prototypes */
146 typedef struct efx_rxq_s efx_rxq_t;
150 typedef struct efx_nic_s efx_nic_t;
152 extern __checkReturn efx_rc_t
154 __in efx_family_t family,
155 __in efsys_identifier_t *esip,
156 __in efsys_bar_t *esbp,
157 __in efsys_lock_t *eslp,
158 __deref_out efx_nic_t **enpp);
160 extern __checkReturn efx_rc_t
162 __in efx_nic_t *enp);
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
170 __in efx_nic_t *enp);
174 extern __checkReturn efx_rc_t
175 efx_nic_register_test(
176 __in efx_nic_t *enp);
178 #endif /* EFSYS_OPT_DIAG */
182 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 __in efx_nic_t *enp);
192 #define EFX_PCIE_LINK_SPEED_GEN1 1
193 #define EFX_PCIE_LINK_SPEED_GEN2 2
194 #define EFX_PCIE_LINK_SPEED_GEN3 3
196 typedef enum efx_pcie_link_performance_e {
197 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
198 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
199 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
200 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
201 } efx_pcie_link_performance_t;
203 extern __checkReturn efx_rc_t
204 efx_nic_calculate_pcie_link_bandwidth(
205 __in uint32_t pcie_link_width,
206 __in uint32_t pcie_link_gen,
207 __out uint32_t *bandwidth_mbpsp);
209 extern __checkReturn efx_rc_t
210 efx_nic_check_pcie_link_speed(
212 __in uint32_t pcie_link_width,
213 __in uint32_t pcie_link_gen,
214 __out efx_pcie_link_performance_t *resultp);
218 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
219 /* Huntington and Medford require MCDIv2 commands */
220 #define WITH_MCDI_V2 1
223 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
225 typedef enum efx_mcdi_exception_e {
226 EFX_MCDI_EXCEPTION_MC_REBOOT,
227 EFX_MCDI_EXCEPTION_MC_BADASSERT,
228 } efx_mcdi_exception_t;
230 #if EFSYS_OPT_MCDI_LOGGING
231 typedef enum efx_log_msg_e {
233 EFX_LOG_MCDI_REQUEST,
234 EFX_LOG_MCDI_RESPONSE,
236 #endif /* EFSYS_OPT_MCDI_LOGGING */
238 typedef struct efx_mcdi_transport_s {
240 efsys_mem_t *emt_dma_mem;
241 void (*emt_execute)(void *, efx_mcdi_req_t *);
242 void (*emt_ev_cpl)(void *);
243 void (*emt_exception)(void *, efx_mcdi_exception_t);
244 #if EFSYS_OPT_MCDI_LOGGING
245 void (*emt_logger)(void *, efx_log_msg_t,
246 void *, size_t, void *, size_t);
247 #endif /* EFSYS_OPT_MCDI_LOGGING */
248 #if EFSYS_OPT_MCDI_PROXY_AUTH
249 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
250 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
251 } efx_mcdi_transport_t;
253 extern __checkReturn efx_rc_t
256 __in const efx_mcdi_transport_t *mtp);
258 extern __checkReturn efx_rc_t
260 __in efx_nic_t *enp);
264 __in efx_nic_t *enp);
267 efx_mcdi_get_timeout(
269 __in efx_mcdi_req_t *emrp,
270 __out uint32_t *usec_timeoutp);
273 efx_mcdi_request_start(
275 __in efx_mcdi_req_t *emrp,
276 __in boolean_t ev_cpl);
278 extern __checkReturn boolean_t
279 efx_mcdi_request_poll(
280 __in efx_nic_t *enp);
282 extern __checkReturn boolean_t
283 efx_mcdi_request_abort(
284 __in efx_nic_t *enp);
288 __in efx_nic_t *enp);
290 #endif /* EFSYS_OPT_MCDI */
294 #define EFX_NINTR_SIENA 1024
296 typedef enum efx_intr_type_e {
297 EFX_INTR_INVALID = 0,
303 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
305 extern __checkReturn efx_rc_t
308 __in efx_intr_type_t type,
309 __in efsys_mem_t *esmp);
313 __in efx_nic_t *enp);
317 __in efx_nic_t *enp);
320 efx_intr_disable_unlocked(
321 __in efx_nic_t *enp);
323 #define EFX_INTR_NEVQS 32
325 extern __checkReturn efx_rc_t
328 __in unsigned int level);
331 efx_intr_status_line(
333 __out boolean_t *fatalp,
334 __out uint32_t *maskp);
337 efx_intr_status_message(
339 __in unsigned int message,
340 __out boolean_t *fatalp);
344 __in efx_nic_t *enp);
348 __in efx_nic_t *enp);
352 #if EFSYS_OPT_MAC_STATS
354 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
355 typedef enum efx_mac_stat_e {
358 EFX_MAC_RX_UNICST_PKTS,
359 EFX_MAC_RX_MULTICST_PKTS,
360 EFX_MAC_RX_BRDCST_PKTS,
361 EFX_MAC_RX_PAUSE_PKTS,
362 EFX_MAC_RX_LE_64_PKTS,
363 EFX_MAC_RX_65_TO_127_PKTS,
364 EFX_MAC_RX_128_TO_255_PKTS,
365 EFX_MAC_RX_256_TO_511_PKTS,
366 EFX_MAC_RX_512_TO_1023_PKTS,
367 EFX_MAC_RX_1024_TO_15XX_PKTS,
368 EFX_MAC_RX_GE_15XX_PKTS,
370 EFX_MAC_RX_FCS_ERRORS,
371 EFX_MAC_RX_DROP_EVENTS,
372 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
373 EFX_MAC_RX_SYMBOL_ERRORS,
374 EFX_MAC_RX_ALIGN_ERRORS,
375 EFX_MAC_RX_INTERNAL_ERRORS,
376 EFX_MAC_RX_JABBER_PKTS,
377 EFX_MAC_RX_LANE0_CHAR_ERR,
378 EFX_MAC_RX_LANE1_CHAR_ERR,
379 EFX_MAC_RX_LANE2_CHAR_ERR,
380 EFX_MAC_RX_LANE3_CHAR_ERR,
381 EFX_MAC_RX_LANE0_DISP_ERR,
382 EFX_MAC_RX_LANE1_DISP_ERR,
383 EFX_MAC_RX_LANE2_DISP_ERR,
384 EFX_MAC_RX_LANE3_DISP_ERR,
385 EFX_MAC_RX_MATCH_FAULT,
386 EFX_MAC_RX_NODESC_DROP_CNT,
389 EFX_MAC_TX_UNICST_PKTS,
390 EFX_MAC_TX_MULTICST_PKTS,
391 EFX_MAC_TX_BRDCST_PKTS,
392 EFX_MAC_TX_PAUSE_PKTS,
393 EFX_MAC_TX_LE_64_PKTS,
394 EFX_MAC_TX_65_TO_127_PKTS,
395 EFX_MAC_TX_128_TO_255_PKTS,
396 EFX_MAC_TX_256_TO_511_PKTS,
397 EFX_MAC_TX_512_TO_1023_PKTS,
398 EFX_MAC_TX_1024_TO_15XX_PKTS,
399 EFX_MAC_TX_GE_15XX_PKTS,
401 EFX_MAC_TX_SGL_COL_PKTS,
402 EFX_MAC_TX_MULT_COL_PKTS,
403 EFX_MAC_TX_EX_COL_PKTS,
404 EFX_MAC_TX_LATE_COL_PKTS,
406 EFX_MAC_TX_EX_DEF_PKTS,
407 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
408 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
409 EFX_MAC_PM_TRUNC_VFIFO_FULL,
410 EFX_MAC_PM_DISCARD_VFIFO_FULL,
411 EFX_MAC_PM_TRUNC_QBB,
412 EFX_MAC_PM_DISCARD_QBB,
413 EFX_MAC_PM_DISCARD_MAPPING,
414 EFX_MAC_RXDP_Q_DISABLED_PKTS,
415 EFX_MAC_RXDP_DI_DROPPED_PKTS,
416 EFX_MAC_RXDP_STREAMING_PKTS,
417 EFX_MAC_RXDP_HLB_FETCH,
418 EFX_MAC_RXDP_HLB_WAIT,
419 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
420 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
421 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
422 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
423 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
424 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
425 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
426 EFX_MAC_VADAPTER_RX_BAD_BYTES,
427 EFX_MAC_VADAPTER_RX_OVERFLOW,
428 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
429 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
430 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
431 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
432 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
433 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
434 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
435 EFX_MAC_VADAPTER_TX_BAD_BYTES,
436 EFX_MAC_VADAPTER_TX_OVERFLOW,
440 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
442 #endif /* EFSYS_OPT_MAC_STATS */
444 typedef enum efx_link_mode_e {
445 EFX_LINK_UNKNOWN = 0,
461 #define EFX_MAC_ADDR_LEN 6
463 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
465 #define EFX_MAC_MULTICAST_LIST_MAX 256
467 #define EFX_MAC_SDU_MAX 9202
469 #define EFX_MAC_PDU_ADJUSTMENT \
473 + /* bug16011 */ 16) \
475 #define EFX_MAC_PDU(_sdu) \
476 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
479 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
480 * the SDU rounded up slightly.
482 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
484 #define EFX_MAC_PDU_MIN 60
485 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
487 extern __checkReturn efx_rc_t
492 extern __checkReturn efx_rc_t
497 extern __checkReturn efx_rc_t
502 extern __checkReturn efx_rc_t
505 __in boolean_t all_unicst,
506 __in boolean_t mulcst,
507 __in boolean_t all_mulcst,
508 __in boolean_t brdcst);
510 extern __checkReturn efx_rc_t
511 efx_mac_multicast_list_set(
513 __in_ecount(6*count) uint8_t const *addrs,
516 extern __checkReturn efx_rc_t
517 efx_mac_filter_default_rxq_set(
520 __in boolean_t using_rss);
523 efx_mac_filter_default_rxq_clear(
524 __in efx_nic_t *enp);
526 extern __checkReturn efx_rc_t
529 __in boolean_t enabled);
531 extern __checkReturn efx_rc_t
534 __out boolean_t *mac_upp);
536 #define EFX_FCNTL_RESPOND 0x00000001
537 #define EFX_FCNTL_GENERATE 0x00000002
539 extern __checkReturn efx_rc_t
542 __in unsigned int fcntl,
543 __in boolean_t autoneg);
548 __out unsigned int *fcntl_wantedp,
549 __out unsigned int *fcntl_linkp);
552 #if EFSYS_OPT_MAC_STATS
556 extern __checkReturn const char *
559 __in unsigned int id);
561 #endif /* EFSYS_OPT_NAMES */
563 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
565 #define EFX_MAC_STATS_MASK_NPAGES \
566 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
567 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
570 * Get mask of MAC statistics supported by the hardware.
572 * If mask_size is insufficient to return the mask, EINVAL error is
573 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
574 * (which is sizeof (uint32_t)) is sufficient.
576 extern __checkReturn efx_rc_t
577 efx_mac_stats_get_mask(
579 __out_bcount(mask_size) uint32_t *maskp,
580 __in size_t mask_size);
582 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
583 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
584 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
586 #define EFX_MAC_STATS_SIZE 0x400
588 extern __checkReturn efx_rc_t
590 __in efx_nic_t *enp);
593 * Upload mac statistics supported by the hardware into the given buffer.
595 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
598 * The hardware will only DMA statistics that it understands (of course).
599 * Drivers should not make any assumptions about which statistics are
600 * supported, especially when the statistics are generated by firmware.
602 * Thus, drivers should zero this buffer before use, so that not-understood
603 * statistics read back as zero.
605 extern __checkReturn efx_rc_t
606 efx_mac_stats_upload(
608 __in efsys_mem_t *esmp);
610 extern __checkReturn efx_rc_t
611 efx_mac_stats_periodic(
613 __in efsys_mem_t *esmp,
614 __in uint16_t period_ms,
615 __in boolean_t events);
617 extern __checkReturn efx_rc_t
618 efx_mac_stats_update(
620 __in efsys_mem_t *esmp,
621 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
622 __inout_opt uint32_t *generationp);
624 #endif /* EFSYS_OPT_MAC_STATS */
628 typedef enum efx_mon_type_e {
640 __in efx_nic_t *enp);
642 #endif /* EFSYS_OPT_NAMES */
644 extern __checkReturn efx_rc_t
646 __in efx_nic_t *enp);
648 #if EFSYS_OPT_MON_STATS
650 #define EFX_MON_STATS_PAGE_SIZE 0x100
651 #define EFX_MON_MASK_ELEMENT_SIZE 32
653 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
654 typedef enum efx_mon_stat_e {
661 EFX_MON_STAT_EXT_TEMP,
662 EFX_MON_STAT_INT_TEMP,
665 EFX_MON_STAT_INT_COOLING,
666 EFX_MON_STAT_EXT_COOLING,
674 EFX_MON_STAT_AOE_TEMP,
675 EFX_MON_STAT_PSU_AOE_TEMP,
676 EFX_MON_STAT_PSU_TEMP,
682 EFX_MON_STAT_VAOE_IN,
684 EFX_MON_STAT_IAOE_IN,
685 EFX_MON_STAT_NIC_POWER,
689 EFX_MON_STAT_0_9V_ADC,
690 EFX_MON_STAT_INT_TEMP2,
691 EFX_MON_STAT_VREG_TEMP,
692 EFX_MON_STAT_VREG_0_9V_TEMP,
693 EFX_MON_STAT_VREG_1_2V_TEMP,
694 EFX_MON_STAT_INT_VPTAT,
695 EFX_MON_STAT_INT_ADC_TEMP,
696 EFX_MON_STAT_EXT_VPTAT,
697 EFX_MON_STAT_EXT_ADC_TEMP,
698 EFX_MON_STAT_AMBIENT_TEMP,
699 EFX_MON_STAT_AIRFLOW,
700 EFX_MON_STAT_VDD08D_VSS08D_CSR,
701 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
702 EFX_MON_STAT_HOTPOINT_TEMP,
703 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
704 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
705 EFX_MON_STAT_MUM_VCC,
708 EFX_MON_STAT_0V9_A_TEMP,
711 EFX_MON_STAT_0V9_B_TEMP,
712 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
713 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
714 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
715 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
716 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
717 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
718 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
719 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
720 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
721 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
722 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
723 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
724 EFX_MON_STAT_SODIMM_VOUT,
725 EFX_MON_STAT_SODIMM_0_TEMP,
726 EFX_MON_STAT_SODIMM_1_TEMP,
727 EFX_MON_STAT_PHY0_VCC,
728 EFX_MON_STAT_PHY1_VCC,
729 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
730 EFX_MON_STAT_BOARD_FRONT_TEMP,
731 EFX_MON_STAT_BOARD_BACK_TEMP,
739 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
741 typedef enum efx_mon_stat_state_e {
742 EFX_MON_STAT_STATE_OK = 0,
743 EFX_MON_STAT_STATE_WARNING = 1,
744 EFX_MON_STAT_STATE_FATAL = 2,
745 EFX_MON_STAT_STATE_BROKEN = 3,
746 EFX_MON_STAT_STATE_NO_READING = 4,
747 } efx_mon_stat_state_t;
749 typedef struct efx_mon_stat_value_s {
752 } efx_mon_stat_value_t;
759 __in efx_mon_stat_t id);
761 #endif /* EFSYS_OPT_NAMES */
763 extern __checkReturn efx_rc_t
764 efx_mon_stats_update(
766 __in efsys_mem_t *esmp,
767 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
769 #endif /* EFSYS_OPT_MON_STATS */
773 __in efx_nic_t *enp);
777 extern __checkReturn efx_rc_t
779 __in efx_nic_t *enp);
781 #if EFSYS_OPT_PHY_LED_CONTROL
783 typedef enum efx_phy_led_mode_e {
784 EFX_PHY_LED_DEFAULT = 0,
789 } efx_phy_led_mode_t;
791 extern __checkReturn efx_rc_t
794 __in efx_phy_led_mode_t mode);
796 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
798 extern __checkReturn efx_rc_t
800 __in efx_nic_t *enp);
802 #if EFSYS_OPT_LOOPBACK
804 typedef enum efx_loopback_type_e {
805 EFX_LOOPBACK_OFF = 0,
806 EFX_LOOPBACK_DATA = 1,
807 EFX_LOOPBACK_GMAC = 2,
808 EFX_LOOPBACK_XGMII = 3,
809 EFX_LOOPBACK_XGXS = 4,
810 EFX_LOOPBACK_XAUI = 5,
811 EFX_LOOPBACK_GMII = 6,
812 EFX_LOOPBACK_SGMII = 7,
813 EFX_LOOPBACK_XGBR = 8,
814 EFX_LOOPBACK_XFI = 9,
815 EFX_LOOPBACK_XAUI_FAR = 10,
816 EFX_LOOPBACK_GMII_FAR = 11,
817 EFX_LOOPBACK_SGMII_FAR = 12,
818 EFX_LOOPBACK_XFI_FAR = 13,
819 EFX_LOOPBACK_GPHY = 14,
820 EFX_LOOPBACK_PHY_XS = 15,
821 EFX_LOOPBACK_PCS = 16,
822 EFX_LOOPBACK_PMA_PMD = 17,
823 EFX_LOOPBACK_XPORT = 18,
824 EFX_LOOPBACK_XGMII_WS = 19,
825 EFX_LOOPBACK_XAUI_WS = 20,
826 EFX_LOOPBACK_XAUI_WS_FAR = 21,
827 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
828 EFX_LOOPBACK_GMII_WS = 23,
829 EFX_LOOPBACK_XFI_WS = 24,
830 EFX_LOOPBACK_XFI_WS_FAR = 25,
831 EFX_LOOPBACK_PHYXS_WS = 26,
832 EFX_LOOPBACK_PMA_INT = 27,
833 EFX_LOOPBACK_SD_NEAR = 28,
834 EFX_LOOPBACK_SD_FAR = 29,
835 EFX_LOOPBACK_PMA_INT_WS = 30,
836 EFX_LOOPBACK_SD_FEP2_WS = 31,
837 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
838 EFX_LOOPBACK_SD_FEP_WS = 33,
839 EFX_LOOPBACK_SD_FES_WS = 34,
841 } efx_loopback_type_t;
843 typedef enum efx_loopback_kind_e {
844 EFX_LOOPBACK_KIND_OFF = 0,
845 EFX_LOOPBACK_KIND_ALL,
846 EFX_LOOPBACK_KIND_MAC,
847 EFX_LOOPBACK_KIND_PHY,
849 } efx_loopback_kind_t;
853 __in efx_loopback_kind_t loopback_kind,
854 __out efx_qword_t *maskp);
856 extern __checkReturn efx_rc_t
857 efx_port_loopback_set(
859 __in efx_link_mode_t link_mode,
860 __in efx_loopback_type_t type);
864 extern __checkReturn const char *
865 efx_loopback_type_name(
867 __in efx_loopback_type_t type);
869 #endif /* EFSYS_OPT_NAMES */
871 #endif /* EFSYS_OPT_LOOPBACK */
873 extern __checkReturn efx_rc_t
876 __out_opt efx_link_mode_t *link_modep);
880 __in efx_nic_t *enp);
882 typedef enum efx_phy_cap_type_e {
883 EFX_PHY_CAP_INVALID = 0,
890 EFX_PHY_CAP_10000FDX,
894 EFX_PHY_CAP_40000FDX,
896 EFX_PHY_CAP_100000FDX,
897 EFX_PHY_CAP_25000FDX,
898 EFX_PHY_CAP_50000FDX,
900 } efx_phy_cap_type_t;
903 #define EFX_PHY_CAP_CURRENT 0x00000000
904 #define EFX_PHY_CAP_DEFAULT 0x00000001
905 #define EFX_PHY_CAP_PERM 0x00000002
911 __out uint32_t *maskp);
913 extern __checkReturn efx_rc_t
921 __out uint32_t *maskp);
923 extern __checkReturn efx_rc_t
926 __out uint32_t *ouip);
928 typedef enum efx_phy_media_type_e {
929 EFX_PHY_MEDIA_INVALID = 0,
934 EFX_PHY_MEDIA_SFP_PLUS,
935 EFX_PHY_MEDIA_BASE_T,
936 EFX_PHY_MEDIA_QSFP_PLUS,
938 } efx_phy_media_type_t;
941 * Get the type of medium currently used. If the board has ports for
942 * modules, a module is present, and we recognise the media type of
943 * the module, then this will be the media type of the module.
944 * Otherwise it will be the media type of the port.
947 efx_phy_media_type_get(
949 __out efx_phy_media_type_t *typep);
951 extern __checkReturn efx_rc_t
952 efx_phy_module_get_info(
954 __in uint8_t dev_addr,
957 __out_bcount(len) uint8_t *data);
959 #if EFSYS_OPT_PHY_STATS
961 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
962 typedef enum efx_phy_stat_e {
964 EFX_PHY_STAT_PMA_PMD_LINK_UP,
965 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
966 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
967 EFX_PHY_STAT_PMA_PMD_REV_A,
968 EFX_PHY_STAT_PMA_PMD_REV_B,
969 EFX_PHY_STAT_PMA_PMD_REV_C,
970 EFX_PHY_STAT_PMA_PMD_REV_D,
971 EFX_PHY_STAT_PCS_LINK_UP,
972 EFX_PHY_STAT_PCS_RX_FAULT,
973 EFX_PHY_STAT_PCS_TX_FAULT,
974 EFX_PHY_STAT_PCS_BER,
975 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
976 EFX_PHY_STAT_PHY_XS_LINK_UP,
977 EFX_PHY_STAT_PHY_XS_RX_FAULT,
978 EFX_PHY_STAT_PHY_XS_TX_FAULT,
979 EFX_PHY_STAT_PHY_XS_ALIGN,
980 EFX_PHY_STAT_PHY_XS_SYNC_A,
981 EFX_PHY_STAT_PHY_XS_SYNC_B,
982 EFX_PHY_STAT_PHY_XS_SYNC_C,
983 EFX_PHY_STAT_PHY_XS_SYNC_D,
984 EFX_PHY_STAT_AN_LINK_UP,
985 EFX_PHY_STAT_AN_MASTER,
986 EFX_PHY_STAT_AN_LOCAL_RX_OK,
987 EFX_PHY_STAT_AN_REMOTE_RX_OK,
988 EFX_PHY_STAT_CL22EXT_LINK_UP,
993 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
994 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
995 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
996 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
997 EFX_PHY_STAT_AN_COMPLETE,
998 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
999 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1000 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1001 EFX_PHY_STAT_PCS_FW_VERSION_0,
1002 EFX_PHY_STAT_PCS_FW_VERSION_1,
1003 EFX_PHY_STAT_PCS_FW_VERSION_2,
1004 EFX_PHY_STAT_PCS_FW_VERSION_3,
1005 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1006 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1007 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1008 EFX_PHY_STAT_PCS_OP_MODE,
1012 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1018 __in efx_nic_t *enp,
1019 __in efx_phy_stat_t stat);
1021 #endif /* EFSYS_OPT_NAMES */
1023 #define EFX_PHY_STATS_SIZE 0x100
1025 extern __checkReturn efx_rc_t
1026 efx_phy_stats_update(
1027 __in efx_nic_t *enp,
1028 __in efsys_mem_t *esmp,
1029 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1031 #endif /* EFSYS_OPT_PHY_STATS */
1036 typedef enum efx_bist_type_e {
1037 EFX_BIST_TYPE_UNKNOWN,
1038 EFX_BIST_TYPE_PHY_NORMAL,
1039 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1040 EFX_BIST_TYPE_PHY_CABLE_LONG,
1041 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1042 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1043 EFX_BIST_TYPE_REG, /* Test the register memories */
1044 EFX_BIST_TYPE_NTYPES,
1047 typedef enum efx_bist_result_e {
1048 EFX_BIST_RESULT_UNKNOWN,
1049 EFX_BIST_RESULT_RUNNING,
1050 EFX_BIST_RESULT_PASSED,
1051 EFX_BIST_RESULT_FAILED,
1052 } efx_bist_result_t;
1054 typedef enum efx_phy_cable_status_e {
1055 EFX_PHY_CABLE_STATUS_OK,
1056 EFX_PHY_CABLE_STATUS_INVALID,
1057 EFX_PHY_CABLE_STATUS_OPEN,
1058 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1059 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1060 EFX_PHY_CABLE_STATUS_BUSY,
1061 } efx_phy_cable_status_t;
1063 typedef enum efx_bist_value_e {
1064 EFX_BIST_PHY_CABLE_LENGTH_A,
1065 EFX_BIST_PHY_CABLE_LENGTH_B,
1066 EFX_BIST_PHY_CABLE_LENGTH_C,
1067 EFX_BIST_PHY_CABLE_LENGTH_D,
1068 EFX_BIST_PHY_CABLE_STATUS_A,
1069 EFX_BIST_PHY_CABLE_STATUS_B,
1070 EFX_BIST_PHY_CABLE_STATUS_C,
1071 EFX_BIST_PHY_CABLE_STATUS_D,
1072 EFX_BIST_FAULT_CODE,
1074 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1080 EFX_BIST_MEM_EXPECT,
1081 EFX_BIST_MEM_ACTUAL,
1083 EFX_BIST_MEM_ECC_PARITY,
1084 EFX_BIST_MEM_ECC_FATAL,
1088 extern __checkReturn efx_rc_t
1089 efx_bist_enable_offline(
1090 __in efx_nic_t *enp);
1092 extern __checkReturn efx_rc_t
1094 __in efx_nic_t *enp,
1095 __in efx_bist_type_t type);
1097 extern __checkReturn efx_rc_t
1099 __in efx_nic_t *enp,
1100 __in efx_bist_type_t type,
1101 __out efx_bist_result_t *resultp,
1102 __out_opt uint32_t *value_maskp,
1103 __out_ecount_opt(count) unsigned long *valuesp,
1108 __in efx_nic_t *enp,
1109 __in efx_bist_type_t type);
1111 #endif /* EFSYS_OPT_BIST */
1113 #define EFX_FEATURE_IPV6 0x00000001
1114 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1115 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1116 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1117 #define EFX_FEATURE_MCDI 0x00000020
1118 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1119 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1120 #define EFX_FEATURE_TURBO 0x00000100
1121 #define EFX_FEATURE_MCDI_DMA 0x00000200
1122 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1123 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1124 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1125 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1126 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1128 typedef enum efx_tunnel_protocol_e {
1129 EFX_TUNNEL_PROTOCOL_NONE = 0,
1130 EFX_TUNNEL_PROTOCOL_VXLAN,
1131 EFX_TUNNEL_PROTOCOL_GENEVE,
1132 EFX_TUNNEL_PROTOCOL_NVGRE,
1134 } efx_tunnel_protocol_t;
1136 typedef enum efx_vi_window_shift_e {
1137 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1138 EFX_VI_WINDOW_SHIFT_8K = 13,
1139 EFX_VI_WINDOW_SHIFT_16K = 14,
1140 EFX_VI_WINDOW_SHIFT_64K = 16,
1141 } efx_vi_window_shift_t;
1143 typedef struct efx_nic_cfg_s {
1144 uint32_t enc_board_type;
1145 uint32_t enc_phy_type;
1147 char enc_phy_name[21];
1149 char enc_phy_revision[21];
1150 efx_mon_type_t enc_mon_type;
1151 #if EFSYS_OPT_MON_STATS
1152 uint32_t enc_mon_stat_dma_buf_size;
1153 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1155 unsigned int enc_features;
1156 efx_vi_window_shift_t enc_vi_window_shift;
1157 uint8_t enc_mac_addr[6];
1158 uint8_t enc_port; /* PHY port number */
1159 uint32_t enc_intr_vec_base;
1160 uint32_t enc_intr_limit;
1161 uint32_t enc_evq_limit;
1162 uint32_t enc_txq_limit;
1163 uint32_t enc_rxq_limit;
1164 uint32_t enc_txq_max_ndescs;
1165 uint32_t enc_buftbl_limit;
1166 uint32_t enc_piobuf_limit;
1167 uint32_t enc_piobuf_size;
1168 uint32_t enc_piobuf_min_alloc_size;
1169 uint32_t enc_evq_timer_quantum_ns;
1170 uint32_t enc_evq_timer_max_us;
1171 uint32_t enc_clk_mult;
1172 uint32_t enc_rx_prefix_size;
1173 uint32_t enc_rx_buf_align_start;
1174 uint32_t enc_rx_buf_align_end;
1175 uint32_t enc_rx_scale_max_exclusive_contexts;
1176 #if EFSYS_OPT_LOOPBACK
1177 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1178 #endif /* EFSYS_OPT_LOOPBACK */
1179 #if EFSYS_OPT_PHY_FLAGS
1180 uint32_t enc_phy_flags_mask;
1181 #endif /* EFSYS_OPT_PHY_FLAGS */
1182 #if EFSYS_OPT_PHY_LED_CONTROL
1183 uint32_t enc_led_mask;
1184 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1185 #if EFSYS_OPT_PHY_STATS
1186 uint64_t enc_phy_stat_mask;
1187 #endif /* EFSYS_OPT_PHY_STATS */
1189 uint8_t enc_mcdi_mdio_channel;
1190 #if EFSYS_OPT_PHY_STATS
1191 uint32_t enc_mcdi_phy_stat_mask;
1192 #endif /* EFSYS_OPT_PHY_STATS */
1193 #if EFSYS_OPT_MON_STATS
1194 uint32_t *enc_mcdi_sensor_maskp;
1195 uint32_t enc_mcdi_sensor_mask_size;
1196 #endif /* EFSYS_OPT_MON_STATS */
1197 #endif /* EFSYS_OPT_MCDI */
1199 uint32_t enc_bist_mask;
1200 #endif /* EFSYS_OPT_BIST */
1201 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1204 uint32_t enc_privilege_mask;
1205 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1206 boolean_t enc_bug26807_workaround;
1207 boolean_t enc_bug35388_workaround;
1208 boolean_t enc_bug41750_workaround;
1209 boolean_t enc_bug61265_workaround;
1210 boolean_t enc_rx_batching_enabled;
1211 /* Maximum number of descriptors completed in an rx event. */
1212 uint32_t enc_rx_batch_max;
1213 /* Number of rx descriptors the hardware requires for a push. */
1214 uint32_t enc_rx_push_align;
1215 /* Maximum amount of data in DMA descriptor */
1216 uint32_t enc_tx_dma_desc_size_max;
1218 * Boundary which DMA descriptor data must not cross or 0 if no
1221 uint32_t enc_tx_dma_desc_boundary;
1223 * Maximum number of bytes into the packet the TCP header can start for
1224 * the hardware to apply TSO packet edits.
1226 uint32_t enc_tx_tso_tcp_header_offset_limit;
1227 boolean_t enc_fw_assisted_tso_enabled;
1228 boolean_t enc_fw_assisted_tso_v2_enabled;
1229 /* Number of TSO contexts on the NIC (FATSOv2) */
1230 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1231 boolean_t enc_hw_tx_insert_vlan_enabled;
1232 /* Number of PFs on the NIC */
1233 uint32_t enc_hw_pf_count;
1234 /* Datapath firmware vadapter/vport/vswitch support */
1235 boolean_t enc_datapath_cap_evb;
1236 boolean_t enc_rx_disable_scatter_supported;
1237 boolean_t enc_allow_set_mac_with_installed_filters;
1238 boolean_t enc_enhanced_set_mac_supported;
1239 boolean_t enc_init_evq_v2_supported;
1240 boolean_t enc_rx_packed_stream_supported;
1241 boolean_t enc_rx_var_packed_stream_supported;
1242 boolean_t enc_pm_and_rxdp_counters;
1243 boolean_t enc_mac_stats_40g_tx_size_bins;
1244 uint32_t enc_tunnel_encapsulations_supported;
1246 * NIC global maximum for unique UDP tunnel ports shared by all
1249 uint32_t enc_tunnel_config_udp_entries_max;
1250 /* External port identifier */
1251 uint8_t enc_external_port;
1252 uint32_t enc_mcdi_max_payload_length;
1253 /* VPD may be per-PF or global */
1254 boolean_t enc_vpd_is_global;
1255 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1256 uint32_t enc_required_pcie_bandwidth_mbps;
1257 uint32_t enc_max_pcie_link_gen;
1258 /* Firmware verifies integrity of NVRAM updates */
1259 uint32_t enc_nvram_update_verify_result_supported;
1262 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1263 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1265 #define EFX_PCI_FUNCTION(_encp) \
1266 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1268 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1270 extern const efx_nic_cfg_t *
1272 __in efx_nic_t *enp);
1274 typedef struct efx_nic_fw_info_s {
1275 /* Basic FW version information */
1276 uint16_t enfi_mc_fw_version[4];
1278 * If datapath capabilities can be detected,
1279 * additional FW information is to be shown
1281 boolean_t enfi_dpcpu_fw_ids_valid;
1282 /* Rx and Tx datapath CPU FW IDs */
1283 uint16_t enfi_rx_dpcpu_fw_id;
1284 uint16_t enfi_tx_dpcpu_fw_id;
1285 } efx_nic_fw_info_t;
1287 extern __checkReturn efx_rc_t
1288 efx_nic_get_fw_version(
1289 __in efx_nic_t *enp,
1290 __out efx_nic_fw_info_t *enfip);
1292 /* Driver resource limits (minimum required/maximum usable). */
1293 typedef struct efx_drv_limits_s {
1294 uint32_t edl_min_evq_count;
1295 uint32_t edl_max_evq_count;
1297 uint32_t edl_min_rxq_count;
1298 uint32_t edl_max_rxq_count;
1300 uint32_t edl_min_txq_count;
1301 uint32_t edl_max_txq_count;
1303 /* PIO blocks (sub-allocated from piobuf) */
1304 uint32_t edl_min_pio_alloc_size;
1305 uint32_t edl_max_pio_alloc_count;
1308 extern __checkReturn efx_rc_t
1309 efx_nic_set_drv_limits(
1310 __inout efx_nic_t *enp,
1311 __in efx_drv_limits_t *edlp);
1313 typedef enum efx_nic_region_e {
1314 EFX_REGION_VI, /* Memory BAR UC mapping */
1315 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1318 extern __checkReturn efx_rc_t
1319 efx_nic_get_bar_region(
1320 __in efx_nic_t *enp,
1321 __in efx_nic_region_t region,
1322 __out uint32_t *offsetp,
1323 __out size_t *sizep);
1325 extern __checkReturn efx_rc_t
1326 efx_nic_get_vi_pool(
1327 __in efx_nic_t *enp,
1328 __out uint32_t *evq_countp,
1329 __out uint32_t *rxq_countp,
1330 __out uint32_t *txq_countp);
1335 typedef enum efx_vpd_tag_e {
1342 typedef uint16_t efx_vpd_keyword_t;
1344 typedef struct efx_vpd_value_s {
1345 efx_vpd_tag_t evv_tag;
1346 efx_vpd_keyword_t evv_keyword;
1348 uint8_t evv_value[0x100];
1352 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1354 extern __checkReturn efx_rc_t
1356 __in efx_nic_t *enp);
1358 extern __checkReturn efx_rc_t
1360 __in efx_nic_t *enp,
1361 __out size_t *sizep);
1363 extern __checkReturn efx_rc_t
1365 __in efx_nic_t *enp,
1366 __out_bcount(size) caddr_t data,
1369 extern __checkReturn efx_rc_t
1371 __in efx_nic_t *enp,
1372 __in_bcount(size) caddr_t data,
1375 extern __checkReturn efx_rc_t
1377 __in efx_nic_t *enp,
1378 __in_bcount(size) caddr_t data,
1381 extern __checkReturn efx_rc_t
1383 __in efx_nic_t *enp,
1384 __in_bcount(size) caddr_t data,
1386 __inout efx_vpd_value_t *evvp);
1388 extern __checkReturn efx_rc_t
1390 __in efx_nic_t *enp,
1391 __inout_bcount(size) caddr_t data,
1393 __in efx_vpd_value_t *evvp);
1395 extern __checkReturn efx_rc_t
1397 __in efx_nic_t *enp,
1398 __inout_bcount(size) caddr_t data,
1400 __out efx_vpd_value_t *evvp,
1401 __inout unsigned int *contp);
1403 extern __checkReturn efx_rc_t
1405 __in efx_nic_t *enp,
1406 __in_bcount(size) caddr_t data,
1411 __in efx_nic_t *enp);
1413 #endif /* EFSYS_OPT_VPD */
1419 typedef enum efx_nvram_type_e {
1420 EFX_NVRAM_INVALID = 0,
1422 EFX_NVRAM_BOOTROM_CFG,
1423 EFX_NVRAM_MC_FIRMWARE,
1424 EFX_NVRAM_MC_GOLDEN,
1430 EFX_NVRAM_FPGA_BACKUP,
1431 EFX_NVRAM_DYNAMIC_CFG,
1434 EFX_NVRAM_MUM_FIRMWARE,
1438 extern __checkReturn efx_rc_t
1440 __in efx_nic_t *enp);
1444 extern __checkReturn efx_rc_t
1446 __in efx_nic_t *enp);
1448 #endif /* EFSYS_OPT_DIAG */
1450 extern __checkReturn efx_rc_t
1452 __in efx_nic_t *enp,
1453 __in efx_nvram_type_t type,
1454 __out size_t *sizep);
1456 extern __checkReturn efx_rc_t
1458 __in efx_nic_t *enp,
1459 __in efx_nvram_type_t type,
1460 __out_opt size_t *pref_chunkp);
1462 extern __checkReturn efx_rc_t
1463 efx_nvram_rw_finish(
1464 __in efx_nic_t *enp,
1465 __in efx_nvram_type_t type,
1466 __out_opt uint32_t *verify_resultp);
1468 extern __checkReturn efx_rc_t
1469 efx_nvram_get_version(
1470 __in efx_nic_t *enp,
1471 __in efx_nvram_type_t type,
1472 __out uint32_t *subtypep,
1473 __out_ecount(4) uint16_t version[4]);
1475 extern __checkReturn efx_rc_t
1476 efx_nvram_read_chunk(
1477 __in efx_nic_t *enp,
1478 __in efx_nvram_type_t type,
1479 __in unsigned int offset,
1480 __out_bcount(size) caddr_t data,
1483 extern __checkReturn efx_rc_t
1484 efx_nvram_read_backup(
1485 __in efx_nic_t *enp,
1486 __in efx_nvram_type_t type,
1487 __in unsigned int offset,
1488 __out_bcount(size) caddr_t data,
1491 extern __checkReturn efx_rc_t
1492 efx_nvram_set_version(
1493 __in efx_nic_t *enp,
1494 __in efx_nvram_type_t type,
1495 __in_ecount(4) uint16_t version[4]);
1497 extern __checkReturn efx_rc_t
1499 __in efx_nic_t *enp,
1500 __in efx_nvram_type_t type,
1501 __in_bcount(partn_size) caddr_t partn_data,
1502 __in size_t partn_size);
1504 extern __checkReturn efx_rc_t
1506 __in efx_nic_t *enp,
1507 __in efx_nvram_type_t type);
1509 extern __checkReturn efx_rc_t
1510 efx_nvram_write_chunk(
1511 __in efx_nic_t *enp,
1512 __in efx_nvram_type_t type,
1513 __in unsigned int offset,
1514 __in_bcount(size) caddr_t data,
1519 __in efx_nic_t *enp);
1521 #endif /* EFSYS_OPT_NVRAM */
1523 #if EFSYS_OPT_BOOTCFG
1525 /* Report size and offset of bootcfg sector in NVRAM partition. */
1526 extern __checkReturn efx_rc_t
1527 efx_bootcfg_sector_info(
1528 __in efx_nic_t *enp,
1530 __out_opt uint32_t *sector_countp,
1531 __out size_t *offsetp,
1532 __out size_t *max_sizep);
1535 * Copy bootcfg sector data to a target buffer which may differ in size.
1536 * Optionally corrects format errors in source buffer.
1539 efx_bootcfg_copy_sector(
1540 __in efx_nic_t *enp,
1541 __inout_bcount(sector_length)
1543 __in size_t sector_length,
1544 __out_bcount(data_size) uint8_t *data,
1545 __in size_t data_size,
1546 __in boolean_t handle_format_errors);
1550 __in efx_nic_t *enp,
1551 __out_bcount(size) uint8_t *data,
1556 __in efx_nic_t *enp,
1557 __in_bcount(size) uint8_t *data,
1560 #endif /* EFSYS_OPT_BOOTCFG */
1564 typedef enum efx_pattern_type_t {
1565 EFX_PATTERN_BYTE_INCREMENT = 0,
1566 EFX_PATTERN_ALL_THE_SAME,
1567 EFX_PATTERN_BIT_ALTERNATE,
1568 EFX_PATTERN_BYTE_ALTERNATE,
1569 EFX_PATTERN_BYTE_CHANGING,
1570 EFX_PATTERN_BIT_SWEEP,
1572 } efx_pattern_type_t;
1575 (*efx_sram_pattern_fn_t)(
1577 __in boolean_t negate,
1578 __out efx_qword_t *eqp);
1580 extern __checkReturn efx_rc_t
1582 __in efx_nic_t *enp,
1583 __in efx_pattern_type_t type);
1585 #endif /* EFSYS_OPT_DIAG */
1587 extern __checkReturn efx_rc_t
1588 efx_sram_buf_tbl_set(
1589 __in efx_nic_t *enp,
1591 __in efsys_mem_t *esmp,
1595 efx_sram_buf_tbl_clear(
1596 __in efx_nic_t *enp,
1600 #define EFX_BUF_TBL_SIZE 0x20000
1602 #define EFX_BUF_SIZE 4096
1606 typedef struct efx_evq_s efx_evq_t;
1608 #if EFSYS_OPT_QSTATS
1610 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1611 typedef enum efx_ev_qstat_e {
1617 EV_RX_PAUSE_FRM_ERR,
1618 EV_RX_BUF_OWNER_ID_ERR,
1619 EV_RX_IPV4_HDR_CHKSUM_ERR,
1620 EV_RX_TCP_UDP_CHKSUM_ERR,
1624 EV_RX_MCAST_HASH_MATCH,
1641 EV_DRIVER_SRM_UPD_DONE,
1642 EV_DRIVER_TX_DESCQ_FLS_DONE,
1643 EV_DRIVER_RX_DESCQ_FLS_DONE,
1644 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1645 EV_DRIVER_RX_DSC_ERROR,
1646 EV_DRIVER_TX_DSC_ERROR,
1652 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1654 #endif /* EFSYS_OPT_QSTATS */
1656 extern __checkReturn efx_rc_t
1658 __in efx_nic_t *enp);
1662 __in efx_nic_t *enp);
1664 #define EFX_EVQ_MAXNEVS 32768
1665 #define EFX_EVQ_MINNEVS 512
1667 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1668 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1670 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1671 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1672 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1673 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1675 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1676 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1677 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1679 extern __checkReturn efx_rc_t
1681 __in efx_nic_t *enp,
1682 __in unsigned int index,
1683 __in efsys_mem_t *esmp,
1687 __in uint32_t flags,
1688 __deref_out efx_evq_t **eepp);
1692 __in efx_evq_t *eep,
1693 __in uint16_t data);
1695 typedef __checkReturn boolean_t
1696 (*efx_initialized_ev_t)(
1697 __in_opt void *arg);
1699 #define EFX_PKT_UNICAST 0x0004
1700 #define EFX_PKT_START 0x0008
1702 #define EFX_PKT_VLAN_TAGGED 0x0010
1703 #define EFX_CKSUM_TCPUDP 0x0020
1704 #define EFX_CKSUM_IPV4 0x0040
1705 #define EFX_PKT_CONT 0x0080
1707 #define EFX_CHECK_VLAN 0x0100
1708 #define EFX_PKT_TCP 0x0200
1709 #define EFX_PKT_UDP 0x0400
1710 #define EFX_PKT_IPV4 0x0800
1712 #define EFX_PKT_IPV6 0x1000
1713 #define EFX_PKT_PREFIX_LEN 0x2000
1714 #define EFX_ADDR_MISMATCH 0x4000
1715 #define EFX_DISCARD 0x8000
1718 * The following flags are used only for packed stream
1719 * mode. The values for the flags are reused to fit into 16 bit,
1720 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1721 * packed stream mode
1723 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1724 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1727 #define EFX_EV_RX_NLABELS 32
1728 #define EFX_EV_TX_NLABELS 32
1730 typedef __checkReturn boolean_t
1733 __in uint32_t label,
1736 __in uint16_t flags);
1738 #if EFSYS_OPT_RX_PACKED_STREAM
1741 * Packed stream mode is documented in SF-112241-TC.
1742 * The general idea is that, instead of putting each incoming
1743 * packet into a separate buffer which is specified in a RX
1744 * descriptor, a large buffer is provided to the hardware and
1745 * packets are put there in a continuous stream.
1746 * The main advantage of such an approach is that RX queue refilling
1747 * happens much less frequently.
1750 typedef __checkReturn boolean_t
1753 __in uint32_t label,
1755 __in uint32_t pkt_count,
1756 __in uint16_t flags);
1760 typedef __checkReturn boolean_t
1763 __in uint32_t label,
1766 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1767 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1768 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1769 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1770 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1771 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1772 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1773 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1774 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1776 typedef __checkReturn boolean_t
1777 (*efx_exception_ev_t)(
1779 __in uint32_t label,
1780 __in uint32_t data);
1782 typedef __checkReturn boolean_t
1783 (*efx_rxq_flush_done_ev_t)(
1785 __in uint32_t rxq_index);
1787 typedef __checkReturn boolean_t
1788 (*efx_rxq_flush_failed_ev_t)(
1790 __in uint32_t rxq_index);
1792 typedef __checkReturn boolean_t
1793 (*efx_txq_flush_done_ev_t)(
1795 __in uint32_t txq_index);
1797 typedef __checkReturn boolean_t
1798 (*efx_software_ev_t)(
1800 __in uint16_t magic);
1802 typedef __checkReturn boolean_t
1805 __in uint32_t code);
1807 #define EFX_SRAM_CLEAR 0
1808 #define EFX_SRAM_UPDATE 1
1809 #define EFX_SRAM_ILLEGAL_CLEAR 2
1811 typedef __checkReturn boolean_t
1812 (*efx_wake_up_ev_t)(
1814 __in uint32_t label);
1816 typedef __checkReturn boolean_t
1819 __in uint32_t label);
1821 typedef __checkReturn boolean_t
1822 (*efx_link_change_ev_t)(
1824 __in efx_link_mode_t link_mode);
1826 #if EFSYS_OPT_MON_STATS
1828 typedef __checkReturn boolean_t
1829 (*efx_monitor_ev_t)(
1831 __in efx_mon_stat_t id,
1832 __in efx_mon_stat_value_t value);
1834 #endif /* EFSYS_OPT_MON_STATS */
1836 #if EFSYS_OPT_MAC_STATS
1838 typedef __checkReturn boolean_t
1839 (*efx_mac_stats_ev_t)(
1841 __in uint32_t generation);
1843 #endif /* EFSYS_OPT_MAC_STATS */
1845 typedef struct efx_ev_callbacks_s {
1846 efx_initialized_ev_t eec_initialized;
1848 #if EFSYS_OPT_RX_PACKED_STREAM
1849 efx_rx_ps_ev_t eec_rx_ps;
1852 efx_exception_ev_t eec_exception;
1853 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1854 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1855 efx_txq_flush_done_ev_t eec_txq_flush_done;
1856 efx_software_ev_t eec_software;
1857 efx_sram_ev_t eec_sram;
1858 efx_wake_up_ev_t eec_wake_up;
1859 efx_timer_ev_t eec_timer;
1860 efx_link_change_ev_t eec_link_change;
1861 #if EFSYS_OPT_MON_STATS
1862 efx_monitor_ev_t eec_monitor;
1863 #endif /* EFSYS_OPT_MON_STATS */
1864 #if EFSYS_OPT_MAC_STATS
1865 efx_mac_stats_ev_t eec_mac_stats;
1866 #endif /* EFSYS_OPT_MAC_STATS */
1867 } efx_ev_callbacks_t;
1869 extern __checkReturn boolean_t
1871 __in efx_evq_t *eep,
1872 __in unsigned int count);
1874 #if EFSYS_OPT_EV_PREFETCH
1878 __in efx_evq_t *eep,
1879 __in unsigned int count);
1881 #endif /* EFSYS_OPT_EV_PREFETCH */
1885 __in efx_evq_t *eep,
1886 __inout unsigned int *countp,
1887 __in const efx_ev_callbacks_t *eecp,
1888 __in_opt void *arg);
1890 extern __checkReturn efx_rc_t
1891 efx_ev_usecs_to_ticks(
1892 __in efx_nic_t *enp,
1893 __in unsigned int usecs,
1894 __out unsigned int *ticksp);
1896 extern __checkReturn efx_rc_t
1898 __in efx_evq_t *eep,
1899 __in unsigned int us);
1901 extern __checkReturn efx_rc_t
1903 __in efx_evq_t *eep,
1904 __in unsigned int count);
1906 #if EFSYS_OPT_QSTATS
1912 __in efx_nic_t *enp,
1913 __in unsigned int id);
1915 #endif /* EFSYS_OPT_NAMES */
1918 efx_ev_qstats_update(
1919 __in efx_evq_t *eep,
1920 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1922 #endif /* EFSYS_OPT_QSTATS */
1926 __in efx_evq_t *eep);
1930 extern __checkReturn efx_rc_t
1932 __inout efx_nic_t *enp);
1936 __in efx_nic_t *enp);
1938 #if EFSYS_OPT_RX_SCATTER
1939 __checkReturn efx_rc_t
1940 efx_rx_scatter_enable(
1941 __in efx_nic_t *enp,
1942 __in unsigned int buf_size);
1943 #endif /* EFSYS_OPT_RX_SCATTER */
1945 /* Handle to represent use of the default RSS context. */
1946 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1948 #if EFSYS_OPT_RX_SCALE
1950 typedef enum efx_rx_hash_alg_e {
1951 EFX_RX_HASHALG_LFSR = 0,
1952 EFX_RX_HASHALG_TOEPLITZ
1953 } efx_rx_hash_alg_t;
1955 #define EFX_RX_HASH_IPV4 (1U << 0)
1956 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1957 #define EFX_RX_HASH_IPV6 (1U << 2)
1958 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1960 typedef unsigned int efx_rx_hash_type_t;
1962 typedef enum efx_rx_hash_support_e {
1963 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1964 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1965 } efx_rx_hash_support_t;
1967 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1968 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1969 #define EFX_MAXRSS 64 /* RX indirection entry range */
1970 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1972 typedef enum efx_rx_scale_context_type_e {
1973 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1974 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1975 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1976 } efx_rx_scale_context_type_t;
1978 extern __checkReturn efx_rc_t
1979 efx_rx_hash_default_support_get(
1980 __in efx_nic_t *enp,
1981 __out efx_rx_hash_support_t *supportp);
1984 extern __checkReturn efx_rc_t
1985 efx_rx_scale_default_support_get(
1986 __in efx_nic_t *enp,
1987 __out efx_rx_scale_context_type_t *typep);
1989 extern __checkReturn efx_rc_t
1990 efx_rx_scale_context_alloc(
1991 __in efx_nic_t *enp,
1992 __in efx_rx_scale_context_type_t type,
1993 __in uint32_t num_queues,
1994 __out uint32_t *rss_contextp);
1996 extern __checkReturn efx_rc_t
1997 efx_rx_scale_context_free(
1998 __in efx_nic_t *enp,
1999 __in uint32_t rss_context);
2001 extern __checkReturn efx_rc_t
2002 efx_rx_scale_mode_set(
2003 __in efx_nic_t *enp,
2004 __in uint32_t rss_context,
2005 __in efx_rx_hash_alg_t alg,
2006 __in efx_rx_hash_type_t type,
2007 __in boolean_t insert);
2009 extern __checkReturn efx_rc_t
2010 efx_rx_scale_tbl_set(
2011 __in efx_nic_t *enp,
2012 __in uint32_t rss_context,
2013 __in_ecount(n) unsigned int *table,
2016 extern __checkReturn efx_rc_t
2017 efx_rx_scale_key_set(
2018 __in efx_nic_t *enp,
2019 __in uint32_t rss_context,
2020 __in_ecount(n) uint8_t *key,
2023 extern __checkReturn uint32_t
2024 efx_pseudo_hdr_hash_get(
2025 __in efx_rxq_t *erp,
2026 __in efx_rx_hash_alg_t func,
2027 __in uint8_t *buffer);
2029 #endif /* EFSYS_OPT_RX_SCALE */
2031 extern __checkReturn efx_rc_t
2032 efx_pseudo_hdr_pkt_length_get(
2033 __in efx_rxq_t *erp,
2034 __in uint8_t *buffer,
2035 __out uint16_t *pkt_lengthp);
2037 #define EFX_RXQ_MAXNDESCS 4096
2038 #define EFX_RXQ_MINNDESCS 512
2040 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2041 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2042 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2043 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2045 typedef enum efx_rxq_type_e {
2046 EFX_RXQ_TYPE_DEFAULT,
2047 EFX_RXQ_TYPE_PACKED_STREAM,
2052 * Dummy flag to be used instead of 0 to make it clear that the argument
2053 * is receive queue flags.
2055 #define EFX_RXQ_FLAG_NONE 0x0
2056 #define EFX_RXQ_FLAG_SCATTER 0x1
2058 * If tunnels are supported and Rx event can provide information about
2059 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2060 * full-feature firmware variant running), outer classes are requested by
2061 * default. However, if the driver supports tunnels, the flag allows to
2062 * request inner classes which are required to be able to interpret inner
2063 * Rx checksum offload results.
2065 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2067 extern __checkReturn efx_rc_t
2069 __in efx_nic_t *enp,
2070 __in unsigned int index,
2071 __in unsigned int label,
2072 __in efx_rxq_type_t type,
2073 __in efsys_mem_t *esmp,
2076 __in unsigned int flags,
2077 __in efx_evq_t *eep,
2078 __deref_out efx_rxq_t **erpp);
2080 #if EFSYS_OPT_RX_PACKED_STREAM
2082 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2083 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2084 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2085 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2086 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2088 extern __checkReturn efx_rc_t
2089 efx_rx_qcreate_packed_stream(
2090 __in efx_nic_t *enp,
2091 __in unsigned int index,
2092 __in unsigned int label,
2093 __in uint32_t ps_buf_size,
2094 __in efsys_mem_t *esmp,
2096 __in efx_evq_t *eep,
2097 __deref_out efx_rxq_t **erpp);
2101 typedef struct efx_buffer_s {
2102 efsys_dma_addr_t eb_addr;
2107 typedef struct efx_desc_s {
2113 __in efx_rxq_t *erp,
2114 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2116 __in unsigned int ndescs,
2117 __in unsigned int completed,
2118 __in unsigned int added);
2122 __in efx_rxq_t *erp,
2123 __in unsigned int added,
2124 __inout unsigned int *pushedp);
2126 #if EFSYS_OPT_RX_PACKED_STREAM
2129 efx_rx_qpush_ps_credits(
2130 __in efx_rxq_t *erp);
2132 extern __checkReturn uint8_t *
2133 efx_rx_qps_packet_info(
2134 __in efx_rxq_t *erp,
2135 __in uint8_t *buffer,
2136 __in uint32_t buffer_length,
2137 __in uint32_t current_offset,
2138 __out uint16_t *lengthp,
2139 __out uint32_t *next_offsetp,
2140 __out uint32_t *timestamp);
2143 extern __checkReturn efx_rc_t
2145 __in efx_rxq_t *erp);
2149 __in efx_rxq_t *erp);
2153 __in efx_rxq_t *erp);
2157 typedef struct efx_txq_s efx_txq_t;
2159 #if EFSYS_OPT_QSTATS
2161 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2162 typedef enum efx_tx_qstat_e {
2168 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2170 #endif /* EFSYS_OPT_QSTATS */
2172 extern __checkReturn efx_rc_t
2174 __in efx_nic_t *enp);
2178 __in efx_nic_t *enp);
2180 #define EFX_TXQ_MINNDESCS 512
2182 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2183 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2184 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2186 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2188 #define EFX_TXQ_CKSUM_IPV4 0x0001
2189 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2190 #define EFX_TXQ_FATSOV2 0x0004
2191 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2192 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2194 extern __checkReturn efx_rc_t
2196 __in efx_nic_t *enp,
2197 __in unsigned int index,
2198 __in unsigned int label,
2199 __in efsys_mem_t *esmp,
2202 __in uint16_t flags,
2203 __in efx_evq_t *eep,
2204 __deref_out efx_txq_t **etpp,
2205 __out unsigned int *addedp);
2207 extern __checkReturn efx_rc_t
2209 __in efx_txq_t *etp,
2210 __in_ecount(ndescs) efx_buffer_t *eb,
2211 __in unsigned int ndescs,
2212 __in unsigned int completed,
2213 __inout unsigned int *addedp);
2215 extern __checkReturn efx_rc_t
2217 __in efx_txq_t *etp,
2218 __in unsigned int ns);
2222 __in efx_txq_t *etp,
2223 __in unsigned int added,
2224 __in unsigned int pushed);
2226 extern __checkReturn efx_rc_t
2228 __in efx_txq_t *etp);
2232 __in efx_txq_t *etp);
2234 extern __checkReturn efx_rc_t
2236 __in efx_txq_t *etp);
2239 efx_tx_qpio_disable(
2240 __in efx_txq_t *etp);
2242 extern __checkReturn efx_rc_t
2244 __in efx_txq_t *etp,
2245 __in_ecount(buf_length) uint8_t *buffer,
2246 __in size_t buf_length,
2247 __in size_t pio_buf_offset);
2249 extern __checkReturn efx_rc_t
2251 __in efx_txq_t *etp,
2252 __in size_t pkt_length,
2253 __in unsigned int completed,
2254 __inout unsigned int *addedp);
2256 extern __checkReturn efx_rc_t
2258 __in efx_txq_t *etp,
2259 __in_ecount(n) efx_desc_t *ed,
2260 __in unsigned int n,
2261 __in unsigned int completed,
2262 __inout unsigned int *addedp);
2265 efx_tx_qdesc_dma_create(
2266 __in efx_txq_t *etp,
2267 __in efsys_dma_addr_t addr,
2270 __out efx_desc_t *edp);
2273 efx_tx_qdesc_tso_create(
2274 __in efx_txq_t *etp,
2275 __in uint16_t ipv4_id,
2276 __in uint32_t tcp_seq,
2277 __in uint8_t tcp_flags,
2278 __out efx_desc_t *edp);
2280 /* Number of FATSOv2 option descriptors */
2281 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2283 /* Maximum number of DMA segments per TSO packet (not superframe) */
2284 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2287 efx_tx_qdesc_tso2_create(
2288 __in efx_txq_t *etp,
2289 __in uint16_t ipv4_id,
2290 __in uint32_t tcp_seq,
2291 __in uint16_t tcp_mss,
2292 __out_ecount(count) efx_desc_t *edp,
2296 efx_tx_qdesc_vlantci_create(
2297 __in efx_txq_t *etp,
2299 __out efx_desc_t *edp);
2302 efx_tx_qdesc_checksum_create(
2303 __in efx_txq_t *etp,
2304 __in uint16_t flags,
2305 __out efx_desc_t *edp);
2307 #if EFSYS_OPT_QSTATS
2313 __in efx_nic_t *etp,
2314 __in unsigned int id);
2316 #endif /* EFSYS_OPT_NAMES */
2319 efx_tx_qstats_update(
2320 __in efx_txq_t *etp,
2321 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2323 #endif /* EFSYS_OPT_QSTATS */
2327 __in efx_txq_t *etp);
2332 #if EFSYS_OPT_FILTER
2334 #define EFX_ETHER_TYPE_IPV4 0x0800
2335 #define EFX_ETHER_TYPE_IPV6 0x86DD
2337 #define EFX_IPPROTO_TCP 6
2338 #define EFX_IPPROTO_UDP 17
2339 #define EFX_IPPROTO_GRE 47
2341 /* Use RSS to spread across multiple queues */
2342 #define EFX_FILTER_FLAG_RX_RSS 0x01
2343 /* Enable RX scatter */
2344 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2346 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2347 * May only be set by the filter implementation for each type.
2348 * A removal request will restore the automatic filter in its place.
2350 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2351 /* Filter is for RX */
2352 #define EFX_FILTER_FLAG_RX 0x08
2353 /* Filter is for TX */
2354 #define EFX_FILTER_FLAG_TX 0x10
2356 typedef uint8_t efx_filter_flags_t;
2359 * Flags which specify the fields to match on. The values are the same as in the
2360 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2363 /* Match by remote IP host address */
2364 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2365 /* Match by local IP host address */
2366 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2367 /* Match by remote MAC address */
2368 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2369 /* Match by remote TCP/UDP port */
2370 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2371 /* Match by remote TCP/UDP port */
2372 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2373 /* Match by local TCP/UDP port */
2374 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2375 /* Match by Ether-type */
2376 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2377 /* Match by inner VLAN ID */
2378 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2379 /* Match by outer VLAN ID */
2380 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2381 /* Match by IP transport protocol */
2382 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2383 /* For encapsulated packets, match all multicast inner frames */
2384 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2385 /* For encapsulated packets, match all unicast inner frames */
2386 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2387 /* Match otherwise-unmatched multicast and broadcast packets */
2388 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2389 /* Match otherwise-unmatched unicast packets */
2390 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2392 typedef uint32_t efx_filter_match_flags_t;
2394 typedef enum efx_filter_priority_s {
2395 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2396 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2397 * address list or hardware
2398 * requirements. This may only be used
2399 * by the filter implementation for
2401 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2402 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2403 * client (e.g. SR-IOV, HyperV VMQ etc.)
2405 } efx_filter_priority_t;
2408 * FIXME: All these fields are assumed to be in little-endian byte order.
2409 * It may be better for some to be big-endian. See bug42804.
2412 typedef struct efx_filter_spec_s {
2413 efx_filter_match_flags_t efs_match_flags;
2414 uint8_t efs_priority;
2415 efx_filter_flags_t efs_flags;
2416 uint16_t efs_dmaq_id;
2417 uint32_t efs_rss_context;
2418 uint16_t efs_outer_vid;
2419 uint16_t efs_inner_vid;
2420 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2421 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2422 uint16_t efs_ether_type;
2423 uint8_t efs_ip_proto;
2424 efx_tunnel_protocol_t efs_encap_type;
2425 uint16_t efs_loc_port;
2426 uint16_t efs_rem_port;
2427 efx_oword_t efs_rem_host;
2428 efx_oword_t efs_loc_host;
2429 } efx_filter_spec_t;
2432 /* Default values for use in filter specifications */
2433 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2434 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2436 extern __checkReturn efx_rc_t
2438 __in efx_nic_t *enp);
2442 __in efx_nic_t *enp);
2444 extern __checkReturn efx_rc_t
2446 __in efx_nic_t *enp,
2447 __inout efx_filter_spec_t *spec);
2449 extern __checkReturn efx_rc_t
2451 __in efx_nic_t *enp,
2452 __inout efx_filter_spec_t *spec);
2454 extern __checkReturn efx_rc_t
2456 __in efx_nic_t *enp);
2458 extern __checkReturn efx_rc_t
2459 efx_filter_supported_filters(
2460 __in efx_nic_t *enp,
2461 __out_ecount(buffer_length) uint32_t *buffer,
2462 __in size_t buffer_length,
2463 __out size_t *list_lengthp);
2466 efx_filter_spec_init_rx(
2467 __out efx_filter_spec_t *spec,
2468 __in efx_filter_priority_t priority,
2469 __in efx_filter_flags_t flags,
2470 __in efx_rxq_t *erp);
2473 efx_filter_spec_init_tx(
2474 __out efx_filter_spec_t *spec,
2475 __in efx_txq_t *etp);
2477 extern __checkReturn efx_rc_t
2478 efx_filter_spec_set_ipv4_local(
2479 __inout efx_filter_spec_t *spec,
2482 __in uint16_t port);
2484 extern __checkReturn efx_rc_t
2485 efx_filter_spec_set_ipv4_full(
2486 __inout efx_filter_spec_t *spec,
2488 __in uint32_t lhost,
2489 __in uint16_t lport,
2490 __in uint32_t rhost,
2491 __in uint16_t rport);
2493 extern __checkReturn efx_rc_t
2494 efx_filter_spec_set_eth_local(
2495 __inout efx_filter_spec_t *spec,
2497 __in const uint8_t *addr);
2500 efx_filter_spec_set_ether_type(
2501 __inout efx_filter_spec_t *spec,
2502 __in uint16_t ether_type);
2504 extern __checkReturn efx_rc_t
2505 efx_filter_spec_set_uc_def(
2506 __inout efx_filter_spec_t *spec);
2508 extern __checkReturn efx_rc_t
2509 efx_filter_spec_set_mc_def(
2510 __inout efx_filter_spec_t *spec);
2512 typedef enum efx_filter_inner_frame_match_e {
2513 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2514 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2515 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2516 } efx_filter_inner_frame_match_t;
2518 extern __checkReturn efx_rc_t
2519 efx_filter_spec_set_encap_type(
2520 __inout efx_filter_spec_t *spec,
2521 __in efx_tunnel_protocol_t encap_type,
2522 __in efx_filter_inner_frame_match_t inner_frame_match);
2524 #if EFSYS_OPT_RX_SCALE
2525 extern __checkReturn efx_rc_t
2526 efx_filter_spec_set_rss_context(
2527 __inout efx_filter_spec_t *spec,
2528 __in uint32_t rss_context);
2530 #endif /* EFSYS_OPT_FILTER */
2534 extern __checkReturn uint32_t
2536 __in_ecount(count) uint32_t const *input,
2538 __in uint32_t init);
2540 extern __checkReturn uint32_t
2542 __in_ecount(length) uint8_t const *input,
2544 __in uint32_t init);
2546 #if EFSYS_OPT_LICENSING
2550 typedef struct efx_key_stats_s {
2552 uint32_t eks_invalid;
2553 uint32_t eks_blacklisted;
2554 uint32_t eks_unverifiable;
2555 uint32_t eks_wrong_node;
2556 uint32_t eks_licensed_apps_lo;
2557 uint32_t eks_licensed_apps_hi;
2558 uint32_t eks_licensed_features_lo;
2559 uint32_t eks_licensed_features_hi;
2562 extern __checkReturn efx_rc_t
2564 __in efx_nic_t *enp);
2568 __in efx_nic_t *enp);
2570 extern __checkReturn boolean_t
2571 efx_lic_check_support(
2572 __in efx_nic_t *enp);
2574 extern __checkReturn efx_rc_t
2575 efx_lic_update_licenses(
2576 __in efx_nic_t *enp);
2578 extern __checkReturn efx_rc_t
2579 efx_lic_get_key_stats(
2580 __in efx_nic_t *enp,
2581 __out efx_key_stats_t *ksp);
2583 extern __checkReturn efx_rc_t
2585 __in efx_nic_t *enp,
2586 __in uint64_t app_id,
2587 __out boolean_t *licensedp);
2589 extern __checkReturn efx_rc_t
2591 __in efx_nic_t *enp,
2592 __in size_t buffer_size,
2593 __out uint32_t *typep,
2594 __out size_t *lengthp,
2595 __out_opt uint8_t *bufferp);
2598 extern __checkReturn efx_rc_t
2600 __in efx_nic_t *enp,
2601 __in_bcount(buffer_size)
2603 __in size_t buffer_size,
2604 __out uint32_t *startp);
2606 extern __checkReturn efx_rc_t
2608 __in efx_nic_t *enp,
2609 __in_bcount(buffer_size)
2611 __in size_t buffer_size,
2612 __in uint32_t offset,
2613 __out uint32_t *endp);
2615 extern __checkReturn __success(return != B_FALSE) boolean_t
2617 __in efx_nic_t *enp,
2618 __in_bcount(buffer_size)
2620 __in size_t buffer_size,
2621 __in uint32_t offset,
2622 __out uint32_t *startp,
2623 __out uint32_t *lengthp);
2625 extern __checkReturn __success(return != B_FALSE) boolean_t
2626 efx_lic_validate_key(
2627 __in efx_nic_t *enp,
2628 __in_bcount(length) caddr_t keyp,
2629 __in uint32_t length);
2631 extern __checkReturn efx_rc_t
2633 __in efx_nic_t *enp,
2634 __in_bcount(buffer_size)
2636 __in size_t buffer_size,
2637 __in uint32_t offset,
2638 __in uint32_t length,
2639 __out_bcount_part(key_max_size, *lengthp)
2641 __in size_t key_max_size,
2642 __out uint32_t *lengthp);
2644 extern __checkReturn efx_rc_t
2646 __in efx_nic_t *enp,
2647 __in_bcount(buffer_size)
2649 __in size_t buffer_size,
2650 __in uint32_t offset,
2651 __in_bcount(length) caddr_t keyp,
2652 __in uint32_t length,
2653 __out uint32_t *lengthp);
2655 __checkReturn efx_rc_t
2657 __in efx_nic_t *enp,
2658 __in_bcount(buffer_size)
2660 __in size_t buffer_size,
2661 __in uint32_t offset,
2662 __in uint32_t length,
2664 __out uint32_t *deltap);
2666 extern __checkReturn efx_rc_t
2667 efx_lic_create_partition(
2668 __in efx_nic_t *enp,
2669 __in_bcount(buffer_size)
2671 __in size_t buffer_size);
2673 extern __checkReturn efx_rc_t
2674 efx_lic_finish_partition(
2675 __in efx_nic_t *enp,
2676 __in_bcount(buffer_size)
2678 __in size_t buffer_size);
2680 #endif /* EFSYS_OPT_LICENSING */
2684 #if EFSYS_OPT_TUNNEL
2686 extern __checkReturn efx_rc_t
2688 __in efx_nic_t *enp);
2692 __in efx_nic_t *enp);
2695 * For overlay network encapsulation using UDP, the firmware needs to know
2696 * the configured UDP port for the overlay so it can decode encapsulated
2698 * The UDP port/protocol list is global.
2701 extern __checkReturn efx_rc_t
2702 efx_tunnel_config_udp_add(
2703 __in efx_nic_t *enp,
2704 __in uint16_t port /* host/cpu-endian */,
2705 __in efx_tunnel_protocol_t protocol);
2707 extern __checkReturn efx_rc_t
2708 efx_tunnel_config_udp_remove(
2709 __in efx_nic_t *enp,
2710 __in uint16_t port /* host/cpu-endian */,
2711 __in efx_tunnel_protocol_t protocol);
2714 efx_tunnel_config_clear(
2715 __in efx_nic_t *enp);
2718 * Apply tunnel UDP ports configuration to hardware.
2720 * EAGAIN is returned if hardware will be reset (datapath and management CPU
2723 extern __checkReturn efx_rc_t
2724 efx_tunnel_reconfigure(
2725 __in efx_nic_t *enp);
2727 #endif /* EFSYS_OPT_TUNNEL */
2734 #endif /* _SYS_EFX_H */