2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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39 #include "efx_check.h"
40 #include "efx_phy_ids.h"
46 #define EFX_STATIC_ASSERT(_cond) \
47 ((void)sizeof (char[(_cond) ? 1 : -1]))
49 #define EFX_ARRAY_SIZE(_array) \
50 (sizeof (_array) / sizeof ((_array)[0]))
52 #define EFX_FIELD_OFFSET(_type, _field) \
53 ((size_t)&(((_type *)0)->_field))
55 /* The macro expands divider twice */
56 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
60 typedef __success(return == 0) int efx_rc_t;
65 typedef enum efx_family_e {
67 EFX_FAMILY_FALCON, /* Obsolete and not supported */
69 EFX_FAMILY_HUNTINGTON,
75 extern __checkReturn efx_rc_t
79 __out efx_family_t *efp,
80 __out unsigned int *membarp);
83 #define EFX_PCI_VENID_SFC 0x1924
85 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
87 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
88 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
89 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
91 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
92 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
93 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
95 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
96 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
98 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
99 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
100 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
103 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
104 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
107 #define EFX_MEM_BAR_SIENA 2
109 #define EFX_MEM_BAR_HUNTINGTON_PF 2
110 #define EFX_MEM_BAR_HUNTINGTON_VF 0
112 #define EFX_MEM_BAR_MEDFORD_PF 2
113 #define EFX_MEM_BAR_MEDFORD_VF 0
115 #define EFX_MEM_BAR_MEDFORD2 0
123 EFX_ERR_BUFID_DC_OOB,
136 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
137 extern __checkReturn uint32_t
139 __in uint32_t crc_init,
140 __in_ecount(length) uint8_t const *input,
144 /* Type prototypes */
146 typedef struct efx_rxq_s efx_rxq_t;
150 typedef struct efx_nic_s efx_nic_t;
152 extern __checkReturn efx_rc_t
154 __in efx_family_t family,
155 __in efsys_identifier_t *esip,
156 __in efsys_bar_t *esbp,
157 __in efsys_lock_t *eslp,
158 __deref_out efx_nic_t **enpp);
160 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
161 typedef enum efx_fw_variant_e {
162 EFX_FW_VARIANT_FULL_FEATURED,
163 EFX_FW_VARIANT_LOW_LATENCY,
164 EFX_FW_VARIANT_PACKED_STREAM,
165 EFX_FW_VARIANT_HIGH_TX_RATE,
166 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
167 EFX_FW_VARIANT_RULES_ENGINE,
169 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
172 extern __checkReturn efx_rc_t
175 __in efx_fw_variant_t efv);
177 extern __checkReturn efx_rc_t
179 __in efx_nic_t *enp);
181 extern __checkReturn efx_rc_t
183 __in efx_nic_t *enp);
187 extern __checkReturn efx_rc_t
188 efx_nic_register_test(
189 __in efx_nic_t *enp);
191 #endif /* EFSYS_OPT_DIAG */
195 __in efx_nic_t *enp);
199 __in efx_nic_t *enp);
203 __in efx_nic_t *enp);
205 #define EFX_PCIE_LINK_SPEED_GEN1 1
206 #define EFX_PCIE_LINK_SPEED_GEN2 2
207 #define EFX_PCIE_LINK_SPEED_GEN3 3
209 typedef enum efx_pcie_link_performance_e {
210 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
211 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
212 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
213 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
214 } efx_pcie_link_performance_t;
216 extern __checkReturn efx_rc_t
217 efx_nic_calculate_pcie_link_bandwidth(
218 __in uint32_t pcie_link_width,
219 __in uint32_t pcie_link_gen,
220 __out uint32_t *bandwidth_mbpsp);
222 extern __checkReturn efx_rc_t
223 efx_nic_check_pcie_link_speed(
225 __in uint32_t pcie_link_width,
226 __in uint32_t pcie_link_gen,
227 __out efx_pcie_link_performance_t *resultp);
231 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
232 /* Huntington and Medford require MCDIv2 commands */
233 #define WITH_MCDI_V2 1
236 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
238 typedef enum efx_mcdi_exception_e {
239 EFX_MCDI_EXCEPTION_MC_REBOOT,
240 EFX_MCDI_EXCEPTION_MC_BADASSERT,
241 } efx_mcdi_exception_t;
243 #if EFSYS_OPT_MCDI_LOGGING
244 typedef enum efx_log_msg_e {
246 EFX_LOG_MCDI_REQUEST,
247 EFX_LOG_MCDI_RESPONSE,
249 #endif /* EFSYS_OPT_MCDI_LOGGING */
251 typedef struct efx_mcdi_transport_s {
253 efsys_mem_t *emt_dma_mem;
254 void (*emt_execute)(void *, efx_mcdi_req_t *);
255 void (*emt_ev_cpl)(void *);
256 void (*emt_exception)(void *, efx_mcdi_exception_t);
257 #if EFSYS_OPT_MCDI_LOGGING
258 void (*emt_logger)(void *, efx_log_msg_t,
259 void *, size_t, void *, size_t);
260 #endif /* EFSYS_OPT_MCDI_LOGGING */
261 #if EFSYS_OPT_MCDI_PROXY_AUTH
262 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
263 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
264 } efx_mcdi_transport_t;
266 extern __checkReturn efx_rc_t
269 __in const efx_mcdi_transport_t *mtp);
271 extern __checkReturn efx_rc_t
273 __in efx_nic_t *enp);
277 __in efx_nic_t *enp);
280 efx_mcdi_get_timeout(
282 __in efx_mcdi_req_t *emrp,
283 __out uint32_t *usec_timeoutp);
286 efx_mcdi_request_start(
288 __in efx_mcdi_req_t *emrp,
289 __in boolean_t ev_cpl);
291 extern __checkReturn boolean_t
292 efx_mcdi_request_poll(
293 __in efx_nic_t *enp);
295 extern __checkReturn boolean_t
296 efx_mcdi_request_abort(
297 __in efx_nic_t *enp);
301 __in efx_nic_t *enp);
303 #endif /* EFSYS_OPT_MCDI */
307 #define EFX_NINTR_SIENA 1024
309 typedef enum efx_intr_type_e {
310 EFX_INTR_INVALID = 0,
316 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
318 extern __checkReturn efx_rc_t
321 __in efx_intr_type_t type,
322 __in efsys_mem_t *esmp);
326 __in efx_nic_t *enp);
330 __in efx_nic_t *enp);
333 efx_intr_disable_unlocked(
334 __in efx_nic_t *enp);
336 #define EFX_INTR_NEVQS 32
338 extern __checkReturn efx_rc_t
341 __in unsigned int level);
344 efx_intr_status_line(
346 __out boolean_t *fatalp,
347 __out uint32_t *maskp);
350 efx_intr_status_message(
352 __in unsigned int message,
353 __out boolean_t *fatalp);
357 __in efx_nic_t *enp);
361 __in efx_nic_t *enp);
365 #if EFSYS_OPT_MAC_STATS
367 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7d59c0d68431a5d1 */
368 typedef enum efx_mac_stat_e {
371 EFX_MAC_RX_UNICST_PKTS,
372 EFX_MAC_RX_MULTICST_PKTS,
373 EFX_MAC_RX_BRDCST_PKTS,
374 EFX_MAC_RX_PAUSE_PKTS,
375 EFX_MAC_RX_LE_64_PKTS,
376 EFX_MAC_RX_65_TO_127_PKTS,
377 EFX_MAC_RX_128_TO_255_PKTS,
378 EFX_MAC_RX_256_TO_511_PKTS,
379 EFX_MAC_RX_512_TO_1023_PKTS,
380 EFX_MAC_RX_1024_TO_15XX_PKTS,
381 EFX_MAC_RX_GE_15XX_PKTS,
383 EFX_MAC_RX_FCS_ERRORS,
384 EFX_MAC_RX_DROP_EVENTS,
385 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
386 EFX_MAC_RX_SYMBOL_ERRORS,
387 EFX_MAC_RX_ALIGN_ERRORS,
388 EFX_MAC_RX_INTERNAL_ERRORS,
389 EFX_MAC_RX_JABBER_PKTS,
390 EFX_MAC_RX_LANE0_CHAR_ERR,
391 EFX_MAC_RX_LANE1_CHAR_ERR,
392 EFX_MAC_RX_LANE2_CHAR_ERR,
393 EFX_MAC_RX_LANE3_CHAR_ERR,
394 EFX_MAC_RX_LANE0_DISP_ERR,
395 EFX_MAC_RX_LANE1_DISP_ERR,
396 EFX_MAC_RX_LANE2_DISP_ERR,
397 EFX_MAC_RX_LANE3_DISP_ERR,
398 EFX_MAC_RX_MATCH_FAULT,
399 EFX_MAC_RX_NODESC_DROP_CNT,
402 EFX_MAC_TX_UNICST_PKTS,
403 EFX_MAC_TX_MULTICST_PKTS,
404 EFX_MAC_TX_BRDCST_PKTS,
405 EFX_MAC_TX_PAUSE_PKTS,
406 EFX_MAC_TX_LE_64_PKTS,
407 EFX_MAC_TX_65_TO_127_PKTS,
408 EFX_MAC_TX_128_TO_255_PKTS,
409 EFX_MAC_TX_256_TO_511_PKTS,
410 EFX_MAC_TX_512_TO_1023_PKTS,
411 EFX_MAC_TX_1024_TO_15XX_PKTS,
412 EFX_MAC_TX_GE_15XX_PKTS,
414 EFX_MAC_TX_SGL_COL_PKTS,
415 EFX_MAC_TX_MULT_COL_PKTS,
416 EFX_MAC_TX_EX_COL_PKTS,
417 EFX_MAC_TX_LATE_COL_PKTS,
419 EFX_MAC_TX_EX_DEF_PKTS,
420 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
421 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
422 EFX_MAC_PM_TRUNC_VFIFO_FULL,
423 EFX_MAC_PM_DISCARD_VFIFO_FULL,
424 EFX_MAC_PM_TRUNC_QBB,
425 EFX_MAC_PM_DISCARD_QBB,
426 EFX_MAC_PM_DISCARD_MAPPING,
427 EFX_MAC_RXDP_Q_DISABLED_PKTS,
428 EFX_MAC_RXDP_DI_DROPPED_PKTS,
429 EFX_MAC_RXDP_STREAMING_PKTS,
430 EFX_MAC_RXDP_HLB_FETCH,
431 EFX_MAC_RXDP_HLB_WAIT,
432 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
433 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
434 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
435 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
436 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
437 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
438 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
439 EFX_MAC_VADAPTER_RX_BAD_BYTES,
440 EFX_MAC_VADAPTER_RX_OVERFLOW,
441 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
442 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
443 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
444 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
445 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
446 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
447 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
448 EFX_MAC_VADAPTER_TX_BAD_BYTES,
449 EFX_MAC_VADAPTER_TX_OVERFLOW,
450 EFX_MAC_FEC_UNCORRECTED_ERRORS,
451 EFX_MAC_FEC_CORRECTED_ERRORS,
452 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
453 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
454 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
455 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
456 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
457 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
458 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
459 EFX_MAC_CTPIO_OVERFLOW_FAIL,
460 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
461 EFX_MAC_CTPIO_TIMEOUT_FAIL,
462 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
463 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
464 EFX_MAC_CTPIO_INVALID_WR_FAIL,
465 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
466 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
467 EFX_MAC_CTPIO_RUNT_FALLBACK,
468 EFX_MAC_CTPIO_SUCCESS,
469 EFX_MAC_CTPIO_FALLBACK,
470 EFX_MAC_CTPIO_POISON,
475 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
477 #endif /* EFSYS_OPT_MAC_STATS */
479 typedef enum efx_link_mode_e {
480 EFX_LINK_UNKNOWN = 0,
496 #define EFX_MAC_ADDR_LEN 6
498 #define EFX_VNI_OR_VSID_LEN 3
500 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
502 #define EFX_MAC_MULTICAST_LIST_MAX 256
504 #define EFX_MAC_SDU_MAX 9202
506 #define EFX_MAC_PDU_ADJUSTMENT \
510 + /* bug16011 */ 16) \
512 #define EFX_MAC_PDU(_sdu) \
513 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
516 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
517 * the SDU rounded up slightly.
519 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
521 #define EFX_MAC_PDU_MIN 60
522 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
524 extern __checkReturn efx_rc_t
529 extern __checkReturn efx_rc_t
534 extern __checkReturn efx_rc_t
539 extern __checkReturn efx_rc_t
542 __in boolean_t all_unicst,
543 __in boolean_t mulcst,
544 __in boolean_t all_mulcst,
545 __in boolean_t brdcst);
547 extern __checkReturn efx_rc_t
548 efx_mac_multicast_list_set(
550 __in_ecount(6*count) uint8_t const *addrs,
553 extern __checkReturn efx_rc_t
554 efx_mac_filter_default_rxq_set(
557 __in boolean_t using_rss);
560 efx_mac_filter_default_rxq_clear(
561 __in efx_nic_t *enp);
563 extern __checkReturn efx_rc_t
566 __in boolean_t enabled);
568 extern __checkReturn efx_rc_t
571 __out boolean_t *mac_upp);
573 #define EFX_FCNTL_RESPOND 0x00000001
574 #define EFX_FCNTL_GENERATE 0x00000002
576 extern __checkReturn efx_rc_t
579 __in unsigned int fcntl,
580 __in boolean_t autoneg);
585 __out unsigned int *fcntl_wantedp,
586 __out unsigned int *fcntl_linkp);
589 #if EFSYS_OPT_MAC_STATS
593 extern __checkReturn const char *
596 __in unsigned int id);
598 #endif /* EFSYS_OPT_NAMES */
600 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
602 #define EFX_MAC_STATS_MASK_NPAGES \
603 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
604 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
607 * Get mask of MAC statistics supported by the hardware.
609 * If mask_size is insufficient to return the mask, EINVAL error is
610 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
611 * (which is sizeof (uint32_t)) is sufficient.
613 extern __checkReturn efx_rc_t
614 efx_mac_stats_get_mask(
616 __out_bcount(mask_size) uint32_t *maskp,
617 __in size_t mask_size);
619 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
620 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
621 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
624 extern __checkReturn efx_rc_t
626 __in efx_nic_t *enp);
629 * Upload mac statistics supported by the hardware into the given buffer.
631 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
632 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
634 * The hardware will only DMA statistics that it understands (of course).
635 * Drivers should not make any assumptions about which statistics are
636 * supported, especially when the statistics are generated by firmware.
638 * Thus, drivers should zero this buffer before use, so that not-understood
639 * statistics read back as zero.
641 extern __checkReturn efx_rc_t
642 efx_mac_stats_upload(
644 __in efsys_mem_t *esmp);
646 extern __checkReturn efx_rc_t
647 efx_mac_stats_periodic(
649 __in efsys_mem_t *esmp,
650 __in uint16_t period_ms,
651 __in boolean_t events);
653 extern __checkReturn efx_rc_t
654 efx_mac_stats_update(
656 __in efsys_mem_t *esmp,
657 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
658 __inout_opt uint32_t *generationp);
660 #endif /* EFSYS_OPT_MAC_STATS */
664 typedef enum efx_mon_type_e {
676 __in efx_nic_t *enp);
678 #endif /* EFSYS_OPT_NAMES */
680 extern __checkReturn efx_rc_t
682 __in efx_nic_t *enp);
684 #if EFSYS_OPT_MON_STATS
686 #define EFX_MON_STATS_PAGE_SIZE 0x100
687 #define EFX_MON_MASK_ELEMENT_SIZE 32
689 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
690 typedef enum efx_mon_stat_e {
697 EFX_MON_STAT_EXT_TEMP,
698 EFX_MON_STAT_INT_TEMP,
701 EFX_MON_STAT_INT_COOLING,
702 EFX_MON_STAT_EXT_COOLING,
710 EFX_MON_STAT_AOE_TEMP,
711 EFX_MON_STAT_PSU_AOE_TEMP,
712 EFX_MON_STAT_PSU_TEMP,
718 EFX_MON_STAT_VAOE_IN,
720 EFX_MON_STAT_IAOE_IN,
721 EFX_MON_STAT_NIC_POWER,
725 EFX_MON_STAT_0_9V_ADC,
726 EFX_MON_STAT_INT_TEMP2,
727 EFX_MON_STAT_VREG_TEMP,
728 EFX_MON_STAT_VREG_0_9V_TEMP,
729 EFX_MON_STAT_VREG_1_2V_TEMP,
730 EFX_MON_STAT_INT_VPTAT,
731 EFX_MON_STAT_INT_ADC_TEMP,
732 EFX_MON_STAT_EXT_VPTAT,
733 EFX_MON_STAT_EXT_ADC_TEMP,
734 EFX_MON_STAT_AMBIENT_TEMP,
735 EFX_MON_STAT_AIRFLOW,
736 EFX_MON_STAT_VDD08D_VSS08D_CSR,
737 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
738 EFX_MON_STAT_HOTPOINT_TEMP,
739 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
740 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
741 EFX_MON_STAT_MUM_VCC,
744 EFX_MON_STAT_0V9_A_TEMP,
747 EFX_MON_STAT_0V9_B_TEMP,
748 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
749 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
750 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
751 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
752 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
753 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
754 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
755 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
756 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
757 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
758 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
759 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
760 EFX_MON_STAT_SODIMM_VOUT,
761 EFX_MON_STAT_SODIMM_0_TEMP,
762 EFX_MON_STAT_SODIMM_1_TEMP,
763 EFX_MON_STAT_PHY0_VCC,
764 EFX_MON_STAT_PHY1_VCC,
765 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
766 EFX_MON_STAT_BOARD_FRONT_TEMP,
767 EFX_MON_STAT_BOARD_BACK_TEMP,
777 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
779 typedef enum efx_mon_stat_state_e {
780 EFX_MON_STAT_STATE_OK = 0,
781 EFX_MON_STAT_STATE_WARNING = 1,
782 EFX_MON_STAT_STATE_FATAL = 2,
783 EFX_MON_STAT_STATE_BROKEN = 3,
784 EFX_MON_STAT_STATE_NO_READING = 4,
785 } efx_mon_stat_state_t;
787 typedef struct efx_mon_stat_value_s {
790 } efx_mon_stat_value_t;
797 __in efx_mon_stat_t id);
799 #endif /* EFSYS_OPT_NAMES */
801 extern __checkReturn efx_rc_t
802 efx_mon_stats_update(
804 __in efsys_mem_t *esmp,
805 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
807 #endif /* EFSYS_OPT_MON_STATS */
811 __in efx_nic_t *enp);
815 extern __checkReturn efx_rc_t
817 __in efx_nic_t *enp);
819 #if EFSYS_OPT_PHY_LED_CONTROL
821 typedef enum efx_phy_led_mode_e {
822 EFX_PHY_LED_DEFAULT = 0,
827 } efx_phy_led_mode_t;
829 extern __checkReturn efx_rc_t
832 __in efx_phy_led_mode_t mode);
834 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
836 extern __checkReturn efx_rc_t
838 __in efx_nic_t *enp);
840 #if EFSYS_OPT_LOOPBACK
842 typedef enum efx_loopback_type_e {
843 EFX_LOOPBACK_OFF = 0,
844 EFX_LOOPBACK_DATA = 1,
845 EFX_LOOPBACK_GMAC = 2,
846 EFX_LOOPBACK_XGMII = 3,
847 EFX_LOOPBACK_XGXS = 4,
848 EFX_LOOPBACK_XAUI = 5,
849 EFX_LOOPBACK_GMII = 6,
850 EFX_LOOPBACK_SGMII = 7,
851 EFX_LOOPBACK_XGBR = 8,
852 EFX_LOOPBACK_XFI = 9,
853 EFX_LOOPBACK_XAUI_FAR = 10,
854 EFX_LOOPBACK_GMII_FAR = 11,
855 EFX_LOOPBACK_SGMII_FAR = 12,
856 EFX_LOOPBACK_XFI_FAR = 13,
857 EFX_LOOPBACK_GPHY = 14,
858 EFX_LOOPBACK_PHY_XS = 15,
859 EFX_LOOPBACK_PCS = 16,
860 EFX_LOOPBACK_PMA_PMD = 17,
861 EFX_LOOPBACK_XPORT = 18,
862 EFX_LOOPBACK_XGMII_WS = 19,
863 EFX_LOOPBACK_XAUI_WS = 20,
864 EFX_LOOPBACK_XAUI_WS_FAR = 21,
865 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
866 EFX_LOOPBACK_GMII_WS = 23,
867 EFX_LOOPBACK_XFI_WS = 24,
868 EFX_LOOPBACK_XFI_WS_FAR = 25,
869 EFX_LOOPBACK_PHYXS_WS = 26,
870 EFX_LOOPBACK_PMA_INT = 27,
871 EFX_LOOPBACK_SD_NEAR = 28,
872 EFX_LOOPBACK_SD_FAR = 29,
873 EFX_LOOPBACK_PMA_INT_WS = 30,
874 EFX_LOOPBACK_SD_FEP2_WS = 31,
875 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
876 EFX_LOOPBACK_SD_FEP_WS = 33,
877 EFX_LOOPBACK_SD_FES_WS = 34,
878 EFX_LOOPBACK_AOE_INT_NEAR = 35,
879 EFX_LOOPBACK_DATA_WS = 36,
880 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
882 } efx_loopback_type_t;
884 typedef enum efx_loopback_kind_e {
885 EFX_LOOPBACK_KIND_OFF = 0,
886 EFX_LOOPBACK_KIND_ALL,
887 EFX_LOOPBACK_KIND_MAC,
888 EFX_LOOPBACK_KIND_PHY,
890 } efx_loopback_kind_t;
894 __in efx_loopback_kind_t loopback_kind,
895 __out efx_qword_t *maskp);
897 extern __checkReturn efx_rc_t
898 efx_port_loopback_set(
900 __in efx_link_mode_t link_mode,
901 __in efx_loopback_type_t type);
905 extern __checkReturn const char *
906 efx_loopback_type_name(
908 __in efx_loopback_type_t type);
910 #endif /* EFSYS_OPT_NAMES */
912 #endif /* EFSYS_OPT_LOOPBACK */
914 extern __checkReturn efx_rc_t
917 __out_opt efx_link_mode_t *link_modep);
921 __in efx_nic_t *enp);
923 typedef enum efx_phy_cap_type_e {
924 EFX_PHY_CAP_INVALID = 0,
931 EFX_PHY_CAP_10000FDX,
935 EFX_PHY_CAP_40000FDX,
937 EFX_PHY_CAP_100000FDX,
938 EFX_PHY_CAP_25000FDX,
939 EFX_PHY_CAP_50000FDX,
940 EFX_PHY_CAP_BASER_FEC,
941 EFX_PHY_CAP_BASER_FEC_REQUESTED,
943 EFX_PHY_CAP_RS_FEC_REQUESTED,
944 EFX_PHY_CAP_25G_BASER_FEC,
945 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
947 } efx_phy_cap_type_t;
950 #define EFX_PHY_CAP_CURRENT 0x00000000
951 #define EFX_PHY_CAP_DEFAULT 0x00000001
952 #define EFX_PHY_CAP_PERM 0x00000002
958 __out uint32_t *maskp);
960 extern __checkReturn efx_rc_t
968 __out uint32_t *maskp);
970 extern __checkReturn efx_rc_t
973 __out uint32_t *ouip);
975 typedef enum efx_phy_media_type_e {
976 EFX_PHY_MEDIA_INVALID = 0,
981 EFX_PHY_MEDIA_SFP_PLUS,
982 EFX_PHY_MEDIA_BASE_T,
983 EFX_PHY_MEDIA_QSFP_PLUS,
985 } efx_phy_media_type_t;
988 * Get the type of medium currently used. If the board has ports for
989 * modules, a module is present, and we recognise the media type of
990 * the module, then this will be the media type of the module.
991 * Otherwise it will be the media type of the port.
994 efx_phy_media_type_get(
996 __out efx_phy_media_type_t *typep);
998 extern __checkReturn efx_rc_t
999 efx_phy_module_get_info(
1000 __in efx_nic_t *enp,
1001 __in uint8_t dev_addr,
1002 __in uint8_t offset,
1004 __out_bcount(len) uint8_t *data);
1006 #if EFSYS_OPT_PHY_STATS
1008 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1009 typedef enum efx_phy_stat_e {
1011 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1012 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1013 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1014 EFX_PHY_STAT_PMA_PMD_REV_A,
1015 EFX_PHY_STAT_PMA_PMD_REV_B,
1016 EFX_PHY_STAT_PMA_PMD_REV_C,
1017 EFX_PHY_STAT_PMA_PMD_REV_D,
1018 EFX_PHY_STAT_PCS_LINK_UP,
1019 EFX_PHY_STAT_PCS_RX_FAULT,
1020 EFX_PHY_STAT_PCS_TX_FAULT,
1021 EFX_PHY_STAT_PCS_BER,
1022 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1023 EFX_PHY_STAT_PHY_XS_LINK_UP,
1024 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1025 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1026 EFX_PHY_STAT_PHY_XS_ALIGN,
1027 EFX_PHY_STAT_PHY_XS_SYNC_A,
1028 EFX_PHY_STAT_PHY_XS_SYNC_B,
1029 EFX_PHY_STAT_PHY_XS_SYNC_C,
1030 EFX_PHY_STAT_PHY_XS_SYNC_D,
1031 EFX_PHY_STAT_AN_LINK_UP,
1032 EFX_PHY_STAT_AN_MASTER,
1033 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1034 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1035 EFX_PHY_STAT_CL22EXT_LINK_UP,
1040 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1041 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1042 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1043 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1044 EFX_PHY_STAT_AN_COMPLETE,
1045 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1046 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1047 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1048 EFX_PHY_STAT_PCS_FW_VERSION_0,
1049 EFX_PHY_STAT_PCS_FW_VERSION_1,
1050 EFX_PHY_STAT_PCS_FW_VERSION_2,
1051 EFX_PHY_STAT_PCS_FW_VERSION_3,
1052 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1053 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1054 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1055 EFX_PHY_STAT_PCS_OP_MODE,
1059 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1065 __in efx_nic_t *enp,
1066 __in efx_phy_stat_t stat);
1068 #endif /* EFSYS_OPT_NAMES */
1070 #define EFX_PHY_STATS_SIZE 0x100
1072 extern __checkReturn efx_rc_t
1073 efx_phy_stats_update(
1074 __in efx_nic_t *enp,
1075 __in efsys_mem_t *esmp,
1076 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1078 #endif /* EFSYS_OPT_PHY_STATS */
1083 typedef enum efx_bist_type_e {
1084 EFX_BIST_TYPE_UNKNOWN,
1085 EFX_BIST_TYPE_PHY_NORMAL,
1086 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1087 EFX_BIST_TYPE_PHY_CABLE_LONG,
1088 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1089 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1090 EFX_BIST_TYPE_REG, /* Test the register memories */
1091 EFX_BIST_TYPE_NTYPES,
1094 typedef enum efx_bist_result_e {
1095 EFX_BIST_RESULT_UNKNOWN,
1096 EFX_BIST_RESULT_RUNNING,
1097 EFX_BIST_RESULT_PASSED,
1098 EFX_BIST_RESULT_FAILED,
1099 } efx_bist_result_t;
1101 typedef enum efx_phy_cable_status_e {
1102 EFX_PHY_CABLE_STATUS_OK,
1103 EFX_PHY_CABLE_STATUS_INVALID,
1104 EFX_PHY_CABLE_STATUS_OPEN,
1105 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1106 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1107 EFX_PHY_CABLE_STATUS_BUSY,
1108 } efx_phy_cable_status_t;
1110 typedef enum efx_bist_value_e {
1111 EFX_BIST_PHY_CABLE_LENGTH_A,
1112 EFX_BIST_PHY_CABLE_LENGTH_B,
1113 EFX_BIST_PHY_CABLE_LENGTH_C,
1114 EFX_BIST_PHY_CABLE_LENGTH_D,
1115 EFX_BIST_PHY_CABLE_STATUS_A,
1116 EFX_BIST_PHY_CABLE_STATUS_B,
1117 EFX_BIST_PHY_CABLE_STATUS_C,
1118 EFX_BIST_PHY_CABLE_STATUS_D,
1119 EFX_BIST_FAULT_CODE,
1121 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1127 EFX_BIST_MEM_EXPECT,
1128 EFX_BIST_MEM_ACTUAL,
1130 EFX_BIST_MEM_ECC_PARITY,
1131 EFX_BIST_MEM_ECC_FATAL,
1135 extern __checkReturn efx_rc_t
1136 efx_bist_enable_offline(
1137 __in efx_nic_t *enp);
1139 extern __checkReturn efx_rc_t
1141 __in efx_nic_t *enp,
1142 __in efx_bist_type_t type);
1144 extern __checkReturn efx_rc_t
1146 __in efx_nic_t *enp,
1147 __in efx_bist_type_t type,
1148 __out efx_bist_result_t *resultp,
1149 __out_opt uint32_t *value_maskp,
1150 __out_ecount_opt(count) unsigned long *valuesp,
1155 __in efx_nic_t *enp,
1156 __in efx_bist_type_t type);
1158 #endif /* EFSYS_OPT_BIST */
1160 #define EFX_FEATURE_IPV6 0x00000001
1161 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1162 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1163 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1164 #define EFX_FEATURE_MCDI 0x00000020
1165 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1166 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1167 #define EFX_FEATURE_TURBO 0x00000100
1168 #define EFX_FEATURE_MCDI_DMA 0x00000200
1169 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1170 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1171 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1172 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1173 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1175 typedef enum efx_tunnel_protocol_e {
1176 EFX_TUNNEL_PROTOCOL_NONE = 0,
1177 EFX_TUNNEL_PROTOCOL_VXLAN,
1178 EFX_TUNNEL_PROTOCOL_GENEVE,
1179 EFX_TUNNEL_PROTOCOL_NVGRE,
1181 } efx_tunnel_protocol_t;
1183 typedef enum efx_vi_window_shift_e {
1184 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1185 EFX_VI_WINDOW_SHIFT_8K = 13,
1186 EFX_VI_WINDOW_SHIFT_16K = 14,
1187 EFX_VI_WINDOW_SHIFT_64K = 16,
1188 } efx_vi_window_shift_t;
1190 typedef struct efx_nic_cfg_s {
1191 uint32_t enc_board_type;
1192 uint32_t enc_phy_type;
1194 char enc_phy_name[21];
1196 char enc_phy_revision[21];
1197 efx_mon_type_t enc_mon_type;
1198 #if EFSYS_OPT_MON_STATS
1199 uint32_t enc_mon_stat_dma_buf_size;
1200 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1202 unsigned int enc_features;
1203 efx_vi_window_shift_t enc_vi_window_shift;
1204 uint8_t enc_mac_addr[6];
1205 uint8_t enc_port; /* PHY port number */
1206 uint32_t enc_intr_vec_base;
1207 uint32_t enc_intr_limit;
1208 uint32_t enc_evq_limit;
1209 uint32_t enc_txq_limit;
1210 uint32_t enc_rxq_limit;
1211 uint32_t enc_txq_max_ndescs;
1212 uint32_t enc_buftbl_limit;
1213 uint32_t enc_piobuf_limit;
1214 uint32_t enc_piobuf_size;
1215 uint32_t enc_piobuf_min_alloc_size;
1216 uint32_t enc_evq_timer_quantum_ns;
1217 uint32_t enc_evq_timer_max_us;
1218 uint32_t enc_clk_mult;
1219 uint32_t enc_rx_prefix_size;
1220 uint32_t enc_rx_buf_align_start;
1221 uint32_t enc_rx_buf_align_end;
1222 uint32_t enc_rx_scale_max_exclusive_contexts;
1224 * Mask of supported hash algorithms.
1225 * Hash algorithm types are used as the bit indices.
1227 uint32_t enc_rx_scale_hash_alg_mask;
1229 * Indicates whether port numbers can be included to the
1230 * input data for hash computation.
1232 boolean_t enc_rx_scale_l4_hash_supported;
1233 boolean_t enc_rx_scale_additional_modes_supported;
1234 #if EFSYS_OPT_LOOPBACK
1235 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1236 #endif /* EFSYS_OPT_LOOPBACK */
1237 #if EFSYS_OPT_PHY_FLAGS
1238 uint32_t enc_phy_flags_mask;
1239 #endif /* EFSYS_OPT_PHY_FLAGS */
1240 #if EFSYS_OPT_PHY_LED_CONTROL
1241 uint32_t enc_led_mask;
1242 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1243 #if EFSYS_OPT_PHY_STATS
1244 uint64_t enc_phy_stat_mask;
1245 #endif /* EFSYS_OPT_PHY_STATS */
1247 uint8_t enc_mcdi_mdio_channel;
1248 #if EFSYS_OPT_PHY_STATS
1249 uint32_t enc_mcdi_phy_stat_mask;
1250 #endif /* EFSYS_OPT_PHY_STATS */
1251 #if EFSYS_OPT_MON_STATS
1252 uint32_t *enc_mcdi_sensor_maskp;
1253 uint32_t enc_mcdi_sensor_mask_size;
1254 #endif /* EFSYS_OPT_MON_STATS */
1255 #endif /* EFSYS_OPT_MCDI */
1257 uint32_t enc_bist_mask;
1258 #endif /* EFSYS_OPT_BIST */
1259 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1262 uint32_t enc_privilege_mask;
1263 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1264 boolean_t enc_bug26807_workaround;
1265 boolean_t enc_bug35388_workaround;
1266 boolean_t enc_bug41750_workaround;
1267 boolean_t enc_bug61265_workaround;
1268 boolean_t enc_rx_batching_enabled;
1269 /* Maximum number of descriptors completed in an rx event. */
1270 uint32_t enc_rx_batch_max;
1271 /* Number of rx descriptors the hardware requires for a push. */
1272 uint32_t enc_rx_push_align;
1273 /* Maximum amount of data in DMA descriptor */
1274 uint32_t enc_tx_dma_desc_size_max;
1276 * Boundary which DMA descriptor data must not cross or 0 if no
1279 uint32_t enc_tx_dma_desc_boundary;
1281 * Maximum number of bytes into the packet the TCP header can start for
1282 * the hardware to apply TSO packet edits.
1284 uint32_t enc_tx_tso_tcp_header_offset_limit;
1285 boolean_t enc_fw_assisted_tso_enabled;
1286 boolean_t enc_fw_assisted_tso_v2_enabled;
1287 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1288 /* Number of TSO contexts on the NIC (FATSOv2) */
1289 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1290 boolean_t enc_hw_tx_insert_vlan_enabled;
1291 /* Number of PFs on the NIC */
1292 uint32_t enc_hw_pf_count;
1293 /* Datapath firmware vadapter/vport/vswitch support */
1294 boolean_t enc_datapath_cap_evb;
1295 boolean_t enc_rx_disable_scatter_supported;
1296 boolean_t enc_allow_set_mac_with_installed_filters;
1297 boolean_t enc_enhanced_set_mac_supported;
1298 boolean_t enc_init_evq_v2_supported;
1299 boolean_t enc_rx_packed_stream_supported;
1300 boolean_t enc_rx_var_packed_stream_supported;
1301 boolean_t enc_rx_es_super_buffer_supported;
1302 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1303 boolean_t enc_pm_and_rxdp_counters;
1304 boolean_t enc_mac_stats_40g_tx_size_bins;
1305 uint32_t enc_tunnel_encapsulations_supported;
1307 * NIC global maximum for unique UDP tunnel ports shared by all
1310 uint32_t enc_tunnel_config_udp_entries_max;
1311 /* External port identifier */
1312 uint8_t enc_external_port;
1313 uint32_t enc_mcdi_max_payload_length;
1314 /* VPD may be per-PF or global */
1315 boolean_t enc_vpd_is_global;
1316 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1317 uint32_t enc_required_pcie_bandwidth_mbps;
1318 uint32_t enc_max_pcie_link_gen;
1319 /* Firmware verifies integrity of NVRAM updates */
1320 uint32_t enc_nvram_update_verify_result_supported;
1321 /* Firmware support for extended MAC_STATS buffer */
1322 uint32_t enc_mac_stats_nstats;
1323 boolean_t enc_fec_counters;
1324 /* Firmware support for "FLAG" and "MARK" filter actions */
1325 boolean_t enc_filter_action_flag_supported;
1326 boolean_t enc_filter_action_mark_supported;
1329 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1330 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1332 #define EFX_PCI_FUNCTION(_encp) \
1333 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1335 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1337 extern const efx_nic_cfg_t *
1339 __in efx_nic_t *enp);
1341 /* RxDPCPU firmware id values by which FW variant can be identified */
1342 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1343 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1344 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1345 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1346 #define EFX_RXDP_DPDK_FW_ID 0x6
1348 typedef struct efx_nic_fw_info_s {
1349 /* Basic FW version information */
1350 uint16_t enfi_mc_fw_version[4];
1352 * If datapath capabilities can be detected,
1353 * additional FW information is to be shown
1355 boolean_t enfi_dpcpu_fw_ids_valid;
1356 /* Rx and Tx datapath CPU FW IDs */
1357 uint16_t enfi_rx_dpcpu_fw_id;
1358 uint16_t enfi_tx_dpcpu_fw_id;
1359 } efx_nic_fw_info_t;
1361 extern __checkReturn efx_rc_t
1362 efx_nic_get_fw_version(
1363 __in efx_nic_t *enp,
1364 __out efx_nic_fw_info_t *enfip);
1366 /* Driver resource limits (minimum required/maximum usable). */
1367 typedef struct efx_drv_limits_s {
1368 uint32_t edl_min_evq_count;
1369 uint32_t edl_max_evq_count;
1371 uint32_t edl_min_rxq_count;
1372 uint32_t edl_max_rxq_count;
1374 uint32_t edl_min_txq_count;
1375 uint32_t edl_max_txq_count;
1377 /* PIO blocks (sub-allocated from piobuf) */
1378 uint32_t edl_min_pio_alloc_size;
1379 uint32_t edl_max_pio_alloc_count;
1382 extern __checkReturn efx_rc_t
1383 efx_nic_set_drv_limits(
1384 __inout efx_nic_t *enp,
1385 __in efx_drv_limits_t *edlp);
1387 typedef enum efx_nic_region_e {
1388 EFX_REGION_VI, /* Memory BAR UC mapping */
1389 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1392 extern __checkReturn efx_rc_t
1393 efx_nic_get_bar_region(
1394 __in efx_nic_t *enp,
1395 __in efx_nic_region_t region,
1396 __out uint32_t *offsetp,
1397 __out size_t *sizep);
1399 extern __checkReturn efx_rc_t
1400 efx_nic_get_vi_pool(
1401 __in efx_nic_t *enp,
1402 __out uint32_t *evq_countp,
1403 __out uint32_t *rxq_countp,
1404 __out uint32_t *txq_countp);
1409 typedef enum efx_vpd_tag_e {
1416 typedef uint16_t efx_vpd_keyword_t;
1418 typedef struct efx_vpd_value_s {
1419 efx_vpd_tag_t evv_tag;
1420 efx_vpd_keyword_t evv_keyword;
1422 uint8_t evv_value[0x100];
1426 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1428 extern __checkReturn efx_rc_t
1430 __in efx_nic_t *enp);
1432 extern __checkReturn efx_rc_t
1434 __in efx_nic_t *enp,
1435 __out size_t *sizep);
1437 extern __checkReturn efx_rc_t
1439 __in efx_nic_t *enp,
1440 __out_bcount(size) caddr_t data,
1443 extern __checkReturn efx_rc_t
1445 __in efx_nic_t *enp,
1446 __in_bcount(size) caddr_t data,
1449 extern __checkReturn efx_rc_t
1451 __in efx_nic_t *enp,
1452 __in_bcount(size) caddr_t data,
1455 extern __checkReturn efx_rc_t
1457 __in efx_nic_t *enp,
1458 __in_bcount(size) caddr_t data,
1460 __inout efx_vpd_value_t *evvp);
1462 extern __checkReturn efx_rc_t
1464 __in efx_nic_t *enp,
1465 __inout_bcount(size) caddr_t data,
1467 __in efx_vpd_value_t *evvp);
1469 extern __checkReturn efx_rc_t
1471 __in efx_nic_t *enp,
1472 __inout_bcount(size) caddr_t data,
1474 __out efx_vpd_value_t *evvp,
1475 __inout unsigned int *contp);
1477 extern __checkReturn efx_rc_t
1479 __in efx_nic_t *enp,
1480 __in_bcount(size) caddr_t data,
1485 __in efx_nic_t *enp);
1487 #endif /* EFSYS_OPT_VPD */
1493 typedef enum efx_nvram_type_e {
1494 EFX_NVRAM_INVALID = 0,
1496 EFX_NVRAM_BOOTROM_CFG,
1497 EFX_NVRAM_MC_FIRMWARE,
1498 EFX_NVRAM_MC_GOLDEN,
1504 EFX_NVRAM_FPGA_BACKUP,
1505 EFX_NVRAM_DYNAMIC_CFG,
1508 EFX_NVRAM_MUM_FIRMWARE,
1512 extern __checkReturn efx_rc_t
1514 __in efx_nic_t *enp);
1518 extern __checkReturn efx_rc_t
1520 __in efx_nic_t *enp);
1522 #endif /* EFSYS_OPT_DIAG */
1524 extern __checkReturn efx_rc_t
1526 __in efx_nic_t *enp,
1527 __in efx_nvram_type_t type,
1528 __out size_t *sizep);
1530 extern __checkReturn efx_rc_t
1532 __in efx_nic_t *enp,
1533 __in efx_nvram_type_t type,
1534 __out_opt size_t *pref_chunkp);
1536 extern __checkReturn efx_rc_t
1537 efx_nvram_rw_finish(
1538 __in efx_nic_t *enp,
1539 __in efx_nvram_type_t type,
1540 __out_opt uint32_t *verify_resultp);
1542 extern __checkReturn efx_rc_t
1543 efx_nvram_get_version(
1544 __in efx_nic_t *enp,
1545 __in efx_nvram_type_t type,
1546 __out uint32_t *subtypep,
1547 __out_ecount(4) uint16_t version[4]);
1549 extern __checkReturn efx_rc_t
1550 efx_nvram_read_chunk(
1551 __in efx_nic_t *enp,
1552 __in efx_nvram_type_t type,
1553 __in unsigned int offset,
1554 __out_bcount(size) caddr_t data,
1557 extern __checkReturn efx_rc_t
1558 efx_nvram_read_backup(
1559 __in efx_nic_t *enp,
1560 __in efx_nvram_type_t type,
1561 __in unsigned int offset,
1562 __out_bcount(size) caddr_t data,
1565 extern __checkReturn efx_rc_t
1566 efx_nvram_set_version(
1567 __in efx_nic_t *enp,
1568 __in efx_nvram_type_t type,
1569 __in_ecount(4) uint16_t version[4]);
1571 extern __checkReturn efx_rc_t
1573 __in efx_nic_t *enp,
1574 __in efx_nvram_type_t type,
1575 __in_bcount(partn_size) caddr_t partn_data,
1576 __in size_t partn_size);
1578 extern __checkReturn efx_rc_t
1580 __in efx_nic_t *enp,
1581 __in efx_nvram_type_t type);
1583 extern __checkReturn efx_rc_t
1584 efx_nvram_write_chunk(
1585 __in efx_nic_t *enp,
1586 __in efx_nvram_type_t type,
1587 __in unsigned int offset,
1588 __in_bcount(size) caddr_t data,
1593 __in efx_nic_t *enp);
1595 #endif /* EFSYS_OPT_NVRAM */
1597 #if EFSYS_OPT_BOOTCFG
1599 /* Report size and offset of bootcfg sector in NVRAM partition. */
1600 extern __checkReturn efx_rc_t
1601 efx_bootcfg_sector_info(
1602 __in efx_nic_t *enp,
1604 __out_opt uint32_t *sector_countp,
1605 __out size_t *offsetp,
1606 __out size_t *max_sizep);
1609 * Copy bootcfg sector data to a target buffer which may differ in size.
1610 * Optionally corrects format errors in source buffer.
1613 efx_bootcfg_copy_sector(
1614 __in efx_nic_t *enp,
1615 __inout_bcount(sector_length)
1617 __in size_t sector_length,
1618 __out_bcount(data_size) uint8_t *data,
1619 __in size_t data_size,
1620 __in boolean_t handle_format_errors);
1624 __in efx_nic_t *enp,
1625 __out_bcount(size) uint8_t *data,
1630 __in efx_nic_t *enp,
1631 __in_bcount(size) uint8_t *data,
1634 #endif /* EFSYS_OPT_BOOTCFG */
1636 #if EFSYS_OPT_IMAGE_LAYOUT
1638 #include "ef10_signed_image_layout.h"
1641 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1644 * The image header format is extensible. However, older drivers require an
1645 * exact match of image header version and header length when validating and
1646 * writing firmware images.
1648 * To avoid breaking backward compatibility, we use the upper bits of the
1649 * controller version fields to contain an extra version number used for
1650 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1651 * version). See bug39254 and SF-102785-PS for details.
1653 typedef struct efx_image_header_s {
1655 uint32_t eih_version;
1657 uint32_t eih_subtype;
1658 uint32_t eih_code_size;
1661 uint32_t eih_controller_version_min;
1663 uint16_t eih_controller_version_min_short;
1664 uint8_t eih_extra_version_a;
1665 uint8_t eih_extra_version_b;
1669 uint32_t eih_controller_version_max;
1671 uint16_t eih_controller_version_max_short;
1672 uint8_t eih_extra_version_c;
1673 uint8_t eih_extra_version_d;
1676 uint16_t eih_code_version_a;
1677 uint16_t eih_code_version_b;
1678 uint16_t eih_code_version_c;
1679 uint16_t eih_code_version_d;
1680 } efx_image_header_t;
1682 #define EFX_IMAGE_HEADER_SIZE (40)
1683 #define EFX_IMAGE_HEADER_VERSION (4)
1684 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1687 typedef struct efx_image_trailer_s {
1689 } efx_image_trailer_t;
1691 #define EFX_IMAGE_TRAILER_SIZE (4)
1693 typedef enum efx_image_format_e {
1694 EFX_IMAGE_FORMAT_NO_IMAGE,
1695 EFX_IMAGE_FORMAT_INVALID,
1696 EFX_IMAGE_FORMAT_UNSIGNED,
1697 EFX_IMAGE_FORMAT_SIGNED,
1698 } efx_image_format_t;
1700 typedef struct efx_image_info_s {
1701 efx_image_format_t eii_format;
1702 uint8_t * eii_imagep;
1703 size_t eii_image_size;
1704 efx_image_header_t * eii_headerp;
1707 extern __checkReturn efx_rc_t
1708 efx_check_reflash_image(
1710 __in uint32_t buffer_size,
1711 __out efx_image_info_t *infop);
1713 extern __checkReturn efx_rc_t
1714 efx_build_signed_image_write_buffer(
1715 __out_bcount(buffer_size)
1717 __in uint32_t buffer_size,
1718 __in efx_image_info_t *infop,
1719 __out efx_image_header_t **headerpp);
1721 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1725 typedef enum efx_pattern_type_t {
1726 EFX_PATTERN_BYTE_INCREMENT = 0,
1727 EFX_PATTERN_ALL_THE_SAME,
1728 EFX_PATTERN_BIT_ALTERNATE,
1729 EFX_PATTERN_BYTE_ALTERNATE,
1730 EFX_PATTERN_BYTE_CHANGING,
1731 EFX_PATTERN_BIT_SWEEP,
1733 } efx_pattern_type_t;
1736 (*efx_sram_pattern_fn_t)(
1738 __in boolean_t negate,
1739 __out efx_qword_t *eqp);
1741 extern __checkReturn efx_rc_t
1743 __in efx_nic_t *enp,
1744 __in efx_pattern_type_t type);
1746 #endif /* EFSYS_OPT_DIAG */
1748 extern __checkReturn efx_rc_t
1749 efx_sram_buf_tbl_set(
1750 __in efx_nic_t *enp,
1752 __in efsys_mem_t *esmp,
1756 efx_sram_buf_tbl_clear(
1757 __in efx_nic_t *enp,
1761 #define EFX_BUF_TBL_SIZE 0x20000
1763 #define EFX_BUF_SIZE 4096
1767 typedef struct efx_evq_s efx_evq_t;
1769 #if EFSYS_OPT_QSTATS
1771 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1772 typedef enum efx_ev_qstat_e {
1778 EV_RX_PAUSE_FRM_ERR,
1779 EV_RX_BUF_OWNER_ID_ERR,
1780 EV_RX_IPV4_HDR_CHKSUM_ERR,
1781 EV_RX_TCP_UDP_CHKSUM_ERR,
1785 EV_RX_MCAST_HASH_MATCH,
1802 EV_DRIVER_SRM_UPD_DONE,
1803 EV_DRIVER_TX_DESCQ_FLS_DONE,
1804 EV_DRIVER_RX_DESCQ_FLS_DONE,
1805 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1806 EV_DRIVER_RX_DSC_ERROR,
1807 EV_DRIVER_TX_DSC_ERROR,
1813 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1815 #endif /* EFSYS_OPT_QSTATS */
1817 extern __checkReturn efx_rc_t
1819 __in efx_nic_t *enp);
1823 __in efx_nic_t *enp);
1825 #define EFX_EVQ_MAXNEVS 32768
1826 #define EFX_EVQ_MINNEVS 512
1828 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1829 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1831 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1832 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1833 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1834 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1836 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1837 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1838 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1840 extern __checkReturn efx_rc_t
1842 __in efx_nic_t *enp,
1843 __in unsigned int index,
1844 __in efsys_mem_t *esmp,
1848 __in uint32_t flags,
1849 __deref_out efx_evq_t **eepp);
1853 __in efx_evq_t *eep,
1854 __in uint16_t data);
1856 typedef __checkReturn boolean_t
1857 (*efx_initialized_ev_t)(
1858 __in_opt void *arg);
1860 #define EFX_PKT_UNICAST 0x0004
1861 #define EFX_PKT_START 0x0008
1863 #define EFX_PKT_VLAN_TAGGED 0x0010
1864 #define EFX_CKSUM_TCPUDP 0x0020
1865 #define EFX_CKSUM_IPV4 0x0040
1866 #define EFX_PKT_CONT 0x0080
1868 #define EFX_CHECK_VLAN 0x0100
1869 #define EFX_PKT_TCP 0x0200
1870 #define EFX_PKT_UDP 0x0400
1871 #define EFX_PKT_IPV4 0x0800
1873 #define EFX_PKT_IPV6 0x1000
1874 #define EFX_PKT_PREFIX_LEN 0x2000
1875 #define EFX_ADDR_MISMATCH 0x4000
1876 #define EFX_DISCARD 0x8000
1879 * The following flags are used only for packed stream
1880 * mode. The values for the flags are reused to fit into 16 bit,
1881 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1882 * packed stream mode
1884 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1885 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1888 #define EFX_EV_RX_NLABELS 32
1889 #define EFX_EV_TX_NLABELS 32
1891 typedef __checkReturn boolean_t
1894 __in uint32_t label,
1897 __in uint16_t flags);
1899 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1902 * Packed stream mode is documented in SF-112241-TC.
1903 * The general idea is that, instead of putting each incoming
1904 * packet into a separate buffer which is specified in a RX
1905 * descriptor, a large buffer is provided to the hardware and
1906 * packets are put there in a continuous stream.
1907 * The main advantage of such an approach is that RX queue refilling
1908 * happens much less frequently.
1910 * Equal stride packed stream mode is documented in SF-119419-TC.
1911 * The general idea is to utilize advantages of the packed stream,
1912 * but avoid indirection in packets representation.
1913 * The main advantage of such an approach is that RX queue refilling
1914 * happens much less frequently and packets buffers are independent
1915 * from upper layers point of view.
1918 typedef __checkReturn boolean_t
1921 __in uint32_t label,
1923 __in uint32_t pkt_count,
1924 __in uint16_t flags);
1928 typedef __checkReturn boolean_t
1931 __in uint32_t label,
1934 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1935 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1936 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1937 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1938 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1939 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1940 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1941 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1942 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1944 typedef __checkReturn boolean_t
1945 (*efx_exception_ev_t)(
1947 __in uint32_t label,
1948 __in uint32_t data);
1950 typedef __checkReturn boolean_t
1951 (*efx_rxq_flush_done_ev_t)(
1953 __in uint32_t rxq_index);
1955 typedef __checkReturn boolean_t
1956 (*efx_rxq_flush_failed_ev_t)(
1958 __in uint32_t rxq_index);
1960 typedef __checkReturn boolean_t
1961 (*efx_txq_flush_done_ev_t)(
1963 __in uint32_t txq_index);
1965 typedef __checkReturn boolean_t
1966 (*efx_software_ev_t)(
1968 __in uint16_t magic);
1970 typedef __checkReturn boolean_t
1973 __in uint32_t code);
1975 #define EFX_SRAM_CLEAR 0
1976 #define EFX_SRAM_UPDATE 1
1977 #define EFX_SRAM_ILLEGAL_CLEAR 2
1979 typedef __checkReturn boolean_t
1980 (*efx_wake_up_ev_t)(
1982 __in uint32_t label);
1984 typedef __checkReturn boolean_t
1987 __in uint32_t label);
1989 typedef __checkReturn boolean_t
1990 (*efx_link_change_ev_t)(
1992 __in efx_link_mode_t link_mode);
1994 #if EFSYS_OPT_MON_STATS
1996 typedef __checkReturn boolean_t
1997 (*efx_monitor_ev_t)(
1999 __in efx_mon_stat_t id,
2000 __in efx_mon_stat_value_t value);
2002 #endif /* EFSYS_OPT_MON_STATS */
2004 #if EFSYS_OPT_MAC_STATS
2006 typedef __checkReturn boolean_t
2007 (*efx_mac_stats_ev_t)(
2009 __in uint32_t generation);
2011 #endif /* EFSYS_OPT_MAC_STATS */
2013 typedef struct efx_ev_callbacks_s {
2014 efx_initialized_ev_t eec_initialized;
2016 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2017 efx_rx_ps_ev_t eec_rx_ps;
2020 efx_exception_ev_t eec_exception;
2021 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2022 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2023 efx_txq_flush_done_ev_t eec_txq_flush_done;
2024 efx_software_ev_t eec_software;
2025 efx_sram_ev_t eec_sram;
2026 efx_wake_up_ev_t eec_wake_up;
2027 efx_timer_ev_t eec_timer;
2028 efx_link_change_ev_t eec_link_change;
2029 #if EFSYS_OPT_MON_STATS
2030 efx_monitor_ev_t eec_monitor;
2031 #endif /* EFSYS_OPT_MON_STATS */
2032 #if EFSYS_OPT_MAC_STATS
2033 efx_mac_stats_ev_t eec_mac_stats;
2034 #endif /* EFSYS_OPT_MAC_STATS */
2035 } efx_ev_callbacks_t;
2037 extern __checkReturn boolean_t
2039 __in efx_evq_t *eep,
2040 __in unsigned int count);
2042 #if EFSYS_OPT_EV_PREFETCH
2046 __in efx_evq_t *eep,
2047 __in unsigned int count);
2049 #endif /* EFSYS_OPT_EV_PREFETCH */
2053 __in efx_evq_t *eep,
2054 __inout unsigned int *countp,
2055 __in const efx_ev_callbacks_t *eecp,
2056 __in_opt void *arg);
2058 extern __checkReturn efx_rc_t
2059 efx_ev_usecs_to_ticks(
2060 __in efx_nic_t *enp,
2061 __in unsigned int usecs,
2062 __out unsigned int *ticksp);
2064 extern __checkReturn efx_rc_t
2066 __in efx_evq_t *eep,
2067 __in unsigned int us);
2069 extern __checkReturn efx_rc_t
2071 __in efx_evq_t *eep,
2072 __in unsigned int count);
2074 #if EFSYS_OPT_QSTATS
2080 __in efx_nic_t *enp,
2081 __in unsigned int id);
2083 #endif /* EFSYS_OPT_NAMES */
2086 efx_ev_qstats_update(
2087 __in efx_evq_t *eep,
2088 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2090 #endif /* EFSYS_OPT_QSTATS */
2094 __in efx_evq_t *eep);
2098 extern __checkReturn efx_rc_t
2100 __inout efx_nic_t *enp);
2104 __in efx_nic_t *enp);
2106 #if EFSYS_OPT_RX_SCATTER
2107 __checkReturn efx_rc_t
2108 efx_rx_scatter_enable(
2109 __in efx_nic_t *enp,
2110 __in unsigned int buf_size);
2111 #endif /* EFSYS_OPT_RX_SCATTER */
2113 /* Handle to represent use of the default RSS context. */
2114 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2116 #if EFSYS_OPT_RX_SCALE
2118 typedef enum efx_rx_hash_alg_e {
2119 EFX_RX_HASHALG_LFSR = 0,
2120 EFX_RX_HASHALG_TOEPLITZ,
2121 EFX_RX_HASHALG_PACKED_STREAM,
2123 } efx_rx_hash_alg_t;
2126 * Legacy hash type flags.
2128 * They represent standard tuples for distinct traffic classes.
2130 #define EFX_RX_HASH_IPV4 (1U << 0)
2131 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2132 #define EFX_RX_HASH_IPV6 (1U << 2)
2133 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2135 #define EFX_RX_HASH_LEGACY_MASK \
2136 (EFX_RX_HASH_IPV4 | \
2137 EFX_RX_HASH_TCPIPV4 | \
2138 EFX_RX_HASH_IPV6 | \
2139 EFX_RX_HASH_TCPIPV6)
2142 * The type of the argument used by efx_rx_scale_mode_set() to
2143 * provide a means for the client drivers to configure hashing.
2145 * A properly constructed value can either be:
2146 * - a combination of legacy flags
2147 * - a combination of EFX_RX_HASH() flags
2149 typedef unsigned int efx_rx_hash_type_t;
2151 typedef enum efx_rx_hash_support_e {
2152 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2153 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2154 } efx_rx_hash_support_t;
2156 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2157 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2158 #define EFX_MAXRSS 64 /* RX indirection entry range */
2159 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2161 typedef enum efx_rx_scale_context_type_e {
2162 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2163 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2164 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2165 } efx_rx_scale_context_type_t;
2168 * Traffic classes eligible for hash computation.
2170 * Select packet headers used in computing the receive hash.
2171 * This uses the same encoding as the RSS_MODES field of
2172 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2174 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2175 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2176 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2177 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2178 #define EFX_RX_CLASS_IPV4_LBN 16
2179 #define EFX_RX_CLASS_IPV4_WIDTH 4
2180 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2181 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2182 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2183 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2184 #define EFX_RX_CLASS_IPV6_LBN 28
2185 #define EFX_RX_CLASS_IPV6_WIDTH 4
2187 #define EFX_RX_NCLASSES 6
2190 * Ancillary flags used to construct generic hash tuples.
2191 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2193 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2194 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2195 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2196 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2199 * Generic hash tuples.
2201 * They express combinations of packet fields
2202 * which can contribute to the hash value for
2203 * a particular traffic class.
2205 #define EFX_RX_CLASS_HASH_DISABLE 0
2207 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2208 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2210 #define EFX_RX_CLASS_HASH_2TUPLE \
2211 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2212 EFX_RX_CLASS_HASH_DST_ADDR)
2214 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2215 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2216 EFX_RX_CLASS_HASH_SRC_PORT)
2218 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2219 (EFX_RX_CLASS_HASH_DST_ADDR | \
2220 EFX_RX_CLASS_HASH_DST_PORT)
2222 #define EFX_RX_CLASS_HASH_4TUPLE \
2223 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2224 EFX_RX_CLASS_HASH_DST_ADDR | \
2225 EFX_RX_CLASS_HASH_SRC_PORT | \
2226 EFX_RX_CLASS_HASH_DST_PORT)
2228 #define EFX_RX_CLASS_HASH_NTUPLES 7
2231 * Hash flag constructor.
2233 * Resulting flags encode hash tuples for specific traffic classes.
2234 * The client drivers are encouraged to use these flags to form
2235 * a hash type value.
2237 #define EFX_RX_HASH(_class, _tuple) \
2238 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2239 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2242 * The maximum number of EFX_RX_HASH() flags.
2244 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2246 extern __checkReturn efx_rc_t
2247 efx_rx_scale_hash_flags_get(
2248 __in efx_nic_t *enp,
2249 __in efx_rx_hash_alg_t hash_alg,
2250 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flagsp,
2251 __out unsigned int *nflagsp);
2253 extern __checkReturn efx_rc_t
2254 efx_rx_hash_default_support_get(
2255 __in efx_nic_t *enp,
2256 __out efx_rx_hash_support_t *supportp);
2259 extern __checkReturn efx_rc_t
2260 efx_rx_scale_default_support_get(
2261 __in efx_nic_t *enp,
2262 __out efx_rx_scale_context_type_t *typep);
2264 extern __checkReturn efx_rc_t
2265 efx_rx_scale_context_alloc(
2266 __in efx_nic_t *enp,
2267 __in efx_rx_scale_context_type_t type,
2268 __in uint32_t num_queues,
2269 __out uint32_t *rss_contextp);
2271 extern __checkReturn efx_rc_t
2272 efx_rx_scale_context_free(
2273 __in efx_nic_t *enp,
2274 __in uint32_t rss_context);
2276 extern __checkReturn efx_rc_t
2277 efx_rx_scale_mode_set(
2278 __in efx_nic_t *enp,
2279 __in uint32_t rss_context,
2280 __in efx_rx_hash_alg_t alg,
2281 __in efx_rx_hash_type_t type,
2282 __in boolean_t insert);
2284 extern __checkReturn efx_rc_t
2285 efx_rx_scale_tbl_set(
2286 __in efx_nic_t *enp,
2287 __in uint32_t rss_context,
2288 __in_ecount(n) unsigned int *table,
2291 extern __checkReturn efx_rc_t
2292 efx_rx_scale_key_set(
2293 __in efx_nic_t *enp,
2294 __in uint32_t rss_context,
2295 __in_ecount(n) uint8_t *key,
2298 extern __checkReturn uint32_t
2299 efx_pseudo_hdr_hash_get(
2300 __in efx_rxq_t *erp,
2301 __in efx_rx_hash_alg_t func,
2302 __in uint8_t *buffer);
2304 #endif /* EFSYS_OPT_RX_SCALE */
2306 extern __checkReturn efx_rc_t
2307 efx_pseudo_hdr_pkt_length_get(
2308 __in efx_rxq_t *erp,
2309 __in uint8_t *buffer,
2310 __out uint16_t *pkt_lengthp);
2312 #define EFX_RXQ_MAXNDESCS 4096
2313 #define EFX_RXQ_MINNDESCS 512
2315 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2316 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2317 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2318 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2320 typedef enum efx_rxq_type_e {
2321 EFX_RXQ_TYPE_DEFAULT,
2322 EFX_RXQ_TYPE_PACKED_STREAM,
2323 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2328 * Dummy flag to be used instead of 0 to make it clear that the argument
2329 * is receive queue flags.
2331 #define EFX_RXQ_FLAG_NONE 0x0
2332 #define EFX_RXQ_FLAG_SCATTER 0x1
2334 * If tunnels are supported and Rx event can provide information about
2335 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2336 * full-feature firmware variant running), outer classes are requested by
2337 * default. However, if the driver supports tunnels, the flag allows to
2338 * request inner classes which are required to be able to interpret inner
2339 * Rx checksum offload results.
2341 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2343 extern __checkReturn efx_rc_t
2345 __in efx_nic_t *enp,
2346 __in unsigned int index,
2347 __in unsigned int label,
2348 __in efx_rxq_type_t type,
2349 __in efsys_mem_t *esmp,
2352 __in unsigned int flags,
2353 __in efx_evq_t *eep,
2354 __deref_out efx_rxq_t **erpp);
2356 #if EFSYS_OPT_RX_PACKED_STREAM
2358 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2359 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2360 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2361 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2362 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2364 extern __checkReturn efx_rc_t
2365 efx_rx_qcreate_packed_stream(
2366 __in efx_nic_t *enp,
2367 __in unsigned int index,
2368 __in unsigned int label,
2369 __in uint32_t ps_buf_size,
2370 __in efsys_mem_t *esmp,
2372 __in efx_evq_t *eep,
2373 __deref_out efx_rxq_t **erpp);
2377 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2379 /* Maximum head-of-line block timeout in nanoseconds */
2380 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2382 extern __checkReturn efx_rc_t
2383 efx_rx_qcreate_es_super_buffer(
2384 __in efx_nic_t *enp,
2385 __in unsigned int index,
2386 __in unsigned int label,
2387 __in uint32_t n_bufs_per_desc,
2388 __in uint32_t max_dma_len,
2389 __in uint32_t buf_stride,
2390 __in uint32_t hol_block_timeout,
2391 __in efsys_mem_t *esmp,
2393 __in unsigned int flags,
2394 __in efx_evq_t *eep,
2395 __deref_out efx_rxq_t **erpp);
2399 typedef struct efx_buffer_s {
2400 efsys_dma_addr_t eb_addr;
2405 typedef struct efx_desc_s {
2411 __in efx_rxq_t *erp,
2412 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2414 __in unsigned int ndescs,
2415 __in unsigned int completed,
2416 __in unsigned int added);
2420 __in efx_rxq_t *erp,
2421 __in unsigned int added,
2422 __inout unsigned int *pushedp);
2424 #if EFSYS_OPT_RX_PACKED_STREAM
2427 efx_rx_qpush_ps_credits(
2428 __in efx_rxq_t *erp);
2430 extern __checkReturn uint8_t *
2431 efx_rx_qps_packet_info(
2432 __in efx_rxq_t *erp,
2433 __in uint8_t *buffer,
2434 __in uint32_t buffer_length,
2435 __in uint32_t current_offset,
2436 __out uint16_t *lengthp,
2437 __out uint32_t *next_offsetp,
2438 __out uint32_t *timestamp);
2441 extern __checkReturn efx_rc_t
2443 __in efx_rxq_t *erp);
2447 __in efx_rxq_t *erp);
2451 __in efx_rxq_t *erp);
2455 typedef struct efx_txq_s efx_txq_t;
2457 #if EFSYS_OPT_QSTATS
2459 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2460 typedef enum efx_tx_qstat_e {
2466 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2468 #endif /* EFSYS_OPT_QSTATS */
2470 extern __checkReturn efx_rc_t
2472 __in efx_nic_t *enp);
2476 __in efx_nic_t *enp);
2478 #define EFX_TXQ_MINNDESCS 512
2480 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2481 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2482 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2484 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2486 #define EFX_TXQ_CKSUM_IPV4 0x0001
2487 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2488 #define EFX_TXQ_FATSOV2 0x0004
2489 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2490 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2492 extern __checkReturn efx_rc_t
2494 __in efx_nic_t *enp,
2495 __in unsigned int index,
2496 __in unsigned int label,
2497 __in efsys_mem_t *esmp,
2500 __in uint16_t flags,
2501 __in efx_evq_t *eep,
2502 __deref_out efx_txq_t **etpp,
2503 __out unsigned int *addedp);
2505 extern __checkReturn efx_rc_t
2507 __in efx_txq_t *etp,
2508 __in_ecount(ndescs) efx_buffer_t *eb,
2509 __in unsigned int ndescs,
2510 __in unsigned int completed,
2511 __inout unsigned int *addedp);
2513 extern __checkReturn efx_rc_t
2515 __in efx_txq_t *etp,
2516 __in unsigned int ns);
2520 __in efx_txq_t *etp,
2521 __in unsigned int added,
2522 __in unsigned int pushed);
2524 extern __checkReturn efx_rc_t
2526 __in efx_txq_t *etp);
2530 __in efx_txq_t *etp);
2532 extern __checkReturn efx_rc_t
2534 __in efx_txq_t *etp);
2537 efx_tx_qpio_disable(
2538 __in efx_txq_t *etp);
2540 extern __checkReturn efx_rc_t
2542 __in efx_txq_t *etp,
2543 __in_ecount(buf_length) uint8_t *buffer,
2544 __in size_t buf_length,
2545 __in size_t pio_buf_offset);
2547 extern __checkReturn efx_rc_t
2549 __in efx_txq_t *etp,
2550 __in size_t pkt_length,
2551 __in unsigned int completed,
2552 __inout unsigned int *addedp);
2554 extern __checkReturn efx_rc_t
2556 __in efx_txq_t *etp,
2557 __in_ecount(n) efx_desc_t *ed,
2558 __in unsigned int n,
2559 __in unsigned int completed,
2560 __inout unsigned int *addedp);
2563 efx_tx_qdesc_dma_create(
2564 __in efx_txq_t *etp,
2565 __in efsys_dma_addr_t addr,
2568 __out efx_desc_t *edp);
2571 efx_tx_qdesc_tso_create(
2572 __in efx_txq_t *etp,
2573 __in uint16_t ipv4_id,
2574 __in uint32_t tcp_seq,
2575 __in uint8_t tcp_flags,
2576 __out efx_desc_t *edp);
2578 /* Number of FATSOv2 option descriptors */
2579 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2581 /* Maximum number of DMA segments per TSO packet (not superframe) */
2582 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2585 efx_tx_qdesc_tso2_create(
2586 __in efx_txq_t *etp,
2587 __in uint16_t ipv4_id,
2588 __in uint16_t outer_ipv4_id,
2589 __in uint32_t tcp_seq,
2590 __in uint16_t tcp_mss,
2591 __out_ecount(count) efx_desc_t *edp,
2595 efx_tx_qdesc_vlantci_create(
2596 __in efx_txq_t *etp,
2598 __out efx_desc_t *edp);
2601 efx_tx_qdesc_checksum_create(
2602 __in efx_txq_t *etp,
2603 __in uint16_t flags,
2604 __out efx_desc_t *edp);
2606 #if EFSYS_OPT_QSTATS
2612 __in efx_nic_t *etp,
2613 __in unsigned int id);
2615 #endif /* EFSYS_OPT_NAMES */
2618 efx_tx_qstats_update(
2619 __in efx_txq_t *etp,
2620 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2622 #endif /* EFSYS_OPT_QSTATS */
2626 __in efx_txq_t *etp);
2631 #if EFSYS_OPT_FILTER
2633 #define EFX_ETHER_TYPE_IPV4 0x0800
2634 #define EFX_ETHER_TYPE_IPV6 0x86DD
2636 #define EFX_IPPROTO_TCP 6
2637 #define EFX_IPPROTO_UDP 17
2638 #define EFX_IPPROTO_GRE 47
2640 /* Use RSS to spread across multiple queues */
2641 #define EFX_FILTER_FLAG_RX_RSS 0x01
2642 /* Enable RX scatter */
2643 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2645 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2646 * May only be set by the filter implementation for each type.
2647 * A removal request will restore the automatic filter in its place.
2649 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2650 /* Filter is for RX */
2651 #define EFX_FILTER_FLAG_RX 0x08
2652 /* Filter is for TX */
2653 #define EFX_FILTER_FLAG_TX 0x10
2655 typedef uint8_t efx_filter_flags_t;
2658 * Flags which specify the fields to match on. The values are the same as in the
2659 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2662 /* Match by remote IP host address */
2663 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2664 /* Match by local IP host address */
2665 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2666 /* Match by remote MAC address */
2667 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2668 /* Match by remote TCP/UDP port */
2669 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2670 /* Match by remote TCP/UDP port */
2671 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2672 /* Match by local TCP/UDP port */
2673 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2674 /* Match by Ether-type */
2675 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2676 /* Match by inner VLAN ID */
2677 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2678 /* Match by outer VLAN ID */
2679 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2680 /* Match by IP transport protocol */
2681 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2682 /* Match by VNI or VSID */
2683 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2684 /* For encapsulated packets, match by inner frame local MAC address */
2685 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2686 /* For encapsulated packets, match all multicast inner frames */
2687 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2688 /* For encapsulated packets, match all unicast inner frames */
2689 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2691 * Match by encap type, this flag does not correspond to
2692 * the MCDI match flags and any unoccupied value may be used
2694 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2695 /* Match otherwise-unmatched multicast and broadcast packets */
2696 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2697 /* Match otherwise-unmatched unicast packets */
2698 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2700 typedef uint32_t efx_filter_match_flags_t;
2702 typedef enum efx_filter_priority_s {
2703 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2704 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2705 * address list or hardware
2706 * requirements. This may only be used
2707 * by the filter implementation for
2709 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2710 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2711 * client (e.g. SR-IOV, HyperV VMQ etc.)
2713 } efx_filter_priority_t;
2716 * FIXME: All these fields are assumed to be in little-endian byte order.
2717 * It may be better for some to be big-endian. See bug42804.
2720 typedef struct efx_filter_spec_s {
2721 efx_filter_match_flags_t efs_match_flags;
2722 uint8_t efs_priority;
2723 efx_filter_flags_t efs_flags;
2724 uint16_t efs_dmaq_id;
2725 uint32_t efs_rss_context;
2726 uint16_t efs_outer_vid;
2727 uint16_t efs_inner_vid;
2728 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2729 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2730 uint16_t efs_ether_type;
2731 uint8_t efs_ip_proto;
2732 efx_tunnel_protocol_t efs_encap_type;
2733 uint16_t efs_loc_port;
2734 uint16_t efs_rem_port;
2735 efx_oword_t efs_rem_host;
2736 efx_oword_t efs_loc_host;
2737 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2738 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2739 } efx_filter_spec_t;
2742 /* Default values for use in filter specifications */
2743 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2744 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2746 extern __checkReturn efx_rc_t
2748 __in efx_nic_t *enp);
2752 __in efx_nic_t *enp);
2754 extern __checkReturn efx_rc_t
2756 __in efx_nic_t *enp,
2757 __inout efx_filter_spec_t *spec);
2759 extern __checkReturn efx_rc_t
2761 __in efx_nic_t *enp,
2762 __inout efx_filter_spec_t *spec);
2764 extern __checkReturn efx_rc_t
2766 __in efx_nic_t *enp);
2768 extern __checkReturn efx_rc_t
2769 efx_filter_supported_filters(
2770 __in efx_nic_t *enp,
2771 __out_ecount(buffer_length) uint32_t *buffer,
2772 __in size_t buffer_length,
2773 __out size_t *list_lengthp);
2776 efx_filter_spec_init_rx(
2777 __out efx_filter_spec_t *spec,
2778 __in efx_filter_priority_t priority,
2779 __in efx_filter_flags_t flags,
2780 __in efx_rxq_t *erp);
2783 efx_filter_spec_init_tx(
2784 __out efx_filter_spec_t *spec,
2785 __in efx_txq_t *etp);
2787 extern __checkReturn efx_rc_t
2788 efx_filter_spec_set_ipv4_local(
2789 __inout efx_filter_spec_t *spec,
2792 __in uint16_t port);
2794 extern __checkReturn efx_rc_t
2795 efx_filter_spec_set_ipv4_full(
2796 __inout efx_filter_spec_t *spec,
2798 __in uint32_t lhost,
2799 __in uint16_t lport,
2800 __in uint32_t rhost,
2801 __in uint16_t rport);
2803 extern __checkReturn efx_rc_t
2804 efx_filter_spec_set_eth_local(
2805 __inout efx_filter_spec_t *spec,
2807 __in const uint8_t *addr);
2810 efx_filter_spec_set_ether_type(
2811 __inout efx_filter_spec_t *spec,
2812 __in uint16_t ether_type);
2814 extern __checkReturn efx_rc_t
2815 efx_filter_spec_set_uc_def(
2816 __inout efx_filter_spec_t *spec);
2818 extern __checkReturn efx_rc_t
2819 efx_filter_spec_set_mc_def(
2820 __inout efx_filter_spec_t *spec);
2822 typedef enum efx_filter_inner_frame_match_e {
2823 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2824 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2825 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2826 } efx_filter_inner_frame_match_t;
2828 extern __checkReturn efx_rc_t
2829 efx_filter_spec_set_encap_type(
2830 __inout efx_filter_spec_t *spec,
2831 __in efx_tunnel_protocol_t encap_type,
2832 __in efx_filter_inner_frame_match_t inner_frame_match);
2834 extern __checkReturn efx_rc_t
2835 efx_filter_spec_set_vxlan_full(
2836 __inout efx_filter_spec_t *spec,
2837 __in const uint8_t *vxlan_id,
2838 __in const uint8_t *inner_addr,
2839 __in const uint8_t *outer_addr);
2841 #if EFSYS_OPT_RX_SCALE
2842 extern __checkReturn efx_rc_t
2843 efx_filter_spec_set_rss_context(
2844 __inout efx_filter_spec_t *spec,
2845 __in uint32_t rss_context);
2847 #endif /* EFSYS_OPT_FILTER */
2851 extern __checkReturn uint32_t
2853 __in_ecount(count) uint32_t const *input,
2855 __in uint32_t init);
2857 extern __checkReturn uint32_t
2859 __in_ecount(length) uint8_t const *input,
2861 __in uint32_t init);
2863 #if EFSYS_OPT_LICENSING
2867 typedef struct efx_key_stats_s {
2869 uint32_t eks_invalid;
2870 uint32_t eks_blacklisted;
2871 uint32_t eks_unverifiable;
2872 uint32_t eks_wrong_node;
2873 uint32_t eks_licensed_apps_lo;
2874 uint32_t eks_licensed_apps_hi;
2875 uint32_t eks_licensed_features_lo;
2876 uint32_t eks_licensed_features_hi;
2879 extern __checkReturn efx_rc_t
2881 __in efx_nic_t *enp);
2885 __in efx_nic_t *enp);
2887 extern __checkReturn boolean_t
2888 efx_lic_check_support(
2889 __in efx_nic_t *enp);
2891 extern __checkReturn efx_rc_t
2892 efx_lic_update_licenses(
2893 __in efx_nic_t *enp);
2895 extern __checkReturn efx_rc_t
2896 efx_lic_get_key_stats(
2897 __in efx_nic_t *enp,
2898 __out efx_key_stats_t *ksp);
2900 extern __checkReturn efx_rc_t
2902 __in efx_nic_t *enp,
2903 __in uint64_t app_id,
2904 __out boolean_t *licensedp);
2906 extern __checkReturn efx_rc_t
2908 __in efx_nic_t *enp,
2909 __in size_t buffer_size,
2910 __out uint32_t *typep,
2911 __out size_t *lengthp,
2912 __out_opt uint8_t *bufferp);
2915 extern __checkReturn efx_rc_t
2917 __in efx_nic_t *enp,
2918 __in_bcount(buffer_size)
2920 __in size_t buffer_size,
2921 __out uint32_t *startp);
2923 extern __checkReturn efx_rc_t
2925 __in efx_nic_t *enp,
2926 __in_bcount(buffer_size)
2928 __in size_t buffer_size,
2929 __in uint32_t offset,
2930 __out uint32_t *endp);
2932 extern __checkReturn __success(return != B_FALSE) boolean_t
2934 __in efx_nic_t *enp,
2935 __in_bcount(buffer_size)
2937 __in size_t buffer_size,
2938 __in uint32_t offset,
2939 __out uint32_t *startp,
2940 __out uint32_t *lengthp);
2942 extern __checkReturn __success(return != B_FALSE) boolean_t
2943 efx_lic_validate_key(
2944 __in efx_nic_t *enp,
2945 __in_bcount(length) caddr_t keyp,
2946 __in uint32_t length);
2948 extern __checkReturn efx_rc_t
2950 __in efx_nic_t *enp,
2951 __in_bcount(buffer_size)
2953 __in size_t buffer_size,
2954 __in uint32_t offset,
2955 __in uint32_t length,
2956 __out_bcount_part(key_max_size, *lengthp)
2958 __in size_t key_max_size,
2959 __out uint32_t *lengthp);
2961 extern __checkReturn efx_rc_t
2963 __in efx_nic_t *enp,
2964 __in_bcount(buffer_size)
2966 __in size_t buffer_size,
2967 __in uint32_t offset,
2968 __in_bcount(length) caddr_t keyp,
2969 __in uint32_t length,
2970 __out uint32_t *lengthp);
2972 __checkReturn efx_rc_t
2974 __in efx_nic_t *enp,
2975 __in_bcount(buffer_size)
2977 __in size_t buffer_size,
2978 __in uint32_t offset,
2979 __in uint32_t length,
2981 __out uint32_t *deltap);
2983 extern __checkReturn efx_rc_t
2984 efx_lic_create_partition(
2985 __in efx_nic_t *enp,
2986 __in_bcount(buffer_size)
2988 __in size_t buffer_size);
2990 extern __checkReturn efx_rc_t
2991 efx_lic_finish_partition(
2992 __in efx_nic_t *enp,
2993 __in_bcount(buffer_size)
2995 __in size_t buffer_size);
2997 #endif /* EFSYS_OPT_LICENSING */
3001 #if EFSYS_OPT_TUNNEL
3003 extern __checkReturn efx_rc_t
3005 __in efx_nic_t *enp);
3009 __in efx_nic_t *enp);
3012 * For overlay network encapsulation using UDP, the firmware needs to know
3013 * the configured UDP port for the overlay so it can decode encapsulated
3015 * The UDP port/protocol list is global.
3018 extern __checkReturn efx_rc_t
3019 efx_tunnel_config_udp_add(
3020 __in efx_nic_t *enp,
3021 __in uint16_t port /* host/cpu-endian */,
3022 __in efx_tunnel_protocol_t protocol);
3024 extern __checkReturn efx_rc_t
3025 efx_tunnel_config_udp_remove(
3026 __in efx_nic_t *enp,
3027 __in uint16_t port /* host/cpu-endian */,
3028 __in efx_tunnel_protocol_t protocol);
3031 efx_tunnel_config_clear(
3032 __in efx_nic_t *enp);
3035 * Apply tunnel UDP ports configuration to hardware.
3037 * EAGAIN is returned if hardware will be reset (datapath and management CPU
3040 extern __checkReturn efx_rc_t
3041 efx_tunnel_reconfigure(
3042 __in efx_nic_t *enp);
3044 #endif /* EFSYS_OPT_TUNNEL */
3046 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3049 * Firmware subvariant choice options.
3051 * It may be switched to no Tx checksum if attached drivers are either
3052 * preboot or firmware subvariant aware and no VIS are allocated.
3053 * If may be always switched to default explicitly using set request or
3054 * implicitly if unaware driver is attaching. If switching is done when
3055 * a driver is attached, it gets MC_REBOOT event and should recreate its
3058 * See SF-119419-TC DPDK Firmware Driver Interface and
3059 * SF-109306-TC EF10 for Driver Writers for details.
3061 typedef enum efx_nic_fw_subvariant_e {
3062 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3063 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3064 EFX_NIC_FW_SUBVARIANT_NTYPES
3065 } efx_nic_fw_subvariant_t;
3067 extern __checkReturn efx_rc_t
3068 efx_nic_get_fw_subvariant(
3069 __in efx_nic_t *enp,
3070 __out efx_nic_fw_subvariant_t *subvariantp);
3072 extern __checkReturn efx_rc_t
3073 efx_nic_set_fw_subvariant(
3074 __in efx_nic_t *enp,
3075 __in efx_nic_fw_subvariant_t subvariant);
3077 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3083 #endif /* _SYS_EFX_H */