2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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38 #include "efx_annote.h"
40 #include "efx_check.h"
41 #include "efx_phy_ids.h"
47 #define EFX_STATIC_ASSERT(_cond) \
48 ((void)sizeof (char[(_cond) ? 1 : -1]))
50 #define EFX_ARRAY_SIZE(_array) \
51 (sizeof (_array) / sizeof ((_array)[0]))
53 #define EFX_FIELD_OFFSET(_type, _field) \
54 ((size_t)&(((_type *)0)->_field))
56 /* The macro expands divider twice */
57 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
59 /* Round value up to the nearest power of two. */
60 #define EFX_P2ROUNDUP(_type, _value, _align) \
61 (-(-(_type)(_value) & -(_type)(_align)))
63 /* Align value down to the nearest power of two. */
64 #define EFX_P2ALIGN(_type, _value, _align) \
65 ((_type)(_value) & -(_type)(_align))
67 /* Test if value is power of 2 aligned. */
68 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
69 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
73 typedef __success(return == 0) int efx_rc_t;
77 typedef enum efx_family_e {
79 EFX_FAMILY_FALCON, /* Obsolete and not supported */
81 EFX_FAMILY_HUNTINGTON,
87 extern __checkReturn efx_rc_t
91 __out efx_family_t *efp,
92 __out unsigned int *membarp);
94 #define EFX_PCI_VENID_SFC 0x1924
96 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
98 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
99 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
100 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
102 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
103 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
104 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
106 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
107 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
109 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
110 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
111 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
113 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
114 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
115 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
117 #define EFX_MEM_BAR_SIENA 2
119 #define EFX_MEM_BAR_HUNTINGTON_PF 2
120 #define EFX_MEM_BAR_HUNTINGTON_VF 0
122 #define EFX_MEM_BAR_MEDFORD_PF 2
123 #define EFX_MEM_BAR_MEDFORD_VF 0
125 #define EFX_MEM_BAR_MEDFORD2 0
132 EFX_ERR_BUFID_DC_OOB,
145 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
146 extern __checkReturn uint32_t
148 __in uint32_t crc_init,
149 __in_ecount(length) uint8_t const *input,
152 /* Type prototypes */
154 typedef struct efx_rxq_s efx_rxq_t;
158 typedef struct efx_nic_s efx_nic_t;
160 extern __checkReturn efx_rc_t
162 __in efx_family_t family,
163 __in efsys_identifier_t *esip,
164 __in efsys_bar_t *esbp,
165 __in efsys_lock_t *eslp,
166 __deref_out efx_nic_t **enpp);
168 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
169 typedef enum efx_fw_variant_e {
170 EFX_FW_VARIANT_FULL_FEATURED,
171 EFX_FW_VARIANT_LOW_LATENCY,
172 EFX_FW_VARIANT_PACKED_STREAM,
173 EFX_FW_VARIANT_HIGH_TX_RATE,
174 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
175 EFX_FW_VARIANT_RULES_ENGINE,
177 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
180 extern __checkReturn efx_rc_t
183 __in efx_fw_variant_t efv);
185 extern __checkReturn efx_rc_t
187 __in efx_nic_t *enp);
189 extern __checkReturn efx_rc_t
191 __in efx_nic_t *enp);
193 extern __checkReturn boolean_t
194 efx_nic_hw_unavailable(
195 __in efx_nic_t *enp);
198 efx_nic_set_hw_unavailable(
199 __in efx_nic_t *enp);
203 extern __checkReturn efx_rc_t
204 efx_nic_register_test(
205 __in efx_nic_t *enp);
207 #endif /* EFSYS_OPT_DIAG */
211 __in efx_nic_t *enp);
215 __in efx_nic_t *enp);
219 __in efx_nic_t *enp);
221 #define EFX_PCIE_LINK_SPEED_GEN1 1
222 #define EFX_PCIE_LINK_SPEED_GEN2 2
223 #define EFX_PCIE_LINK_SPEED_GEN3 3
225 typedef enum efx_pcie_link_performance_e {
226 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
227 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
228 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
229 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
230 } efx_pcie_link_performance_t;
232 extern __checkReturn efx_rc_t
233 efx_nic_calculate_pcie_link_bandwidth(
234 __in uint32_t pcie_link_width,
235 __in uint32_t pcie_link_gen,
236 __out uint32_t *bandwidth_mbpsp);
238 extern __checkReturn efx_rc_t
239 efx_nic_check_pcie_link_speed(
241 __in uint32_t pcie_link_width,
242 __in uint32_t pcie_link_gen,
243 __out efx_pcie_link_performance_t *resultp);
247 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
248 /* Huntington and Medford require MCDIv2 commands */
249 #define WITH_MCDI_V2 1
252 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
254 typedef enum efx_mcdi_exception_e {
255 EFX_MCDI_EXCEPTION_MC_REBOOT,
256 EFX_MCDI_EXCEPTION_MC_BADASSERT,
257 } efx_mcdi_exception_t;
259 #if EFSYS_OPT_MCDI_LOGGING
260 typedef enum efx_log_msg_e {
262 EFX_LOG_MCDI_REQUEST,
263 EFX_LOG_MCDI_RESPONSE,
265 #endif /* EFSYS_OPT_MCDI_LOGGING */
267 typedef struct efx_mcdi_transport_s {
269 efsys_mem_t *emt_dma_mem;
270 void (*emt_execute)(void *, efx_mcdi_req_t *);
271 void (*emt_ev_cpl)(void *);
272 void (*emt_exception)(void *, efx_mcdi_exception_t);
273 #if EFSYS_OPT_MCDI_LOGGING
274 void (*emt_logger)(void *, efx_log_msg_t,
275 void *, size_t, void *, size_t);
276 #endif /* EFSYS_OPT_MCDI_LOGGING */
277 #if EFSYS_OPT_MCDI_PROXY_AUTH
278 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
279 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
280 } efx_mcdi_transport_t;
282 extern __checkReturn efx_rc_t
285 __in const efx_mcdi_transport_t *mtp);
287 extern __checkReturn efx_rc_t
289 __in efx_nic_t *enp);
293 __in efx_nic_t *enp);
296 efx_mcdi_get_timeout(
298 __in efx_mcdi_req_t *emrp,
299 __out uint32_t *usec_timeoutp);
302 efx_mcdi_request_start(
304 __in efx_mcdi_req_t *emrp,
305 __in boolean_t ev_cpl);
307 extern __checkReturn boolean_t
308 efx_mcdi_request_poll(
309 __in efx_nic_t *enp);
311 extern __checkReturn boolean_t
312 efx_mcdi_request_abort(
313 __in efx_nic_t *enp);
317 __in efx_nic_t *enp);
319 #endif /* EFSYS_OPT_MCDI */
323 #define EFX_NINTR_SIENA 1024
325 typedef enum efx_intr_type_e {
326 EFX_INTR_INVALID = 0,
332 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
334 extern __checkReturn efx_rc_t
337 __in efx_intr_type_t type,
338 __in_opt efsys_mem_t *esmp);
342 __in efx_nic_t *enp);
346 __in efx_nic_t *enp);
349 efx_intr_disable_unlocked(
350 __in efx_nic_t *enp);
352 #define EFX_INTR_NEVQS 32
354 extern __checkReturn efx_rc_t
357 __in unsigned int level);
360 efx_intr_status_line(
362 __out boolean_t *fatalp,
363 __out uint32_t *maskp);
366 efx_intr_status_message(
368 __in unsigned int message,
369 __out boolean_t *fatalp);
373 __in efx_nic_t *enp);
377 __in efx_nic_t *enp);
381 #if EFSYS_OPT_MAC_STATS
383 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
384 typedef enum efx_mac_stat_e {
387 EFX_MAC_RX_UNICST_PKTS,
388 EFX_MAC_RX_MULTICST_PKTS,
389 EFX_MAC_RX_BRDCST_PKTS,
390 EFX_MAC_RX_PAUSE_PKTS,
391 EFX_MAC_RX_LE_64_PKTS,
392 EFX_MAC_RX_65_TO_127_PKTS,
393 EFX_MAC_RX_128_TO_255_PKTS,
394 EFX_MAC_RX_256_TO_511_PKTS,
395 EFX_MAC_RX_512_TO_1023_PKTS,
396 EFX_MAC_RX_1024_TO_15XX_PKTS,
397 EFX_MAC_RX_GE_15XX_PKTS,
399 EFX_MAC_RX_FCS_ERRORS,
400 EFX_MAC_RX_DROP_EVENTS,
401 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
402 EFX_MAC_RX_SYMBOL_ERRORS,
403 EFX_MAC_RX_ALIGN_ERRORS,
404 EFX_MAC_RX_INTERNAL_ERRORS,
405 EFX_MAC_RX_JABBER_PKTS,
406 EFX_MAC_RX_LANE0_CHAR_ERR,
407 EFX_MAC_RX_LANE1_CHAR_ERR,
408 EFX_MAC_RX_LANE2_CHAR_ERR,
409 EFX_MAC_RX_LANE3_CHAR_ERR,
410 EFX_MAC_RX_LANE0_DISP_ERR,
411 EFX_MAC_RX_LANE1_DISP_ERR,
412 EFX_MAC_RX_LANE2_DISP_ERR,
413 EFX_MAC_RX_LANE3_DISP_ERR,
414 EFX_MAC_RX_MATCH_FAULT,
415 EFX_MAC_RX_NODESC_DROP_CNT,
418 EFX_MAC_TX_UNICST_PKTS,
419 EFX_MAC_TX_MULTICST_PKTS,
420 EFX_MAC_TX_BRDCST_PKTS,
421 EFX_MAC_TX_PAUSE_PKTS,
422 EFX_MAC_TX_LE_64_PKTS,
423 EFX_MAC_TX_65_TO_127_PKTS,
424 EFX_MAC_TX_128_TO_255_PKTS,
425 EFX_MAC_TX_256_TO_511_PKTS,
426 EFX_MAC_TX_512_TO_1023_PKTS,
427 EFX_MAC_TX_1024_TO_15XX_PKTS,
428 EFX_MAC_TX_GE_15XX_PKTS,
430 EFX_MAC_TX_SGL_COL_PKTS,
431 EFX_MAC_TX_MULT_COL_PKTS,
432 EFX_MAC_TX_EX_COL_PKTS,
433 EFX_MAC_TX_LATE_COL_PKTS,
435 EFX_MAC_TX_EX_DEF_PKTS,
436 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
437 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
438 EFX_MAC_PM_TRUNC_VFIFO_FULL,
439 EFX_MAC_PM_DISCARD_VFIFO_FULL,
440 EFX_MAC_PM_TRUNC_QBB,
441 EFX_MAC_PM_DISCARD_QBB,
442 EFX_MAC_PM_DISCARD_MAPPING,
443 EFX_MAC_RXDP_Q_DISABLED_PKTS,
444 EFX_MAC_RXDP_DI_DROPPED_PKTS,
445 EFX_MAC_RXDP_STREAMING_PKTS,
446 EFX_MAC_RXDP_HLB_FETCH,
447 EFX_MAC_RXDP_HLB_WAIT,
448 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
449 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
450 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
451 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
452 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
453 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
454 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
455 EFX_MAC_VADAPTER_RX_BAD_BYTES,
456 EFX_MAC_VADAPTER_RX_OVERFLOW,
457 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
458 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
459 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
460 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
461 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
462 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
463 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
464 EFX_MAC_VADAPTER_TX_BAD_BYTES,
465 EFX_MAC_VADAPTER_TX_OVERFLOW,
466 EFX_MAC_FEC_UNCORRECTED_ERRORS,
467 EFX_MAC_FEC_CORRECTED_ERRORS,
468 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
469 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
470 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
471 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
472 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
473 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
474 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
475 EFX_MAC_CTPIO_OVERFLOW_FAIL,
476 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
477 EFX_MAC_CTPIO_TIMEOUT_FAIL,
478 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
479 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
480 EFX_MAC_CTPIO_INVALID_WR_FAIL,
481 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
482 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
483 EFX_MAC_CTPIO_RUNT_FALLBACK,
484 EFX_MAC_CTPIO_SUCCESS,
485 EFX_MAC_CTPIO_FALLBACK,
486 EFX_MAC_CTPIO_POISON,
488 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
489 EFX_MAC_RXDP_HLB_IDLE,
490 EFX_MAC_RXDP_HLB_TIMEOUT,
494 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
496 #endif /* EFSYS_OPT_MAC_STATS */
498 typedef enum efx_link_mode_e {
499 EFX_LINK_UNKNOWN = 0,
515 #define EFX_MAC_ADDR_LEN 6
517 #define EFX_VNI_OR_VSID_LEN 3
519 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
521 #define EFX_MAC_MULTICAST_LIST_MAX 256
523 #define EFX_MAC_SDU_MAX 9202
525 #define EFX_MAC_PDU_ADJUSTMENT \
529 + /* bug16011 */ 16) \
531 #define EFX_MAC_PDU(_sdu) \
532 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
535 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
536 * the SDU rounded up slightly.
538 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
540 #define EFX_MAC_PDU_MIN 60
541 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
543 extern __checkReturn efx_rc_t
548 extern __checkReturn efx_rc_t
553 extern __checkReturn efx_rc_t
558 extern __checkReturn efx_rc_t
561 __in boolean_t all_unicst,
562 __in boolean_t mulcst,
563 __in boolean_t all_mulcst,
564 __in boolean_t brdcst);
566 extern __checkReturn efx_rc_t
567 efx_mac_multicast_list_set(
569 __in_ecount(6*count) uint8_t const *addrs,
572 extern __checkReturn efx_rc_t
573 efx_mac_filter_default_rxq_set(
576 __in boolean_t using_rss);
579 efx_mac_filter_default_rxq_clear(
580 __in efx_nic_t *enp);
582 extern __checkReturn efx_rc_t
585 __in boolean_t enabled);
587 extern __checkReturn efx_rc_t
590 __out boolean_t *mac_upp);
592 #define EFX_FCNTL_RESPOND 0x00000001
593 #define EFX_FCNTL_GENERATE 0x00000002
595 extern __checkReturn efx_rc_t
598 __in unsigned int fcntl,
599 __in boolean_t autoneg);
604 __out unsigned int *fcntl_wantedp,
605 __out unsigned int *fcntl_linkp);
607 #if EFSYS_OPT_MAC_STATS
611 extern __checkReturn const char *
614 __in unsigned int id);
616 #endif /* EFSYS_OPT_NAMES */
618 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
620 #define EFX_MAC_STATS_MASK_NPAGES \
621 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
622 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
623 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
626 * Get mask of MAC statistics supported by the hardware.
628 * If mask_size is insufficient to return the mask, EINVAL error is
629 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
630 * (which is sizeof (uint32_t)) is sufficient.
632 extern __checkReturn efx_rc_t
633 efx_mac_stats_get_mask(
635 __out_bcount(mask_size) uint32_t *maskp,
636 __in size_t mask_size);
638 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
639 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
640 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
642 extern __checkReturn efx_rc_t
644 __in efx_nic_t *enp);
647 * Upload mac statistics supported by the hardware into the given buffer.
649 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
650 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
652 * The hardware will only DMA statistics that it understands (of course).
653 * Drivers should not make any assumptions about which statistics are
654 * supported, especially when the statistics are generated by firmware.
656 * Thus, drivers should zero this buffer before use, so that not-understood
657 * statistics read back as zero.
659 extern __checkReturn efx_rc_t
660 efx_mac_stats_upload(
662 __in efsys_mem_t *esmp);
664 extern __checkReturn efx_rc_t
665 efx_mac_stats_periodic(
667 __in efsys_mem_t *esmp,
668 __in uint16_t period_ms,
669 __in boolean_t events);
671 extern __checkReturn efx_rc_t
672 efx_mac_stats_update(
674 __in efsys_mem_t *esmp,
675 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
676 __inout_opt uint32_t *generationp);
678 #endif /* EFSYS_OPT_MAC_STATS */
682 typedef enum efx_mon_type_e {
694 __in efx_nic_t *enp);
696 #endif /* EFSYS_OPT_NAMES */
698 extern __checkReturn efx_rc_t
700 __in efx_nic_t *enp);
702 #if EFSYS_OPT_MON_STATS
704 #define EFX_MON_STATS_PAGE_SIZE 0x100
705 #define EFX_MON_MASK_ELEMENT_SIZE 32
707 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
708 typedef enum efx_mon_stat_e {
709 EFX_MON_STAT_CONTROLLER_TEMP,
710 EFX_MON_STAT_PHY_COMMON_TEMP,
711 EFX_MON_STAT_CONTROLLER_COOLING,
712 EFX_MON_STAT_PHY0_TEMP,
713 EFX_MON_STAT_PHY0_COOLING,
714 EFX_MON_STAT_PHY1_TEMP,
715 EFX_MON_STAT_PHY1_COOLING,
721 EFX_MON_STAT_IN_12V0,
722 EFX_MON_STAT_IN_1V2A,
723 EFX_MON_STAT_IN_VREF,
724 EFX_MON_STAT_OUT_VAOE,
725 EFX_MON_STAT_AOE_TEMP,
726 EFX_MON_STAT_PSU_AOE_TEMP,
727 EFX_MON_STAT_PSU_TEMP,
733 EFX_MON_STAT_IN_VAOE,
734 EFX_MON_STAT_OUT_IAOE,
735 EFX_MON_STAT_IN_IAOE,
736 EFX_MON_STAT_NIC_POWER,
738 EFX_MON_STAT_IN_I0V9,
739 EFX_MON_STAT_IN_I1V2,
740 EFX_MON_STAT_IN_0V9_ADC,
741 EFX_MON_STAT_CONTROLLER_2_TEMP,
742 EFX_MON_STAT_VREG_INTERNAL_TEMP,
743 EFX_MON_STAT_VREG_0V9_TEMP,
744 EFX_MON_STAT_VREG_1V2_TEMP,
745 EFX_MON_STAT_CONTROLLER_VPTAT,
746 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
747 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
748 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
749 EFX_MON_STAT_AMBIENT_TEMP,
750 EFX_MON_STAT_AIRFLOW,
751 EFX_MON_STAT_VDD08D_VSS08D_CSR,
752 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
753 EFX_MON_STAT_HOTPOINT_TEMP,
754 EFX_MON_STAT_PHY_POWER_PORT0,
755 EFX_MON_STAT_PHY_POWER_PORT1,
756 EFX_MON_STAT_MUM_VCC,
757 EFX_MON_STAT_IN_0V9_A,
758 EFX_MON_STAT_IN_I0V9_A,
759 EFX_MON_STAT_VREG_0V9_A_TEMP,
760 EFX_MON_STAT_IN_0V9_B,
761 EFX_MON_STAT_IN_I0V9_B,
762 EFX_MON_STAT_VREG_0V9_B_TEMP,
763 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
764 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
765 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
766 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
767 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
768 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
769 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
770 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
771 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
772 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
773 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
774 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
775 EFX_MON_STAT_SODIMM_VOUT,
776 EFX_MON_STAT_SODIMM_0_TEMP,
777 EFX_MON_STAT_SODIMM_1_TEMP,
778 EFX_MON_STAT_PHY0_VCC,
779 EFX_MON_STAT_PHY1_VCC,
780 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
781 EFX_MON_STAT_BOARD_FRONT_TEMP,
782 EFX_MON_STAT_BOARD_BACK_TEMP,
783 EFX_MON_STAT_IN_I1V8,
784 EFX_MON_STAT_IN_I2V5,
785 EFX_MON_STAT_IN_I3V3,
786 EFX_MON_STAT_IN_I12V0,
788 EFX_MON_STAT_IN_I1V3,
792 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
794 typedef enum efx_mon_stat_state_e {
795 EFX_MON_STAT_STATE_OK = 0,
796 EFX_MON_STAT_STATE_WARNING = 1,
797 EFX_MON_STAT_STATE_FATAL = 2,
798 EFX_MON_STAT_STATE_BROKEN = 3,
799 EFX_MON_STAT_STATE_NO_READING = 4,
800 } efx_mon_stat_state_t;
802 typedef enum efx_mon_stat_unit_e {
803 EFX_MON_STAT_UNIT_UNKNOWN = 0,
804 EFX_MON_STAT_UNIT_BOOL,
805 EFX_MON_STAT_UNIT_TEMP_C,
806 EFX_MON_STAT_UNIT_VOLTAGE_MV,
807 EFX_MON_STAT_UNIT_CURRENT_MA,
808 EFX_MON_STAT_UNIT_POWER_W,
809 EFX_MON_STAT_UNIT_RPM,
811 } efx_mon_stat_unit_t;
813 typedef struct efx_mon_stat_value_s {
815 efx_mon_stat_state_t emsv_state;
816 efx_mon_stat_unit_t emsv_unit;
817 } efx_mon_stat_value_t;
819 typedef struct efx_mon_limit_value_s {
820 uint16_t emlv_warning_min;
821 uint16_t emlv_warning_max;
822 uint16_t emlv_fatal_min;
823 uint16_t emlv_fatal_max;
824 } efx_mon_stat_limits_t;
826 typedef enum efx_mon_stat_portmask_e {
827 EFX_MON_STAT_PORTMAP_NONE = 0,
828 EFX_MON_STAT_PORTMAP_PORT0 = 1,
829 EFX_MON_STAT_PORTMAP_PORT1 = 2,
830 EFX_MON_STAT_PORTMAP_PORT2 = 3,
831 EFX_MON_STAT_PORTMAP_PORT3 = 4,
832 EFX_MON_STAT_PORTMAP_ALL = (-1),
833 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
834 } efx_mon_stat_portmask_t;
841 __in efx_mon_stat_t id);
844 efx_mon_stat_description(
846 __in efx_mon_stat_t id);
848 #endif /* EFSYS_OPT_NAMES */
850 extern __checkReturn boolean_t
851 efx_mon_mcdi_to_efx_stat(
853 __out efx_mon_stat_t *statp);
855 extern __checkReturn boolean_t
856 efx_mon_get_stat_unit(
857 __in efx_mon_stat_t stat,
858 __out efx_mon_stat_unit_t *unitp);
860 extern __checkReturn boolean_t
861 efx_mon_get_stat_portmap(
862 __in efx_mon_stat_t stat,
863 __out efx_mon_stat_portmask_t *maskp);
865 extern __checkReturn efx_rc_t
866 efx_mon_stats_update(
868 __in efsys_mem_t *esmp,
869 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
871 extern __checkReturn efx_rc_t
872 efx_mon_limits_update(
874 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
876 #endif /* EFSYS_OPT_MON_STATS */
880 __in efx_nic_t *enp);
884 extern __checkReturn efx_rc_t
886 __in efx_nic_t *enp);
888 #if EFSYS_OPT_PHY_LED_CONTROL
890 typedef enum efx_phy_led_mode_e {
891 EFX_PHY_LED_DEFAULT = 0,
896 } efx_phy_led_mode_t;
898 extern __checkReturn efx_rc_t
901 __in efx_phy_led_mode_t mode);
903 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
905 extern __checkReturn efx_rc_t
907 __in efx_nic_t *enp);
909 #if EFSYS_OPT_LOOPBACK
911 typedef enum efx_loopback_type_e {
912 EFX_LOOPBACK_OFF = 0,
913 EFX_LOOPBACK_DATA = 1,
914 EFX_LOOPBACK_GMAC = 2,
915 EFX_LOOPBACK_XGMII = 3,
916 EFX_LOOPBACK_XGXS = 4,
917 EFX_LOOPBACK_XAUI = 5,
918 EFX_LOOPBACK_GMII = 6,
919 EFX_LOOPBACK_SGMII = 7,
920 EFX_LOOPBACK_XGBR = 8,
921 EFX_LOOPBACK_XFI = 9,
922 EFX_LOOPBACK_XAUI_FAR = 10,
923 EFX_LOOPBACK_GMII_FAR = 11,
924 EFX_LOOPBACK_SGMII_FAR = 12,
925 EFX_LOOPBACK_XFI_FAR = 13,
926 EFX_LOOPBACK_GPHY = 14,
927 EFX_LOOPBACK_PHY_XS = 15,
928 EFX_LOOPBACK_PCS = 16,
929 EFX_LOOPBACK_PMA_PMD = 17,
930 EFX_LOOPBACK_XPORT = 18,
931 EFX_LOOPBACK_XGMII_WS = 19,
932 EFX_LOOPBACK_XAUI_WS = 20,
933 EFX_LOOPBACK_XAUI_WS_FAR = 21,
934 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
935 EFX_LOOPBACK_GMII_WS = 23,
936 EFX_LOOPBACK_XFI_WS = 24,
937 EFX_LOOPBACK_XFI_WS_FAR = 25,
938 EFX_LOOPBACK_PHYXS_WS = 26,
939 EFX_LOOPBACK_PMA_INT = 27,
940 EFX_LOOPBACK_SD_NEAR = 28,
941 EFX_LOOPBACK_SD_FAR = 29,
942 EFX_LOOPBACK_PMA_INT_WS = 30,
943 EFX_LOOPBACK_SD_FEP2_WS = 31,
944 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
945 EFX_LOOPBACK_SD_FEP_WS = 33,
946 EFX_LOOPBACK_SD_FES_WS = 34,
947 EFX_LOOPBACK_AOE_INT_NEAR = 35,
948 EFX_LOOPBACK_DATA_WS = 36,
949 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
951 } efx_loopback_type_t;
953 typedef enum efx_loopback_kind_e {
954 EFX_LOOPBACK_KIND_OFF = 0,
955 EFX_LOOPBACK_KIND_ALL,
956 EFX_LOOPBACK_KIND_MAC,
957 EFX_LOOPBACK_KIND_PHY,
959 } efx_loopback_kind_t;
963 __in efx_loopback_kind_t loopback_kind,
964 __out efx_qword_t *maskp);
966 extern __checkReturn efx_rc_t
967 efx_port_loopback_set(
969 __in efx_link_mode_t link_mode,
970 __in efx_loopback_type_t type);
974 extern __checkReturn const char *
975 efx_loopback_type_name(
977 __in efx_loopback_type_t type);
979 #endif /* EFSYS_OPT_NAMES */
981 #endif /* EFSYS_OPT_LOOPBACK */
983 extern __checkReturn efx_rc_t
986 __out_opt efx_link_mode_t *link_modep);
990 __in efx_nic_t *enp);
992 typedef enum efx_phy_cap_type_e {
993 EFX_PHY_CAP_INVALID = 0,
1000 EFX_PHY_CAP_10000FDX,
1004 EFX_PHY_CAP_40000FDX,
1006 EFX_PHY_CAP_100000FDX,
1007 EFX_PHY_CAP_25000FDX,
1008 EFX_PHY_CAP_50000FDX,
1009 EFX_PHY_CAP_BASER_FEC,
1010 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1012 EFX_PHY_CAP_RS_FEC_REQUESTED,
1013 EFX_PHY_CAP_25G_BASER_FEC,
1014 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1016 } efx_phy_cap_type_t;
1018 #define EFX_PHY_CAP_CURRENT 0x00000000
1019 #define EFX_PHY_CAP_DEFAULT 0x00000001
1020 #define EFX_PHY_CAP_PERM 0x00000002
1023 efx_phy_adv_cap_get(
1024 __in efx_nic_t *enp,
1026 __out uint32_t *maskp);
1028 extern __checkReturn efx_rc_t
1029 efx_phy_adv_cap_set(
1030 __in efx_nic_t *enp,
1031 __in uint32_t mask);
1035 __in efx_nic_t *enp,
1036 __out uint32_t *maskp);
1038 extern __checkReturn efx_rc_t
1040 __in efx_nic_t *enp,
1041 __out uint32_t *ouip);
1043 typedef enum efx_phy_media_type_e {
1044 EFX_PHY_MEDIA_INVALID = 0,
1049 EFX_PHY_MEDIA_SFP_PLUS,
1050 EFX_PHY_MEDIA_BASE_T,
1051 EFX_PHY_MEDIA_QSFP_PLUS,
1052 EFX_PHY_MEDIA_NTYPES
1053 } efx_phy_media_type_t;
1056 * Get the type of medium currently used. If the board has ports for
1057 * modules, a module is present, and we recognise the media type of
1058 * the module, then this will be the media type of the module.
1059 * Otherwise it will be the media type of the port.
1062 efx_phy_media_type_get(
1063 __in efx_nic_t *enp,
1064 __out efx_phy_media_type_t *typep);
1067 * 2-wire device address of the base information in accordance with SFF-8472
1068 * Diagnostic Monitoring Interface for Optical Transceivers section
1069 * 4 Memory Organization.
1071 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1074 * 2-wire device address of the digital diagnostics monitoring interface
1075 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1076 * Transceivers section 4 Memory Organization.
1078 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1081 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1082 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1085 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1088 * Maximum accessible data offset for PHY module information.
1090 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1092 extern __checkReturn efx_rc_t
1093 efx_phy_module_get_info(
1094 __in efx_nic_t *enp,
1095 __in uint8_t dev_addr,
1098 __out_bcount(len) uint8_t *data);
1100 #if EFSYS_OPT_PHY_STATS
1102 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1103 typedef enum efx_phy_stat_e {
1105 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1106 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1107 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1108 EFX_PHY_STAT_PMA_PMD_REV_A,
1109 EFX_PHY_STAT_PMA_PMD_REV_B,
1110 EFX_PHY_STAT_PMA_PMD_REV_C,
1111 EFX_PHY_STAT_PMA_PMD_REV_D,
1112 EFX_PHY_STAT_PCS_LINK_UP,
1113 EFX_PHY_STAT_PCS_RX_FAULT,
1114 EFX_PHY_STAT_PCS_TX_FAULT,
1115 EFX_PHY_STAT_PCS_BER,
1116 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1117 EFX_PHY_STAT_PHY_XS_LINK_UP,
1118 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1119 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1120 EFX_PHY_STAT_PHY_XS_ALIGN,
1121 EFX_PHY_STAT_PHY_XS_SYNC_A,
1122 EFX_PHY_STAT_PHY_XS_SYNC_B,
1123 EFX_PHY_STAT_PHY_XS_SYNC_C,
1124 EFX_PHY_STAT_PHY_XS_SYNC_D,
1125 EFX_PHY_STAT_AN_LINK_UP,
1126 EFX_PHY_STAT_AN_MASTER,
1127 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1128 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1129 EFX_PHY_STAT_CL22EXT_LINK_UP,
1134 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1135 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1136 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1137 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1138 EFX_PHY_STAT_AN_COMPLETE,
1139 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1140 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1141 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1142 EFX_PHY_STAT_PCS_FW_VERSION_0,
1143 EFX_PHY_STAT_PCS_FW_VERSION_1,
1144 EFX_PHY_STAT_PCS_FW_VERSION_2,
1145 EFX_PHY_STAT_PCS_FW_VERSION_3,
1146 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1147 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1148 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1149 EFX_PHY_STAT_PCS_OP_MODE,
1153 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1159 __in efx_nic_t *enp,
1160 __in efx_phy_stat_t stat);
1162 #endif /* EFSYS_OPT_NAMES */
1164 #define EFX_PHY_STATS_SIZE 0x100
1166 extern __checkReturn efx_rc_t
1167 efx_phy_stats_update(
1168 __in efx_nic_t *enp,
1169 __in efsys_mem_t *esmp,
1170 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1172 #endif /* EFSYS_OPT_PHY_STATS */
1176 typedef enum efx_bist_type_e {
1177 EFX_BIST_TYPE_UNKNOWN,
1178 EFX_BIST_TYPE_PHY_NORMAL,
1179 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1180 EFX_BIST_TYPE_PHY_CABLE_LONG,
1181 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1182 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1183 EFX_BIST_TYPE_REG, /* Test the register memories */
1184 EFX_BIST_TYPE_NTYPES,
1187 typedef enum efx_bist_result_e {
1188 EFX_BIST_RESULT_UNKNOWN,
1189 EFX_BIST_RESULT_RUNNING,
1190 EFX_BIST_RESULT_PASSED,
1191 EFX_BIST_RESULT_FAILED,
1192 } efx_bist_result_t;
1194 typedef enum efx_phy_cable_status_e {
1195 EFX_PHY_CABLE_STATUS_OK,
1196 EFX_PHY_CABLE_STATUS_INVALID,
1197 EFX_PHY_CABLE_STATUS_OPEN,
1198 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1199 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1200 EFX_PHY_CABLE_STATUS_BUSY,
1201 } efx_phy_cable_status_t;
1203 typedef enum efx_bist_value_e {
1204 EFX_BIST_PHY_CABLE_LENGTH_A,
1205 EFX_BIST_PHY_CABLE_LENGTH_B,
1206 EFX_BIST_PHY_CABLE_LENGTH_C,
1207 EFX_BIST_PHY_CABLE_LENGTH_D,
1208 EFX_BIST_PHY_CABLE_STATUS_A,
1209 EFX_BIST_PHY_CABLE_STATUS_B,
1210 EFX_BIST_PHY_CABLE_STATUS_C,
1211 EFX_BIST_PHY_CABLE_STATUS_D,
1212 EFX_BIST_FAULT_CODE,
1214 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1220 EFX_BIST_MEM_EXPECT,
1221 EFX_BIST_MEM_ACTUAL,
1223 EFX_BIST_MEM_ECC_PARITY,
1224 EFX_BIST_MEM_ECC_FATAL,
1228 extern __checkReturn efx_rc_t
1229 efx_bist_enable_offline(
1230 __in efx_nic_t *enp);
1232 extern __checkReturn efx_rc_t
1234 __in efx_nic_t *enp,
1235 __in efx_bist_type_t type);
1237 extern __checkReturn efx_rc_t
1239 __in efx_nic_t *enp,
1240 __in efx_bist_type_t type,
1241 __out efx_bist_result_t *resultp,
1242 __out_opt uint32_t *value_maskp,
1243 __out_ecount_opt(count) unsigned long *valuesp,
1248 __in efx_nic_t *enp,
1249 __in efx_bist_type_t type);
1251 #endif /* EFSYS_OPT_BIST */
1253 #define EFX_FEATURE_IPV6 0x00000001
1254 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1255 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1256 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1257 #define EFX_FEATURE_MCDI 0x00000020
1258 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1259 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1260 #define EFX_FEATURE_TURBO 0x00000100
1261 #define EFX_FEATURE_MCDI_DMA 0x00000200
1262 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1263 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1264 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1265 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1266 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1267 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1269 typedef enum efx_tunnel_protocol_e {
1270 EFX_TUNNEL_PROTOCOL_NONE = 0,
1271 EFX_TUNNEL_PROTOCOL_VXLAN,
1272 EFX_TUNNEL_PROTOCOL_GENEVE,
1273 EFX_TUNNEL_PROTOCOL_NVGRE,
1275 } efx_tunnel_protocol_t;
1277 typedef enum efx_vi_window_shift_e {
1278 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1279 EFX_VI_WINDOW_SHIFT_8K = 13,
1280 EFX_VI_WINDOW_SHIFT_16K = 14,
1281 EFX_VI_WINDOW_SHIFT_64K = 16,
1282 } efx_vi_window_shift_t;
1284 typedef struct efx_nic_cfg_s {
1285 uint32_t enc_board_type;
1286 uint32_t enc_phy_type;
1288 char enc_phy_name[21];
1290 char enc_phy_revision[21];
1291 efx_mon_type_t enc_mon_type;
1292 #if EFSYS_OPT_MON_STATS
1293 uint32_t enc_mon_stat_dma_buf_size;
1294 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1296 unsigned int enc_features;
1297 efx_vi_window_shift_t enc_vi_window_shift;
1298 uint8_t enc_mac_addr[6];
1299 uint8_t enc_port; /* PHY port number */
1300 uint32_t enc_intr_vec_base;
1301 uint32_t enc_intr_limit;
1302 uint32_t enc_evq_limit;
1303 uint32_t enc_txq_limit;
1304 uint32_t enc_rxq_limit;
1305 uint32_t enc_txq_max_ndescs;
1306 uint32_t enc_buftbl_limit;
1307 uint32_t enc_piobuf_limit;
1308 uint32_t enc_piobuf_size;
1309 uint32_t enc_piobuf_min_alloc_size;
1310 uint32_t enc_evq_timer_quantum_ns;
1311 uint32_t enc_evq_timer_max_us;
1312 uint32_t enc_clk_mult;
1313 uint32_t enc_rx_prefix_size;
1314 uint32_t enc_rx_buf_align_start;
1315 uint32_t enc_rx_buf_align_end;
1316 #if EFSYS_OPT_RX_SCALE
1317 uint32_t enc_rx_scale_max_exclusive_contexts;
1319 * Mask of supported hash algorithms.
1320 * Hash algorithm types are used as the bit indices.
1322 uint32_t enc_rx_scale_hash_alg_mask;
1324 * Indicates whether port numbers can be included to the
1325 * input data for hash computation.
1327 boolean_t enc_rx_scale_l4_hash_supported;
1328 boolean_t enc_rx_scale_additional_modes_supported;
1329 #endif /* EFSYS_OPT_RX_SCALE */
1330 #if EFSYS_OPT_LOOPBACK
1331 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1332 #endif /* EFSYS_OPT_LOOPBACK */
1333 #if EFSYS_OPT_PHY_FLAGS
1334 uint32_t enc_phy_flags_mask;
1335 #endif /* EFSYS_OPT_PHY_FLAGS */
1336 #if EFSYS_OPT_PHY_LED_CONTROL
1337 uint32_t enc_led_mask;
1338 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1339 #if EFSYS_OPT_PHY_STATS
1340 uint64_t enc_phy_stat_mask;
1341 #endif /* EFSYS_OPT_PHY_STATS */
1343 uint8_t enc_mcdi_mdio_channel;
1344 #if EFSYS_OPT_PHY_STATS
1345 uint32_t enc_mcdi_phy_stat_mask;
1346 #endif /* EFSYS_OPT_PHY_STATS */
1347 #if EFSYS_OPT_MON_STATS
1348 uint32_t *enc_mcdi_sensor_maskp;
1349 uint32_t enc_mcdi_sensor_mask_size;
1350 #endif /* EFSYS_OPT_MON_STATS */
1351 #endif /* EFSYS_OPT_MCDI */
1353 uint32_t enc_bist_mask;
1354 #endif /* EFSYS_OPT_BIST */
1355 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1358 uint32_t enc_privilege_mask;
1359 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1360 boolean_t enc_bug26807_workaround;
1361 boolean_t enc_bug35388_workaround;
1362 boolean_t enc_bug41750_workaround;
1363 boolean_t enc_bug61265_workaround;
1364 boolean_t enc_bug61297_workaround;
1365 boolean_t enc_rx_batching_enabled;
1366 /* Maximum number of descriptors completed in an rx event. */
1367 uint32_t enc_rx_batch_max;
1368 /* Number of rx descriptors the hardware requires for a push. */
1369 uint32_t enc_rx_push_align;
1370 /* Maximum amount of data in DMA descriptor */
1371 uint32_t enc_tx_dma_desc_size_max;
1373 * Boundary which DMA descriptor data must not cross or 0 if no
1376 uint32_t enc_tx_dma_desc_boundary;
1378 * Maximum number of bytes into the packet the TCP header can start for
1379 * the hardware to apply TSO packet edits.
1381 uint32_t enc_tx_tso_tcp_header_offset_limit;
1382 boolean_t enc_fw_assisted_tso_enabled;
1383 boolean_t enc_fw_assisted_tso_v2_enabled;
1384 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1385 /* Number of TSO contexts on the NIC (FATSOv2) */
1386 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1387 boolean_t enc_hw_tx_insert_vlan_enabled;
1388 /* Number of PFs on the NIC */
1389 uint32_t enc_hw_pf_count;
1390 /* Datapath firmware vadapter/vport/vswitch support */
1391 boolean_t enc_datapath_cap_evb;
1392 boolean_t enc_rx_disable_scatter_supported;
1393 boolean_t enc_allow_set_mac_with_installed_filters;
1394 boolean_t enc_enhanced_set_mac_supported;
1395 boolean_t enc_init_evq_v2_supported;
1396 boolean_t enc_rx_packed_stream_supported;
1397 boolean_t enc_rx_var_packed_stream_supported;
1398 boolean_t enc_rx_es_super_buffer_supported;
1399 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1400 boolean_t enc_pm_and_rxdp_counters;
1401 boolean_t enc_mac_stats_40g_tx_size_bins;
1402 uint32_t enc_tunnel_encapsulations_supported;
1404 * NIC global maximum for unique UDP tunnel ports shared by all
1407 uint32_t enc_tunnel_config_udp_entries_max;
1408 /* External port identifier */
1409 uint8_t enc_external_port;
1410 uint32_t enc_mcdi_max_payload_length;
1411 /* VPD may be per-PF or global */
1412 boolean_t enc_vpd_is_global;
1413 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1414 uint32_t enc_required_pcie_bandwidth_mbps;
1415 uint32_t enc_max_pcie_link_gen;
1416 /* Firmware verifies integrity of NVRAM updates */
1417 uint32_t enc_nvram_update_verify_result_supported;
1418 /* Firmware support for extended MAC_STATS buffer */
1419 uint32_t enc_mac_stats_nstats;
1420 boolean_t enc_fec_counters;
1421 boolean_t enc_hlb_counters;
1422 /* Firmware support for "FLAG" and "MARK" filter actions */
1423 boolean_t enc_filter_action_flag_supported;
1424 boolean_t enc_filter_action_mark_supported;
1425 uint32_t enc_filter_action_mark_max;
1428 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1429 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1431 #define EFX_PCI_FUNCTION(_encp) \
1432 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1434 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1436 extern const efx_nic_cfg_t *
1438 __in efx_nic_t *enp);
1440 /* RxDPCPU firmware id values by which FW variant can be identified */
1441 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1442 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1443 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1444 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1445 #define EFX_RXDP_DPDK_FW_ID 0x6
1447 typedef struct efx_nic_fw_info_s {
1448 /* Basic FW version information */
1449 uint16_t enfi_mc_fw_version[4];
1451 * If datapath capabilities can be detected,
1452 * additional FW information is to be shown
1454 boolean_t enfi_dpcpu_fw_ids_valid;
1455 /* Rx and Tx datapath CPU FW IDs */
1456 uint16_t enfi_rx_dpcpu_fw_id;
1457 uint16_t enfi_tx_dpcpu_fw_id;
1458 } efx_nic_fw_info_t;
1460 extern __checkReturn efx_rc_t
1461 efx_nic_get_fw_version(
1462 __in efx_nic_t *enp,
1463 __out efx_nic_fw_info_t *enfip);
1465 /* Driver resource limits (minimum required/maximum usable). */
1466 typedef struct efx_drv_limits_s {
1467 uint32_t edl_min_evq_count;
1468 uint32_t edl_max_evq_count;
1470 uint32_t edl_min_rxq_count;
1471 uint32_t edl_max_rxq_count;
1473 uint32_t edl_min_txq_count;
1474 uint32_t edl_max_txq_count;
1476 /* PIO blocks (sub-allocated from piobuf) */
1477 uint32_t edl_min_pio_alloc_size;
1478 uint32_t edl_max_pio_alloc_count;
1481 extern __checkReturn efx_rc_t
1482 efx_nic_set_drv_limits(
1483 __inout efx_nic_t *enp,
1484 __in efx_drv_limits_t *edlp);
1486 typedef enum efx_nic_region_e {
1487 EFX_REGION_VI, /* Memory BAR UC mapping */
1488 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1491 extern __checkReturn efx_rc_t
1492 efx_nic_get_bar_region(
1493 __in efx_nic_t *enp,
1494 __in efx_nic_region_t region,
1495 __out uint32_t *offsetp,
1496 __out size_t *sizep);
1498 extern __checkReturn efx_rc_t
1499 efx_nic_get_vi_pool(
1500 __in efx_nic_t *enp,
1501 __out uint32_t *evq_countp,
1502 __out uint32_t *rxq_countp,
1503 __out uint32_t *txq_countp);
1507 typedef enum efx_vpd_tag_e {
1514 typedef uint16_t efx_vpd_keyword_t;
1516 typedef struct efx_vpd_value_s {
1517 efx_vpd_tag_t evv_tag;
1518 efx_vpd_keyword_t evv_keyword;
1520 uint8_t evv_value[0x100];
1523 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1525 extern __checkReturn efx_rc_t
1527 __in efx_nic_t *enp);
1529 extern __checkReturn efx_rc_t
1531 __in efx_nic_t *enp,
1532 __out size_t *sizep);
1534 extern __checkReturn efx_rc_t
1536 __in efx_nic_t *enp,
1537 __out_bcount(size) caddr_t data,
1540 extern __checkReturn efx_rc_t
1542 __in efx_nic_t *enp,
1543 __in_bcount(size) caddr_t data,
1546 extern __checkReturn efx_rc_t
1548 __in efx_nic_t *enp,
1549 __in_bcount(size) caddr_t data,
1552 extern __checkReturn efx_rc_t
1554 __in efx_nic_t *enp,
1555 __in_bcount(size) caddr_t data,
1557 __inout efx_vpd_value_t *evvp);
1559 extern __checkReturn efx_rc_t
1561 __in efx_nic_t *enp,
1562 __inout_bcount(size) caddr_t data,
1564 __in efx_vpd_value_t *evvp);
1566 extern __checkReturn efx_rc_t
1568 __in efx_nic_t *enp,
1569 __inout_bcount(size) caddr_t data,
1571 __out efx_vpd_value_t *evvp,
1572 __inout unsigned int *contp);
1574 extern __checkReturn efx_rc_t
1576 __in efx_nic_t *enp,
1577 __in_bcount(size) caddr_t data,
1582 __in efx_nic_t *enp);
1584 #endif /* EFSYS_OPT_VPD */
1590 typedef enum efx_nvram_type_e {
1591 EFX_NVRAM_INVALID = 0,
1593 EFX_NVRAM_BOOTROM_CFG,
1594 EFX_NVRAM_MC_FIRMWARE,
1595 EFX_NVRAM_MC_GOLDEN,
1601 EFX_NVRAM_FPGA_BACKUP,
1602 EFX_NVRAM_DYNAMIC_CFG,
1605 EFX_NVRAM_MUM_FIRMWARE,
1606 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1607 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1611 extern __checkReturn efx_rc_t
1613 __in efx_nic_t *enp);
1617 extern __checkReturn efx_rc_t
1619 __in efx_nic_t *enp);
1621 #endif /* EFSYS_OPT_DIAG */
1623 extern __checkReturn efx_rc_t
1625 __in efx_nic_t *enp,
1626 __in efx_nvram_type_t type,
1627 __out size_t *sizep);
1629 extern __checkReturn efx_rc_t
1631 __in efx_nic_t *enp,
1632 __in efx_nvram_type_t type,
1633 __out_opt size_t *pref_chunkp);
1635 extern __checkReturn efx_rc_t
1636 efx_nvram_rw_finish(
1637 __in efx_nic_t *enp,
1638 __in efx_nvram_type_t type,
1639 __out_opt uint32_t *verify_resultp);
1641 extern __checkReturn efx_rc_t
1642 efx_nvram_get_version(
1643 __in efx_nic_t *enp,
1644 __in efx_nvram_type_t type,
1645 __out uint32_t *subtypep,
1646 __out_ecount(4) uint16_t version[4]);
1648 extern __checkReturn efx_rc_t
1649 efx_nvram_read_chunk(
1650 __in efx_nic_t *enp,
1651 __in efx_nvram_type_t type,
1652 __in unsigned int offset,
1653 __out_bcount(size) caddr_t data,
1656 extern __checkReturn efx_rc_t
1657 efx_nvram_read_backup(
1658 __in efx_nic_t *enp,
1659 __in efx_nvram_type_t type,
1660 __in unsigned int offset,
1661 __out_bcount(size) caddr_t data,
1664 extern __checkReturn efx_rc_t
1665 efx_nvram_set_version(
1666 __in efx_nic_t *enp,
1667 __in efx_nvram_type_t type,
1668 __in_ecount(4) uint16_t version[4]);
1670 extern __checkReturn efx_rc_t
1672 __in efx_nic_t *enp,
1673 __in efx_nvram_type_t type,
1674 __in_bcount(partn_size) caddr_t partn_data,
1675 __in size_t partn_size);
1677 extern __checkReturn efx_rc_t
1679 __in efx_nic_t *enp,
1680 __in efx_nvram_type_t type);
1682 extern __checkReturn efx_rc_t
1683 efx_nvram_write_chunk(
1684 __in efx_nic_t *enp,
1685 __in efx_nvram_type_t type,
1686 __in unsigned int offset,
1687 __in_bcount(size) caddr_t data,
1692 __in efx_nic_t *enp);
1694 #endif /* EFSYS_OPT_NVRAM */
1696 #if EFSYS_OPT_BOOTCFG
1698 /* Report size and offset of bootcfg sector in NVRAM partition. */
1699 extern __checkReturn efx_rc_t
1700 efx_bootcfg_sector_info(
1701 __in efx_nic_t *enp,
1703 __out_opt uint32_t *sector_countp,
1704 __out size_t *offsetp,
1705 __out size_t *max_sizep);
1708 * Copy bootcfg sector data to a target buffer which may differ in size.
1709 * Optionally corrects format errors in source buffer.
1712 efx_bootcfg_copy_sector(
1713 __in efx_nic_t *enp,
1714 __inout_bcount(sector_length)
1716 __in size_t sector_length,
1717 __out_bcount(data_size) uint8_t *data,
1718 __in size_t data_size,
1719 __in boolean_t handle_format_errors);
1723 __in efx_nic_t *enp,
1724 __out_bcount(size) uint8_t *data,
1729 __in efx_nic_t *enp,
1730 __in_bcount(size) uint8_t *data,
1734 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1735 * (see https://tools.ietf.org/html/rfc1533)
1737 * Summarising the format: the buffer is a sequence of options. All options
1738 * begin with a tag octet, which uniquely identifies the option. Fixed-
1739 * length options without data consist of only a tag octet. Only options PAD
1740 * (0) and END (255) are fixed length. All other options are variable-length
1741 * with a length octet following the tag octet. The value of the length
1742 * octet does not include the two octets specifying the tag and length. The
1743 * length octet is followed by "length" octets of data.
1745 * Option data may be a sequence of sub-options in the same format. The data
1746 * content of the encapsulating option is one or more encapsulated sub-options,
1747 * with no terminating END tag is required.
1749 * To be valid, the top-level sequence of options should be terminated by an
1750 * END tag. The buffer should be padded with the PAD byte.
1752 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1753 * checksum octet. The full buffer (including after the END tag) contributes
1754 * to the checksum, hence the need to fill the buffer to the end with PAD.
1757 #define EFX_DHCP_END ((uint8_t)0xff)
1758 #define EFX_DHCP_PAD ((uint8_t)0)
1760 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1761 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1763 extern __checkReturn uint8_t
1765 __in_bcount(size) uint8_t const *data,
1768 extern __checkReturn efx_rc_t
1770 __in_bcount(size) uint8_t const *data,
1772 __out_opt size_t *usedp);
1774 extern __checkReturn efx_rc_t
1776 __in_bcount(buffer_length) uint8_t *bufferp,
1777 __in size_t buffer_length,
1779 __deref_out uint8_t **valuepp,
1780 __out size_t *value_lengthp);
1782 extern __checkReturn efx_rc_t
1784 __in_bcount(buffer_length) uint8_t *bufferp,
1785 __in size_t buffer_length,
1786 __deref_out uint8_t **endpp);
1788 extern __checkReturn efx_rc_t
1789 efx_dhcp_delete_tag(
1790 __inout_bcount(buffer_length) uint8_t *bufferp,
1791 __in size_t buffer_length,
1794 extern __checkReturn efx_rc_t
1796 __inout_bcount(buffer_length) uint8_t *bufferp,
1797 __in size_t buffer_length,
1799 __in_bcount_opt(value_length) uint8_t *valuep,
1800 __in size_t value_length);
1802 extern __checkReturn efx_rc_t
1803 efx_dhcp_update_tag(
1804 __inout_bcount(buffer_length) uint8_t *bufferp,
1805 __in size_t buffer_length,
1807 __in uint8_t *value_locationp,
1808 __in_bcount_opt(value_length) uint8_t *valuep,
1809 __in size_t value_length);
1811 #endif /* EFSYS_OPT_BOOTCFG */
1813 #if EFSYS_OPT_IMAGE_LAYOUT
1815 #include "ef10_signed_image_layout.h"
1818 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1821 * The image header format is extensible. However, older drivers require an
1822 * exact match of image header version and header length when validating and
1823 * writing firmware images.
1825 * To avoid breaking backward compatibility, we use the upper bits of the
1826 * controller version fields to contain an extra version number used for
1827 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1828 * version). See bug39254 and SF-102785-PS for details.
1830 typedef struct efx_image_header_s {
1832 uint32_t eih_version;
1834 uint32_t eih_subtype;
1835 uint32_t eih_code_size;
1838 uint32_t eih_controller_version_min;
1840 uint16_t eih_controller_version_min_short;
1841 uint8_t eih_extra_version_a;
1842 uint8_t eih_extra_version_b;
1846 uint32_t eih_controller_version_max;
1848 uint16_t eih_controller_version_max_short;
1849 uint8_t eih_extra_version_c;
1850 uint8_t eih_extra_version_d;
1853 uint16_t eih_code_version_a;
1854 uint16_t eih_code_version_b;
1855 uint16_t eih_code_version_c;
1856 uint16_t eih_code_version_d;
1857 } efx_image_header_t;
1859 #define EFX_IMAGE_HEADER_SIZE (40)
1860 #define EFX_IMAGE_HEADER_VERSION (4)
1861 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1863 typedef struct efx_image_trailer_s {
1865 } efx_image_trailer_t;
1867 #define EFX_IMAGE_TRAILER_SIZE (4)
1869 typedef enum efx_image_format_e {
1870 EFX_IMAGE_FORMAT_NO_IMAGE,
1871 EFX_IMAGE_FORMAT_INVALID,
1872 EFX_IMAGE_FORMAT_UNSIGNED,
1873 EFX_IMAGE_FORMAT_SIGNED,
1874 } efx_image_format_t;
1876 typedef struct efx_image_info_s {
1877 efx_image_format_t eii_format;
1878 uint8_t * eii_imagep;
1879 size_t eii_image_size;
1880 efx_image_header_t * eii_headerp;
1883 extern __checkReturn efx_rc_t
1884 efx_check_reflash_image(
1886 __in uint32_t buffer_size,
1887 __out efx_image_info_t *infop);
1889 extern __checkReturn efx_rc_t
1890 efx_build_signed_image_write_buffer(
1891 __out_bcount(buffer_size)
1893 __in uint32_t buffer_size,
1894 __in efx_image_info_t *infop,
1895 __out efx_image_header_t **headerpp);
1897 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1901 typedef enum efx_pattern_type_t {
1902 EFX_PATTERN_BYTE_INCREMENT = 0,
1903 EFX_PATTERN_ALL_THE_SAME,
1904 EFX_PATTERN_BIT_ALTERNATE,
1905 EFX_PATTERN_BYTE_ALTERNATE,
1906 EFX_PATTERN_BYTE_CHANGING,
1907 EFX_PATTERN_BIT_SWEEP,
1909 } efx_pattern_type_t;
1912 (*efx_sram_pattern_fn_t)(
1914 __in boolean_t negate,
1915 __out efx_qword_t *eqp);
1917 extern __checkReturn efx_rc_t
1919 __in efx_nic_t *enp,
1920 __in efx_pattern_type_t type);
1922 #endif /* EFSYS_OPT_DIAG */
1924 extern __checkReturn efx_rc_t
1925 efx_sram_buf_tbl_set(
1926 __in efx_nic_t *enp,
1928 __in efsys_mem_t *esmp,
1932 efx_sram_buf_tbl_clear(
1933 __in efx_nic_t *enp,
1937 #define EFX_BUF_TBL_SIZE 0x20000
1939 #define EFX_BUF_SIZE 4096
1943 typedef struct efx_evq_s efx_evq_t;
1945 #if EFSYS_OPT_QSTATS
1947 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1948 typedef enum efx_ev_qstat_e {
1954 EV_RX_PAUSE_FRM_ERR,
1955 EV_RX_BUF_OWNER_ID_ERR,
1956 EV_RX_IPV4_HDR_CHKSUM_ERR,
1957 EV_RX_TCP_UDP_CHKSUM_ERR,
1961 EV_RX_MCAST_HASH_MATCH,
1978 EV_DRIVER_SRM_UPD_DONE,
1979 EV_DRIVER_TX_DESCQ_FLS_DONE,
1980 EV_DRIVER_RX_DESCQ_FLS_DONE,
1981 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1982 EV_DRIVER_RX_DSC_ERROR,
1983 EV_DRIVER_TX_DSC_ERROR,
1989 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1991 #endif /* EFSYS_OPT_QSTATS */
1993 extern __checkReturn efx_rc_t
1995 __in efx_nic_t *enp);
1999 __in efx_nic_t *enp);
2001 #define EFX_EVQ_MAXNEVS 32768
2002 #define EFX_EVQ_MINNEVS 512
2004 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
2005 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
2007 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2008 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2009 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2010 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2012 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2013 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2014 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2016 extern __checkReturn efx_rc_t
2018 __in efx_nic_t *enp,
2019 __in unsigned int index,
2020 __in efsys_mem_t *esmp,
2024 __in uint32_t flags,
2025 __deref_out efx_evq_t **eepp);
2029 __in efx_evq_t *eep,
2030 __in uint16_t data);
2032 typedef __checkReturn boolean_t
2033 (*efx_initialized_ev_t)(
2034 __in_opt void *arg);
2036 #define EFX_PKT_UNICAST 0x0004
2037 #define EFX_PKT_START 0x0008
2039 #define EFX_PKT_VLAN_TAGGED 0x0010
2040 #define EFX_CKSUM_TCPUDP 0x0020
2041 #define EFX_CKSUM_IPV4 0x0040
2042 #define EFX_PKT_CONT 0x0080
2044 #define EFX_CHECK_VLAN 0x0100
2045 #define EFX_PKT_TCP 0x0200
2046 #define EFX_PKT_UDP 0x0400
2047 #define EFX_PKT_IPV4 0x0800
2049 #define EFX_PKT_IPV6 0x1000
2050 #define EFX_PKT_PREFIX_LEN 0x2000
2051 #define EFX_ADDR_MISMATCH 0x4000
2052 #define EFX_DISCARD 0x8000
2055 * The following flags are used only for packed stream
2056 * mode. The values for the flags are reused to fit into 16 bit,
2057 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2058 * packed stream mode
2060 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2061 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2063 #define EFX_EV_RX_NLABELS 32
2064 #define EFX_EV_TX_NLABELS 32
2066 typedef __checkReturn boolean_t
2069 __in uint32_t label,
2072 __in uint16_t flags);
2074 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2077 * Packed stream mode is documented in SF-112241-TC.
2078 * The general idea is that, instead of putting each incoming
2079 * packet into a separate buffer which is specified in a RX
2080 * descriptor, a large buffer is provided to the hardware and
2081 * packets are put there in a continuous stream.
2082 * The main advantage of such an approach is that RX queue refilling
2083 * happens much less frequently.
2085 * Equal stride packed stream mode is documented in SF-119419-TC.
2086 * The general idea is to utilize advantages of the packed stream,
2087 * but avoid indirection in packets representation.
2088 * The main advantage of such an approach is that RX queue refilling
2089 * happens much less frequently and packets buffers are independent
2090 * from upper layers point of view.
2093 typedef __checkReturn boolean_t
2096 __in uint32_t label,
2098 __in uint32_t pkt_count,
2099 __in uint16_t flags);
2103 typedef __checkReturn boolean_t
2106 __in uint32_t label,
2109 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2110 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2111 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2112 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2113 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2114 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2115 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2116 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2117 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2119 typedef __checkReturn boolean_t
2120 (*efx_exception_ev_t)(
2122 __in uint32_t label,
2123 __in uint32_t data);
2125 typedef __checkReturn boolean_t
2126 (*efx_rxq_flush_done_ev_t)(
2128 __in uint32_t rxq_index);
2130 typedef __checkReturn boolean_t
2131 (*efx_rxq_flush_failed_ev_t)(
2133 __in uint32_t rxq_index);
2135 typedef __checkReturn boolean_t
2136 (*efx_txq_flush_done_ev_t)(
2138 __in uint32_t txq_index);
2140 typedef __checkReturn boolean_t
2141 (*efx_software_ev_t)(
2143 __in uint16_t magic);
2145 typedef __checkReturn boolean_t
2148 __in uint32_t code);
2150 #define EFX_SRAM_CLEAR 0
2151 #define EFX_SRAM_UPDATE 1
2152 #define EFX_SRAM_ILLEGAL_CLEAR 2
2154 typedef __checkReturn boolean_t
2155 (*efx_wake_up_ev_t)(
2157 __in uint32_t label);
2159 typedef __checkReturn boolean_t
2162 __in uint32_t label);
2164 typedef __checkReturn boolean_t
2165 (*efx_link_change_ev_t)(
2167 __in efx_link_mode_t link_mode);
2169 #if EFSYS_OPT_MON_STATS
2171 typedef __checkReturn boolean_t
2172 (*efx_monitor_ev_t)(
2174 __in efx_mon_stat_t id,
2175 __in efx_mon_stat_value_t value);
2177 #endif /* EFSYS_OPT_MON_STATS */
2179 #if EFSYS_OPT_MAC_STATS
2181 typedef __checkReturn boolean_t
2182 (*efx_mac_stats_ev_t)(
2184 __in uint32_t generation);
2186 #endif /* EFSYS_OPT_MAC_STATS */
2188 typedef struct efx_ev_callbacks_s {
2189 efx_initialized_ev_t eec_initialized;
2191 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2192 efx_rx_ps_ev_t eec_rx_ps;
2195 efx_exception_ev_t eec_exception;
2196 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2197 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2198 efx_txq_flush_done_ev_t eec_txq_flush_done;
2199 efx_software_ev_t eec_software;
2200 efx_sram_ev_t eec_sram;
2201 efx_wake_up_ev_t eec_wake_up;
2202 efx_timer_ev_t eec_timer;
2203 efx_link_change_ev_t eec_link_change;
2204 #if EFSYS_OPT_MON_STATS
2205 efx_monitor_ev_t eec_monitor;
2206 #endif /* EFSYS_OPT_MON_STATS */
2207 #if EFSYS_OPT_MAC_STATS
2208 efx_mac_stats_ev_t eec_mac_stats;
2209 #endif /* EFSYS_OPT_MAC_STATS */
2210 } efx_ev_callbacks_t;
2212 extern __checkReturn boolean_t
2214 __in efx_evq_t *eep,
2215 __in unsigned int count);
2217 #if EFSYS_OPT_EV_PREFETCH
2221 __in efx_evq_t *eep,
2222 __in unsigned int count);
2224 #endif /* EFSYS_OPT_EV_PREFETCH */
2228 __in efx_evq_t *eep,
2229 __inout unsigned int *countp,
2230 __in const efx_ev_callbacks_t *eecp,
2231 __in_opt void *arg);
2233 extern __checkReturn efx_rc_t
2234 efx_ev_usecs_to_ticks(
2235 __in efx_nic_t *enp,
2236 __in unsigned int usecs,
2237 __out unsigned int *ticksp);
2239 extern __checkReturn efx_rc_t
2241 __in efx_evq_t *eep,
2242 __in unsigned int us);
2244 extern __checkReturn efx_rc_t
2246 __in efx_evq_t *eep,
2247 __in unsigned int count);
2249 #if EFSYS_OPT_QSTATS
2255 __in efx_nic_t *enp,
2256 __in unsigned int id);
2258 #endif /* EFSYS_OPT_NAMES */
2261 efx_ev_qstats_update(
2262 __in efx_evq_t *eep,
2263 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2265 #endif /* EFSYS_OPT_QSTATS */
2269 __in efx_evq_t *eep);
2273 extern __checkReturn efx_rc_t
2275 __inout efx_nic_t *enp);
2279 __in efx_nic_t *enp);
2281 #if EFSYS_OPT_RX_SCATTER
2282 __checkReturn efx_rc_t
2283 efx_rx_scatter_enable(
2284 __in efx_nic_t *enp,
2285 __in unsigned int buf_size);
2286 #endif /* EFSYS_OPT_RX_SCATTER */
2288 /* Handle to represent use of the default RSS context. */
2289 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2291 #if EFSYS_OPT_RX_SCALE
2293 typedef enum efx_rx_hash_alg_e {
2294 EFX_RX_HASHALG_LFSR = 0,
2295 EFX_RX_HASHALG_TOEPLITZ,
2296 EFX_RX_HASHALG_PACKED_STREAM,
2298 } efx_rx_hash_alg_t;
2301 * Legacy hash type flags.
2303 * They represent standard tuples for distinct traffic classes.
2305 #define EFX_RX_HASH_IPV4 (1U << 0)
2306 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2307 #define EFX_RX_HASH_IPV6 (1U << 2)
2308 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2310 #define EFX_RX_HASH_LEGACY_MASK \
2311 (EFX_RX_HASH_IPV4 | \
2312 EFX_RX_HASH_TCPIPV4 | \
2313 EFX_RX_HASH_IPV6 | \
2314 EFX_RX_HASH_TCPIPV6)
2317 * The type of the argument used by efx_rx_scale_mode_set() to
2318 * provide a means for the client drivers to configure hashing.
2320 * A properly constructed value can either be:
2321 * - a combination of legacy flags
2322 * - a combination of EFX_RX_HASH() flags
2324 typedef uint32_t efx_rx_hash_type_t;
2326 typedef enum efx_rx_hash_support_e {
2327 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2328 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2329 } efx_rx_hash_support_t;
2331 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2332 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2333 #define EFX_MAXRSS 64 /* RX indirection entry range */
2334 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2336 typedef enum efx_rx_scale_context_type_e {
2337 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2338 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2339 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2340 } efx_rx_scale_context_type_t;
2343 * Traffic classes eligible for hash computation.
2345 * Select packet headers used in computing the receive hash.
2346 * This uses the same encoding as the RSS_MODES field of
2347 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2349 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2350 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2351 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2352 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2353 #define EFX_RX_CLASS_IPV4_LBN 16
2354 #define EFX_RX_CLASS_IPV4_WIDTH 4
2355 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2356 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2357 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2358 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2359 #define EFX_RX_CLASS_IPV6_LBN 28
2360 #define EFX_RX_CLASS_IPV6_WIDTH 4
2362 #define EFX_RX_NCLASSES 6
2365 * Ancillary flags used to construct generic hash tuples.
2366 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2368 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2369 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2370 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2371 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2374 * Generic hash tuples.
2376 * They express combinations of packet fields
2377 * which can contribute to the hash value for
2378 * a particular traffic class.
2380 #define EFX_RX_CLASS_HASH_DISABLE 0
2382 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2383 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2385 #define EFX_RX_CLASS_HASH_2TUPLE \
2386 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2387 EFX_RX_CLASS_HASH_DST_ADDR)
2389 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2390 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2391 EFX_RX_CLASS_HASH_SRC_PORT)
2393 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2394 (EFX_RX_CLASS_HASH_DST_ADDR | \
2395 EFX_RX_CLASS_HASH_DST_PORT)
2397 #define EFX_RX_CLASS_HASH_4TUPLE \
2398 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2399 EFX_RX_CLASS_HASH_DST_ADDR | \
2400 EFX_RX_CLASS_HASH_SRC_PORT | \
2401 EFX_RX_CLASS_HASH_DST_PORT)
2403 #define EFX_RX_CLASS_HASH_NTUPLES 7
2406 * Hash flag constructor.
2408 * Resulting flags encode hash tuples for specific traffic classes.
2409 * The client drivers are encouraged to use these flags to form
2410 * a hash type value.
2412 #define EFX_RX_HASH(_class, _tuple) \
2413 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2414 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2417 * The maximum number of EFX_RX_HASH() flags.
2419 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2421 extern __checkReturn efx_rc_t
2422 efx_rx_scale_hash_flags_get(
2423 __in efx_nic_t *enp,
2424 __in efx_rx_hash_alg_t hash_alg,
2425 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2426 __in unsigned int max_nflags,
2427 __out unsigned int *nflagsp);
2429 extern __checkReturn efx_rc_t
2430 efx_rx_hash_default_support_get(
2431 __in efx_nic_t *enp,
2432 __out efx_rx_hash_support_t *supportp);
2434 extern __checkReturn efx_rc_t
2435 efx_rx_scale_default_support_get(
2436 __in efx_nic_t *enp,
2437 __out efx_rx_scale_context_type_t *typep);
2439 extern __checkReturn efx_rc_t
2440 efx_rx_scale_context_alloc(
2441 __in efx_nic_t *enp,
2442 __in efx_rx_scale_context_type_t type,
2443 __in uint32_t num_queues,
2444 __out uint32_t *rss_contextp);
2446 extern __checkReturn efx_rc_t
2447 efx_rx_scale_context_free(
2448 __in efx_nic_t *enp,
2449 __in uint32_t rss_context);
2451 extern __checkReturn efx_rc_t
2452 efx_rx_scale_mode_set(
2453 __in efx_nic_t *enp,
2454 __in uint32_t rss_context,
2455 __in efx_rx_hash_alg_t alg,
2456 __in efx_rx_hash_type_t type,
2457 __in boolean_t insert);
2459 extern __checkReturn efx_rc_t
2460 efx_rx_scale_tbl_set(
2461 __in efx_nic_t *enp,
2462 __in uint32_t rss_context,
2463 __in_ecount(n) unsigned int *table,
2466 extern __checkReturn efx_rc_t
2467 efx_rx_scale_key_set(
2468 __in efx_nic_t *enp,
2469 __in uint32_t rss_context,
2470 __in_ecount(n) uint8_t *key,
2473 extern __checkReturn uint32_t
2474 efx_pseudo_hdr_hash_get(
2475 __in efx_rxq_t *erp,
2476 __in efx_rx_hash_alg_t func,
2477 __in uint8_t *buffer);
2479 #endif /* EFSYS_OPT_RX_SCALE */
2481 extern __checkReturn efx_rc_t
2482 efx_pseudo_hdr_pkt_length_get(
2483 __in efx_rxq_t *erp,
2484 __in uint8_t *buffer,
2485 __out uint16_t *pkt_lengthp);
2487 #define EFX_RXQ_MAXNDESCS 4096
2488 #define EFX_RXQ_MINNDESCS 512
2490 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2491 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2492 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2493 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2495 typedef enum efx_rxq_type_e {
2496 EFX_RXQ_TYPE_DEFAULT,
2497 EFX_RXQ_TYPE_PACKED_STREAM,
2498 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2503 * Dummy flag to be used instead of 0 to make it clear that the argument
2504 * is receive queue flags.
2506 #define EFX_RXQ_FLAG_NONE 0x0
2507 #define EFX_RXQ_FLAG_SCATTER 0x1
2509 * If tunnels are supported and Rx event can provide information about
2510 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2511 * full-feature firmware variant running), outer classes are requested by
2512 * default. However, if the driver supports tunnels, the flag allows to
2513 * request inner classes which are required to be able to interpret inner
2514 * Rx checksum offload results.
2516 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2518 extern __checkReturn efx_rc_t
2520 __in efx_nic_t *enp,
2521 __in unsigned int index,
2522 __in unsigned int label,
2523 __in efx_rxq_type_t type,
2524 __in efsys_mem_t *esmp,
2527 __in unsigned int flags,
2528 __in efx_evq_t *eep,
2529 __deref_out efx_rxq_t **erpp);
2531 #if EFSYS_OPT_RX_PACKED_STREAM
2533 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2534 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2535 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2536 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2537 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2539 extern __checkReturn efx_rc_t
2540 efx_rx_qcreate_packed_stream(
2541 __in efx_nic_t *enp,
2542 __in unsigned int index,
2543 __in unsigned int label,
2544 __in uint32_t ps_buf_size,
2545 __in efsys_mem_t *esmp,
2547 __in efx_evq_t *eep,
2548 __deref_out efx_rxq_t **erpp);
2552 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2554 /* Maximum head-of-line block timeout in nanoseconds */
2555 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2557 extern __checkReturn efx_rc_t
2558 efx_rx_qcreate_es_super_buffer(
2559 __in efx_nic_t *enp,
2560 __in unsigned int index,
2561 __in unsigned int label,
2562 __in uint32_t n_bufs_per_desc,
2563 __in uint32_t max_dma_len,
2564 __in uint32_t buf_stride,
2565 __in uint32_t hol_block_timeout,
2566 __in efsys_mem_t *esmp,
2568 __in unsigned int flags,
2569 __in efx_evq_t *eep,
2570 __deref_out efx_rxq_t **erpp);
2574 typedef struct efx_buffer_s {
2575 efsys_dma_addr_t eb_addr;
2580 typedef struct efx_desc_s {
2586 __in efx_rxq_t *erp,
2587 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2589 __in unsigned int ndescs,
2590 __in unsigned int completed,
2591 __in unsigned int added);
2595 __in efx_rxq_t *erp,
2596 __in unsigned int added,
2597 __inout unsigned int *pushedp);
2599 #if EFSYS_OPT_RX_PACKED_STREAM
2602 efx_rx_qpush_ps_credits(
2603 __in efx_rxq_t *erp);
2605 extern __checkReturn uint8_t *
2606 efx_rx_qps_packet_info(
2607 __in efx_rxq_t *erp,
2608 __in uint8_t *buffer,
2609 __in uint32_t buffer_length,
2610 __in uint32_t current_offset,
2611 __out uint16_t *lengthp,
2612 __out uint32_t *next_offsetp,
2613 __out uint32_t *timestamp);
2616 extern __checkReturn efx_rc_t
2618 __in efx_rxq_t *erp);
2622 __in efx_rxq_t *erp);
2626 __in efx_rxq_t *erp);
2630 typedef struct efx_txq_s efx_txq_t;
2632 #if EFSYS_OPT_QSTATS
2634 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2635 typedef enum efx_tx_qstat_e {
2641 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2643 #endif /* EFSYS_OPT_QSTATS */
2645 extern __checkReturn efx_rc_t
2647 __in efx_nic_t *enp);
2651 __in efx_nic_t *enp);
2653 #define EFX_TXQ_MINNDESCS 512
2655 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2656 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2657 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2659 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2661 #define EFX_TXQ_CKSUM_IPV4 0x0001
2662 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2663 #define EFX_TXQ_FATSOV2 0x0004
2664 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2665 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2667 extern __checkReturn efx_rc_t
2669 __in efx_nic_t *enp,
2670 __in unsigned int index,
2671 __in unsigned int label,
2672 __in efsys_mem_t *esmp,
2675 __in uint16_t flags,
2676 __in efx_evq_t *eep,
2677 __deref_out efx_txq_t **etpp,
2678 __out unsigned int *addedp);
2680 extern __checkReturn efx_rc_t
2682 __in efx_txq_t *etp,
2683 __in_ecount(ndescs) efx_buffer_t *eb,
2684 __in unsigned int ndescs,
2685 __in unsigned int completed,
2686 __inout unsigned int *addedp);
2688 extern __checkReturn efx_rc_t
2690 __in efx_txq_t *etp,
2691 __in unsigned int ns);
2695 __in efx_txq_t *etp,
2696 __in unsigned int added,
2697 __in unsigned int pushed);
2699 extern __checkReturn efx_rc_t
2701 __in efx_txq_t *etp);
2705 __in efx_txq_t *etp);
2707 extern __checkReturn efx_rc_t
2709 __in efx_txq_t *etp);
2712 efx_tx_qpio_disable(
2713 __in efx_txq_t *etp);
2715 extern __checkReturn efx_rc_t
2717 __in efx_txq_t *etp,
2718 __in_ecount(buf_length) uint8_t *buffer,
2719 __in size_t buf_length,
2720 __in size_t pio_buf_offset);
2722 extern __checkReturn efx_rc_t
2724 __in efx_txq_t *etp,
2725 __in size_t pkt_length,
2726 __in unsigned int completed,
2727 __inout unsigned int *addedp);
2729 extern __checkReturn efx_rc_t
2731 __in efx_txq_t *etp,
2732 __in_ecount(n) efx_desc_t *ed,
2733 __in unsigned int n,
2734 __in unsigned int completed,
2735 __inout unsigned int *addedp);
2738 efx_tx_qdesc_dma_create(
2739 __in efx_txq_t *etp,
2740 __in efsys_dma_addr_t addr,
2743 __out efx_desc_t *edp);
2746 efx_tx_qdesc_tso_create(
2747 __in efx_txq_t *etp,
2748 __in uint16_t ipv4_id,
2749 __in uint32_t tcp_seq,
2750 __in uint8_t tcp_flags,
2751 __out efx_desc_t *edp);
2753 /* Number of FATSOv2 option descriptors */
2754 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2756 /* Maximum number of DMA segments per TSO packet (not superframe) */
2757 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2760 efx_tx_qdesc_tso2_create(
2761 __in efx_txq_t *etp,
2762 __in uint16_t ipv4_id,
2763 __in uint16_t outer_ipv4_id,
2764 __in uint32_t tcp_seq,
2765 __in uint16_t tcp_mss,
2766 __out_ecount(count) efx_desc_t *edp,
2770 efx_tx_qdesc_vlantci_create(
2771 __in efx_txq_t *etp,
2773 __out efx_desc_t *edp);
2776 efx_tx_qdesc_checksum_create(
2777 __in efx_txq_t *etp,
2778 __in uint16_t flags,
2779 __out efx_desc_t *edp);
2781 #if EFSYS_OPT_QSTATS
2787 __in efx_nic_t *etp,
2788 __in unsigned int id);
2790 #endif /* EFSYS_OPT_NAMES */
2793 efx_tx_qstats_update(
2794 __in efx_txq_t *etp,
2795 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2797 #endif /* EFSYS_OPT_QSTATS */
2801 __in efx_txq_t *etp);
2805 #if EFSYS_OPT_FILTER
2807 #define EFX_ETHER_TYPE_IPV4 0x0800
2808 #define EFX_ETHER_TYPE_IPV6 0x86DD
2810 #define EFX_IPPROTO_TCP 6
2811 #define EFX_IPPROTO_UDP 17
2812 #define EFX_IPPROTO_GRE 47
2814 /* Use RSS to spread across multiple queues */
2815 #define EFX_FILTER_FLAG_RX_RSS 0x01
2816 /* Enable RX scatter */
2817 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2819 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2820 * May only be set by the filter implementation for each type.
2821 * A removal request will restore the automatic filter in its place.
2823 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2824 /* Filter is for RX */
2825 #define EFX_FILTER_FLAG_RX 0x08
2826 /* Filter is for TX */
2827 #define EFX_FILTER_FLAG_TX 0x10
2828 /* Set match flag on the received packet */
2829 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2830 /* Set match mark on the received packet */
2831 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2833 typedef uint8_t efx_filter_flags_t;
2836 * Flags which specify the fields to match on. The values are the same as in the
2837 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2840 /* Match by remote IP host address */
2841 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2842 /* Match by local IP host address */
2843 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2844 /* Match by remote MAC address */
2845 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2846 /* Match by remote TCP/UDP port */
2847 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2848 /* Match by remote TCP/UDP port */
2849 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2850 /* Match by local TCP/UDP port */
2851 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2852 /* Match by Ether-type */
2853 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2854 /* Match by inner VLAN ID */
2855 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2856 /* Match by outer VLAN ID */
2857 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2858 /* Match by IP transport protocol */
2859 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2860 /* Match by VNI or VSID */
2861 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2862 /* For encapsulated packets, match by inner frame local MAC address */
2863 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2864 /* For encapsulated packets, match all multicast inner frames */
2865 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2866 /* For encapsulated packets, match all unicast inner frames */
2867 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2869 * Match by encap type, this flag does not correspond to
2870 * the MCDI match flags and any unoccupied value may be used
2872 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2873 /* Match otherwise-unmatched multicast and broadcast packets */
2874 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2875 /* Match otherwise-unmatched unicast packets */
2876 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2878 typedef uint32_t efx_filter_match_flags_t;
2880 typedef enum efx_filter_priority_s {
2881 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2882 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2883 * address list or hardware
2884 * requirements. This may only be used
2885 * by the filter implementation for
2887 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2888 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2889 * client (e.g. SR-IOV, HyperV VMQ etc.)
2891 } efx_filter_priority_t;
2894 * FIXME: All these fields are assumed to be in little-endian byte order.
2895 * It may be better for some to be big-endian. See bug42804.
2898 typedef struct efx_filter_spec_s {
2899 efx_filter_match_flags_t efs_match_flags;
2900 uint8_t efs_priority;
2901 efx_filter_flags_t efs_flags;
2902 uint16_t efs_dmaq_id;
2903 uint32_t efs_rss_context;
2905 /* Fields below here are hashed for software filter lookup */
2906 uint16_t efs_outer_vid;
2907 uint16_t efs_inner_vid;
2908 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2909 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2910 uint16_t efs_ether_type;
2911 uint8_t efs_ip_proto;
2912 efx_tunnel_protocol_t efs_encap_type;
2913 uint16_t efs_loc_port;
2914 uint16_t efs_rem_port;
2915 efx_oword_t efs_rem_host;
2916 efx_oword_t efs_loc_host;
2917 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2918 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2919 } efx_filter_spec_t;
2921 /* Default values for use in filter specifications */
2922 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2923 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2925 extern __checkReturn efx_rc_t
2927 __in efx_nic_t *enp);
2931 __in efx_nic_t *enp);
2933 extern __checkReturn efx_rc_t
2935 __in efx_nic_t *enp,
2936 __inout efx_filter_spec_t *spec);
2938 extern __checkReturn efx_rc_t
2940 __in efx_nic_t *enp,
2941 __inout efx_filter_spec_t *spec);
2943 extern __checkReturn efx_rc_t
2945 __in efx_nic_t *enp);
2947 extern __checkReturn efx_rc_t
2948 efx_filter_supported_filters(
2949 __in efx_nic_t *enp,
2950 __out_ecount(buffer_length) uint32_t *buffer,
2951 __in size_t buffer_length,
2952 __out size_t *list_lengthp);
2955 efx_filter_spec_init_rx(
2956 __out efx_filter_spec_t *spec,
2957 __in efx_filter_priority_t priority,
2958 __in efx_filter_flags_t flags,
2959 __in efx_rxq_t *erp);
2962 efx_filter_spec_init_tx(
2963 __out efx_filter_spec_t *spec,
2964 __in efx_txq_t *etp);
2966 extern __checkReturn efx_rc_t
2967 efx_filter_spec_set_ipv4_local(
2968 __inout efx_filter_spec_t *spec,
2971 __in uint16_t port);
2973 extern __checkReturn efx_rc_t
2974 efx_filter_spec_set_ipv4_full(
2975 __inout efx_filter_spec_t *spec,
2977 __in uint32_t lhost,
2978 __in uint16_t lport,
2979 __in uint32_t rhost,
2980 __in uint16_t rport);
2982 extern __checkReturn efx_rc_t
2983 efx_filter_spec_set_eth_local(
2984 __inout efx_filter_spec_t *spec,
2986 __in const uint8_t *addr);
2989 efx_filter_spec_set_ether_type(
2990 __inout efx_filter_spec_t *spec,
2991 __in uint16_t ether_type);
2993 extern __checkReturn efx_rc_t
2994 efx_filter_spec_set_uc_def(
2995 __inout efx_filter_spec_t *spec);
2997 extern __checkReturn efx_rc_t
2998 efx_filter_spec_set_mc_def(
2999 __inout efx_filter_spec_t *spec);
3001 typedef enum efx_filter_inner_frame_match_e {
3002 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3003 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3004 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3005 } efx_filter_inner_frame_match_t;
3007 extern __checkReturn efx_rc_t
3008 efx_filter_spec_set_encap_type(
3009 __inout efx_filter_spec_t *spec,
3010 __in efx_tunnel_protocol_t encap_type,
3011 __in efx_filter_inner_frame_match_t inner_frame_match);
3013 extern __checkReturn efx_rc_t
3014 efx_filter_spec_set_vxlan(
3015 __inout efx_filter_spec_t *spec,
3016 __in const uint8_t *vni,
3017 __in const uint8_t *inner_addr,
3018 __in const uint8_t *outer_addr);
3020 extern __checkReturn efx_rc_t
3021 efx_filter_spec_set_geneve(
3022 __inout efx_filter_spec_t *spec,
3023 __in const uint8_t *vni,
3024 __in const uint8_t *inner_addr,
3025 __in const uint8_t *outer_addr);
3027 extern __checkReturn efx_rc_t
3028 efx_filter_spec_set_nvgre(
3029 __inout efx_filter_spec_t *spec,
3030 __in const uint8_t *vsid,
3031 __in const uint8_t *inner_addr,
3032 __in const uint8_t *outer_addr);
3034 #if EFSYS_OPT_RX_SCALE
3035 extern __checkReturn efx_rc_t
3036 efx_filter_spec_set_rss_context(
3037 __inout efx_filter_spec_t *spec,
3038 __in uint32_t rss_context);
3040 #endif /* EFSYS_OPT_FILTER */
3044 extern __checkReturn uint32_t
3046 __in_ecount(count) uint32_t const *input,
3048 __in uint32_t init);
3050 extern __checkReturn uint32_t
3052 __in_ecount(length) uint8_t const *input,
3054 __in uint32_t init);
3056 #if EFSYS_OPT_LICENSING
3060 typedef struct efx_key_stats_s {
3062 uint32_t eks_invalid;
3063 uint32_t eks_blacklisted;
3064 uint32_t eks_unverifiable;
3065 uint32_t eks_wrong_node;
3066 uint32_t eks_licensed_apps_lo;
3067 uint32_t eks_licensed_apps_hi;
3068 uint32_t eks_licensed_features_lo;
3069 uint32_t eks_licensed_features_hi;
3072 extern __checkReturn efx_rc_t
3074 __in efx_nic_t *enp);
3078 __in efx_nic_t *enp);
3080 extern __checkReturn boolean_t
3081 efx_lic_check_support(
3082 __in efx_nic_t *enp);
3084 extern __checkReturn efx_rc_t
3085 efx_lic_update_licenses(
3086 __in efx_nic_t *enp);
3088 extern __checkReturn efx_rc_t
3089 efx_lic_get_key_stats(
3090 __in efx_nic_t *enp,
3091 __out efx_key_stats_t *ksp);
3093 extern __checkReturn efx_rc_t
3095 __in efx_nic_t *enp,
3096 __in uint64_t app_id,
3097 __out boolean_t *licensedp);
3099 extern __checkReturn efx_rc_t
3101 __in efx_nic_t *enp,
3102 __in size_t buffer_size,
3103 __out uint32_t *typep,
3104 __out size_t *lengthp,
3105 __out_opt uint8_t *bufferp);
3107 extern __checkReturn efx_rc_t
3109 __in efx_nic_t *enp,
3110 __in_bcount(buffer_size)
3112 __in size_t buffer_size,
3113 __out uint32_t *startp);
3115 extern __checkReturn efx_rc_t
3117 __in efx_nic_t *enp,
3118 __in_bcount(buffer_size)
3120 __in size_t buffer_size,
3121 __in uint32_t offset,
3122 __out uint32_t *endp);
3124 extern __checkReturn __success(return != B_FALSE) boolean_t
3126 __in efx_nic_t *enp,
3127 __in_bcount(buffer_size)
3129 __in size_t buffer_size,
3130 __in uint32_t offset,
3131 __out uint32_t *startp,
3132 __out uint32_t *lengthp);
3134 extern __checkReturn __success(return != B_FALSE) boolean_t
3135 efx_lic_validate_key(
3136 __in efx_nic_t *enp,
3137 __in_bcount(length) caddr_t keyp,
3138 __in uint32_t length);
3140 extern __checkReturn efx_rc_t
3142 __in efx_nic_t *enp,
3143 __in_bcount(buffer_size)
3145 __in size_t buffer_size,
3146 __in uint32_t offset,
3147 __in uint32_t length,
3148 __out_bcount_part(key_max_size, *lengthp)
3150 __in size_t key_max_size,
3151 __out uint32_t *lengthp);
3153 extern __checkReturn efx_rc_t
3155 __in efx_nic_t *enp,
3156 __in_bcount(buffer_size)
3158 __in size_t buffer_size,
3159 __in uint32_t offset,
3160 __in_bcount(length) caddr_t keyp,
3161 __in uint32_t length,
3162 __out uint32_t *lengthp);
3164 __checkReturn efx_rc_t
3166 __in efx_nic_t *enp,
3167 __in_bcount(buffer_size)
3169 __in size_t buffer_size,
3170 __in uint32_t offset,
3171 __in uint32_t length,
3173 __out uint32_t *deltap);
3175 extern __checkReturn efx_rc_t
3176 efx_lic_create_partition(
3177 __in efx_nic_t *enp,
3178 __in_bcount(buffer_size)
3180 __in size_t buffer_size);
3182 extern __checkReturn efx_rc_t
3183 efx_lic_finish_partition(
3184 __in efx_nic_t *enp,
3185 __in_bcount(buffer_size)
3187 __in size_t buffer_size);
3189 #endif /* EFSYS_OPT_LICENSING */
3193 #if EFSYS_OPT_TUNNEL
3195 extern __checkReturn efx_rc_t
3197 __in efx_nic_t *enp);
3201 __in efx_nic_t *enp);
3204 * For overlay network encapsulation using UDP, the firmware needs to know
3205 * the configured UDP port for the overlay so it can decode encapsulated
3207 * The UDP port/protocol list is global.
3210 extern __checkReturn efx_rc_t
3211 efx_tunnel_config_udp_add(
3212 __in efx_nic_t *enp,
3213 __in uint16_t port /* host/cpu-endian */,
3214 __in efx_tunnel_protocol_t protocol);
3216 extern __checkReturn efx_rc_t
3217 efx_tunnel_config_udp_remove(
3218 __in efx_nic_t *enp,
3219 __in uint16_t port /* host/cpu-endian */,
3220 __in efx_tunnel_protocol_t protocol);
3223 efx_tunnel_config_clear(
3224 __in efx_nic_t *enp);
3227 * Apply tunnel UDP ports configuration to hardware.
3229 * EAGAIN is returned if hardware will be reset (datapath and management CPU
3232 extern __checkReturn efx_rc_t
3233 efx_tunnel_reconfigure(
3234 __in efx_nic_t *enp);
3236 #endif /* EFSYS_OPT_TUNNEL */
3238 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3241 * Firmware subvariant choice options.
3243 * It may be switched to no Tx checksum if attached drivers are either
3244 * preboot or firmware subvariant aware and no VIS are allocated.
3245 * If may be always switched to default explicitly using set request or
3246 * implicitly if unaware driver is attaching. If switching is done when
3247 * a driver is attached, it gets MC_REBOOT event and should recreate its
3250 * See SF-119419-TC DPDK Firmware Driver Interface and
3251 * SF-109306-TC EF10 for Driver Writers for details.
3253 typedef enum efx_nic_fw_subvariant_e {
3254 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3255 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3256 EFX_NIC_FW_SUBVARIANT_NTYPES
3257 } efx_nic_fw_subvariant_t;
3259 extern __checkReturn efx_rc_t
3260 efx_nic_get_fw_subvariant(
3261 __in efx_nic_t *enp,
3262 __out efx_nic_fw_subvariant_t *subvariantp);
3264 extern __checkReturn efx_rc_t
3265 efx_nic_set_fw_subvariant(
3266 __in efx_nic_t *enp,
3267 __in efx_nic_fw_subvariant_t subvariant);
3269 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3271 typedef enum efx_phy_fec_type_e {
3272 EFX_PHY_FEC_NONE = 0,
3275 } efx_phy_fec_type_t;
3277 extern __checkReturn efx_rc_t
3278 efx_phy_fec_type_get(
3279 __in efx_nic_t *enp,
3280 __out efx_phy_fec_type_t *typep);
3282 typedef struct efx_phy_link_state_s {
3283 uint32_t epls_adv_cap_mask;
3284 uint32_t epls_lp_cap_mask;
3285 uint32_t epls_ld_cap_mask;
3286 unsigned int epls_fcntl;
3287 efx_phy_fec_type_t epls_fec;
3288 efx_link_mode_t epls_link_mode;
3289 } efx_phy_link_state_t;
3291 extern __checkReturn efx_rc_t
3292 efx_phy_link_state_get(
3293 __in efx_nic_t *enp,
3294 __out efx_phy_link_state_t *eplsp);
3300 #endif /* _SYS_EFX_H */