2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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30 * policies, either expressed or implied, of the FreeBSD Project.
38 #include "efx_annote.h"
40 #include "efx_check.h"
41 #include "efx_phy_ids.h"
47 #define EFX_STATIC_ASSERT(_cond) \
48 ((void)sizeof (char[(_cond) ? 1 : -1]))
50 #define EFX_ARRAY_SIZE(_array) \
51 (sizeof (_array) / sizeof ((_array)[0]))
53 #define EFX_FIELD_OFFSET(_type, _field) \
54 ((size_t)&(((_type *)0)->_field))
56 /* The macro expands divider twice */
57 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
61 typedef __success(return == 0) int efx_rc_t;
66 typedef enum efx_family_e {
68 EFX_FAMILY_FALCON, /* Obsolete and not supported */
70 EFX_FAMILY_HUNTINGTON,
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
84 #define EFX_PCI_VENID_SFC 0x1924
86 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
88 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
89 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
90 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
92 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
93 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
94 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
96 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
97 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
99 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
100 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
101 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
103 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
104 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
105 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
108 #define EFX_MEM_BAR_SIENA 2
110 #define EFX_MEM_BAR_HUNTINGTON_PF 2
111 #define EFX_MEM_BAR_HUNTINGTON_VF 0
113 #define EFX_MEM_BAR_MEDFORD_PF 2
114 #define EFX_MEM_BAR_MEDFORD_VF 0
116 #define EFX_MEM_BAR_MEDFORD2 0
124 EFX_ERR_BUFID_DC_OOB,
137 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
138 extern __checkReturn uint32_t
140 __in uint32_t crc_init,
141 __in_ecount(length) uint8_t const *input,
145 /* Type prototypes */
147 typedef struct efx_rxq_s efx_rxq_t;
151 typedef struct efx_nic_s efx_nic_t;
153 extern __checkReturn efx_rc_t
155 __in efx_family_t family,
156 __in efsys_identifier_t *esip,
157 __in efsys_bar_t *esbp,
158 __in efsys_lock_t *eslp,
159 __deref_out efx_nic_t **enpp);
161 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
162 typedef enum efx_fw_variant_e {
163 EFX_FW_VARIANT_FULL_FEATURED,
164 EFX_FW_VARIANT_LOW_LATENCY,
165 EFX_FW_VARIANT_PACKED_STREAM,
166 EFX_FW_VARIANT_HIGH_TX_RATE,
167 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
168 EFX_FW_VARIANT_RULES_ENGINE,
170 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
173 extern __checkReturn efx_rc_t
176 __in efx_fw_variant_t efv);
178 extern __checkReturn efx_rc_t
180 __in efx_nic_t *enp);
182 extern __checkReturn efx_rc_t
184 __in efx_nic_t *enp);
188 extern __checkReturn efx_rc_t
189 efx_nic_register_test(
190 __in efx_nic_t *enp);
192 #endif /* EFSYS_OPT_DIAG */
196 __in efx_nic_t *enp);
200 __in efx_nic_t *enp);
204 __in efx_nic_t *enp);
206 #define EFX_PCIE_LINK_SPEED_GEN1 1
207 #define EFX_PCIE_LINK_SPEED_GEN2 2
208 #define EFX_PCIE_LINK_SPEED_GEN3 3
210 typedef enum efx_pcie_link_performance_e {
211 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
212 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
213 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
214 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
215 } efx_pcie_link_performance_t;
217 extern __checkReturn efx_rc_t
218 efx_nic_calculate_pcie_link_bandwidth(
219 __in uint32_t pcie_link_width,
220 __in uint32_t pcie_link_gen,
221 __out uint32_t *bandwidth_mbpsp);
223 extern __checkReturn efx_rc_t
224 efx_nic_check_pcie_link_speed(
226 __in uint32_t pcie_link_width,
227 __in uint32_t pcie_link_gen,
228 __out efx_pcie_link_performance_t *resultp);
232 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
233 /* Huntington and Medford require MCDIv2 commands */
234 #define WITH_MCDI_V2 1
237 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
239 typedef enum efx_mcdi_exception_e {
240 EFX_MCDI_EXCEPTION_MC_REBOOT,
241 EFX_MCDI_EXCEPTION_MC_BADASSERT,
242 } efx_mcdi_exception_t;
244 #if EFSYS_OPT_MCDI_LOGGING
245 typedef enum efx_log_msg_e {
247 EFX_LOG_MCDI_REQUEST,
248 EFX_LOG_MCDI_RESPONSE,
250 #endif /* EFSYS_OPT_MCDI_LOGGING */
252 typedef struct efx_mcdi_transport_s {
254 efsys_mem_t *emt_dma_mem;
255 void (*emt_execute)(void *, efx_mcdi_req_t *);
256 void (*emt_ev_cpl)(void *);
257 void (*emt_exception)(void *, efx_mcdi_exception_t);
258 #if EFSYS_OPT_MCDI_LOGGING
259 void (*emt_logger)(void *, efx_log_msg_t,
260 void *, size_t, void *, size_t);
261 #endif /* EFSYS_OPT_MCDI_LOGGING */
262 #if EFSYS_OPT_MCDI_PROXY_AUTH
263 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
264 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
265 } efx_mcdi_transport_t;
267 extern __checkReturn efx_rc_t
270 __in const efx_mcdi_transport_t *mtp);
272 extern __checkReturn efx_rc_t
274 __in efx_nic_t *enp);
278 __in efx_nic_t *enp);
281 efx_mcdi_get_timeout(
283 __in efx_mcdi_req_t *emrp,
284 __out uint32_t *usec_timeoutp);
287 efx_mcdi_request_start(
289 __in efx_mcdi_req_t *emrp,
290 __in boolean_t ev_cpl);
292 extern __checkReturn boolean_t
293 efx_mcdi_request_poll(
294 __in efx_nic_t *enp);
296 extern __checkReturn boolean_t
297 efx_mcdi_request_abort(
298 __in efx_nic_t *enp);
302 __in efx_nic_t *enp);
304 #endif /* EFSYS_OPT_MCDI */
308 #define EFX_NINTR_SIENA 1024
310 typedef enum efx_intr_type_e {
311 EFX_INTR_INVALID = 0,
317 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
319 extern __checkReturn efx_rc_t
322 __in efx_intr_type_t type,
323 __in efsys_mem_t *esmp);
327 __in efx_nic_t *enp);
331 __in efx_nic_t *enp);
334 efx_intr_disable_unlocked(
335 __in efx_nic_t *enp);
337 #define EFX_INTR_NEVQS 32
339 extern __checkReturn efx_rc_t
342 __in unsigned int level);
345 efx_intr_status_line(
347 __out boolean_t *fatalp,
348 __out uint32_t *maskp);
351 efx_intr_status_message(
353 __in unsigned int message,
354 __out boolean_t *fatalp);
358 __in efx_nic_t *enp);
362 __in efx_nic_t *enp);
366 #if EFSYS_OPT_MAC_STATS
368 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
369 typedef enum efx_mac_stat_e {
372 EFX_MAC_RX_UNICST_PKTS,
373 EFX_MAC_RX_MULTICST_PKTS,
374 EFX_MAC_RX_BRDCST_PKTS,
375 EFX_MAC_RX_PAUSE_PKTS,
376 EFX_MAC_RX_LE_64_PKTS,
377 EFX_MAC_RX_65_TO_127_PKTS,
378 EFX_MAC_RX_128_TO_255_PKTS,
379 EFX_MAC_RX_256_TO_511_PKTS,
380 EFX_MAC_RX_512_TO_1023_PKTS,
381 EFX_MAC_RX_1024_TO_15XX_PKTS,
382 EFX_MAC_RX_GE_15XX_PKTS,
384 EFX_MAC_RX_FCS_ERRORS,
385 EFX_MAC_RX_DROP_EVENTS,
386 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
387 EFX_MAC_RX_SYMBOL_ERRORS,
388 EFX_MAC_RX_ALIGN_ERRORS,
389 EFX_MAC_RX_INTERNAL_ERRORS,
390 EFX_MAC_RX_JABBER_PKTS,
391 EFX_MAC_RX_LANE0_CHAR_ERR,
392 EFX_MAC_RX_LANE1_CHAR_ERR,
393 EFX_MAC_RX_LANE2_CHAR_ERR,
394 EFX_MAC_RX_LANE3_CHAR_ERR,
395 EFX_MAC_RX_LANE0_DISP_ERR,
396 EFX_MAC_RX_LANE1_DISP_ERR,
397 EFX_MAC_RX_LANE2_DISP_ERR,
398 EFX_MAC_RX_LANE3_DISP_ERR,
399 EFX_MAC_RX_MATCH_FAULT,
400 EFX_MAC_RX_NODESC_DROP_CNT,
403 EFX_MAC_TX_UNICST_PKTS,
404 EFX_MAC_TX_MULTICST_PKTS,
405 EFX_MAC_TX_BRDCST_PKTS,
406 EFX_MAC_TX_PAUSE_PKTS,
407 EFX_MAC_TX_LE_64_PKTS,
408 EFX_MAC_TX_65_TO_127_PKTS,
409 EFX_MAC_TX_128_TO_255_PKTS,
410 EFX_MAC_TX_256_TO_511_PKTS,
411 EFX_MAC_TX_512_TO_1023_PKTS,
412 EFX_MAC_TX_1024_TO_15XX_PKTS,
413 EFX_MAC_TX_GE_15XX_PKTS,
415 EFX_MAC_TX_SGL_COL_PKTS,
416 EFX_MAC_TX_MULT_COL_PKTS,
417 EFX_MAC_TX_EX_COL_PKTS,
418 EFX_MAC_TX_LATE_COL_PKTS,
420 EFX_MAC_TX_EX_DEF_PKTS,
421 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
422 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
423 EFX_MAC_PM_TRUNC_VFIFO_FULL,
424 EFX_MAC_PM_DISCARD_VFIFO_FULL,
425 EFX_MAC_PM_TRUNC_QBB,
426 EFX_MAC_PM_DISCARD_QBB,
427 EFX_MAC_PM_DISCARD_MAPPING,
428 EFX_MAC_RXDP_Q_DISABLED_PKTS,
429 EFX_MAC_RXDP_DI_DROPPED_PKTS,
430 EFX_MAC_RXDP_STREAMING_PKTS,
431 EFX_MAC_RXDP_HLB_FETCH,
432 EFX_MAC_RXDP_HLB_WAIT,
433 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
434 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
435 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
436 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
437 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
438 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
439 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
440 EFX_MAC_VADAPTER_RX_BAD_BYTES,
441 EFX_MAC_VADAPTER_RX_OVERFLOW,
442 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
443 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
444 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
445 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
446 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
447 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
448 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
449 EFX_MAC_VADAPTER_TX_BAD_BYTES,
450 EFX_MAC_VADAPTER_TX_OVERFLOW,
451 EFX_MAC_FEC_UNCORRECTED_ERRORS,
452 EFX_MAC_FEC_CORRECTED_ERRORS,
453 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
454 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
455 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
456 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
457 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
458 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
459 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
460 EFX_MAC_CTPIO_OVERFLOW_FAIL,
461 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
462 EFX_MAC_CTPIO_TIMEOUT_FAIL,
463 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
464 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
465 EFX_MAC_CTPIO_INVALID_WR_FAIL,
466 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
467 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
468 EFX_MAC_CTPIO_RUNT_FALLBACK,
469 EFX_MAC_CTPIO_SUCCESS,
470 EFX_MAC_CTPIO_FALLBACK,
471 EFX_MAC_CTPIO_POISON,
473 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
474 EFX_MAC_RXDP_HLB_IDLE,
475 EFX_MAC_RXDP_HLB_TIMEOUT,
479 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
481 #endif /* EFSYS_OPT_MAC_STATS */
483 typedef enum efx_link_mode_e {
484 EFX_LINK_UNKNOWN = 0,
500 #define EFX_MAC_ADDR_LEN 6
502 #define EFX_VNI_OR_VSID_LEN 3
504 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
506 #define EFX_MAC_MULTICAST_LIST_MAX 256
508 #define EFX_MAC_SDU_MAX 9202
510 #define EFX_MAC_PDU_ADJUSTMENT \
514 + /* bug16011 */ 16) \
516 #define EFX_MAC_PDU(_sdu) \
517 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
520 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
521 * the SDU rounded up slightly.
523 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
525 #define EFX_MAC_PDU_MIN 60
526 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
528 extern __checkReturn efx_rc_t
533 extern __checkReturn efx_rc_t
538 extern __checkReturn efx_rc_t
543 extern __checkReturn efx_rc_t
546 __in boolean_t all_unicst,
547 __in boolean_t mulcst,
548 __in boolean_t all_mulcst,
549 __in boolean_t brdcst);
551 extern __checkReturn efx_rc_t
552 efx_mac_multicast_list_set(
554 __in_ecount(6*count) uint8_t const *addrs,
557 extern __checkReturn efx_rc_t
558 efx_mac_filter_default_rxq_set(
561 __in boolean_t using_rss);
564 efx_mac_filter_default_rxq_clear(
565 __in efx_nic_t *enp);
567 extern __checkReturn efx_rc_t
570 __in boolean_t enabled);
572 extern __checkReturn efx_rc_t
575 __out boolean_t *mac_upp);
577 #define EFX_FCNTL_RESPOND 0x00000001
578 #define EFX_FCNTL_GENERATE 0x00000002
580 extern __checkReturn efx_rc_t
583 __in unsigned int fcntl,
584 __in boolean_t autoneg);
589 __out unsigned int *fcntl_wantedp,
590 __out unsigned int *fcntl_linkp);
593 #if EFSYS_OPT_MAC_STATS
597 extern __checkReturn const char *
600 __in unsigned int id);
602 #endif /* EFSYS_OPT_NAMES */
604 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
606 #define EFX_MAC_STATS_MASK_NPAGES \
607 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
608 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
611 * Get mask of MAC statistics supported by the hardware.
613 * If mask_size is insufficient to return the mask, EINVAL error is
614 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
615 * (which is sizeof (uint32_t)) is sufficient.
617 extern __checkReturn efx_rc_t
618 efx_mac_stats_get_mask(
620 __out_bcount(mask_size) uint32_t *maskp,
621 __in size_t mask_size);
623 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
624 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
625 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
628 extern __checkReturn efx_rc_t
630 __in efx_nic_t *enp);
633 * Upload mac statistics supported by the hardware into the given buffer.
635 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
636 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
638 * The hardware will only DMA statistics that it understands (of course).
639 * Drivers should not make any assumptions about which statistics are
640 * supported, especially when the statistics are generated by firmware.
642 * Thus, drivers should zero this buffer before use, so that not-understood
643 * statistics read back as zero.
645 extern __checkReturn efx_rc_t
646 efx_mac_stats_upload(
648 __in efsys_mem_t *esmp);
650 extern __checkReturn efx_rc_t
651 efx_mac_stats_periodic(
653 __in efsys_mem_t *esmp,
654 __in uint16_t period_ms,
655 __in boolean_t events);
657 extern __checkReturn efx_rc_t
658 efx_mac_stats_update(
660 __in efsys_mem_t *esmp,
661 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
662 __inout_opt uint32_t *generationp);
664 #endif /* EFSYS_OPT_MAC_STATS */
668 typedef enum efx_mon_type_e {
680 __in efx_nic_t *enp);
682 #endif /* EFSYS_OPT_NAMES */
684 extern __checkReturn efx_rc_t
686 __in efx_nic_t *enp);
688 #if EFSYS_OPT_MON_STATS
690 #define EFX_MON_STATS_PAGE_SIZE 0x100
691 #define EFX_MON_MASK_ELEMENT_SIZE 32
693 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
694 typedef enum efx_mon_stat_e {
695 EFX_MON_STAT_CONTROLLER_TEMP,
696 EFX_MON_STAT_PHY_COMMON_TEMP,
697 EFX_MON_STAT_CONTROLLER_COOLING,
698 EFX_MON_STAT_PHY0_TEMP,
699 EFX_MON_STAT_PHY0_COOLING,
700 EFX_MON_STAT_PHY1_TEMP,
701 EFX_MON_STAT_PHY1_COOLING,
707 EFX_MON_STAT_IN_12V0,
708 EFX_MON_STAT_IN_1V2A,
709 EFX_MON_STAT_IN_VREF,
710 EFX_MON_STAT_OUT_VAOE,
711 EFX_MON_STAT_AOE_TEMP,
712 EFX_MON_STAT_PSU_AOE_TEMP,
713 EFX_MON_STAT_PSU_TEMP,
719 EFX_MON_STAT_IN_VAOE,
720 EFX_MON_STAT_OUT_IAOE,
721 EFX_MON_STAT_IN_IAOE,
722 EFX_MON_STAT_NIC_POWER,
724 EFX_MON_STAT_IN_I0V9,
725 EFX_MON_STAT_IN_I1V2,
726 EFX_MON_STAT_IN_0V9_ADC,
727 EFX_MON_STAT_CONTROLLER_2_TEMP,
728 EFX_MON_STAT_VREG_INTERNAL_TEMP,
729 EFX_MON_STAT_VREG_0V9_TEMP,
730 EFX_MON_STAT_VREG_1V2_TEMP,
731 EFX_MON_STAT_CONTROLLER_VPTAT,
732 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
733 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
734 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
735 EFX_MON_STAT_AMBIENT_TEMP,
736 EFX_MON_STAT_AIRFLOW,
737 EFX_MON_STAT_VDD08D_VSS08D_CSR,
738 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
739 EFX_MON_STAT_HOTPOINT_TEMP,
740 EFX_MON_STAT_PHY_POWER_PORT0,
741 EFX_MON_STAT_PHY_POWER_PORT1,
742 EFX_MON_STAT_MUM_VCC,
743 EFX_MON_STAT_IN_0V9_A,
744 EFX_MON_STAT_IN_I0V9_A,
745 EFX_MON_STAT_VREG_0V9_A_TEMP,
746 EFX_MON_STAT_IN_0V9_B,
747 EFX_MON_STAT_IN_I0V9_B,
748 EFX_MON_STAT_VREG_0V9_B_TEMP,
749 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
750 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
751 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
752 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
753 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
754 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
755 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
756 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
757 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
758 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
759 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
760 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
761 EFX_MON_STAT_SODIMM_VOUT,
762 EFX_MON_STAT_SODIMM_0_TEMP,
763 EFX_MON_STAT_SODIMM_1_TEMP,
764 EFX_MON_STAT_PHY0_VCC,
765 EFX_MON_STAT_PHY1_VCC,
766 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
767 EFX_MON_STAT_BOARD_FRONT_TEMP,
768 EFX_MON_STAT_BOARD_BACK_TEMP,
769 EFX_MON_STAT_IN_I1V8,
770 EFX_MON_STAT_IN_I2V5,
771 EFX_MON_STAT_IN_I3V3,
772 EFX_MON_STAT_IN_I12V0,
774 EFX_MON_STAT_IN_I1V3,
778 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
780 typedef enum efx_mon_stat_state_e {
781 EFX_MON_STAT_STATE_OK = 0,
782 EFX_MON_STAT_STATE_WARNING = 1,
783 EFX_MON_STAT_STATE_FATAL = 2,
784 EFX_MON_STAT_STATE_BROKEN = 3,
785 EFX_MON_STAT_STATE_NO_READING = 4,
786 } efx_mon_stat_state_t;
788 typedef enum efx_mon_stat_unit_e {
789 EFX_MON_STAT_UNIT_UNKNOWN = 0,
790 EFX_MON_STAT_UNIT_BOOL,
791 EFX_MON_STAT_UNIT_TEMP_C,
792 EFX_MON_STAT_UNIT_VOLTAGE_MV,
793 EFX_MON_STAT_UNIT_CURRENT_MA,
794 EFX_MON_STAT_UNIT_POWER_W,
795 EFX_MON_STAT_UNIT_RPM,
797 } efx_mon_stat_unit_t;
799 typedef struct efx_mon_stat_value_s {
801 efx_mon_stat_state_t emsv_state;
802 efx_mon_stat_unit_t emsv_unit;
803 } efx_mon_stat_value_t;
805 typedef struct efx_mon_limit_value_s {
806 uint16_t emlv_warning_min;
807 uint16_t emlv_warning_max;
808 uint16_t emlv_fatal_min;
809 uint16_t emlv_fatal_max;
810 } efx_mon_stat_limits_t;
812 typedef enum efx_mon_stat_portmask_e {
813 EFX_MON_STAT_PORTMAP_NONE = 0,
814 EFX_MON_STAT_PORTMAP_PORT0 = 1,
815 EFX_MON_STAT_PORTMAP_PORT1 = 2,
816 EFX_MON_STAT_PORTMAP_PORT2 = 3,
817 EFX_MON_STAT_PORTMAP_PORT3 = 4,
818 EFX_MON_STAT_PORTMAP_ALL = (-1),
819 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
820 } efx_mon_stat_portmask_t;
827 __in efx_mon_stat_t id);
830 efx_mon_stat_description(
832 __in efx_mon_stat_t id);
834 #endif /* EFSYS_OPT_NAMES */
836 extern __checkReturn boolean_t
837 efx_mon_mcdi_to_efx_stat(
839 __out efx_mon_stat_t *statp);
841 extern __checkReturn boolean_t
842 efx_mon_get_stat_unit(
843 __in efx_mon_stat_t stat,
844 __out efx_mon_stat_unit_t *unitp);
846 extern __checkReturn boolean_t
847 efx_mon_get_stat_portmap(
848 __in efx_mon_stat_t stat,
849 __out efx_mon_stat_portmask_t *maskp);
851 extern __checkReturn efx_rc_t
852 efx_mon_stats_update(
854 __in efsys_mem_t *esmp,
855 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
857 extern __checkReturn efx_rc_t
858 efx_mon_limits_update(
860 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
862 #endif /* EFSYS_OPT_MON_STATS */
866 __in efx_nic_t *enp);
870 extern __checkReturn efx_rc_t
872 __in efx_nic_t *enp);
874 #if EFSYS_OPT_PHY_LED_CONTROL
876 typedef enum efx_phy_led_mode_e {
877 EFX_PHY_LED_DEFAULT = 0,
882 } efx_phy_led_mode_t;
884 extern __checkReturn efx_rc_t
887 __in efx_phy_led_mode_t mode);
889 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
891 extern __checkReturn efx_rc_t
893 __in efx_nic_t *enp);
895 #if EFSYS_OPT_LOOPBACK
897 typedef enum efx_loopback_type_e {
898 EFX_LOOPBACK_OFF = 0,
899 EFX_LOOPBACK_DATA = 1,
900 EFX_LOOPBACK_GMAC = 2,
901 EFX_LOOPBACK_XGMII = 3,
902 EFX_LOOPBACK_XGXS = 4,
903 EFX_LOOPBACK_XAUI = 5,
904 EFX_LOOPBACK_GMII = 6,
905 EFX_LOOPBACK_SGMII = 7,
906 EFX_LOOPBACK_XGBR = 8,
907 EFX_LOOPBACK_XFI = 9,
908 EFX_LOOPBACK_XAUI_FAR = 10,
909 EFX_LOOPBACK_GMII_FAR = 11,
910 EFX_LOOPBACK_SGMII_FAR = 12,
911 EFX_LOOPBACK_XFI_FAR = 13,
912 EFX_LOOPBACK_GPHY = 14,
913 EFX_LOOPBACK_PHY_XS = 15,
914 EFX_LOOPBACK_PCS = 16,
915 EFX_LOOPBACK_PMA_PMD = 17,
916 EFX_LOOPBACK_XPORT = 18,
917 EFX_LOOPBACK_XGMII_WS = 19,
918 EFX_LOOPBACK_XAUI_WS = 20,
919 EFX_LOOPBACK_XAUI_WS_FAR = 21,
920 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
921 EFX_LOOPBACK_GMII_WS = 23,
922 EFX_LOOPBACK_XFI_WS = 24,
923 EFX_LOOPBACK_XFI_WS_FAR = 25,
924 EFX_LOOPBACK_PHYXS_WS = 26,
925 EFX_LOOPBACK_PMA_INT = 27,
926 EFX_LOOPBACK_SD_NEAR = 28,
927 EFX_LOOPBACK_SD_FAR = 29,
928 EFX_LOOPBACK_PMA_INT_WS = 30,
929 EFX_LOOPBACK_SD_FEP2_WS = 31,
930 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
931 EFX_LOOPBACK_SD_FEP_WS = 33,
932 EFX_LOOPBACK_SD_FES_WS = 34,
933 EFX_LOOPBACK_AOE_INT_NEAR = 35,
934 EFX_LOOPBACK_DATA_WS = 36,
935 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
937 } efx_loopback_type_t;
939 typedef enum efx_loopback_kind_e {
940 EFX_LOOPBACK_KIND_OFF = 0,
941 EFX_LOOPBACK_KIND_ALL,
942 EFX_LOOPBACK_KIND_MAC,
943 EFX_LOOPBACK_KIND_PHY,
945 } efx_loopback_kind_t;
949 __in efx_loopback_kind_t loopback_kind,
950 __out efx_qword_t *maskp);
952 extern __checkReturn efx_rc_t
953 efx_port_loopback_set(
955 __in efx_link_mode_t link_mode,
956 __in efx_loopback_type_t type);
960 extern __checkReturn const char *
961 efx_loopback_type_name(
963 __in efx_loopback_type_t type);
965 #endif /* EFSYS_OPT_NAMES */
967 #endif /* EFSYS_OPT_LOOPBACK */
969 extern __checkReturn efx_rc_t
972 __out_opt efx_link_mode_t *link_modep);
976 __in efx_nic_t *enp);
978 typedef enum efx_phy_cap_type_e {
979 EFX_PHY_CAP_INVALID = 0,
986 EFX_PHY_CAP_10000FDX,
990 EFX_PHY_CAP_40000FDX,
992 EFX_PHY_CAP_100000FDX,
993 EFX_PHY_CAP_25000FDX,
994 EFX_PHY_CAP_50000FDX,
995 EFX_PHY_CAP_BASER_FEC,
996 EFX_PHY_CAP_BASER_FEC_REQUESTED,
998 EFX_PHY_CAP_RS_FEC_REQUESTED,
999 EFX_PHY_CAP_25G_BASER_FEC,
1000 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1002 } efx_phy_cap_type_t;
1005 #define EFX_PHY_CAP_CURRENT 0x00000000
1006 #define EFX_PHY_CAP_DEFAULT 0x00000001
1007 #define EFX_PHY_CAP_PERM 0x00000002
1010 efx_phy_adv_cap_get(
1011 __in efx_nic_t *enp,
1013 __out uint32_t *maskp);
1015 extern __checkReturn efx_rc_t
1016 efx_phy_adv_cap_set(
1017 __in efx_nic_t *enp,
1018 __in uint32_t mask);
1022 __in efx_nic_t *enp,
1023 __out uint32_t *maskp);
1025 extern __checkReturn efx_rc_t
1027 __in efx_nic_t *enp,
1028 __out uint32_t *ouip);
1030 typedef enum efx_phy_media_type_e {
1031 EFX_PHY_MEDIA_INVALID = 0,
1036 EFX_PHY_MEDIA_SFP_PLUS,
1037 EFX_PHY_MEDIA_BASE_T,
1038 EFX_PHY_MEDIA_QSFP_PLUS,
1039 EFX_PHY_MEDIA_NTYPES
1040 } efx_phy_media_type_t;
1043 * Get the type of medium currently used. If the board has ports for
1044 * modules, a module is present, and we recognise the media type of
1045 * the module, then this will be the media type of the module.
1046 * Otherwise it will be the media type of the port.
1049 efx_phy_media_type_get(
1050 __in efx_nic_t *enp,
1051 __out efx_phy_media_type_t *typep);
1053 extern __checkReturn efx_rc_t
1054 efx_phy_module_get_info(
1055 __in efx_nic_t *enp,
1056 __in uint8_t dev_addr,
1057 __in uint8_t offset,
1059 __out_bcount(len) uint8_t *data);
1061 #if EFSYS_OPT_PHY_STATS
1063 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1064 typedef enum efx_phy_stat_e {
1066 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1067 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1068 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1069 EFX_PHY_STAT_PMA_PMD_REV_A,
1070 EFX_PHY_STAT_PMA_PMD_REV_B,
1071 EFX_PHY_STAT_PMA_PMD_REV_C,
1072 EFX_PHY_STAT_PMA_PMD_REV_D,
1073 EFX_PHY_STAT_PCS_LINK_UP,
1074 EFX_PHY_STAT_PCS_RX_FAULT,
1075 EFX_PHY_STAT_PCS_TX_FAULT,
1076 EFX_PHY_STAT_PCS_BER,
1077 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1078 EFX_PHY_STAT_PHY_XS_LINK_UP,
1079 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1080 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1081 EFX_PHY_STAT_PHY_XS_ALIGN,
1082 EFX_PHY_STAT_PHY_XS_SYNC_A,
1083 EFX_PHY_STAT_PHY_XS_SYNC_B,
1084 EFX_PHY_STAT_PHY_XS_SYNC_C,
1085 EFX_PHY_STAT_PHY_XS_SYNC_D,
1086 EFX_PHY_STAT_AN_LINK_UP,
1087 EFX_PHY_STAT_AN_MASTER,
1088 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1089 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1090 EFX_PHY_STAT_CL22EXT_LINK_UP,
1095 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1096 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1097 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1098 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1099 EFX_PHY_STAT_AN_COMPLETE,
1100 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1101 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1102 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1103 EFX_PHY_STAT_PCS_FW_VERSION_0,
1104 EFX_PHY_STAT_PCS_FW_VERSION_1,
1105 EFX_PHY_STAT_PCS_FW_VERSION_2,
1106 EFX_PHY_STAT_PCS_FW_VERSION_3,
1107 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1108 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1109 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1110 EFX_PHY_STAT_PCS_OP_MODE,
1114 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1120 __in efx_nic_t *enp,
1121 __in efx_phy_stat_t stat);
1123 #endif /* EFSYS_OPT_NAMES */
1125 #define EFX_PHY_STATS_SIZE 0x100
1127 extern __checkReturn efx_rc_t
1128 efx_phy_stats_update(
1129 __in efx_nic_t *enp,
1130 __in efsys_mem_t *esmp,
1131 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1133 #endif /* EFSYS_OPT_PHY_STATS */
1138 typedef enum efx_bist_type_e {
1139 EFX_BIST_TYPE_UNKNOWN,
1140 EFX_BIST_TYPE_PHY_NORMAL,
1141 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1142 EFX_BIST_TYPE_PHY_CABLE_LONG,
1143 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1144 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1145 EFX_BIST_TYPE_REG, /* Test the register memories */
1146 EFX_BIST_TYPE_NTYPES,
1149 typedef enum efx_bist_result_e {
1150 EFX_BIST_RESULT_UNKNOWN,
1151 EFX_BIST_RESULT_RUNNING,
1152 EFX_BIST_RESULT_PASSED,
1153 EFX_BIST_RESULT_FAILED,
1154 } efx_bist_result_t;
1156 typedef enum efx_phy_cable_status_e {
1157 EFX_PHY_CABLE_STATUS_OK,
1158 EFX_PHY_CABLE_STATUS_INVALID,
1159 EFX_PHY_CABLE_STATUS_OPEN,
1160 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1161 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1162 EFX_PHY_CABLE_STATUS_BUSY,
1163 } efx_phy_cable_status_t;
1165 typedef enum efx_bist_value_e {
1166 EFX_BIST_PHY_CABLE_LENGTH_A,
1167 EFX_BIST_PHY_CABLE_LENGTH_B,
1168 EFX_BIST_PHY_CABLE_LENGTH_C,
1169 EFX_BIST_PHY_CABLE_LENGTH_D,
1170 EFX_BIST_PHY_CABLE_STATUS_A,
1171 EFX_BIST_PHY_CABLE_STATUS_B,
1172 EFX_BIST_PHY_CABLE_STATUS_C,
1173 EFX_BIST_PHY_CABLE_STATUS_D,
1174 EFX_BIST_FAULT_CODE,
1176 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1182 EFX_BIST_MEM_EXPECT,
1183 EFX_BIST_MEM_ACTUAL,
1185 EFX_BIST_MEM_ECC_PARITY,
1186 EFX_BIST_MEM_ECC_FATAL,
1190 extern __checkReturn efx_rc_t
1191 efx_bist_enable_offline(
1192 __in efx_nic_t *enp);
1194 extern __checkReturn efx_rc_t
1196 __in efx_nic_t *enp,
1197 __in efx_bist_type_t type);
1199 extern __checkReturn efx_rc_t
1201 __in efx_nic_t *enp,
1202 __in efx_bist_type_t type,
1203 __out efx_bist_result_t *resultp,
1204 __out_opt uint32_t *value_maskp,
1205 __out_ecount_opt(count) unsigned long *valuesp,
1210 __in efx_nic_t *enp,
1211 __in efx_bist_type_t type);
1213 #endif /* EFSYS_OPT_BIST */
1215 #define EFX_FEATURE_IPV6 0x00000001
1216 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1217 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1218 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1219 #define EFX_FEATURE_MCDI 0x00000020
1220 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1221 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1222 #define EFX_FEATURE_TURBO 0x00000100
1223 #define EFX_FEATURE_MCDI_DMA 0x00000200
1224 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1225 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1226 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1227 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1228 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1230 typedef enum efx_tunnel_protocol_e {
1231 EFX_TUNNEL_PROTOCOL_NONE = 0,
1232 EFX_TUNNEL_PROTOCOL_VXLAN,
1233 EFX_TUNNEL_PROTOCOL_GENEVE,
1234 EFX_TUNNEL_PROTOCOL_NVGRE,
1236 } efx_tunnel_protocol_t;
1238 typedef enum efx_vi_window_shift_e {
1239 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1240 EFX_VI_WINDOW_SHIFT_8K = 13,
1241 EFX_VI_WINDOW_SHIFT_16K = 14,
1242 EFX_VI_WINDOW_SHIFT_64K = 16,
1243 } efx_vi_window_shift_t;
1245 typedef struct efx_nic_cfg_s {
1246 uint32_t enc_board_type;
1247 uint32_t enc_phy_type;
1249 char enc_phy_name[21];
1251 char enc_phy_revision[21];
1252 efx_mon_type_t enc_mon_type;
1253 #if EFSYS_OPT_MON_STATS
1254 uint32_t enc_mon_stat_dma_buf_size;
1255 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1257 unsigned int enc_features;
1258 efx_vi_window_shift_t enc_vi_window_shift;
1259 uint8_t enc_mac_addr[6];
1260 uint8_t enc_port; /* PHY port number */
1261 uint32_t enc_intr_vec_base;
1262 uint32_t enc_intr_limit;
1263 uint32_t enc_evq_limit;
1264 uint32_t enc_txq_limit;
1265 uint32_t enc_rxq_limit;
1266 uint32_t enc_txq_max_ndescs;
1267 uint32_t enc_buftbl_limit;
1268 uint32_t enc_piobuf_limit;
1269 uint32_t enc_piobuf_size;
1270 uint32_t enc_piobuf_min_alloc_size;
1271 uint32_t enc_evq_timer_quantum_ns;
1272 uint32_t enc_evq_timer_max_us;
1273 uint32_t enc_clk_mult;
1274 uint32_t enc_rx_prefix_size;
1275 uint32_t enc_rx_buf_align_start;
1276 uint32_t enc_rx_buf_align_end;
1277 uint32_t enc_rx_scale_max_exclusive_contexts;
1279 * Mask of supported hash algorithms.
1280 * Hash algorithm types are used as the bit indices.
1282 uint32_t enc_rx_scale_hash_alg_mask;
1284 * Indicates whether port numbers can be included to the
1285 * input data for hash computation.
1287 boolean_t enc_rx_scale_l4_hash_supported;
1288 boolean_t enc_rx_scale_additional_modes_supported;
1289 #if EFSYS_OPT_LOOPBACK
1290 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1291 #endif /* EFSYS_OPT_LOOPBACK */
1292 #if EFSYS_OPT_PHY_FLAGS
1293 uint32_t enc_phy_flags_mask;
1294 #endif /* EFSYS_OPT_PHY_FLAGS */
1295 #if EFSYS_OPT_PHY_LED_CONTROL
1296 uint32_t enc_led_mask;
1297 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1298 #if EFSYS_OPT_PHY_STATS
1299 uint64_t enc_phy_stat_mask;
1300 #endif /* EFSYS_OPT_PHY_STATS */
1302 uint8_t enc_mcdi_mdio_channel;
1303 #if EFSYS_OPT_PHY_STATS
1304 uint32_t enc_mcdi_phy_stat_mask;
1305 #endif /* EFSYS_OPT_PHY_STATS */
1306 #if EFSYS_OPT_MON_STATS
1307 uint32_t *enc_mcdi_sensor_maskp;
1308 uint32_t enc_mcdi_sensor_mask_size;
1309 #endif /* EFSYS_OPT_MON_STATS */
1310 #endif /* EFSYS_OPT_MCDI */
1312 uint32_t enc_bist_mask;
1313 #endif /* EFSYS_OPT_BIST */
1314 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1317 uint32_t enc_privilege_mask;
1318 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1319 boolean_t enc_bug26807_workaround;
1320 boolean_t enc_bug35388_workaround;
1321 boolean_t enc_bug41750_workaround;
1322 boolean_t enc_bug61265_workaround;
1323 boolean_t enc_bug61297_workaround;
1324 boolean_t enc_rx_batching_enabled;
1325 /* Maximum number of descriptors completed in an rx event. */
1326 uint32_t enc_rx_batch_max;
1327 /* Number of rx descriptors the hardware requires for a push. */
1328 uint32_t enc_rx_push_align;
1329 /* Maximum amount of data in DMA descriptor */
1330 uint32_t enc_tx_dma_desc_size_max;
1332 * Boundary which DMA descriptor data must not cross or 0 if no
1335 uint32_t enc_tx_dma_desc_boundary;
1337 * Maximum number of bytes into the packet the TCP header can start for
1338 * the hardware to apply TSO packet edits.
1340 uint32_t enc_tx_tso_tcp_header_offset_limit;
1341 boolean_t enc_fw_assisted_tso_enabled;
1342 boolean_t enc_fw_assisted_tso_v2_enabled;
1343 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1344 /* Number of TSO contexts on the NIC (FATSOv2) */
1345 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1346 boolean_t enc_hw_tx_insert_vlan_enabled;
1347 /* Number of PFs on the NIC */
1348 uint32_t enc_hw_pf_count;
1349 /* Datapath firmware vadapter/vport/vswitch support */
1350 boolean_t enc_datapath_cap_evb;
1351 boolean_t enc_rx_disable_scatter_supported;
1352 boolean_t enc_allow_set_mac_with_installed_filters;
1353 boolean_t enc_enhanced_set_mac_supported;
1354 boolean_t enc_init_evq_v2_supported;
1355 boolean_t enc_rx_packed_stream_supported;
1356 boolean_t enc_rx_var_packed_stream_supported;
1357 boolean_t enc_rx_es_super_buffer_supported;
1358 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1359 boolean_t enc_pm_and_rxdp_counters;
1360 boolean_t enc_mac_stats_40g_tx_size_bins;
1361 uint32_t enc_tunnel_encapsulations_supported;
1363 * NIC global maximum for unique UDP tunnel ports shared by all
1366 uint32_t enc_tunnel_config_udp_entries_max;
1367 /* External port identifier */
1368 uint8_t enc_external_port;
1369 uint32_t enc_mcdi_max_payload_length;
1370 /* VPD may be per-PF or global */
1371 boolean_t enc_vpd_is_global;
1372 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1373 uint32_t enc_required_pcie_bandwidth_mbps;
1374 uint32_t enc_max_pcie_link_gen;
1375 /* Firmware verifies integrity of NVRAM updates */
1376 uint32_t enc_nvram_update_verify_result_supported;
1377 /* Firmware support for extended MAC_STATS buffer */
1378 uint32_t enc_mac_stats_nstats;
1379 boolean_t enc_fec_counters;
1380 boolean_t enc_hlb_counters;
1381 /* Firmware support for "FLAG" and "MARK" filter actions */
1382 boolean_t enc_filter_action_flag_supported;
1383 boolean_t enc_filter_action_mark_supported;
1384 uint32_t enc_filter_action_mark_max;
1387 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1388 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1390 #define EFX_PCI_FUNCTION(_encp) \
1391 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1393 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1395 extern const efx_nic_cfg_t *
1397 __in efx_nic_t *enp);
1399 /* RxDPCPU firmware id values by which FW variant can be identified */
1400 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1401 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1402 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1403 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1404 #define EFX_RXDP_DPDK_FW_ID 0x6
1406 typedef struct efx_nic_fw_info_s {
1407 /* Basic FW version information */
1408 uint16_t enfi_mc_fw_version[4];
1410 * If datapath capabilities can be detected,
1411 * additional FW information is to be shown
1413 boolean_t enfi_dpcpu_fw_ids_valid;
1414 /* Rx and Tx datapath CPU FW IDs */
1415 uint16_t enfi_rx_dpcpu_fw_id;
1416 uint16_t enfi_tx_dpcpu_fw_id;
1417 } efx_nic_fw_info_t;
1419 extern __checkReturn efx_rc_t
1420 efx_nic_get_fw_version(
1421 __in efx_nic_t *enp,
1422 __out efx_nic_fw_info_t *enfip);
1424 /* Driver resource limits (minimum required/maximum usable). */
1425 typedef struct efx_drv_limits_s {
1426 uint32_t edl_min_evq_count;
1427 uint32_t edl_max_evq_count;
1429 uint32_t edl_min_rxq_count;
1430 uint32_t edl_max_rxq_count;
1432 uint32_t edl_min_txq_count;
1433 uint32_t edl_max_txq_count;
1435 /* PIO blocks (sub-allocated from piobuf) */
1436 uint32_t edl_min_pio_alloc_size;
1437 uint32_t edl_max_pio_alloc_count;
1440 extern __checkReturn efx_rc_t
1441 efx_nic_set_drv_limits(
1442 __inout efx_nic_t *enp,
1443 __in efx_drv_limits_t *edlp);
1445 typedef enum efx_nic_region_e {
1446 EFX_REGION_VI, /* Memory BAR UC mapping */
1447 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1450 extern __checkReturn efx_rc_t
1451 efx_nic_get_bar_region(
1452 __in efx_nic_t *enp,
1453 __in efx_nic_region_t region,
1454 __out uint32_t *offsetp,
1455 __out size_t *sizep);
1457 extern __checkReturn efx_rc_t
1458 efx_nic_get_vi_pool(
1459 __in efx_nic_t *enp,
1460 __out uint32_t *evq_countp,
1461 __out uint32_t *rxq_countp,
1462 __out uint32_t *txq_countp);
1467 typedef enum efx_vpd_tag_e {
1474 typedef uint16_t efx_vpd_keyword_t;
1476 typedef struct efx_vpd_value_s {
1477 efx_vpd_tag_t evv_tag;
1478 efx_vpd_keyword_t evv_keyword;
1480 uint8_t evv_value[0x100];
1484 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1486 extern __checkReturn efx_rc_t
1488 __in efx_nic_t *enp);
1490 extern __checkReturn efx_rc_t
1492 __in efx_nic_t *enp,
1493 __out size_t *sizep);
1495 extern __checkReturn efx_rc_t
1497 __in efx_nic_t *enp,
1498 __out_bcount(size) caddr_t data,
1501 extern __checkReturn efx_rc_t
1503 __in efx_nic_t *enp,
1504 __in_bcount(size) caddr_t data,
1507 extern __checkReturn efx_rc_t
1509 __in efx_nic_t *enp,
1510 __in_bcount(size) caddr_t data,
1513 extern __checkReturn efx_rc_t
1515 __in efx_nic_t *enp,
1516 __in_bcount(size) caddr_t data,
1518 __inout efx_vpd_value_t *evvp);
1520 extern __checkReturn efx_rc_t
1522 __in efx_nic_t *enp,
1523 __inout_bcount(size) caddr_t data,
1525 __in efx_vpd_value_t *evvp);
1527 extern __checkReturn efx_rc_t
1529 __in efx_nic_t *enp,
1530 __inout_bcount(size) caddr_t data,
1532 __out efx_vpd_value_t *evvp,
1533 __inout unsigned int *contp);
1535 extern __checkReturn efx_rc_t
1537 __in efx_nic_t *enp,
1538 __in_bcount(size) caddr_t data,
1543 __in efx_nic_t *enp);
1545 #endif /* EFSYS_OPT_VPD */
1551 typedef enum efx_nvram_type_e {
1552 EFX_NVRAM_INVALID = 0,
1554 EFX_NVRAM_BOOTROM_CFG,
1555 EFX_NVRAM_MC_FIRMWARE,
1556 EFX_NVRAM_MC_GOLDEN,
1562 EFX_NVRAM_FPGA_BACKUP,
1563 EFX_NVRAM_DYNAMIC_CFG,
1566 EFX_NVRAM_MUM_FIRMWARE,
1567 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1568 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1572 extern __checkReturn efx_rc_t
1574 __in efx_nic_t *enp);
1578 extern __checkReturn efx_rc_t
1580 __in efx_nic_t *enp);
1582 #endif /* EFSYS_OPT_DIAG */
1584 extern __checkReturn efx_rc_t
1586 __in efx_nic_t *enp,
1587 __in efx_nvram_type_t type,
1588 __out size_t *sizep);
1590 extern __checkReturn efx_rc_t
1592 __in efx_nic_t *enp,
1593 __in efx_nvram_type_t type,
1594 __out_opt size_t *pref_chunkp);
1596 extern __checkReturn efx_rc_t
1597 efx_nvram_rw_finish(
1598 __in efx_nic_t *enp,
1599 __in efx_nvram_type_t type,
1600 __out_opt uint32_t *verify_resultp);
1602 extern __checkReturn efx_rc_t
1603 efx_nvram_get_version(
1604 __in efx_nic_t *enp,
1605 __in efx_nvram_type_t type,
1606 __out uint32_t *subtypep,
1607 __out_ecount(4) uint16_t version[4]);
1609 extern __checkReturn efx_rc_t
1610 efx_nvram_read_chunk(
1611 __in efx_nic_t *enp,
1612 __in efx_nvram_type_t type,
1613 __in unsigned int offset,
1614 __out_bcount(size) caddr_t data,
1617 extern __checkReturn efx_rc_t
1618 efx_nvram_read_backup(
1619 __in efx_nic_t *enp,
1620 __in efx_nvram_type_t type,
1621 __in unsigned int offset,
1622 __out_bcount(size) caddr_t data,
1625 extern __checkReturn efx_rc_t
1626 efx_nvram_set_version(
1627 __in efx_nic_t *enp,
1628 __in efx_nvram_type_t type,
1629 __in_ecount(4) uint16_t version[4]);
1631 extern __checkReturn efx_rc_t
1633 __in efx_nic_t *enp,
1634 __in efx_nvram_type_t type,
1635 __in_bcount(partn_size) caddr_t partn_data,
1636 __in size_t partn_size);
1638 extern __checkReturn efx_rc_t
1640 __in efx_nic_t *enp,
1641 __in efx_nvram_type_t type);
1643 extern __checkReturn efx_rc_t
1644 efx_nvram_write_chunk(
1645 __in efx_nic_t *enp,
1646 __in efx_nvram_type_t type,
1647 __in unsigned int offset,
1648 __in_bcount(size) caddr_t data,
1653 __in efx_nic_t *enp);
1655 #endif /* EFSYS_OPT_NVRAM */
1657 #if EFSYS_OPT_BOOTCFG
1659 /* Report size and offset of bootcfg sector in NVRAM partition. */
1660 extern __checkReturn efx_rc_t
1661 efx_bootcfg_sector_info(
1662 __in efx_nic_t *enp,
1664 __out_opt uint32_t *sector_countp,
1665 __out size_t *offsetp,
1666 __out size_t *max_sizep);
1669 * Copy bootcfg sector data to a target buffer which may differ in size.
1670 * Optionally corrects format errors in source buffer.
1673 efx_bootcfg_copy_sector(
1674 __in efx_nic_t *enp,
1675 __inout_bcount(sector_length)
1677 __in size_t sector_length,
1678 __out_bcount(data_size) uint8_t *data,
1679 __in size_t data_size,
1680 __in boolean_t handle_format_errors);
1684 __in efx_nic_t *enp,
1685 __out_bcount(size) uint8_t *data,
1690 __in efx_nic_t *enp,
1691 __in_bcount(size) uint8_t *data,
1696 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1697 * (see https://tools.ietf.org/html/rfc1533)
1699 * Summarising the format: the buffer is a sequence of options. All options
1700 * begin with a tag octet, which uniquely identifies the option. Fixed-
1701 * length options without data consist of only a tag octet. Only options PAD
1702 * (0) and END (255) are fixed length. All other options are variable-length
1703 * with a length octet following the tag octet. The value of the length
1704 * octet does not include the two octets specifying the tag and length. The
1705 * length octet is followed by "length" octets of data.
1707 * Option data may be a sequence of sub-options in the same format. The data
1708 * content of the encapsulating option is one or more encapsulated sub-options,
1709 * with no terminating END tag is required.
1711 * To be valid, the top-level sequence of options should be terminated by an
1712 * END tag. The buffer should be padded with the PAD byte.
1714 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1715 * checksum octet. The full buffer (including after the END tag) contributes
1716 * to the checksum, hence the need to fill the buffer to the end with PAD.
1719 #define EFX_DHCP_END ((uint8_t)0xff)
1720 #define EFX_DHCP_PAD ((uint8_t)0)
1722 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1723 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1725 extern __checkReturn uint8_t
1727 __in_bcount(size) uint8_t const *data,
1730 extern __checkReturn efx_rc_t
1732 __in_bcount(size) uint8_t const *data,
1734 __out_opt size_t *usedp);
1736 extern __checkReturn efx_rc_t
1738 __in_bcount(buffer_length) uint8_t *bufferp,
1739 __in size_t buffer_length,
1741 __deref_out uint8_t **valuepp,
1742 __out size_t *value_lengthp);
1744 extern __checkReturn efx_rc_t
1746 __in_bcount(buffer_length) uint8_t *bufferp,
1747 __in size_t buffer_length,
1748 __deref_out uint8_t **endpp);
1751 extern __checkReturn efx_rc_t
1752 efx_dhcp_delete_tag(
1753 __inout_bcount(buffer_length) uint8_t *bufferp,
1754 __in size_t buffer_length,
1757 extern __checkReturn efx_rc_t
1759 __inout_bcount(buffer_length) uint8_t *bufferp,
1760 __in size_t buffer_length,
1762 __in_bcount_opt(value_length) uint8_t *valuep,
1763 __in size_t value_length);
1765 extern __checkReturn efx_rc_t
1766 efx_dhcp_update_tag(
1767 __inout_bcount(buffer_length) uint8_t *bufferp,
1768 __in size_t buffer_length,
1770 __in uint8_t *value_locationp,
1771 __in_bcount_opt(value_length) uint8_t *valuep,
1772 __in size_t value_length);
1775 #endif /* EFSYS_OPT_BOOTCFG */
1777 #if EFSYS_OPT_IMAGE_LAYOUT
1779 #include "ef10_signed_image_layout.h"
1782 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1785 * The image header format is extensible. However, older drivers require an
1786 * exact match of image header version and header length when validating and
1787 * writing firmware images.
1789 * To avoid breaking backward compatibility, we use the upper bits of the
1790 * controller version fields to contain an extra version number used for
1791 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1792 * version). See bug39254 and SF-102785-PS for details.
1794 typedef struct efx_image_header_s {
1796 uint32_t eih_version;
1798 uint32_t eih_subtype;
1799 uint32_t eih_code_size;
1802 uint32_t eih_controller_version_min;
1804 uint16_t eih_controller_version_min_short;
1805 uint8_t eih_extra_version_a;
1806 uint8_t eih_extra_version_b;
1810 uint32_t eih_controller_version_max;
1812 uint16_t eih_controller_version_max_short;
1813 uint8_t eih_extra_version_c;
1814 uint8_t eih_extra_version_d;
1817 uint16_t eih_code_version_a;
1818 uint16_t eih_code_version_b;
1819 uint16_t eih_code_version_c;
1820 uint16_t eih_code_version_d;
1821 } efx_image_header_t;
1823 #define EFX_IMAGE_HEADER_SIZE (40)
1824 #define EFX_IMAGE_HEADER_VERSION (4)
1825 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1828 typedef struct efx_image_trailer_s {
1830 } efx_image_trailer_t;
1832 #define EFX_IMAGE_TRAILER_SIZE (4)
1834 typedef enum efx_image_format_e {
1835 EFX_IMAGE_FORMAT_NO_IMAGE,
1836 EFX_IMAGE_FORMAT_INVALID,
1837 EFX_IMAGE_FORMAT_UNSIGNED,
1838 EFX_IMAGE_FORMAT_SIGNED,
1839 } efx_image_format_t;
1841 typedef struct efx_image_info_s {
1842 efx_image_format_t eii_format;
1843 uint8_t * eii_imagep;
1844 size_t eii_image_size;
1845 efx_image_header_t * eii_headerp;
1848 extern __checkReturn efx_rc_t
1849 efx_check_reflash_image(
1851 __in uint32_t buffer_size,
1852 __out efx_image_info_t *infop);
1854 extern __checkReturn efx_rc_t
1855 efx_build_signed_image_write_buffer(
1856 __out_bcount(buffer_size)
1858 __in uint32_t buffer_size,
1859 __in efx_image_info_t *infop,
1860 __out efx_image_header_t **headerpp);
1862 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1866 typedef enum efx_pattern_type_t {
1867 EFX_PATTERN_BYTE_INCREMENT = 0,
1868 EFX_PATTERN_ALL_THE_SAME,
1869 EFX_PATTERN_BIT_ALTERNATE,
1870 EFX_PATTERN_BYTE_ALTERNATE,
1871 EFX_PATTERN_BYTE_CHANGING,
1872 EFX_PATTERN_BIT_SWEEP,
1874 } efx_pattern_type_t;
1877 (*efx_sram_pattern_fn_t)(
1879 __in boolean_t negate,
1880 __out efx_qword_t *eqp);
1882 extern __checkReturn efx_rc_t
1884 __in efx_nic_t *enp,
1885 __in efx_pattern_type_t type);
1887 #endif /* EFSYS_OPT_DIAG */
1889 extern __checkReturn efx_rc_t
1890 efx_sram_buf_tbl_set(
1891 __in efx_nic_t *enp,
1893 __in efsys_mem_t *esmp,
1897 efx_sram_buf_tbl_clear(
1898 __in efx_nic_t *enp,
1902 #define EFX_BUF_TBL_SIZE 0x20000
1904 #define EFX_BUF_SIZE 4096
1908 typedef struct efx_evq_s efx_evq_t;
1910 #if EFSYS_OPT_QSTATS
1912 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1913 typedef enum efx_ev_qstat_e {
1919 EV_RX_PAUSE_FRM_ERR,
1920 EV_RX_BUF_OWNER_ID_ERR,
1921 EV_RX_IPV4_HDR_CHKSUM_ERR,
1922 EV_RX_TCP_UDP_CHKSUM_ERR,
1926 EV_RX_MCAST_HASH_MATCH,
1943 EV_DRIVER_SRM_UPD_DONE,
1944 EV_DRIVER_TX_DESCQ_FLS_DONE,
1945 EV_DRIVER_RX_DESCQ_FLS_DONE,
1946 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1947 EV_DRIVER_RX_DSC_ERROR,
1948 EV_DRIVER_TX_DSC_ERROR,
1954 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1956 #endif /* EFSYS_OPT_QSTATS */
1958 extern __checkReturn efx_rc_t
1960 __in efx_nic_t *enp);
1964 __in efx_nic_t *enp);
1966 #define EFX_EVQ_MAXNEVS 32768
1967 #define EFX_EVQ_MINNEVS 512
1969 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1970 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1972 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1973 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1974 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1975 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1977 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1978 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1979 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1981 extern __checkReturn efx_rc_t
1983 __in efx_nic_t *enp,
1984 __in unsigned int index,
1985 __in efsys_mem_t *esmp,
1989 __in uint32_t flags,
1990 __deref_out efx_evq_t **eepp);
1994 __in efx_evq_t *eep,
1995 __in uint16_t data);
1997 typedef __checkReturn boolean_t
1998 (*efx_initialized_ev_t)(
1999 __in_opt void *arg);
2001 #define EFX_PKT_UNICAST 0x0004
2002 #define EFX_PKT_START 0x0008
2004 #define EFX_PKT_VLAN_TAGGED 0x0010
2005 #define EFX_CKSUM_TCPUDP 0x0020
2006 #define EFX_CKSUM_IPV4 0x0040
2007 #define EFX_PKT_CONT 0x0080
2009 #define EFX_CHECK_VLAN 0x0100
2010 #define EFX_PKT_TCP 0x0200
2011 #define EFX_PKT_UDP 0x0400
2012 #define EFX_PKT_IPV4 0x0800
2014 #define EFX_PKT_IPV6 0x1000
2015 #define EFX_PKT_PREFIX_LEN 0x2000
2016 #define EFX_ADDR_MISMATCH 0x4000
2017 #define EFX_DISCARD 0x8000
2020 * The following flags are used only for packed stream
2021 * mode. The values for the flags are reused to fit into 16 bit,
2022 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2023 * packed stream mode
2025 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2026 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2029 #define EFX_EV_RX_NLABELS 32
2030 #define EFX_EV_TX_NLABELS 32
2032 typedef __checkReturn boolean_t
2035 __in uint32_t label,
2038 __in uint16_t flags);
2040 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2043 * Packed stream mode is documented in SF-112241-TC.
2044 * The general idea is that, instead of putting each incoming
2045 * packet into a separate buffer which is specified in a RX
2046 * descriptor, a large buffer is provided to the hardware and
2047 * packets are put there in a continuous stream.
2048 * The main advantage of such an approach is that RX queue refilling
2049 * happens much less frequently.
2051 * Equal stride packed stream mode is documented in SF-119419-TC.
2052 * The general idea is to utilize advantages of the packed stream,
2053 * but avoid indirection in packets representation.
2054 * The main advantage of such an approach is that RX queue refilling
2055 * happens much less frequently and packets buffers are independent
2056 * from upper layers point of view.
2059 typedef __checkReturn boolean_t
2062 __in uint32_t label,
2064 __in uint32_t pkt_count,
2065 __in uint16_t flags);
2069 typedef __checkReturn boolean_t
2072 __in uint32_t label,
2075 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2076 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2077 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2078 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2079 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2080 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2081 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2082 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2083 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2085 typedef __checkReturn boolean_t
2086 (*efx_exception_ev_t)(
2088 __in uint32_t label,
2089 __in uint32_t data);
2091 typedef __checkReturn boolean_t
2092 (*efx_rxq_flush_done_ev_t)(
2094 __in uint32_t rxq_index);
2096 typedef __checkReturn boolean_t
2097 (*efx_rxq_flush_failed_ev_t)(
2099 __in uint32_t rxq_index);
2101 typedef __checkReturn boolean_t
2102 (*efx_txq_flush_done_ev_t)(
2104 __in uint32_t txq_index);
2106 typedef __checkReturn boolean_t
2107 (*efx_software_ev_t)(
2109 __in uint16_t magic);
2111 typedef __checkReturn boolean_t
2114 __in uint32_t code);
2116 #define EFX_SRAM_CLEAR 0
2117 #define EFX_SRAM_UPDATE 1
2118 #define EFX_SRAM_ILLEGAL_CLEAR 2
2120 typedef __checkReturn boolean_t
2121 (*efx_wake_up_ev_t)(
2123 __in uint32_t label);
2125 typedef __checkReturn boolean_t
2128 __in uint32_t label);
2130 typedef __checkReturn boolean_t
2131 (*efx_link_change_ev_t)(
2133 __in efx_link_mode_t link_mode);
2135 #if EFSYS_OPT_MON_STATS
2137 typedef __checkReturn boolean_t
2138 (*efx_monitor_ev_t)(
2140 __in efx_mon_stat_t id,
2141 __in efx_mon_stat_value_t value);
2143 #endif /* EFSYS_OPT_MON_STATS */
2145 #if EFSYS_OPT_MAC_STATS
2147 typedef __checkReturn boolean_t
2148 (*efx_mac_stats_ev_t)(
2150 __in uint32_t generation);
2152 #endif /* EFSYS_OPT_MAC_STATS */
2154 typedef struct efx_ev_callbacks_s {
2155 efx_initialized_ev_t eec_initialized;
2157 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2158 efx_rx_ps_ev_t eec_rx_ps;
2161 efx_exception_ev_t eec_exception;
2162 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2163 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2164 efx_txq_flush_done_ev_t eec_txq_flush_done;
2165 efx_software_ev_t eec_software;
2166 efx_sram_ev_t eec_sram;
2167 efx_wake_up_ev_t eec_wake_up;
2168 efx_timer_ev_t eec_timer;
2169 efx_link_change_ev_t eec_link_change;
2170 #if EFSYS_OPT_MON_STATS
2171 efx_monitor_ev_t eec_monitor;
2172 #endif /* EFSYS_OPT_MON_STATS */
2173 #if EFSYS_OPT_MAC_STATS
2174 efx_mac_stats_ev_t eec_mac_stats;
2175 #endif /* EFSYS_OPT_MAC_STATS */
2176 } efx_ev_callbacks_t;
2178 extern __checkReturn boolean_t
2180 __in efx_evq_t *eep,
2181 __in unsigned int count);
2183 #if EFSYS_OPT_EV_PREFETCH
2187 __in efx_evq_t *eep,
2188 __in unsigned int count);
2190 #endif /* EFSYS_OPT_EV_PREFETCH */
2194 __in efx_evq_t *eep,
2195 __inout unsigned int *countp,
2196 __in const efx_ev_callbacks_t *eecp,
2197 __in_opt void *arg);
2199 extern __checkReturn efx_rc_t
2200 efx_ev_usecs_to_ticks(
2201 __in efx_nic_t *enp,
2202 __in unsigned int usecs,
2203 __out unsigned int *ticksp);
2205 extern __checkReturn efx_rc_t
2207 __in efx_evq_t *eep,
2208 __in unsigned int us);
2210 extern __checkReturn efx_rc_t
2212 __in efx_evq_t *eep,
2213 __in unsigned int count);
2215 #if EFSYS_OPT_QSTATS
2221 __in efx_nic_t *enp,
2222 __in unsigned int id);
2224 #endif /* EFSYS_OPT_NAMES */
2227 efx_ev_qstats_update(
2228 __in efx_evq_t *eep,
2229 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2231 #endif /* EFSYS_OPT_QSTATS */
2235 __in efx_evq_t *eep);
2239 extern __checkReturn efx_rc_t
2241 __inout efx_nic_t *enp);
2245 __in efx_nic_t *enp);
2247 #if EFSYS_OPT_RX_SCATTER
2248 __checkReturn efx_rc_t
2249 efx_rx_scatter_enable(
2250 __in efx_nic_t *enp,
2251 __in unsigned int buf_size);
2252 #endif /* EFSYS_OPT_RX_SCATTER */
2254 /* Handle to represent use of the default RSS context. */
2255 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2257 #if EFSYS_OPT_RX_SCALE
2259 typedef enum efx_rx_hash_alg_e {
2260 EFX_RX_HASHALG_LFSR = 0,
2261 EFX_RX_HASHALG_TOEPLITZ,
2262 EFX_RX_HASHALG_PACKED_STREAM,
2264 } efx_rx_hash_alg_t;
2267 * Legacy hash type flags.
2269 * They represent standard tuples for distinct traffic classes.
2271 #define EFX_RX_HASH_IPV4 (1U << 0)
2272 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2273 #define EFX_RX_HASH_IPV6 (1U << 2)
2274 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2276 #define EFX_RX_HASH_LEGACY_MASK \
2277 (EFX_RX_HASH_IPV4 | \
2278 EFX_RX_HASH_TCPIPV4 | \
2279 EFX_RX_HASH_IPV6 | \
2280 EFX_RX_HASH_TCPIPV6)
2283 * The type of the argument used by efx_rx_scale_mode_set() to
2284 * provide a means for the client drivers to configure hashing.
2286 * A properly constructed value can either be:
2287 * - a combination of legacy flags
2288 * - a combination of EFX_RX_HASH() flags
2290 typedef unsigned int efx_rx_hash_type_t;
2292 typedef enum efx_rx_hash_support_e {
2293 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2294 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2295 } efx_rx_hash_support_t;
2297 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2298 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2299 #define EFX_MAXRSS 64 /* RX indirection entry range */
2300 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2302 typedef enum efx_rx_scale_context_type_e {
2303 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2304 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2305 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2306 } efx_rx_scale_context_type_t;
2309 * Traffic classes eligible for hash computation.
2311 * Select packet headers used in computing the receive hash.
2312 * This uses the same encoding as the RSS_MODES field of
2313 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2315 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2316 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2317 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2318 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2319 #define EFX_RX_CLASS_IPV4_LBN 16
2320 #define EFX_RX_CLASS_IPV4_WIDTH 4
2321 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2322 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2323 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2324 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2325 #define EFX_RX_CLASS_IPV6_LBN 28
2326 #define EFX_RX_CLASS_IPV6_WIDTH 4
2328 #define EFX_RX_NCLASSES 6
2331 * Ancillary flags used to construct generic hash tuples.
2332 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2334 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2335 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2336 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2337 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2340 * Generic hash tuples.
2342 * They express combinations of packet fields
2343 * which can contribute to the hash value for
2344 * a particular traffic class.
2346 #define EFX_RX_CLASS_HASH_DISABLE 0
2348 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2349 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2351 #define EFX_RX_CLASS_HASH_2TUPLE \
2352 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2353 EFX_RX_CLASS_HASH_DST_ADDR)
2355 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2356 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2357 EFX_RX_CLASS_HASH_SRC_PORT)
2359 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2360 (EFX_RX_CLASS_HASH_DST_ADDR | \
2361 EFX_RX_CLASS_HASH_DST_PORT)
2363 #define EFX_RX_CLASS_HASH_4TUPLE \
2364 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2365 EFX_RX_CLASS_HASH_DST_ADDR | \
2366 EFX_RX_CLASS_HASH_SRC_PORT | \
2367 EFX_RX_CLASS_HASH_DST_PORT)
2369 #define EFX_RX_CLASS_HASH_NTUPLES 7
2372 * Hash flag constructor.
2374 * Resulting flags encode hash tuples for specific traffic classes.
2375 * The client drivers are encouraged to use these flags to form
2376 * a hash type value.
2378 #define EFX_RX_HASH(_class, _tuple) \
2379 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2380 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2383 * The maximum number of EFX_RX_HASH() flags.
2385 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2387 extern __checkReturn efx_rc_t
2388 efx_rx_scale_hash_flags_get(
2389 __in efx_nic_t *enp,
2390 __in efx_rx_hash_alg_t hash_alg,
2391 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flagsp,
2392 __out unsigned int *nflagsp);
2394 extern __checkReturn efx_rc_t
2395 efx_rx_hash_default_support_get(
2396 __in efx_nic_t *enp,
2397 __out efx_rx_hash_support_t *supportp);
2400 extern __checkReturn efx_rc_t
2401 efx_rx_scale_default_support_get(
2402 __in efx_nic_t *enp,
2403 __out efx_rx_scale_context_type_t *typep);
2405 extern __checkReturn efx_rc_t
2406 efx_rx_scale_context_alloc(
2407 __in efx_nic_t *enp,
2408 __in efx_rx_scale_context_type_t type,
2409 __in uint32_t num_queues,
2410 __out uint32_t *rss_contextp);
2412 extern __checkReturn efx_rc_t
2413 efx_rx_scale_context_free(
2414 __in efx_nic_t *enp,
2415 __in uint32_t rss_context);
2417 extern __checkReturn efx_rc_t
2418 efx_rx_scale_mode_set(
2419 __in efx_nic_t *enp,
2420 __in uint32_t rss_context,
2421 __in efx_rx_hash_alg_t alg,
2422 __in efx_rx_hash_type_t type,
2423 __in boolean_t insert);
2425 extern __checkReturn efx_rc_t
2426 efx_rx_scale_tbl_set(
2427 __in efx_nic_t *enp,
2428 __in uint32_t rss_context,
2429 __in_ecount(n) unsigned int *table,
2432 extern __checkReturn efx_rc_t
2433 efx_rx_scale_key_set(
2434 __in efx_nic_t *enp,
2435 __in uint32_t rss_context,
2436 __in_ecount(n) uint8_t *key,
2439 extern __checkReturn uint32_t
2440 efx_pseudo_hdr_hash_get(
2441 __in efx_rxq_t *erp,
2442 __in efx_rx_hash_alg_t func,
2443 __in uint8_t *buffer);
2445 #endif /* EFSYS_OPT_RX_SCALE */
2447 extern __checkReturn efx_rc_t
2448 efx_pseudo_hdr_pkt_length_get(
2449 __in efx_rxq_t *erp,
2450 __in uint8_t *buffer,
2451 __out uint16_t *pkt_lengthp);
2453 #define EFX_RXQ_MAXNDESCS 4096
2454 #define EFX_RXQ_MINNDESCS 512
2456 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2457 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2458 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2459 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2461 typedef enum efx_rxq_type_e {
2462 EFX_RXQ_TYPE_DEFAULT,
2463 EFX_RXQ_TYPE_PACKED_STREAM,
2464 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2469 * Dummy flag to be used instead of 0 to make it clear that the argument
2470 * is receive queue flags.
2472 #define EFX_RXQ_FLAG_NONE 0x0
2473 #define EFX_RXQ_FLAG_SCATTER 0x1
2475 * If tunnels are supported and Rx event can provide information about
2476 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2477 * full-feature firmware variant running), outer classes are requested by
2478 * default. However, if the driver supports tunnels, the flag allows to
2479 * request inner classes which are required to be able to interpret inner
2480 * Rx checksum offload results.
2482 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2484 extern __checkReturn efx_rc_t
2486 __in efx_nic_t *enp,
2487 __in unsigned int index,
2488 __in unsigned int label,
2489 __in efx_rxq_type_t type,
2490 __in efsys_mem_t *esmp,
2493 __in unsigned int flags,
2494 __in efx_evq_t *eep,
2495 __deref_out efx_rxq_t **erpp);
2497 #if EFSYS_OPT_RX_PACKED_STREAM
2499 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2500 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2501 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2502 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2503 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2505 extern __checkReturn efx_rc_t
2506 efx_rx_qcreate_packed_stream(
2507 __in efx_nic_t *enp,
2508 __in unsigned int index,
2509 __in unsigned int label,
2510 __in uint32_t ps_buf_size,
2511 __in efsys_mem_t *esmp,
2513 __in efx_evq_t *eep,
2514 __deref_out efx_rxq_t **erpp);
2518 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2520 /* Maximum head-of-line block timeout in nanoseconds */
2521 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2523 extern __checkReturn efx_rc_t
2524 efx_rx_qcreate_es_super_buffer(
2525 __in efx_nic_t *enp,
2526 __in unsigned int index,
2527 __in unsigned int label,
2528 __in uint32_t n_bufs_per_desc,
2529 __in uint32_t max_dma_len,
2530 __in uint32_t buf_stride,
2531 __in uint32_t hol_block_timeout,
2532 __in efsys_mem_t *esmp,
2534 __in unsigned int flags,
2535 __in efx_evq_t *eep,
2536 __deref_out efx_rxq_t **erpp);
2540 typedef struct efx_buffer_s {
2541 efsys_dma_addr_t eb_addr;
2546 typedef struct efx_desc_s {
2552 __in efx_rxq_t *erp,
2553 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2555 __in unsigned int ndescs,
2556 __in unsigned int completed,
2557 __in unsigned int added);
2561 __in efx_rxq_t *erp,
2562 __in unsigned int added,
2563 __inout unsigned int *pushedp);
2565 #if EFSYS_OPT_RX_PACKED_STREAM
2568 efx_rx_qpush_ps_credits(
2569 __in efx_rxq_t *erp);
2571 extern __checkReturn uint8_t *
2572 efx_rx_qps_packet_info(
2573 __in efx_rxq_t *erp,
2574 __in uint8_t *buffer,
2575 __in uint32_t buffer_length,
2576 __in uint32_t current_offset,
2577 __out uint16_t *lengthp,
2578 __out uint32_t *next_offsetp,
2579 __out uint32_t *timestamp);
2582 extern __checkReturn efx_rc_t
2584 __in efx_rxq_t *erp);
2588 __in efx_rxq_t *erp);
2592 __in efx_rxq_t *erp);
2596 typedef struct efx_txq_s efx_txq_t;
2598 #if EFSYS_OPT_QSTATS
2600 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2601 typedef enum efx_tx_qstat_e {
2607 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2609 #endif /* EFSYS_OPT_QSTATS */
2611 extern __checkReturn efx_rc_t
2613 __in efx_nic_t *enp);
2617 __in efx_nic_t *enp);
2619 #define EFX_TXQ_MINNDESCS 512
2621 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2622 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2623 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2625 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2627 #define EFX_TXQ_CKSUM_IPV4 0x0001
2628 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2629 #define EFX_TXQ_FATSOV2 0x0004
2630 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2631 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2633 extern __checkReturn efx_rc_t
2635 __in efx_nic_t *enp,
2636 __in unsigned int index,
2637 __in unsigned int label,
2638 __in efsys_mem_t *esmp,
2641 __in uint16_t flags,
2642 __in efx_evq_t *eep,
2643 __deref_out efx_txq_t **etpp,
2644 __out unsigned int *addedp);
2646 extern __checkReturn efx_rc_t
2648 __in efx_txq_t *etp,
2649 __in_ecount(ndescs) efx_buffer_t *eb,
2650 __in unsigned int ndescs,
2651 __in unsigned int completed,
2652 __inout unsigned int *addedp);
2654 extern __checkReturn efx_rc_t
2656 __in efx_txq_t *etp,
2657 __in unsigned int ns);
2661 __in efx_txq_t *etp,
2662 __in unsigned int added,
2663 __in unsigned int pushed);
2665 extern __checkReturn efx_rc_t
2667 __in efx_txq_t *etp);
2671 __in efx_txq_t *etp);
2673 extern __checkReturn efx_rc_t
2675 __in efx_txq_t *etp);
2678 efx_tx_qpio_disable(
2679 __in efx_txq_t *etp);
2681 extern __checkReturn efx_rc_t
2683 __in efx_txq_t *etp,
2684 __in_ecount(buf_length) uint8_t *buffer,
2685 __in size_t buf_length,
2686 __in size_t pio_buf_offset);
2688 extern __checkReturn efx_rc_t
2690 __in efx_txq_t *etp,
2691 __in size_t pkt_length,
2692 __in unsigned int completed,
2693 __inout unsigned int *addedp);
2695 extern __checkReturn efx_rc_t
2697 __in efx_txq_t *etp,
2698 __in_ecount(n) efx_desc_t *ed,
2699 __in unsigned int n,
2700 __in unsigned int completed,
2701 __inout unsigned int *addedp);
2704 efx_tx_qdesc_dma_create(
2705 __in efx_txq_t *etp,
2706 __in efsys_dma_addr_t addr,
2709 __out efx_desc_t *edp);
2712 efx_tx_qdesc_tso_create(
2713 __in efx_txq_t *etp,
2714 __in uint16_t ipv4_id,
2715 __in uint32_t tcp_seq,
2716 __in uint8_t tcp_flags,
2717 __out efx_desc_t *edp);
2719 /* Number of FATSOv2 option descriptors */
2720 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2722 /* Maximum number of DMA segments per TSO packet (not superframe) */
2723 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2726 efx_tx_qdesc_tso2_create(
2727 __in efx_txq_t *etp,
2728 __in uint16_t ipv4_id,
2729 __in uint16_t outer_ipv4_id,
2730 __in uint32_t tcp_seq,
2731 __in uint16_t tcp_mss,
2732 __out_ecount(count) efx_desc_t *edp,
2736 efx_tx_qdesc_vlantci_create(
2737 __in efx_txq_t *etp,
2739 __out efx_desc_t *edp);
2742 efx_tx_qdesc_checksum_create(
2743 __in efx_txq_t *etp,
2744 __in uint16_t flags,
2745 __out efx_desc_t *edp);
2747 #if EFSYS_OPT_QSTATS
2753 __in efx_nic_t *etp,
2754 __in unsigned int id);
2756 #endif /* EFSYS_OPT_NAMES */
2759 efx_tx_qstats_update(
2760 __in efx_txq_t *etp,
2761 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2763 #endif /* EFSYS_OPT_QSTATS */
2767 __in efx_txq_t *etp);
2772 #if EFSYS_OPT_FILTER
2774 #define EFX_ETHER_TYPE_IPV4 0x0800
2775 #define EFX_ETHER_TYPE_IPV6 0x86DD
2777 #define EFX_IPPROTO_TCP 6
2778 #define EFX_IPPROTO_UDP 17
2779 #define EFX_IPPROTO_GRE 47
2781 /* Use RSS to spread across multiple queues */
2782 #define EFX_FILTER_FLAG_RX_RSS 0x01
2783 /* Enable RX scatter */
2784 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2786 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2787 * May only be set by the filter implementation for each type.
2788 * A removal request will restore the automatic filter in its place.
2790 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2791 /* Filter is for RX */
2792 #define EFX_FILTER_FLAG_RX 0x08
2793 /* Filter is for TX */
2794 #define EFX_FILTER_FLAG_TX 0x10
2795 /* Set match flag on the received packet */
2796 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2797 /* Set match mark on the received packet */
2798 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2800 typedef uint8_t efx_filter_flags_t;
2803 * Flags which specify the fields to match on. The values are the same as in the
2804 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2807 /* Match by remote IP host address */
2808 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2809 /* Match by local IP host address */
2810 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2811 /* Match by remote MAC address */
2812 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2813 /* Match by remote TCP/UDP port */
2814 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2815 /* Match by remote TCP/UDP port */
2816 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2817 /* Match by local TCP/UDP port */
2818 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2819 /* Match by Ether-type */
2820 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2821 /* Match by inner VLAN ID */
2822 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2823 /* Match by outer VLAN ID */
2824 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2825 /* Match by IP transport protocol */
2826 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2827 /* Match by VNI or VSID */
2828 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2829 /* For encapsulated packets, match by inner frame local MAC address */
2830 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2831 /* For encapsulated packets, match all multicast inner frames */
2832 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2833 /* For encapsulated packets, match all unicast inner frames */
2834 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2836 * Match by encap type, this flag does not correspond to
2837 * the MCDI match flags and any unoccupied value may be used
2839 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2840 /* Match otherwise-unmatched multicast and broadcast packets */
2841 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2842 /* Match otherwise-unmatched unicast packets */
2843 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2845 typedef uint32_t efx_filter_match_flags_t;
2847 typedef enum efx_filter_priority_s {
2848 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2849 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2850 * address list or hardware
2851 * requirements. This may only be used
2852 * by the filter implementation for
2854 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2855 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2856 * client (e.g. SR-IOV, HyperV VMQ etc.)
2858 } efx_filter_priority_t;
2861 * FIXME: All these fields are assumed to be in little-endian byte order.
2862 * It may be better for some to be big-endian. See bug42804.
2865 typedef struct efx_filter_spec_s {
2866 efx_filter_match_flags_t efs_match_flags;
2867 uint8_t efs_priority;
2868 efx_filter_flags_t efs_flags;
2869 uint16_t efs_dmaq_id;
2870 uint32_t efs_rss_context;
2872 /* Fields below here are hashed for software filter lookup */
2873 uint16_t efs_outer_vid;
2874 uint16_t efs_inner_vid;
2875 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2876 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2877 uint16_t efs_ether_type;
2878 uint8_t efs_ip_proto;
2879 efx_tunnel_protocol_t efs_encap_type;
2880 uint16_t efs_loc_port;
2881 uint16_t efs_rem_port;
2882 efx_oword_t efs_rem_host;
2883 efx_oword_t efs_loc_host;
2884 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2885 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2886 } efx_filter_spec_t;
2889 /* Default values for use in filter specifications */
2890 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2891 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2893 extern __checkReturn efx_rc_t
2895 __in efx_nic_t *enp);
2899 __in efx_nic_t *enp);
2901 extern __checkReturn efx_rc_t
2903 __in efx_nic_t *enp,
2904 __inout efx_filter_spec_t *spec);
2906 extern __checkReturn efx_rc_t
2908 __in efx_nic_t *enp,
2909 __inout efx_filter_spec_t *spec);
2911 extern __checkReturn efx_rc_t
2913 __in efx_nic_t *enp);
2915 extern __checkReturn efx_rc_t
2916 efx_filter_supported_filters(
2917 __in efx_nic_t *enp,
2918 __out_ecount(buffer_length) uint32_t *buffer,
2919 __in size_t buffer_length,
2920 __out size_t *list_lengthp);
2923 efx_filter_spec_init_rx(
2924 __out efx_filter_spec_t *spec,
2925 __in efx_filter_priority_t priority,
2926 __in efx_filter_flags_t flags,
2927 __in efx_rxq_t *erp);
2930 efx_filter_spec_init_tx(
2931 __out efx_filter_spec_t *spec,
2932 __in efx_txq_t *etp);
2934 extern __checkReturn efx_rc_t
2935 efx_filter_spec_set_ipv4_local(
2936 __inout efx_filter_spec_t *spec,
2939 __in uint16_t port);
2941 extern __checkReturn efx_rc_t
2942 efx_filter_spec_set_ipv4_full(
2943 __inout efx_filter_spec_t *spec,
2945 __in uint32_t lhost,
2946 __in uint16_t lport,
2947 __in uint32_t rhost,
2948 __in uint16_t rport);
2950 extern __checkReturn efx_rc_t
2951 efx_filter_spec_set_eth_local(
2952 __inout efx_filter_spec_t *spec,
2954 __in const uint8_t *addr);
2957 efx_filter_spec_set_ether_type(
2958 __inout efx_filter_spec_t *spec,
2959 __in uint16_t ether_type);
2961 extern __checkReturn efx_rc_t
2962 efx_filter_spec_set_uc_def(
2963 __inout efx_filter_spec_t *spec);
2965 extern __checkReturn efx_rc_t
2966 efx_filter_spec_set_mc_def(
2967 __inout efx_filter_spec_t *spec);
2969 typedef enum efx_filter_inner_frame_match_e {
2970 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2971 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2972 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2973 } efx_filter_inner_frame_match_t;
2975 extern __checkReturn efx_rc_t
2976 efx_filter_spec_set_encap_type(
2977 __inout efx_filter_spec_t *spec,
2978 __in efx_tunnel_protocol_t encap_type,
2979 __in efx_filter_inner_frame_match_t inner_frame_match);
2981 extern __checkReturn efx_rc_t
2982 efx_filter_spec_set_vxlan_full(
2983 __inout efx_filter_spec_t *spec,
2984 __in const uint8_t *vxlan_id,
2985 __in const uint8_t *inner_addr,
2986 __in const uint8_t *outer_addr);
2988 #if EFSYS_OPT_RX_SCALE
2989 extern __checkReturn efx_rc_t
2990 efx_filter_spec_set_rss_context(
2991 __inout efx_filter_spec_t *spec,
2992 __in uint32_t rss_context);
2994 #endif /* EFSYS_OPT_FILTER */
2998 extern __checkReturn uint32_t
3000 __in_ecount(count) uint32_t const *input,
3002 __in uint32_t init);
3004 extern __checkReturn uint32_t
3006 __in_ecount(length) uint8_t const *input,
3008 __in uint32_t init);
3010 #if EFSYS_OPT_LICENSING
3014 typedef struct efx_key_stats_s {
3016 uint32_t eks_invalid;
3017 uint32_t eks_blacklisted;
3018 uint32_t eks_unverifiable;
3019 uint32_t eks_wrong_node;
3020 uint32_t eks_licensed_apps_lo;
3021 uint32_t eks_licensed_apps_hi;
3022 uint32_t eks_licensed_features_lo;
3023 uint32_t eks_licensed_features_hi;
3026 extern __checkReturn efx_rc_t
3028 __in efx_nic_t *enp);
3032 __in efx_nic_t *enp);
3034 extern __checkReturn boolean_t
3035 efx_lic_check_support(
3036 __in efx_nic_t *enp);
3038 extern __checkReturn efx_rc_t
3039 efx_lic_update_licenses(
3040 __in efx_nic_t *enp);
3042 extern __checkReturn efx_rc_t
3043 efx_lic_get_key_stats(
3044 __in efx_nic_t *enp,
3045 __out efx_key_stats_t *ksp);
3047 extern __checkReturn efx_rc_t
3049 __in efx_nic_t *enp,
3050 __in uint64_t app_id,
3051 __out boolean_t *licensedp);
3053 extern __checkReturn efx_rc_t
3055 __in efx_nic_t *enp,
3056 __in size_t buffer_size,
3057 __out uint32_t *typep,
3058 __out size_t *lengthp,
3059 __out_opt uint8_t *bufferp);
3062 extern __checkReturn efx_rc_t
3064 __in efx_nic_t *enp,
3065 __in_bcount(buffer_size)
3067 __in size_t buffer_size,
3068 __out uint32_t *startp);
3070 extern __checkReturn efx_rc_t
3072 __in efx_nic_t *enp,
3073 __in_bcount(buffer_size)
3075 __in size_t buffer_size,
3076 __in uint32_t offset,
3077 __out uint32_t *endp);
3079 extern __checkReturn __success(return != B_FALSE) boolean_t
3081 __in efx_nic_t *enp,
3082 __in_bcount(buffer_size)
3084 __in size_t buffer_size,
3085 __in uint32_t offset,
3086 __out uint32_t *startp,
3087 __out uint32_t *lengthp);
3089 extern __checkReturn __success(return != B_FALSE) boolean_t
3090 efx_lic_validate_key(
3091 __in efx_nic_t *enp,
3092 __in_bcount(length) caddr_t keyp,
3093 __in uint32_t length);
3095 extern __checkReturn efx_rc_t
3097 __in efx_nic_t *enp,
3098 __in_bcount(buffer_size)
3100 __in size_t buffer_size,
3101 __in uint32_t offset,
3102 __in uint32_t length,
3103 __out_bcount_part(key_max_size, *lengthp)
3105 __in size_t key_max_size,
3106 __out uint32_t *lengthp);
3108 extern __checkReturn efx_rc_t
3110 __in efx_nic_t *enp,
3111 __in_bcount(buffer_size)
3113 __in size_t buffer_size,
3114 __in uint32_t offset,
3115 __in_bcount(length) caddr_t keyp,
3116 __in uint32_t length,
3117 __out uint32_t *lengthp);
3119 __checkReturn efx_rc_t
3121 __in efx_nic_t *enp,
3122 __in_bcount(buffer_size)
3124 __in size_t buffer_size,
3125 __in uint32_t offset,
3126 __in uint32_t length,
3128 __out uint32_t *deltap);
3130 extern __checkReturn efx_rc_t
3131 efx_lic_create_partition(
3132 __in efx_nic_t *enp,
3133 __in_bcount(buffer_size)
3135 __in size_t buffer_size);
3137 extern __checkReturn efx_rc_t
3138 efx_lic_finish_partition(
3139 __in efx_nic_t *enp,
3140 __in_bcount(buffer_size)
3142 __in size_t buffer_size);
3144 #endif /* EFSYS_OPT_LICENSING */
3148 #if EFSYS_OPT_TUNNEL
3150 extern __checkReturn efx_rc_t
3152 __in efx_nic_t *enp);
3156 __in efx_nic_t *enp);
3159 * For overlay network encapsulation using UDP, the firmware needs to know
3160 * the configured UDP port for the overlay so it can decode encapsulated
3162 * The UDP port/protocol list is global.
3165 extern __checkReturn efx_rc_t
3166 efx_tunnel_config_udp_add(
3167 __in efx_nic_t *enp,
3168 __in uint16_t port /* host/cpu-endian */,
3169 __in efx_tunnel_protocol_t protocol);
3171 extern __checkReturn efx_rc_t
3172 efx_tunnel_config_udp_remove(
3173 __in efx_nic_t *enp,
3174 __in uint16_t port /* host/cpu-endian */,
3175 __in efx_tunnel_protocol_t protocol);
3178 efx_tunnel_config_clear(
3179 __in efx_nic_t *enp);
3182 * Apply tunnel UDP ports configuration to hardware.
3184 * EAGAIN is returned if hardware will be reset (datapath and management CPU
3187 extern __checkReturn efx_rc_t
3188 efx_tunnel_reconfigure(
3189 __in efx_nic_t *enp);
3191 #endif /* EFSYS_OPT_TUNNEL */
3193 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3196 * Firmware subvariant choice options.
3198 * It may be switched to no Tx checksum if attached drivers are either
3199 * preboot or firmware subvariant aware and no VIS are allocated.
3200 * If may be always switched to default explicitly using set request or
3201 * implicitly if unaware driver is attaching. If switching is done when
3202 * a driver is attached, it gets MC_REBOOT event and should recreate its
3205 * See SF-119419-TC DPDK Firmware Driver Interface and
3206 * SF-109306-TC EF10 for Driver Writers for details.
3208 typedef enum efx_nic_fw_subvariant_e {
3209 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3210 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3211 EFX_NIC_FW_SUBVARIANT_NTYPES
3212 } efx_nic_fw_subvariant_t;
3214 extern __checkReturn efx_rc_t
3215 efx_nic_get_fw_subvariant(
3216 __in efx_nic_t *enp,
3217 __out efx_nic_fw_subvariant_t *subvariantp);
3219 extern __checkReturn efx_rc_t
3220 efx_nic_set_fw_subvariant(
3221 __in efx_nic_t *enp,
3222 __in efx_nic_fw_subvariant_t subvariant);
3224 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3230 #endif /* _SYS_EFX_H */