2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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37 #include "efx_check.h"
38 #include "efx_phy_ids.h"
44 #define EFX_STATIC_ASSERT(_cond) \
45 ((void)sizeof(char[(_cond) ? 1 : -1]))
47 #define EFX_ARRAY_SIZE(_array) \
48 (sizeof(_array) / sizeof((_array)[0]))
50 #define EFX_FIELD_OFFSET(_type, _field) \
51 ((size_t) &(((_type *)0)->_field))
55 typedef __success(return == 0) int efx_rc_t;
60 typedef enum efx_family_e {
62 EFX_FAMILY_FALCON, /* Obsolete and not supported */
64 EFX_FAMILY_HUNTINGTON,
69 extern __checkReturn efx_rc_t
73 __out efx_family_t *efp);
76 #define EFX_PCI_VENID_SFC 0x1924
78 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
80 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
81 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
82 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
84 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
85 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
86 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
88 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
89 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
91 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
92 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
93 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 EFX_ERR_BUFID_DC_OOB,
115 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116 extern __checkReturn uint32_t
118 __in uint32_t crc_init,
119 __in_ecount(length) uint8_t const *input,
123 /* Type prototypes */
125 typedef struct efx_rxq_s efx_rxq_t;
129 typedef struct efx_nic_s efx_nic_t;
131 extern __checkReturn efx_rc_t
133 __in efx_family_t family,
134 __in efsys_identifier_t *esip,
135 __in efsys_bar_t *esbp,
136 __in efsys_lock_t *eslp,
137 __deref_out efx_nic_t **enpp);
139 extern __checkReturn efx_rc_t
141 __in efx_nic_t *enp);
143 extern __checkReturn efx_rc_t
145 __in efx_nic_t *enp);
147 extern __checkReturn efx_rc_t
149 __in efx_nic_t *enp);
153 extern __checkReturn efx_rc_t
154 efx_nic_register_test(
155 __in efx_nic_t *enp);
157 #endif /* EFSYS_OPT_DIAG */
161 __in efx_nic_t *enp);
165 __in efx_nic_t *enp);
169 __in efx_nic_t *enp);
171 #define EFX_PCIE_LINK_SPEED_GEN1 1
172 #define EFX_PCIE_LINK_SPEED_GEN2 2
173 #define EFX_PCIE_LINK_SPEED_GEN3 3
175 typedef enum efx_pcie_link_performance_e {
176 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
177 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
178 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
179 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
180 } efx_pcie_link_performance_t;
182 extern __checkReturn efx_rc_t
183 efx_nic_calculate_pcie_link_bandwidth(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out uint32_t *bandwidth_mbpsp);
188 extern __checkReturn efx_rc_t
189 efx_nic_check_pcie_link_speed(
191 __in uint32_t pcie_link_width,
192 __in uint32_t pcie_link_gen,
193 __out efx_pcie_link_performance_t *resultp);
197 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
198 /* Huntington and Medford require MCDIv2 commands */
199 #define WITH_MCDI_V2 1
202 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
204 typedef enum efx_mcdi_exception_e {
205 EFX_MCDI_EXCEPTION_MC_REBOOT,
206 EFX_MCDI_EXCEPTION_MC_BADASSERT,
207 } efx_mcdi_exception_t;
209 #if EFSYS_OPT_MCDI_LOGGING
210 typedef enum efx_log_msg_e {
212 EFX_LOG_MCDI_REQUEST,
213 EFX_LOG_MCDI_RESPONSE,
215 #endif /* EFSYS_OPT_MCDI_LOGGING */
217 typedef struct efx_mcdi_transport_s {
219 efsys_mem_t *emt_dma_mem;
220 void (*emt_execute)(void *, efx_mcdi_req_t *);
221 void (*emt_ev_cpl)(void *);
222 void (*emt_exception)(void *, efx_mcdi_exception_t);
223 #if EFSYS_OPT_MCDI_LOGGING
224 void (*emt_logger)(void *, efx_log_msg_t,
225 void *, size_t, void *, size_t);
226 #endif /* EFSYS_OPT_MCDI_LOGGING */
227 #if EFSYS_OPT_MCDI_PROXY_AUTH
228 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
229 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
230 } efx_mcdi_transport_t;
232 extern __checkReturn efx_rc_t
235 __in const efx_mcdi_transport_t *mtp);
237 extern __checkReturn efx_rc_t
239 __in efx_nic_t *enp);
243 __in efx_nic_t *enp);
246 efx_mcdi_get_timeout(
248 __in efx_mcdi_req_t *emrp,
249 __out uint32_t *usec_timeoutp);
252 efx_mcdi_request_start(
254 __in efx_mcdi_req_t *emrp,
255 __in boolean_t ev_cpl);
257 extern __checkReturn boolean_t
258 efx_mcdi_request_poll(
259 __in efx_nic_t *enp);
261 extern __checkReturn boolean_t
262 efx_mcdi_request_abort(
263 __in efx_nic_t *enp);
267 __in efx_nic_t *enp);
269 #endif /* EFSYS_OPT_MCDI */
273 #define EFX_NINTR_SIENA 1024
275 typedef enum efx_intr_type_e {
276 EFX_INTR_INVALID = 0,
282 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
284 extern __checkReturn efx_rc_t
287 __in efx_intr_type_t type,
288 __in efsys_mem_t *esmp);
292 __in efx_nic_t *enp);
296 __in efx_nic_t *enp);
299 efx_intr_disable_unlocked(
300 __in efx_nic_t *enp);
302 #define EFX_INTR_NEVQS 32
304 extern __checkReturn efx_rc_t
307 __in unsigned int level);
310 efx_intr_status_line(
312 __out boolean_t *fatalp,
313 __out uint32_t *maskp);
316 efx_intr_status_message(
318 __in unsigned int message,
319 __out boolean_t *fatalp);
323 __in efx_nic_t *enp);
327 __in efx_nic_t *enp);
331 #if EFSYS_OPT_MAC_STATS
333 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
334 typedef enum efx_mac_stat_e {
337 EFX_MAC_RX_UNICST_PKTS,
338 EFX_MAC_RX_MULTICST_PKTS,
339 EFX_MAC_RX_BRDCST_PKTS,
340 EFX_MAC_RX_PAUSE_PKTS,
341 EFX_MAC_RX_LE_64_PKTS,
342 EFX_MAC_RX_65_TO_127_PKTS,
343 EFX_MAC_RX_128_TO_255_PKTS,
344 EFX_MAC_RX_256_TO_511_PKTS,
345 EFX_MAC_RX_512_TO_1023_PKTS,
346 EFX_MAC_RX_1024_TO_15XX_PKTS,
347 EFX_MAC_RX_GE_15XX_PKTS,
349 EFX_MAC_RX_FCS_ERRORS,
350 EFX_MAC_RX_DROP_EVENTS,
351 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
352 EFX_MAC_RX_SYMBOL_ERRORS,
353 EFX_MAC_RX_ALIGN_ERRORS,
354 EFX_MAC_RX_INTERNAL_ERRORS,
355 EFX_MAC_RX_JABBER_PKTS,
356 EFX_MAC_RX_LANE0_CHAR_ERR,
357 EFX_MAC_RX_LANE1_CHAR_ERR,
358 EFX_MAC_RX_LANE2_CHAR_ERR,
359 EFX_MAC_RX_LANE3_CHAR_ERR,
360 EFX_MAC_RX_LANE0_DISP_ERR,
361 EFX_MAC_RX_LANE1_DISP_ERR,
362 EFX_MAC_RX_LANE2_DISP_ERR,
363 EFX_MAC_RX_LANE3_DISP_ERR,
364 EFX_MAC_RX_MATCH_FAULT,
365 EFX_MAC_RX_NODESC_DROP_CNT,
368 EFX_MAC_TX_UNICST_PKTS,
369 EFX_MAC_TX_MULTICST_PKTS,
370 EFX_MAC_TX_BRDCST_PKTS,
371 EFX_MAC_TX_PAUSE_PKTS,
372 EFX_MAC_TX_LE_64_PKTS,
373 EFX_MAC_TX_65_TO_127_PKTS,
374 EFX_MAC_TX_128_TO_255_PKTS,
375 EFX_MAC_TX_256_TO_511_PKTS,
376 EFX_MAC_TX_512_TO_1023_PKTS,
377 EFX_MAC_TX_1024_TO_15XX_PKTS,
378 EFX_MAC_TX_GE_15XX_PKTS,
380 EFX_MAC_TX_SGL_COL_PKTS,
381 EFX_MAC_TX_MULT_COL_PKTS,
382 EFX_MAC_TX_EX_COL_PKTS,
383 EFX_MAC_TX_LATE_COL_PKTS,
385 EFX_MAC_TX_EX_DEF_PKTS,
386 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
387 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
388 EFX_MAC_PM_TRUNC_VFIFO_FULL,
389 EFX_MAC_PM_DISCARD_VFIFO_FULL,
390 EFX_MAC_PM_TRUNC_QBB,
391 EFX_MAC_PM_DISCARD_QBB,
392 EFX_MAC_PM_DISCARD_MAPPING,
393 EFX_MAC_RXDP_Q_DISABLED_PKTS,
394 EFX_MAC_RXDP_DI_DROPPED_PKTS,
395 EFX_MAC_RXDP_STREAMING_PKTS,
396 EFX_MAC_RXDP_HLB_FETCH,
397 EFX_MAC_RXDP_HLB_WAIT,
398 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
399 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
400 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
401 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
402 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
403 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
404 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
405 EFX_MAC_VADAPTER_RX_BAD_BYTES,
406 EFX_MAC_VADAPTER_RX_OVERFLOW,
407 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
408 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
409 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
410 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
411 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
412 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
413 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
414 EFX_MAC_VADAPTER_TX_BAD_BYTES,
415 EFX_MAC_VADAPTER_TX_OVERFLOW,
419 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
421 #endif /* EFSYS_OPT_MAC_STATS */
423 typedef enum efx_link_mode_e {
424 EFX_LINK_UNKNOWN = 0,
437 #define EFX_MAC_ADDR_LEN 6
439 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
441 #define EFX_MAC_MULTICAST_LIST_MAX 256
443 #define EFX_MAC_SDU_MAX 9202
445 #define EFX_MAC_PDU_ADJUSTMENT \
449 + /* bug16011 */ 16) \
451 #define EFX_MAC_PDU(_sdu) \
452 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
455 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
456 * the SDU rounded up slightly.
458 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
460 #define EFX_MAC_PDU_MIN 60
461 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
463 extern __checkReturn efx_rc_t
468 extern __checkReturn efx_rc_t
473 extern __checkReturn efx_rc_t
478 extern __checkReturn efx_rc_t
481 __in boolean_t all_unicst,
482 __in boolean_t mulcst,
483 __in boolean_t all_mulcst,
484 __in boolean_t brdcst);
486 extern __checkReturn efx_rc_t
487 efx_mac_multicast_list_set(
489 __in_ecount(6*count) uint8_t const *addrs,
492 extern __checkReturn efx_rc_t
493 efx_mac_filter_default_rxq_set(
496 __in boolean_t using_rss);
499 efx_mac_filter_default_rxq_clear(
500 __in efx_nic_t *enp);
502 extern __checkReturn efx_rc_t
505 __in boolean_t enabled);
507 extern __checkReturn efx_rc_t
510 __out boolean_t *mac_upp);
512 #define EFX_FCNTL_RESPOND 0x00000001
513 #define EFX_FCNTL_GENERATE 0x00000002
515 extern __checkReturn efx_rc_t
518 __in unsigned int fcntl,
519 __in boolean_t autoneg);
524 __out unsigned int *fcntl_wantedp,
525 __out unsigned int *fcntl_linkp);
528 #if EFSYS_OPT_MAC_STATS
532 extern __checkReturn const char *
535 __in unsigned int id);
537 #endif /* EFSYS_OPT_NAMES */
539 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
541 #define EFX_MAC_STATS_MASK_NPAGES \
542 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
543 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
546 * Get mask of MAC statistics supported by the hardware.
548 * If mask_size is insufficient to return the mask, EINVAL error is
549 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
550 * (which is sizeof (uint32_t)) is sufficient.
552 extern __checkReturn efx_rc_t
553 efx_mac_stats_get_mask(
555 __out_bcount(mask_size) uint32_t *maskp,
556 __in size_t mask_size);
558 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
559 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
560 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
562 #define EFX_MAC_STATS_SIZE 0x400
565 * Upload mac statistics supported by the hardware into the given buffer.
567 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
570 * The hardware will only DMA statistics that it understands (of course).
571 * Drivers should not make any assumptions about which statistics are
572 * supported, especially when the statistics are generated by firmware.
574 * Thus, drivers should zero this buffer before use, so that not-understood
575 * statistics read back as zero.
577 extern __checkReturn efx_rc_t
578 efx_mac_stats_upload(
580 __in efsys_mem_t *esmp);
582 extern __checkReturn efx_rc_t
583 efx_mac_stats_periodic(
585 __in efsys_mem_t *esmp,
586 __in uint16_t period_ms,
587 __in boolean_t events);
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_update(
592 __in efsys_mem_t *esmp,
593 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
594 __inout_opt uint32_t *generationp);
596 #endif /* EFSYS_OPT_MAC_STATS */
600 typedef enum efx_mon_type_e {
612 __in efx_nic_t *enp);
614 #endif /* EFSYS_OPT_NAMES */
616 extern __checkReturn efx_rc_t
618 __in efx_nic_t *enp);
620 #if EFSYS_OPT_MON_STATS
622 #define EFX_MON_STATS_PAGE_SIZE 0x100
623 #define EFX_MON_MASK_ELEMENT_SIZE 32
625 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
626 typedef enum efx_mon_stat_e {
633 EFX_MON_STAT_EXT_TEMP,
634 EFX_MON_STAT_INT_TEMP,
637 EFX_MON_STAT_INT_COOLING,
638 EFX_MON_STAT_EXT_COOLING,
646 EFX_MON_STAT_AOE_TEMP,
647 EFX_MON_STAT_PSU_AOE_TEMP,
648 EFX_MON_STAT_PSU_TEMP,
654 EFX_MON_STAT_VAOE_IN,
656 EFX_MON_STAT_IAOE_IN,
657 EFX_MON_STAT_NIC_POWER,
661 EFX_MON_STAT_0_9V_ADC,
662 EFX_MON_STAT_INT_TEMP2,
663 EFX_MON_STAT_VREG_TEMP,
664 EFX_MON_STAT_VREG_0_9V_TEMP,
665 EFX_MON_STAT_VREG_1_2V_TEMP,
666 EFX_MON_STAT_INT_VPTAT,
667 EFX_MON_STAT_INT_ADC_TEMP,
668 EFX_MON_STAT_EXT_VPTAT,
669 EFX_MON_STAT_EXT_ADC_TEMP,
670 EFX_MON_STAT_AMBIENT_TEMP,
671 EFX_MON_STAT_AIRFLOW,
672 EFX_MON_STAT_VDD08D_VSS08D_CSR,
673 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
674 EFX_MON_STAT_HOTPOINT_TEMP,
675 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
676 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
677 EFX_MON_STAT_MUM_VCC,
680 EFX_MON_STAT_0V9_A_TEMP,
683 EFX_MON_STAT_0V9_B_TEMP,
684 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
685 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
686 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
687 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
688 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
689 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
690 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
691 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
692 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
693 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
694 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
695 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
696 EFX_MON_STAT_SODIMM_VOUT,
697 EFX_MON_STAT_SODIMM_0_TEMP,
698 EFX_MON_STAT_SODIMM_1_TEMP,
699 EFX_MON_STAT_PHY0_VCC,
700 EFX_MON_STAT_PHY1_VCC,
701 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
702 EFX_MON_STAT_BOARD_FRONT_TEMP,
703 EFX_MON_STAT_BOARD_BACK_TEMP,
707 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
709 typedef enum efx_mon_stat_state_e {
710 EFX_MON_STAT_STATE_OK = 0,
711 EFX_MON_STAT_STATE_WARNING = 1,
712 EFX_MON_STAT_STATE_FATAL = 2,
713 EFX_MON_STAT_STATE_BROKEN = 3,
714 EFX_MON_STAT_STATE_NO_READING = 4,
715 } efx_mon_stat_state_t;
717 typedef struct efx_mon_stat_value_s {
720 } efx_mon_stat_value_t;
727 __in efx_mon_stat_t id);
729 #endif /* EFSYS_OPT_NAMES */
731 extern __checkReturn efx_rc_t
732 efx_mon_stats_update(
734 __in efsys_mem_t *esmp,
735 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
737 #endif /* EFSYS_OPT_MON_STATS */
741 __in efx_nic_t *enp);
745 extern __checkReturn efx_rc_t
747 __in efx_nic_t *enp);
749 #if EFSYS_OPT_PHY_LED_CONTROL
751 typedef enum efx_phy_led_mode_e {
752 EFX_PHY_LED_DEFAULT = 0,
757 } efx_phy_led_mode_t;
759 extern __checkReturn efx_rc_t
762 __in efx_phy_led_mode_t mode);
764 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
766 extern __checkReturn efx_rc_t
768 __in efx_nic_t *enp);
770 #if EFSYS_OPT_LOOPBACK
772 typedef enum efx_loopback_type_e {
773 EFX_LOOPBACK_OFF = 0,
774 EFX_LOOPBACK_DATA = 1,
775 EFX_LOOPBACK_GMAC = 2,
776 EFX_LOOPBACK_XGMII = 3,
777 EFX_LOOPBACK_XGXS = 4,
778 EFX_LOOPBACK_XAUI = 5,
779 EFX_LOOPBACK_GMII = 6,
780 EFX_LOOPBACK_SGMII = 7,
781 EFX_LOOPBACK_XGBR = 8,
782 EFX_LOOPBACK_XFI = 9,
783 EFX_LOOPBACK_XAUI_FAR = 10,
784 EFX_LOOPBACK_GMII_FAR = 11,
785 EFX_LOOPBACK_SGMII_FAR = 12,
786 EFX_LOOPBACK_XFI_FAR = 13,
787 EFX_LOOPBACK_GPHY = 14,
788 EFX_LOOPBACK_PHY_XS = 15,
789 EFX_LOOPBACK_PCS = 16,
790 EFX_LOOPBACK_PMA_PMD = 17,
791 EFX_LOOPBACK_XPORT = 18,
792 EFX_LOOPBACK_XGMII_WS = 19,
793 EFX_LOOPBACK_XAUI_WS = 20,
794 EFX_LOOPBACK_XAUI_WS_FAR = 21,
795 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
796 EFX_LOOPBACK_GMII_WS = 23,
797 EFX_LOOPBACK_XFI_WS = 24,
798 EFX_LOOPBACK_XFI_WS_FAR = 25,
799 EFX_LOOPBACK_PHYXS_WS = 26,
800 EFX_LOOPBACK_PMA_INT = 27,
801 EFX_LOOPBACK_SD_NEAR = 28,
802 EFX_LOOPBACK_SD_FAR = 29,
803 EFX_LOOPBACK_PMA_INT_WS = 30,
804 EFX_LOOPBACK_SD_FEP2_WS = 31,
805 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
806 EFX_LOOPBACK_SD_FEP_WS = 33,
807 EFX_LOOPBACK_SD_FES_WS = 34,
809 } efx_loopback_type_t;
811 typedef enum efx_loopback_kind_e {
812 EFX_LOOPBACK_KIND_OFF = 0,
813 EFX_LOOPBACK_KIND_ALL,
814 EFX_LOOPBACK_KIND_MAC,
815 EFX_LOOPBACK_KIND_PHY,
817 } efx_loopback_kind_t;
821 __in efx_loopback_kind_t loopback_kind,
822 __out efx_qword_t *maskp);
824 extern __checkReturn efx_rc_t
825 efx_port_loopback_set(
827 __in efx_link_mode_t link_mode,
828 __in efx_loopback_type_t type);
832 extern __checkReturn const char *
833 efx_loopback_type_name(
835 __in efx_loopback_type_t type);
837 #endif /* EFSYS_OPT_NAMES */
839 #endif /* EFSYS_OPT_LOOPBACK */
841 extern __checkReturn efx_rc_t
844 __out_opt efx_link_mode_t *link_modep);
848 __in efx_nic_t *enp);
850 typedef enum efx_phy_cap_type_e {
851 EFX_PHY_CAP_INVALID = 0,
858 EFX_PHY_CAP_10000FDX,
862 EFX_PHY_CAP_40000FDX,
864 } efx_phy_cap_type_t;
867 #define EFX_PHY_CAP_CURRENT 0x00000000
868 #define EFX_PHY_CAP_DEFAULT 0x00000001
869 #define EFX_PHY_CAP_PERM 0x00000002
875 __out uint32_t *maskp);
877 extern __checkReturn efx_rc_t
885 __out uint32_t *maskp);
887 extern __checkReturn efx_rc_t
890 __out uint32_t *ouip);
892 typedef enum efx_phy_media_type_e {
893 EFX_PHY_MEDIA_INVALID = 0,
898 EFX_PHY_MEDIA_SFP_PLUS,
899 EFX_PHY_MEDIA_BASE_T,
900 EFX_PHY_MEDIA_QSFP_PLUS,
902 } efx_phy_media_type_t;
904 /* Get the type of medium currently used. If the board has ports for
905 * modules, a module is present, and we recognise the media type of
906 * the module, then this will be the media type of the module.
907 * Otherwise it will be the media type of the port.
910 efx_phy_media_type_get(
912 __out efx_phy_media_type_t *typep);
915 efx_phy_module_get_info(
917 __in uint8_t dev_addr,
920 __out_bcount(len) uint8_t *data);
922 #if EFSYS_OPT_PHY_STATS
924 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
925 typedef enum efx_phy_stat_e {
927 EFX_PHY_STAT_PMA_PMD_LINK_UP,
928 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
929 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
930 EFX_PHY_STAT_PMA_PMD_REV_A,
931 EFX_PHY_STAT_PMA_PMD_REV_B,
932 EFX_PHY_STAT_PMA_PMD_REV_C,
933 EFX_PHY_STAT_PMA_PMD_REV_D,
934 EFX_PHY_STAT_PCS_LINK_UP,
935 EFX_PHY_STAT_PCS_RX_FAULT,
936 EFX_PHY_STAT_PCS_TX_FAULT,
937 EFX_PHY_STAT_PCS_BER,
938 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
939 EFX_PHY_STAT_PHY_XS_LINK_UP,
940 EFX_PHY_STAT_PHY_XS_RX_FAULT,
941 EFX_PHY_STAT_PHY_XS_TX_FAULT,
942 EFX_PHY_STAT_PHY_XS_ALIGN,
943 EFX_PHY_STAT_PHY_XS_SYNC_A,
944 EFX_PHY_STAT_PHY_XS_SYNC_B,
945 EFX_PHY_STAT_PHY_XS_SYNC_C,
946 EFX_PHY_STAT_PHY_XS_SYNC_D,
947 EFX_PHY_STAT_AN_LINK_UP,
948 EFX_PHY_STAT_AN_MASTER,
949 EFX_PHY_STAT_AN_LOCAL_RX_OK,
950 EFX_PHY_STAT_AN_REMOTE_RX_OK,
951 EFX_PHY_STAT_CL22EXT_LINK_UP,
956 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
957 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
958 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
959 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
960 EFX_PHY_STAT_AN_COMPLETE,
961 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
962 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
963 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
964 EFX_PHY_STAT_PCS_FW_VERSION_0,
965 EFX_PHY_STAT_PCS_FW_VERSION_1,
966 EFX_PHY_STAT_PCS_FW_VERSION_2,
967 EFX_PHY_STAT_PCS_FW_VERSION_3,
968 EFX_PHY_STAT_PCS_FW_BUILD_YY,
969 EFX_PHY_STAT_PCS_FW_BUILD_MM,
970 EFX_PHY_STAT_PCS_FW_BUILD_DD,
971 EFX_PHY_STAT_PCS_OP_MODE,
975 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
982 __in efx_phy_stat_t stat);
984 #endif /* EFSYS_OPT_NAMES */
986 #define EFX_PHY_STATS_SIZE 0x100
988 extern __checkReturn efx_rc_t
989 efx_phy_stats_update(
991 __in efsys_mem_t *esmp,
992 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
994 #endif /* EFSYS_OPT_PHY_STATS */
999 typedef enum efx_bist_type_e {
1000 EFX_BIST_TYPE_UNKNOWN,
1001 EFX_BIST_TYPE_PHY_NORMAL,
1002 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1003 EFX_BIST_TYPE_PHY_CABLE_LONG,
1004 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1005 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1006 EFX_BIST_TYPE_REG, /* Test the register memories */
1007 EFX_BIST_TYPE_NTYPES,
1010 typedef enum efx_bist_result_e {
1011 EFX_BIST_RESULT_UNKNOWN,
1012 EFX_BIST_RESULT_RUNNING,
1013 EFX_BIST_RESULT_PASSED,
1014 EFX_BIST_RESULT_FAILED,
1015 } efx_bist_result_t;
1017 typedef enum efx_phy_cable_status_e {
1018 EFX_PHY_CABLE_STATUS_OK,
1019 EFX_PHY_CABLE_STATUS_INVALID,
1020 EFX_PHY_CABLE_STATUS_OPEN,
1021 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1022 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1023 EFX_PHY_CABLE_STATUS_BUSY,
1024 } efx_phy_cable_status_t;
1026 typedef enum efx_bist_value_e {
1027 EFX_BIST_PHY_CABLE_LENGTH_A,
1028 EFX_BIST_PHY_CABLE_LENGTH_B,
1029 EFX_BIST_PHY_CABLE_LENGTH_C,
1030 EFX_BIST_PHY_CABLE_LENGTH_D,
1031 EFX_BIST_PHY_CABLE_STATUS_A,
1032 EFX_BIST_PHY_CABLE_STATUS_B,
1033 EFX_BIST_PHY_CABLE_STATUS_C,
1034 EFX_BIST_PHY_CABLE_STATUS_D,
1035 EFX_BIST_FAULT_CODE,
1036 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1041 EFX_BIST_MEM_EXPECT,
1042 EFX_BIST_MEM_ACTUAL,
1044 EFX_BIST_MEM_ECC_PARITY,
1045 EFX_BIST_MEM_ECC_FATAL,
1049 extern __checkReturn efx_rc_t
1050 efx_bist_enable_offline(
1051 __in efx_nic_t *enp);
1053 extern __checkReturn efx_rc_t
1055 __in efx_nic_t *enp,
1056 __in efx_bist_type_t type);
1058 extern __checkReturn efx_rc_t
1060 __in efx_nic_t *enp,
1061 __in efx_bist_type_t type,
1062 __out efx_bist_result_t *resultp,
1063 __out_opt uint32_t *value_maskp,
1064 __out_ecount_opt(count) unsigned long *valuesp,
1069 __in efx_nic_t *enp,
1070 __in efx_bist_type_t type);
1072 #endif /* EFSYS_OPT_BIST */
1074 #define EFX_FEATURE_IPV6 0x00000001
1075 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1076 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1077 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1078 #define EFX_FEATURE_MCDI 0x00000020
1079 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1080 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1081 #define EFX_FEATURE_TURBO 0x00000100
1082 #define EFX_FEATURE_MCDI_DMA 0x00000200
1083 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1084 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1085 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1086 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1088 typedef struct efx_nic_cfg_s {
1089 uint32_t enc_board_type;
1090 uint32_t enc_phy_type;
1092 char enc_phy_name[21];
1094 char enc_phy_revision[21];
1095 efx_mon_type_t enc_mon_type;
1096 #if EFSYS_OPT_MON_STATS
1097 uint32_t enc_mon_stat_dma_buf_size;
1098 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1100 unsigned int enc_features;
1101 uint8_t enc_mac_addr[6];
1102 uint8_t enc_port; /* PHY port number */
1103 uint32_t enc_intr_vec_base;
1104 uint32_t enc_intr_limit;
1105 uint32_t enc_evq_limit;
1106 uint32_t enc_txq_limit;
1107 uint32_t enc_rxq_limit;
1108 uint32_t enc_buftbl_limit;
1109 uint32_t enc_piobuf_limit;
1110 uint32_t enc_piobuf_size;
1111 uint32_t enc_piobuf_min_alloc_size;
1112 uint32_t enc_evq_timer_quantum_ns;
1113 uint32_t enc_evq_timer_max_us;
1114 uint32_t enc_clk_mult;
1115 uint32_t enc_rx_prefix_size;
1116 uint32_t enc_rx_buf_align_start;
1117 uint32_t enc_rx_buf_align_end;
1118 #if EFSYS_OPT_LOOPBACK
1119 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1120 #endif /* EFSYS_OPT_LOOPBACK */
1121 #if EFSYS_OPT_PHY_FLAGS
1122 uint32_t enc_phy_flags_mask;
1123 #endif /* EFSYS_OPT_PHY_FLAGS */
1124 #if EFSYS_OPT_PHY_LED_CONTROL
1125 uint32_t enc_led_mask;
1126 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1127 #if EFSYS_OPT_PHY_STATS
1128 uint64_t enc_phy_stat_mask;
1129 #endif /* EFSYS_OPT_PHY_STATS */
1131 uint8_t enc_mcdi_mdio_channel;
1132 #if EFSYS_OPT_PHY_STATS
1133 uint32_t enc_mcdi_phy_stat_mask;
1134 #endif /* EFSYS_OPT_PHY_STATS */
1135 #if EFSYS_OPT_MON_STATS
1136 uint32_t *enc_mcdi_sensor_maskp;
1137 uint32_t enc_mcdi_sensor_mask_size;
1138 #endif /* EFSYS_OPT_MON_STATS */
1139 #endif /* EFSYS_OPT_MCDI */
1141 uint32_t enc_bist_mask;
1142 #endif /* EFSYS_OPT_BIST */
1143 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1146 uint32_t enc_privilege_mask;
1147 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1148 boolean_t enc_bug26807_workaround;
1149 boolean_t enc_bug35388_workaround;
1150 boolean_t enc_bug41750_workaround;
1151 boolean_t enc_bug61265_workaround;
1152 boolean_t enc_rx_batching_enabled;
1153 /* Maximum number of descriptors completed in an rx event. */
1154 uint32_t enc_rx_batch_max;
1155 /* Number of rx descriptors the hardware requires for a push. */
1156 uint32_t enc_rx_push_align;
1157 /* Maximum amount of data in DMA descriptor */
1158 uint32_t enc_tx_dma_desc_size_max;
1160 * Boundary which DMA descriptor data must not cross or 0 if no
1163 uint32_t enc_tx_dma_desc_boundary;
1165 * Maximum number of bytes into the packet the TCP header can start for
1166 * the hardware to apply TSO packet edits.
1168 uint32_t enc_tx_tso_tcp_header_offset_limit;
1169 boolean_t enc_fw_assisted_tso_enabled;
1170 boolean_t enc_fw_assisted_tso_v2_enabled;
1171 /* Number of TSO contexts on the NIC (FATSOv2) */
1172 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1173 boolean_t enc_hw_tx_insert_vlan_enabled;
1174 /* Number of PFs on the NIC */
1175 uint32_t enc_hw_pf_count;
1176 /* Datapath firmware vadapter/vport/vswitch support */
1177 boolean_t enc_datapath_cap_evb;
1178 boolean_t enc_rx_disable_scatter_supported;
1179 boolean_t enc_allow_set_mac_with_installed_filters;
1180 boolean_t enc_enhanced_set_mac_supported;
1181 boolean_t enc_init_evq_v2_supported;
1182 boolean_t enc_pm_and_rxdp_counters;
1183 boolean_t enc_mac_stats_40g_tx_size_bins;
1184 /* External port identifier */
1185 uint8_t enc_external_port;
1186 uint32_t enc_mcdi_max_payload_length;
1187 /* VPD may be per-PF or global */
1188 boolean_t enc_vpd_is_global;
1189 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1190 uint32_t enc_required_pcie_bandwidth_mbps;
1191 uint32_t enc_max_pcie_link_gen;
1192 /* Firmware verifies integrity of NVRAM updates */
1193 uint32_t enc_fw_verified_nvram_update_required;
1196 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1197 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1199 #define EFX_PCI_FUNCTION(_encp) \
1200 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1202 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1204 extern const efx_nic_cfg_t *
1206 __in efx_nic_t *enp);
1208 /* Driver resource limits (minimum required/maximum usable). */
1209 typedef struct efx_drv_limits_s {
1210 uint32_t edl_min_evq_count;
1211 uint32_t edl_max_evq_count;
1213 uint32_t edl_min_rxq_count;
1214 uint32_t edl_max_rxq_count;
1216 uint32_t edl_min_txq_count;
1217 uint32_t edl_max_txq_count;
1219 /* PIO blocks (sub-allocated from piobuf) */
1220 uint32_t edl_min_pio_alloc_size;
1221 uint32_t edl_max_pio_alloc_count;
1224 extern __checkReturn efx_rc_t
1225 efx_nic_set_drv_limits(
1226 __inout efx_nic_t *enp,
1227 __in efx_drv_limits_t *edlp);
1229 typedef enum efx_nic_region_e {
1230 EFX_REGION_VI, /* Memory BAR UC mapping */
1231 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1234 extern __checkReturn efx_rc_t
1235 efx_nic_get_bar_region(
1236 __in efx_nic_t *enp,
1237 __in efx_nic_region_t region,
1238 __out uint32_t *offsetp,
1239 __out size_t *sizep);
1241 extern __checkReturn efx_rc_t
1242 efx_nic_get_vi_pool(
1243 __in efx_nic_t *enp,
1244 __out uint32_t *evq_countp,
1245 __out uint32_t *rxq_countp,
1246 __out uint32_t *txq_countp);
1251 typedef enum efx_vpd_tag_e {
1258 typedef uint16_t efx_vpd_keyword_t;
1260 typedef struct efx_vpd_value_s {
1261 efx_vpd_tag_t evv_tag;
1262 efx_vpd_keyword_t evv_keyword;
1264 uint8_t evv_value[0x100];
1268 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1270 extern __checkReturn efx_rc_t
1272 __in efx_nic_t *enp);
1274 extern __checkReturn efx_rc_t
1276 __in efx_nic_t *enp,
1277 __out size_t *sizep);
1279 extern __checkReturn efx_rc_t
1281 __in efx_nic_t *enp,
1282 __out_bcount(size) caddr_t data,
1285 extern __checkReturn efx_rc_t
1287 __in efx_nic_t *enp,
1288 __in_bcount(size) caddr_t data,
1291 extern __checkReturn efx_rc_t
1293 __in efx_nic_t *enp,
1294 __in_bcount(size) caddr_t data,
1297 extern __checkReturn efx_rc_t
1299 __in efx_nic_t *enp,
1300 __in_bcount(size) caddr_t data,
1302 __inout efx_vpd_value_t *evvp);
1304 extern __checkReturn efx_rc_t
1306 __in efx_nic_t *enp,
1307 __inout_bcount(size) caddr_t data,
1309 __in efx_vpd_value_t *evvp);
1311 extern __checkReturn efx_rc_t
1313 __in efx_nic_t *enp,
1314 __inout_bcount(size) caddr_t data,
1316 __out efx_vpd_value_t *evvp,
1317 __inout unsigned int *contp);
1319 extern __checkReturn efx_rc_t
1321 __in efx_nic_t *enp,
1322 __in_bcount(size) caddr_t data,
1327 __in efx_nic_t *enp);
1329 #endif /* EFSYS_OPT_VPD */
1335 typedef enum efx_nvram_type_e {
1336 EFX_NVRAM_INVALID = 0,
1338 EFX_NVRAM_BOOTROM_CFG,
1339 EFX_NVRAM_MC_FIRMWARE,
1340 EFX_NVRAM_MC_GOLDEN,
1346 EFX_NVRAM_FPGA_BACKUP,
1347 EFX_NVRAM_DYNAMIC_CFG,
1353 extern __checkReturn efx_rc_t
1355 __in efx_nic_t *enp);
1359 extern __checkReturn efx_rc_t
1361 __in efx_nic_t *enp);
1363 #endif /* EFSYS_OPT_DIAG */
1365 extern __checkReturn efx_rc_t
1367 __in efx_nic_t *enp,
1368 __in efx_nvram_type_t type,
1369 __out size_t *sizep);
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __in efx_nvram_type_t type,
1375 __out_opt size_t *pref_chunkp);
1377 extern __checkReturn efx_rc_t
1378 efx_nvram_rw_finish(
1379 __in efx_nic_t *enp,
1380 __in efx_nvram_type_t type);
1382 extern __checkReturn efx_rc_t
1383 efx_nvram_get_version(
1384 __in efx_nic_t *enp,
1385 __in efx_nvram_type_t type,
1386 __out uint32_t *subtypep,
1387 __out_ecount(4) uint16_t version[4]);
1389 extern __checkReturn efx_rc_t
1390 efx_nvram_read_chunk(
1391 __in efx_nic_t *enp,
1392 __in efx_nvram_type_t type,
1393 __in unsigned int offset,
1394 __out_bcount(size) caddr_t data,
1397 extern __checkReturn efx_rc_t
1398 efx_nvram_set_version(
1399 __in efx_nic_t *enp,
1400 __in efx_nvram_type_t type,
1401 __in_ecount(4) uint16_t version[4]);
1403 extern __checkReturn efx_rc_t
1405 __in efx_nic_t *enp,
1406 __in efx_nvram_type_t type,
1407 __in_bcount(partn_size) caddr_t partn_data,
1408 __in size_t partn_size);
1410 extern __checkReturn efx_rc_t
1412 __in efx_nic_t *enp,
1413 __in efx_nvram_type_t type);
1415 extern __checkReturn efx_rc_t
1416 efx_nvram_write_chunk(
1417 __in efx_nic_t *enp,
1418 __in efx_nvram_type_t type,
1419 __in unsigned int offset,
1420 __in_bcount(size) caddr_t data,
1425 __in efx_nic_t *enp);
1427 #endif /* EFSYS_OPT_NVRAM */
1429 #if EFSYS_OPT_BOOTCFG
1431 /* Report size and offset of bootcfg sector in NVRAM partition. */
1432 extern __checkReturn efx_rc_t
1433 efx_bootcfg_sector_info(
1434 __in efx_nic_t *enp,
1436 __out_opt uint32_t *sector_countp,
1437 __out size_t *offsetp,
1438 __out size_t *max_sizep);
1441 * Copy bootcfg sector data to a target buffer which may differ in size.
1442 * Optionally corrects format errors in source buffer.
1445 efx_bootcfg_copy_sector(
1446 __in efx_nic_t *enp,
1447 __inout_bcount(sector_length)
1449 __in size_t sector_length,
1450 __out_bcount(data_size) uint8_t *data,
1451 __in size_t data_size,
1452 __in boolean_t handle_format_errors);
1456 __in efx_nic_t *enp,
1457 __out_bcount(size) caddr_t data,
1462 __in efx_nic_t *enp,
1463 __in_bcount(size) caddr_t data,
1466 #endif /* EFSYS_OPT_BOOTCFG */
1470 typedef enum efx_pattern_type_t {
1471 EFX_PATTERN_BYTE_INCREMENT = 0,
1472 EFX_PATTERN_ALL_THE_SAME,
1473 EFX_PATTERN_BIT_ALTERNATE,
1474 EFX_PATTERN_BYTE_ALTERNATE,
1475 EFX_PATTERN_BYTE_CHANGING,
1476 EFX_PATTERN_BIT_SWEEP,
1478 } efx_pattern_type_t;
1481 (*efx_sram_pattern_fn_t)(
1483 __in boolean_t negate,
1484 __out efx_qword_t *eqp);
1486 extern __checkReturn efx_rc_t
1488 __in efx_nic_t *enp,
1489 __in efx_pattern_type_t type);
1491 #endif /* EFSYS_OPT_DIAG */
1493 extern __checkReturn efx_rc_t
1494 efx_sram_buf_tbl_set(
1495 __in efx_nic_t *enp,
1497 __in efsys_mem_t *esmp,
1501 efx_sram_buf_tbl_clear(
1502 __in efx_nic_t *enp,
1506 #define EFX_BUF_TBL_SIZE 0x20000
1508 #define EFX_BUF_SIZE 4096
1512 typedef struct efx_evq_s efx_evq_t;
1514 #if EFSYS_OPT_QSTATS
1516 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1517 typedef enum efx_ev_qstat_e {
1523 EV_RX_PAUSE_FRM_ERR,
1524 EV_RX_BUF_OWNER_ID_ERR,
1525 EV_RX_IPV4_HDR_CHKSUM_ERR,
1526 EV_RX_TCP_UDP_CHKSUM_ERR,
1530 EV_RX_MCAST_HASH_MATCH,
1547 EV_DRIVER_SRM_UPD_DONE,
1548 EV_DRIVER_TX_DESCQ_FLS_DONE,
1549 EV_DRIVER_RX_DESCQ_FLS_DONE,
1550 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1551 EV_DRIVER_RX_DSC_ERROR,
1552 EV_DRIVER_TX_DSC_ERROR,
1558 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1560 #endif /* EFSYS_OPT_QSTATS */
1562 extern __checkReturn efx_rc_t
1564 __in efx_nic_t *enp);
1568 __in efx_nic_t *enp);
1570 #define EFX_EVQ_MAXNEVS 32768
1571 #define EFX_EVQ_MINNEVS 512
1573 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1574 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1576 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1577 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1578 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1579 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1581 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1582 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1583 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1585 extern __checkReturn efx_rc_t
1587 __in efx_nic_t *enp,
1588 __in unsigned int index,
1589 __in efsys_mem_t *esmp,
1593 __in uint32_t flags,
1594 __deref_out efx_evq_t **eepp);
1598 __in efx_evq_t *eep,
1599 __in uint16_t data);
1601 typedef __checkReturn boolean_t
1602 (*efx_initialized_ev_t)(
1603 __in_opt void *arg);
1605 #define EFX_PKT_UNICAST 0x0004
1606 #define EFX_PKT_START 0x0008
1608 #define EFX_PKT_VLAN_TAGGED 0x0010
1609 #define EFX_CKSUM_TCPUDP 0x0020
1610 #define EFX_CKSUM_IPV4 0x0040
1611 #define EFX_PKT_CONT 0x0080
1613 #define EFX_CHECK_VLAN 0x0100
1614 #define EFX_PKT_TCP 0x0200
1615 #define EFX_PKT_UDP 0x0400
1616 #define EFX_PKT_IPV4 0x0800
1618 #define EFX_PKT_IPV6 0x1000
1619 #define EFX_PKT_PREFIX_LEN 0x2000
1620 #define EFX_ADDR_MISMATCH 0x4000
1621 #define EFX_DISCARD 0x8000
1623 #define EFX_EV_RX_NLABELS 32
1624 #define EFX_EV_TX_NLABELS 32
1626 typedef __checkReturn boolean_t
1629 __in uint32_t label,
1632 __in uint16_t flags);
1634 typedef __checkReturn boolean_t
1637 __in uint32_t label,
1640 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1641 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1642 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1643 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1644 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1645 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1646 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1647 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1648 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1650 typedef __checkReturn boolean_t
1651 (*efx_exception_ev_t)(
1653 __in uint32_t label,
1654 __in uint32_t data);
1656 typedef __checkReturn boolean_t
1657 (*efx_rxq_flush_done_ev_t)(
1659 __in uint32_t rxq_index);
1661 typedef __checkReturn boolean_t
1662 (*efx_rxq_flush_failed_ev_t)(
1664 __in uint32_t rxq_index);
1666 typedef __checkReturn boolean_t
1667 (*efx_txq_flush_done_ev_t)(
1669 __in uint32_t txq_index);
1671 typedef __checkReturn boolean_t
1672 (*efx_software_ev_t)(
1674 __in uint16_t magic);
1676 typedef __checkReturn boolean_t
1679 __in uint32_t code);
1681 #define EFX_SRAM_CLEAR 0
1682 #define EFX_SRAM_UPDATE 1
1683 #define EFX_SRAM_ILLEGAL_CLEAR 2
1685 typedef __checkReturn boolean_t
1686 (*efx_wake_up_ev_t)(
1688 __in uint32_t label);
1690 typedef __checkReturn boolean_t
1693 __in uint32_t label);
1695 typedef __checkReturn boolean_t
1696 (*efx_link_change_ev_t)(
1698 __in efx_link_mode_t link_mode);
1700 #if EFSYS_OPT_MON_STATS
1702 typedef __checkReturn boolean_t
1703 (*efx_monitor_ev_t)(
1705 __in efx_mon_stat_t id,
1706 __in efx_mon_stat_value_t value);
1708 #endif /* EFSYS_OPT_MON_STATS */
1710 #if EFSYS_OPT_MAC_STATS
1712 typedef __checkReturn boolean_t
1713 (*efx_mac_stats_ev_t)(
1715 __in uint32_t generation
1718 #endif /* EFSYS_OPT_MAC_STATS */
1720 typedef struct efx_ev_callbacks_s {
1721 efx_initialized_ev_t eec_initialized;
1724 efx_exception_ev_t eec_exception;
1725 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1726 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1727 efx_txq_flush_done_ev_t eec_txq_flush_done;
1728 efx_software_ev_t eec_software;
1729 efx_sram_ev_t eec_sram;
1730 efx_wake_up_ev_t eec_wake_up;
1731 efx_timer_ev_t eec_timer;
1732 efx_link_change_ev_t eec_link_change;
1733 #if EFSYS_OPT_MON_STATS
1734 efx_monitor_ev_t eec_monitor;
1735 #endif /* EFSYS_OPT_MON_STATS */
1736 #if EFSYS_OPT_MAC_STATS
1737 efx_mac_stats_ev_t eec_mac_stats;
1738 #endif /* EFSYS_OPT_MAC_STATS */
1739 } efx_ev_callbacks_t;
1741 extern __checkReturn boolean_t
1743 __in efx_evq_t *eep,
1744 __in unsigned int count);
1746 #if EFSYS_OPT_EV_PREFETCH
1750 __in efx_evq_t *eep,
1751 __in unsigned int count);
1753 #endif /* EFSYS_OPT_EV_PREFETCH */
1757 __in efx_evq_t *eep,
1758 __inout unsigned int *countp,
1759 __in const efx_ev_callbacks_t *eecp,
1760 __in_opt void *arg);
1762 extern __checkReturn efx_rc_t
1763 efx_ev_usecs_to_ticks(
1764 __in efx_nic_t *enp,
1765 __in unsigned int usecs,
1766 __out unsigned int *ticksp);
1768 extern __checkReturn efx_rc_t
1770 __in efx_evq_t *eep,
1771 __in unsigned int us);
1773 extern __checkReturn efx_rc_t
1775 __in efx_evq_t *eep,
1776 __in unsigned int count);
1778 #if EFSYS_OPT_QSTATS
1784 __in efx_nic_t *enp,
1785 __in unsigned int id);
1787 #endif /* EFSYS_OPT_NAMES */
1790 efx_ev_qstats_update(
1791 __in efx_evq_t *eep,
1792 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1794 #endif /* EFSYS_OPT_QSTATS */
1798 __in efx_evq_t *eep);
1802 extern __checkReturn efx_rc_t
1804 __inout efx_nic_t *enp);
1808 __in efx_nic_t *enp);
1810 #if EFSYS_OPT_RX_SCATTER
1811 __checkReturn efx_rc_t
1812 efx_rx_scatter_enable(
1813 __in efx_nic_t *enp,
1814 __in unsigned int buf_size);
1815 #endif /* EFSYS_OPT_RX_SCATTER */
1817 #if EFSYS_OPT_RX_SCALE
1819 typedef enum efx_rx_hash_alg_e {
1820 EFX_RX_HASHALG_LFSR = 0,
1821 EFX_RX_HASHALG_TOEPLITZ
1822 } efx_rx_hash_alg_t;
1824 #define EFX_RX_HASH_IPV4 (1U << 0)
1825 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1826 #define EFX_RX_HASH_IPV6 (1U << 2)
1827 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1829 typedef unsigned int efx_rx_hash_type_t;
1831 typedef enum efx_rx_hash_support_e {
1832 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1833 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1834 } efx_rx_hash_support_t;
1836 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1837 #define EFX_MAXRSS 64 /* RX indirection entry range */
1838 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1840 typedef enum efx_rx_scale_support_e {
1841 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1842 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1843 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1844 } efx_rx_scale_support_t;
1846 extern __checkReturn efx_rc_t
1847 efx_rx_hash_support_get(
1848 __in efx_nic_t *enp,
1849 __out efx_rx_hash_support_t *supportp);
1852 extern __checkReturn efx_rc_t
1853 efx_rx_scale_support_get(
1854 __in efx_nic_t *enp,
1855 __out efx_rx_scale_support_t *supportp);
1857 extern __checkReturn efx_rc_t
1858 efx_rx_scale_mode_set(
1859 __in efx_nic_t *enp,
1860 __in efx_rx_hash_alg_t alg,
1861 __in efx_rx_hash_type_t type,
1862 __in boolean_t insert);
1864 extern __checkReturn efx_rc_t
1865 efx_rx_scale_tbl_set(
1866 __in efx_nic_t *enp,
1867 __in_ecount(n) unsigned int *table,
1870 extern __checkReturn efx_rc_t
1871 efx_rx_scale_key_set(
1872 __in efx_nic_t *enp,
1873 __in_ecount(n) uint8_t *key,
1876 extern __checkReturn uint32_t
1877 efx_pseudo_hdr_hash_get(
1878 __in efx_rxq_t *erp,
1879 __in efx_rx_hash_alg_t func,
1880 __in uint8_t *buffer);
1882 #endif /* EFSYS_OPT_RX_SCALE */
1884 extern __checkReturn efx_rc_t
1885 efx_pseudo_hdr_pkt_length_get(
1886 __in efx_rxq_t *erp,
1887 __in uint8_t *buffer,
1888 __out uint16_t *pkt_lengthp);
1890 #define EFX_RXQ_MAXNDESCS 4096
1891 #define EFX_RXQ_MINNDESCS 512
1893 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1894 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1895 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1896 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1898 typedef enum efx_rxq_type_e {
1899 EFX_RXQ_TYPE_DEFAULT,
1900 EFX_RXQ_TYPE_SCATTER,
1904 extern __checkReturn efx_rc_t
1906 __in efx_nic_t *enp,
1907 __in unsigned int index,
1908 __in unsigned int label,
1909 __in efx_rxq_type_t type,
1910 __in efsys_mem_t *esmp,
1913 __in efx_evq_t *eep,
1914 __deref_out efx_rxq_t **erpp);
1916 typedef struct efx_buffer_s {
1917 efsys_dma_addr_t eb_addr;
1922 typedef struct efx_desc_s {
1928 __in efx_rxq_t *erp,
1929 __in_ecount(n) efsys_dma_addr_t *addrp,
1931 __in unsigned int n,
1932 __in unsigned int completed,
1933 __in unsigned int added);
1937 __in efx_rxq_t *erp,
1938 __in unsigned int added,
1939 __inout unsigned int *pushedp);
1941 extern __checkReturn efx_rc_t
1943 __in efx_rxq_t *erp);
1947 __in efx_rxq_t *erp);
1951 __in efx_rxq_t *erp);
1955 typedef struct efx_txq_s efx_txq_t;
1957 #if EFSYS_OPT_QSTATS
1959 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1960 typedef enum efx_tx_qstat_e {
1966 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1968 #endif /* EFSYS_OPT_QSTATS */
1970 extern __checkReturn efx_rc_t
1972 __in efx_nic_t *enp);
1976 __in efx_nic_t *enp);
1978 #define EFX_BUG35388_WORKAROUND(_encp) \
1979 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1981 #define EFX_TXQ_MAXNDESCS(_encp) \
1982 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1984 #define EFX_TXQ_MINNDESCS 512
1986 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1987 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1988 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1989 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1991 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1993 #define EFX_TXQ_CKSUM_IPV4 0x0001
1994 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1995 #define EFX_TXQ_FATSOV2 0x0004
1997 extern __checkReturn efx_rc_t
1999 __in efx_nic_t *enp,
2000 __in unsigned int index,
2001 __in unsigned int label,
2002 __in efsys_mem_t *esmp,
2005 __in uint16_t flags,
2006 __in efx_evq_t *eep,
2007 __deref_out efx_txq_t **etpp,
2008 __out unsigned int *addedp);
2010 extern __checkReturn efx_rc_t
2012 __in efx_txq_t *etp,
2013 __in_ecount(n) efx_buffer_t *eb,
2014 __in unsigned int n,
2015 __in unsigned int completed,
2016 __inout unsigned int *addedp);
2018 extern __checkReturn efx_rc_t
2020 __in efx_txq_t *etp,
2021 __in unsigned int ns);
2025 __in efx_txq_t *etp,
2026 __in unsigned int added,
2027 __in unsigned int pushed);
2029 extern __checkReturn efx_rc_t
2031 __in efx_txq_t *etp);
2035 __in efx_txq_t *etp);
2037 extern __checkReturn efx_rc_t
2039 __in efx_txq_t *etp);
2042 efx_tx_qpio_disable(
2043 __in efx_txq_t *etp);
2045 extern __checkReturn efx_rc_t
2047 __in efx_txq_t *etp,
2048 __in_ecount(buf_length) uint8_t *buffer,
2049 __in size_t buf_length,
2050 __in size_t pio_buf_offset);
2052 extern __checkReturn efx_rc_t
2054 __in efx_txq_t *etp,
2055 __in size_t pkt_length,
2056 __in unsigned int completed,
2057 __inout unsigned int *addedp);
2059 extern __checkReturn efx_rc_t
2061 __in efx_txq_t *etp,
2062 __in_ecount(n) efx_desc_t *ed,
2063 __in unsigned int n,
2064 __in unsigned int completed,
2065 __inout unsigned int *addedp);
2068 efx_tx_qdesc_dma_create(
2069 __in efx_txq_t *etp,
2070 __in efsys_dma_addr_t addr,
2073 __out efx_desc_t *edp);
2076 efx_tx_qdesc_tso_create(
2077 __in efx_txq_t *etp,
2078 __in uint16_t ipv4_id,
2079 __in uint32_t tcp_seq,
2080 __in uint8_t tcp_flags,
2081 __out efx_desc_t *edp);
2083 /* Number of FATSOv2 option descriptors */
2084 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2086 /* Maximum number of DMA segments per TSO packet (not superframe) */
2087 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2090 efx_tx_qdesc_tso2_create(
2091 __in efx_txq_t *etp,
2092 __in uint16_t ipv4_id,
2093 __in uint32_t tcp_seq,
2094 __in uint16_t tcp_mss,
2095 __out_ecount(count) efx_desc_t *edp,
2099 efx_tx_qdesc_vlantci_create(
2100 __in efx_txq_t *etp,
2102 __out efx_desc_t *edp);
2104 #if EFSYS_OPT_QSTATS
2110 __in efx_nic_t *etp,
2111 __in unsigned int id);
2113 #endif /* EFSYS_OPT_NAMES */
2116 efx_tx_qstats_update(
2117 __in efx_txq_t *etp,
2118 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2120 #endif /* EFSYS_OPT_QSTATS */
2124 __in efx_txq_t *etp);
2129 #if EFSYS_OPT_FILTER
2131 #define EFX_ETHER_TYPE_IPV4 0x0800
2132 #define EFX_ETHER_TYPE_IPV6 0x86DD
2134 #define EFX_IPPROTO_TCP 6
2135 #define EFX_IPPROTO_UDP 17
2137 /* Use RSS to spread across multiple queues */
2138 #define EFX_FILTER_FLAG_RX_RSS 0x01
2139 /* Enable RX scatter */
2140 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2142 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2143 * May only be set by the filter implementation for each type.
2144 * A removal request will restore the automatic filter in its place.
2146 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2147 /* Filter is for RX */
2148 #define EFX_FILTER_FLAG_RX 0x08
2149 /* Filter is for TX */
2150 #define EFX_FILTER_FLAG_TX 0x10
2152 typedef unsigned int efx_filter_flags_t;
2154 typedef enum efx_filter_match_flags_e {
2155 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2157 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2159 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2160 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2161 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2162 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2163 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2164 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2165 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2166 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2168 /* Match otherwise-unmatched multicast and broadcast packets */
2169 EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000,
2170 /* Match otherwise-unmatched unicast packets */
2171 EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000,
2172 } efx_filter_match_flags_t;
2174 typedef enum efx_filter_priority_s {
2175 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2176 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2177 * address list or hardware
2178 * requirements. This may only be used
2179 * by the filter implementation for
2181 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2182 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2183 * client (e.g. SR-IOV, HyperV VMQ etc.)
2185 } efx_filter_priority_t;
2188 * FIXME: All these fields are assumed to be in little-endian byte order.
2189 * It may be better for some to be big-endian. See bug42804.
2192 typedef struct efx_filter_spec_s {
2193 uint32_t efs_match_flags;
2194 uint32_t efs_priority:2;
2195 uint32_t efs_flags:6;
2196 uint32_t efs_dmaq_id:12;
2197 uint32_t efs_rss_context;
2198 uint16_t efs_outer_vid;
2199 uint16_t efs_inner_vid;
2200 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2201 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2202 uint16_t efs_ether_type;
2203 uint8_t efs_ip_proto;
2204 uint16_t efs_loc_port;
2205 uint16_t efs_rem_port;
2206 efx_oword_t efs_rem_host;
2207 efx_oword_t efs_loc_host;
2208 } efx_filter_spec_t;
2211 /* Default values for use in filter specifications */
2212 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2213 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2214 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2216 extern __checkReturn efx_rc_t
2218 __in efx_nic_t *enp);
2222 __in efx_nic_t *enp);
2224 extern __checkReturn efx_rc_t
2226 __in efx_nic_t *enp,
2227 __inout efx_filter_spec_t *spec);
2229 extern __checkReturn efx_rc_t
2231 __in efx_nic_t *enp,
2232 __inout efx_filter_spec_t *spec);
2234 extern __checkReturn efx_rc_t
2236 __in efx_nic_t *enp);
2238 extern __checkReturn efx_rc_t
2239 efx_filter_supported_filters(
2240 __in efx_nic_t *enp,
2241 __out_ecount(buffer_length) uint32_t *buffer,
2242 __in size_t buffer_length,
2243 __out size_t *list_lengthp);
2246 efx_filter_spec_init_rx(
2247 __out efx_filter_spec_t *spec,
2248 __in efx_filter_priority_t priority,
2249 __in efx_filter_flags_t flags,
2250 __in efx_rxq_t *erp);
2253 efx_filter_spec_init_tx(
2254 __out efx_filter_spec_t *spec,
2255 __in efx_txq_t *etp);
2257 extern __checkReturn efx_rc_t
2258 efx_filter_spec_set_ipv4_local(
2259 __inout efx_filter_spec_t *spec,
2262 __in uint16_t port);
2264 extern __checkReturn efx_rc_t
2265 efx_filter_spec_set_ipv4_full(
2266 __inout efx_filter_spec_t *spec,
2268 __in uint32_t lhost,
2269 __in uint16_t lport,
2270 __in uint32_t rhost,
2271 __in uint16_t rport);
2273 extern __checkReturn efx_rc_t
2274 efx_filter_spec_set_eth_local(
2275 __inout efx_filter_spec_t *spec,
2277 __in const uint8_t *addr);
2279 extern __checkReturn efx_rc_t
2280 efx_filter_spec_set_uc_def(
2281 __inout efx_filter_spec_t *spec);
2283 extern __checkReturn efx_rc_t
2284 efx_filter_spec_set_mc_def(
2285 __inout efx_filter_spec_t *spec);
2287 #endif /* EFSYS_OPT_FILTER */
2291 extern __checkReturn uint32_t
2293 __in_ecount(count) uint32_t const *input,
2295 __in uint32_t init);
2297 extern __checkReturn uint32_t
2299 __in_ecount(length) uint8_t const *input,
2301 __in uint32_t init);
2303 #if EFSYS_OPT_LICENSING
2307 typedef struct efx_key_stats_s {
2309 uint32_t eks_invalid;
2310 uint32_t eks_blacklisted;
2311 uint32_t eks_unverifiable;
2312 uint32_t eks_wrong_node;
2313 uint32_t eks_licensed_apps_lo;
2314 uint32_t eks_licensed_apps_hi;
2315 uint32_t eks_licensed_features_lo;
2316 uint32_t eks_licensed_features_hi;
2319 extern __checkReturn efx_rc_t
2321 __in efx_nic_t *enp);
2325 __in efx_nic_t *enp);
2327 extern __checkReturn boolean_t
2328 efx_lic_check_support(
2329 __in efx_nic_t *enp);
2331 extern __checkReturn efx_rc_t
2332 efx_lic_update_licenses(
2333 __in efx_nic_t *enp);
2335 extern __checkReturn efx_rc_t
2336 efx_lic_get_key_stats(
2337 __in efx_nic_t *enp,
2338 __out efx_key_stats_t *ksp);
2340 extern __checkReturn efx_rc_t
2342 __in efx_nic_t *enp,
2343 __in uint64_t app_id,
2344 __out boolean_t *licensedp);
2346 extern __checkReturn efx_rc_t
2348 __in efx_nic_t *enp,
2349 __in size_t buffer_size,
2350 __out uint32_t *typep,
2351 __out size_t *lengthp,
2352 __out_opt uint8_t *bufferp);
2355 extern __checkReturn efx_rc_t
2357 __in efx_nic_t *enp,
2358 __in_bcount(buffer_size)
2360 __in size_t buffer_size,
2361 __out uint32_t *startp
2364 extern __checkReturn efx_rc_t
2366 __in efx_nic_t *enp,
2367 __in_bcount(buffer_size)
2369 __in size_t buffer_size,
2370 __in uint32_t offset,
2371 __out uint32_t *endp
2374 extern __checkReturn __success(return != B_FALSE) boolean_t
2376 __in efx_nic_t *enp,
2377 __in_bcount(buffer_size)
2379 __in size_t buffer_size,
2380 __in uint32_t offset,
2381 __out uint32_t *startp,
2382 __out uint32_t *lengthp
2385 extern __checkReturn __success(return != B_FALSE) boolean_t
2386 efx_lic_validate_key(
2387 __in efx_nic_t *enp,
2388 __in_bcount(length) caddr_t keyp,
2389 __in uint32_t length
2392 extern __checkReturn efx_rc_t
2394 __in efx_nic_t *enp,
2395 __in_bcount(buffer_size)
2397 __in size_t buffer_size,
2398 __in uint32_t offset,
2399 __in uint32_t length,
2400 __out_bcount_part(key_max_size, *lengthp)
2402 __in size_t key_max_size,
2403 __out uint32_t *lengthp
2406 extern __checkReturn efx_rc_t
2408 __in efx_nic_t *enp,
2409 __in_bcount(buffer_size)
2411 __in size_t buffer_size,
2412 __in uint32_t offset,
2413 __in_bcount(length) caddr_t keyp,
2414 __in uint32_t length,
2415 __out uint32_t *lengthp
2418 __checkReturn efx_rc_t
2420 __in efx_nic_t *enp,
2421 __in_bcount(buffer_size)
2423 __in size_t buffer_size,
2424 __in uint32_t offset,
2425 __in uint32_t length,
2427 __out uint32_t *deltap
2430 extern __checkReturn efx_rc_t
2431 efx_lic_create_partition(
2432 __in efx_nic_t *enp,
2433 __in_bcount(buffer_size)
2435 __in size_t buffer_size
2438 extern __checkReturn efx_rc_t
2439 efx_lic_finish_partition(
2440 __in efx_nic_t *enp,
2441 __in_bcount(buffer_size)
2443 __in size_t buffer_size
2446 #endif /* EFSYS_OPT_LICENSING */
2454 #endif /* _SYS_EFX_H */