2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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30 * policies, either expressed or implied, of the FreeBSD Project.
38 #include "efx_annote.h"
40 #include "efx_check.h"
41 #include "efx_phy_ids.h"
47 #define EFX_STATIC_ASSERT(_cond) \
48 ((void)sizeof (char[(_cond) ? 1 : -1]))
50 #define EFX_ARRAY_SIZE(_array) \
51 (sizeof (_array) / sizeof ((_array)[0]))
53 #define EFX_FIELD_OFFSET(_type, _field) \
54 ((size_t)&(((_type *)0)->_field))
56 /* The macro expands divider twice */
57 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
61 typedef __success(return == 0) int efx_rc_t;
66 typedef enum efx_family_e {
68 EFX_FAMILY_FALCON, /* Obsolete and not supported */
70 EFX_FAMILY_HUNTINGTON,
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
84 #define EFX_PCI_VENID_SFC 0x1924
86 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
88 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
89 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
90 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
92 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
93 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
94 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
96 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
97 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
99 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
100 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
101 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
103 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
104 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
105 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
108 #define EFX_MEM_BAR_SIENA 2
110 #define EFX_MEM_BAR_HUNTINGTON_PF 2
111 #define EFX_MEM_BAR_HUNTINGTON_VF 0
113 #define EFX_MEM_BAR_MEDFORD_PF 2
114 #define EFX_MEM_BAR_MEDFORD_VF 0
116 #define EFX_MEM_BAR_MEDFORD2 0
124 EFX_ERR_BUFID_DC_OOB,
137 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
138 extern __checkReturn uint32_t
140 __in uint32_t crc_init,
141 __in_ecount(length) uint8_t const *input,
145 /* Type prototypes */
147 typedef struct efx_rxq_s efx_rxq_t;
151 typedef struct efx_nic_s efx_nic_t;
153 extern __checkReturn efx_rc_t
155 __in efx_family_t family,
156 __in efsys_identifier_t *esip,
157 __in efsys_bar_t *esbp,
158 __in efsys_lock_t *eslp,
159 __deref_out efx_nic_t **enpp);
161 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
162 typedef enum efx_fw_variant_e {
163 EFX_FW_VARIANT_FULL_FEATURED,
164 EFX_FW_VARIANT_LOW_LATENCY,
165 EFX_FW_VARIANT_PACKED_STREAM,
166 EFX_FW_VARIANT_HIGH_TX_RATE,
167 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
168 EFX_FW_VARIANT_RULES_ENGINE,
170 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
173 extern __checkReturn efx_rc_t
176 __in efx_fw_variant_t efv);
178 extern __checkReturn efx_rc_t
180 __in efx_nic_t *enp);
182 extern __checkReturn efx_rc_t
184 __in efx_nic_t *enp);
186 extern __checkReturn boolean_t
187 efx_nic_hw_unavailable(
188 __in efx_nic_t *enp);
192 extern __checkReturn efx_rc_t
193 efx_nic_register_test(
194 __in efx_nic_t *enp);
196 #endif /* EFSYS_OPT_DIAG */
200 __in efx_nic_t *enp);
204 __in efx_nic_t *enp);
208 __in efx_nic_t *enp);
210 #define EFX_PCIE_LINK_SPEED_GEN1 1
211 #define EFX_PCIE_LINK_SPEED_GEN2 2
212 #define EFX_PCIE_LINK_SPEED_GEN3 3
214 typedef enum efx_pcie_link_performance_e {
215 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
216 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
217 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
218 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
219 } efx_pcie_link_performance_t;
221 extern __checkReturn efx_rc_t
222 efx_nic_calculate_pcie_link_bandwidth(
223 __in uint32_t pcie_link_width,
224 __in uint32_t pcie_link_gen,
225 __out uint32_t *bandwidth_mbpsp);
227 extern __checkReturn efx_rc_t
228 efx_nic_check_pcie_link_speed(
230 __in uint32_t pcie_link_width,
231 __in uint32_t pcie_link_gen,
232 __out efx_pcie_link_performance_t *resultp);
236 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
237 /* Huntington and Medford require MCDIv2 commands */
238 #define WITH_MCDI_V2 1
241 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
243 typedef enum efx_mcdi_exception_e {
244 EFX_MCDI_EXCEPTION_MC_REBOOT,
245 EFX_MCDI_EXCEPTION_MC_BADASSERT,
246 } efx_mcdi_exception_t;
248 #if EFSYS_OPT_MCDI_LOGGING
249 typedef enum efx_log_msg_e {
251 EFX_LOG_MCDI_REQUEST,
252 EFX_LOG_MCDI_RESPONSE,
254 #endif /* EFSYS_OPT_MCDI_LOGGING */
256 typedef struct efx_mcdi_transport_s {
258 efsys_mem_t *emt_dma_mem;
259 void (*emt_execute)(void *, efx_mcdi_req_t *);
260 void (*emt_ev_cpl)(void *);
261 void (*emt_exception)(void *, efx_mcdi_exception_t);
262 #if EFSYS_OPT_MCDI_LOGGING
263 void (*emt_logger)(void *, efx_log_msg_t,
264 void *, size_t, void *, size_t);
265 #endif /* EFSYS_OPT_MCDI_LOGGING */
266 #if EFSYS_OPT_MCDI_PROXY_AUTH
267 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
268 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
269 } efx_mcdi_transport_t;
271 extern __checkReturn efx_rc_t
274 __in const efx_mcdi_transport_t *mtp);
276 extern __checkReturn efx_rc_t
278 __in efx_nic_t *enp);
282 __in efx_nic_t *enp);
285 efx_mcdi_get_timeout(
287 __in efx_mcdi_req_t *emrp,
288 __out uint32_t *usec_timeoutp);
291 efx_mcdi_request_start(
293 __in efx_mcdi_req_t *emrp,
294 __in boolean_t ev_cpl);
296 extern __checkReturn boolean_t
297 efx_mcdi_request_poll(
298 __in efx_nic_t *enp);
300 extern __checkReturn boolean_t
301 efx_mcdi_request_abort(
302 __in efx_nic_t *enp);
306 __in efx_nic_t *enp);
308 #endif /* EFSYS_OPT_MCDI */
312 #define EFX_NINTR_SIENA 1024
314 typedef enum efx_intr_type_e {
315 EFX_INTR_INVALID = 0,
321 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
323 extern __checkReturn efx_rc_t
326 __in efx_intr_type_t type,
327 __in efsys_mem_t *esmp);
331 __in efx_nic_t *enp);
335 __in efx_nic_t *enp);
338 efx_intr_disable_unlocked(
339 __in efx_nic_t *enp);
341 #define EFX_INTR_NEVQS 32
343 extern __checkReturn efx_rc_t
346 __in unsigned int level);
349 efx_intr_status_line(
351 __out boolean_t *fatalp,
352 __out uint32_t *maskp);
355 efx_intr_status_message(
357 __in unsigned int message,
358 __out boolean_t *fatalp);
362 __in efx_nic_t *enp);
366 __in efx_nic_t *enp);
370 #if EFSYS_OPT_MAC_STATS
372 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
373 typedef enum efx_mac_stat_e {
376 EFX_MAC_RX_UNICST_PKTS,
377 EFX_MAC_RX_MULTICST_PKTS,
378 EFX_MAC_RX_BRDCST_PKTS,
379 EFX_MAC_RX_PAUSE_PKTS,
380 EFX_MAC_RX_LE_64_PKTS,
381 EFX_MAC_RX_65_TO_127_PKTS,
382 EFX_MAC_RX_128_TO_255_PKTS,
383 EFX_MAC_RX_256_TO_511_PKTS,
384 EFX_MAC_RX_512_TO_1023_PKTS,
385 EFX_MAC_RX_1024_TO_15XX_PKTS,
386 EFX_MAC_RX_GE_15XX_PKTS,
388 EFX_MAC_RX_FCS_ERRORS,
389 EFX_MAC_RX_DROP_EVENTS,
390 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
391 EFX_MAC_RX_SYMBOL_ERRORS,
392 EFX_MAC_RX_ALIGN_ERRORS,
393 EFX_MAC_RX_INTERNAL_ERRORS,
394 EFX_MAC_RX_JABBER_PKTS,
395 EFX_MAC_RX_LANE0_CHAR_ERR,
396 EFX_MAC_RX_LANE1_CHAR_ERR,
397 EFX_MAC_RX_LANE2_CHAR_ERR,
398 EFX_MAC_RX_LANE3_CHAR_ERR,
399 EFX_MAC_RX_LANE0_DISP_ERR,
400 EFX_MAC_RX_LANE1_DISP_ERR,
401 EFX_MAC_RX_LANE2_DISP_ERR,
402 EFX_MAC_RX_LANE3_DISP_ERR,
403 EFX_MAC_RX_MATCH_FAULT,
404 EFX_MAC_RX_NODESC_DROP_CNT,
407 EFX_MAC_TX_UNICST_PKTS,
408 EFX_MAC_TX_MULTICST_PKTS,
409 EFX_MAC_TX_BRDCST_PKTS,
410 EFX_MAC_TX_PAUSE_PKTS,
411 EFX_MAC_TX_LE_64_PKTS,
412 EFX_MAC_TX_65_TO_127_PKTS,
413 EFX_MAC_TX_128_TO_255_PKTS,
414 EFX_MAC_TX_256_TO_511_PKTS,
415 EFX_MAC_TX_512_TO_1023_PKTS,
416 EFX_MAC_TX_1024_TO_15XX_PKTS,
417 EFX_MAC_TX_GE_15XX_PKTS,
419 EFX_MAC_TX_SGL_COL_PKTS,
420 EFX_MAC_TX_MULT_COL_PKTS,
421 EFX_MAC_TX_EX_COL_PKTS,
422 EFX_MAC_TX_LATE_COL_PKTS,
424 EFX_MAC_TX_EX_DEF_PKTS,
425 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
426 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
427 EFX_MAC_PM_TRUNC_VFIFO_FULL,
428 EFX_MAC_PM_DISCARD_VFIFO_FULL,
429 EFX_MAC_PM_TRUNC_QBB,
430 EFX_MAC_PM_DISCARD_QBB,
431 EFX_MAC_PM_DISCARD_MAPPING,
432 EFX_MAC_RXDP_Q_DISABLED_PKTS,
433 EFX_MAC_RXDP_DI_DROPPED_PKTS,
434 EFX_MAC_RXDP_STREAMING_PKTS,
435 EFX_MAC_RXDP_HLB_FETCH,
436 EFX_MAC_RXDP_HLB_WAIT,
437 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
438 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
439 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
440 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
441 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
442 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
443 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
444 EFX_MAC_VADAPTER_RX_BAD_BYTES,
445 EFX_MAC_VADAPTER_RX_OVERFLOW,
446 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
447 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
448 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
449 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
450 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
451 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
452 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
453 EFX_MAC_VADAPTER_TX_BAD_BYTES,
454 EFX_MAC_VADAPTER_TX_OVERFLOW,
455 EFX_MAC_FEC_UNCORRECTED_ERRORS,
456 EFX_MAC_FEC_CORRECTED_ERRORS,
457 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
458 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
459 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
460 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
461 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
462 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
463 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
464 EFX_MAC_CTPIO_OVERFLOW_FAIL,
465 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
466 EFX_MAC_CTPIO_TIMEOUT_FAIL,
467 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
468 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
469 EFX_MAC_CTPIO_INVALID_WR_FAIL,
470 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
471 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
472 EFX_MAC_CTPIO_RUNT_FALLBACK,
473 EFX_MAC_CTPIO_SUCCESS,
474 EFX_MAC_CTPIO_FALLBACK,
475 EFX_MAC_CTPIO_POISON,
477 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
478 EFX_MAC_RXDP_HLB_IDLE,
479 EFX_MAC_RXDP_HLB_TIMEOUT,
483 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
485 #endif /* EFSYS_OPT_MAC_STATS */
487 typedef enum efx_link_mode_e {
488 EFX_LINK_UNKNOWN = 0,
504 #define EFX_MAC_ADDR_LEN 6
506 #define EFX_VNI_OR_VSID_LEN 3
508 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
510 #define EFX_MAC_MULTICAST_LIST_MAX 256
512 #define EFX_MAC_SDU_MAX 9202
514 #define EFX_MAC_PDU_ADJUSTMENT \
518 + /* bug16011 */ 16) \
520 #define EFX_MAC_PDU(_sdu) \
521 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
524 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
525 * the SDU rounded up slightly.
527 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
529 #define EFX_MAC_PDU_MIN 60
530 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
532 extern __checkReturn efx_rc_t
537 extern __checkReturn efx_rc_t
542 extern __checkReturn efx_rc_t
547 extern __checkReturn efx_rc_t
550 __in boolean_t all_unicst,
551 __in boolean_t mulcst,
552 __in boolean_t all_mulcst,
553 __in boolean_t brdcst);
555 extern __checkReturn efx_rc_t
556 efx_mac_multicast_list_set(
558 __in_ecount(6*count) uint8_t const *addrs,
561 extern __checkReturn efx_rc_t
562 efx_mac_filter_default_rxq_set(
565 __in boolean_t using_rss);
568 efx_mac_filter_default_rxq_clear(
569 __in efx_nic_t *enp);
571 extern __checkReturn efx_rc_t
574 __in boolean_t enabled);
576 extern __checkReturn efx_rc_t
579 __out boolean_t *mac_upp);
581 #define EFX_FCNTL_RESPOND 0x00000001
582 #define EFX_FCNTL_GENERATE 0x00000002
584 extern __checkReturn efx_rc_t
587 __in unsigned int fcntl,
588 __in boolean_t autoneg);
593 __out unsigned int *fcntl_wantedp,
594 __out unsigned int *fcntl_linkp);
597 #if EFSYS_OPT_MAC_STATS
601 extern __checkReturn const char *
604 __in unsigned int id);
606 #endif /* EFSYS_OPT_NAMES */
608 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
610 #define EFX_MAC_STATS_MASK_NPAGES \
611 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
612 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
615 * Get mask of MAC statistics supported by the hardware.
617 * If mask_size is insufficient to return the mask, EINVAL error is
618 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
619 * (which is sizeof (uint32_t)) is sufficient.
621 extern __checkReturn efx_rc_t
622 efx_mac_stats_get_mask(
624 __out_bcount(mask_size) uint32_t *maskp,
625 __in size_t mask_size);
627 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
628 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
629 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
632 extern __checkReturn efx_rc_t
634 __in efx_nic_t *enp);
637 * Upload mac statistics supported by the hardware into the given buffer.
639 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
640 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
642 * The hardware will only DMA statistics that it understands (of course).
643 * Drivers should not make any assumptions about which statistics are
644 * supported, especially when the statistics are generated by firmware.
646 * Thus, drivers should zero this buffer before use, so that not-understood
647 * statistics read back as zero.
649 extern __checkReturn efx_rc_t
650 efx_mac_stats_upload(
652 __in efsys_mem_t *esmp);
654 extern __checkReturn efx_rc_t
655 efx_mac_stats_periodic(
657 __in efsys_mem_t *esmp,
658 __in uint16_t period_ms,
659 __in boolean_t events);
661 extern __checkReturn efx_rc_t
662 efx_mac_stats_update(
664 __in efsys_mem_t *esmp,
665 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
666 __inout_opt uint32_t *generationp);
668 #endif /* EFSYS_OPT_MAC_STATS */
672 typedef enum efx_mon_type_e {
684 __in efx_nic_t *enp);
686 #endif /* EFSYS_OPT_NAMES */
688 extern __checkReturn efx_rc_t
690 __in efx_nic_t *enp);
692 #if EFSYS_OPT_MON_STATS
694 #define EFX_MON_STATS_PAGE_SIZE 0x100
695 #define EFX_MON_MASK_ELEMENT_SIZE 32
697 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
698 typedef enum efx_mon_stat_e {
699 EFX_MON_STAT_CONTROLLER_TEMP,
700 EFX_MON_STAT_PHY_COMMON_TEMP,
701 EFX_MON_STAT_CONTROLLER_COOLING,
702 EFX_MON_STAT_PHY0_TEMP,
703 EFX_MON_STAT_PHY0_COOLING,
704 EFX_MON_STAT_PHY1_TEMP,
705 EFX_MON_STAT_PHY1_COOLING,
711 EFX_MON_STAT_IN_12V0,
712 EFX_MON_STAT_IN_1V2A,
713 EFX_MON_STAT_IN_VREF,
714 EFX_MON_STAT_OUT_VAOE,
715 EFX_MON_STAT_AOE_TEMP,
716 EFX_MON_STAT_PSU_AOE_TEMP,
717 EFX_MON_STAT_PSU_TEMP,
723 EFX_MON_STAT_IN_VAOE,
724 EFX_MON_STAT_OUT_IAOE,
725 EFX_MON_STAT_IN_IAOE,
726 EFX_MON_STAT_NIC_POWER,
728 EFX_MON_STAT_IN_I0V9,
729 EFX_MON_STAT_IN_I1V2,
730 EFX_MON_STAT_IN_0V9_ADC,
731 EFX_MON_STAT_CONTROLLER_2_TEMP,
732 EFX_MON_STAT_VREG_INTERNAL_TEMP,
733 EFX_MON_STAT_VREG_0V9_TEMP,
734 EFX_MON_STAT_VREG_1V2_TEMP,
735 EFX_MON_STAT_CONTROLLER_VPTAT,
736 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
737 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
738 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
739 EFX_MON_STAT_AMBIENT_TEMP,
740 EFX_MON_STAT_AIRFLOW,
741 EFX_MON_STAT_VDD08D_VSS08D_CSR,
742 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
743 EFX_MON_STAT_HOTPOINT_TEMP,
744 EFX_MON_STAT_PHY_POWER_PORT0,
745 EFX_MON_STAT_PHY_POWER_PORT1,
746 EFX_MON_STAT_MUM_VCC,
747 EFX_MON_STAT_IN_0V9_A,
748 EFX_MON_STAT_IN_I0V9_A,
749 EFX_MON_STAT_VREG_0V9_A_TEMP,
750 EFX_MON_STAT_IN_0V9_B,
751 EFX_MON_STAT_IN_I0V9_B,
752 EFX_MON_STAT_VREG_0V9_B_TEMP,
753 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
754 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
755 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
756 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
757 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
758 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
759 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
760 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
761 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
762 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
763 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
764 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
765 EFX_MON_STAT_SODIMM_VOUT,
766 EFX_MON_STAT_SODIMM_0_TEMP,
767 EFX_MON_STAT_SODIMM_1_TEMP,
768 EFX_MON_STAT_PHY0_VCC,
769 EFX_MON_STAT_PHY1_VCC,
770 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
771 EFX_MON_STAT_BOARD_FRONT_TEMP,
772 EFX_MON_STAT_BOARD_BACK_TEMP,
773 EFX_MON_STAT_IN_I1V8,
774 EFX_MON_STAT_IN_I2V5,
775 EFX_MON_STAT_IN_I3V3,
776 EFX_MON_STAT_IN_I12V0,
778 EFX_MON_STAT_IN_I1V3,
782 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
784 typedef enum efx_mon_stat_state_e {
785 EFX_MON_STAT_STATE_OK = 0,
786 EFX_MON_STAT_STATE_WARNING = 1,
787 EFX_MON_STAT_STATE_FATAL = 2,
788 EFX_MON_STAT_STATE_BROKEN = 3,
789 EFX_MON_STAT_STATE_NO_READING = 4,
790 } efx_mon_stat_state_t;
792 typedef enum efx_mon_stat_unit_e {
793 EFX_MON_STAT_UNIT_UNKNOWN = 0,
794 EFX_MON_STAT_UNIT_BOOL,
795 EFX_MON_STAT_UNIT_TEMP_C,
796 EFX_MON_STAT_UNIT_VOLTAGE_MV,
797 EFX_MON_STAT_UNIT_CURRENT_MA,
798 EFX_MON_STAT_UNIT_POWER_W,
799 EFX_MON_STAT_UNIT_RPM,
801 } efx_mon_stat_unit_t;
803 typedef struct efx_mon_stat_value_s {
805 efx_mon_stat_state_t emsv_state;
806 efx_mon_stat_unit_t emsv_unit;
807 } efx_mon_stat_value_t;
809 typedef struct efx_mon_limit_value_s {
810 uint16_t emlv_warning_min;
811 uint16_t emlv_warning_max;
812 uint16_t emlv_fatal_min;
813 uint16_t emlv_fatal_max;
814 } efx_mon_stat_limits_t;
816 typedef enum efx_mon_stat_portmask_e {
817 EFX_MON_STAT_PORTMAP_NONE = 0,
818 EFX_MON_STAT_PORTMAP_PORT0 = 1,
819 EFX_MON_STAT_PORTMAP_PORT1 = 2,
820 EFX_MON_STAT_PORTMAP_PORT2 = 3,
821 EFX_MON_STAT_PORTMAP_PORT3 = 4,
822 EFX_MON_STAT_PORTMAP_ALL = (-1),
823 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
824 } efx_mon_stat_portmask_t;
831 __in efx_mon_stat_t id);
834 efx_mon_stat_description(
836 __in efx_mon_stat_t id);
838 #endif /* EFSYS_OPT_NAMES */
840 extern __checkReturn boolean_t
841 efx_mon_mcdi_to_efx_stat(
843 __out efx_mon_stat_t *statp);
845 extern __checkReturn boolean_t
846 efx_mon_get_stat_unit(
847 __in efx_mon_stat_t stat,
848 __out efx_mon_stat_unit_t *unitp);
850 extern __checkReturn boolean_t
851 efx_mon_get_stat_portmap(
852 __in efx_mon_stat_t stat,
853 __out efx_mon_stat_portmask_t *maskp);
855 extern __checkReturn efx_rc_t
856 efx_mon_stats_update(
858 __in efsys_mem_t *esmp,
859 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
861 extern __checkReturn efx_rc_t
862 efx_mon_limits_update(
864 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
866 #endif /* EFSYS_OPT_MON_STATS */
870 __in efx_nic_t *enp);
874 extern __checkReturn efx_rc_t
876 __in efx_nic_t *enp);
878 #if EFSYS_OPT_PHY_LED_CONTROL
880 typedef enum efx_phy_led_mode_e {
881 EFX_PHY_LED_DEFAULT = 0,
886 } efx_phy_led_mode_t;
888 extern __checkReturn efx_rc_t
891 __in efx_phy_led_mode_t mode);
893 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
895 extern __checkReturn efx_rc_t
897 __in efx_nic_t *enp);
899 #if EFSYS_OPT_LOOPBACK
901 typedef enum efx_loopback_type_e {
902 EFX_LOOPBACK_OFF = 0,
903 EFX_LOOPBACK_DATA = 1,
904 EFX_LOOPBACK_GMAC = 2,
905 EFX_LOOPBACK_XGMII = 3,
906 EFX_LOOPBACK_XGXS = 4,
907 EFX_LOOPBACK_XAUI = 5,
908 EFX_LOOPBACK_GMII = 6,
909 EFX_LOOPBACK_SGMII = 7,
910 EFX_LOOPBACK_XGBR = 8,
911 EFX_LOOPBACK_XFI = 9,
912 EFX_LOOPBACK_XAUI_FAR = 10,
913 EFX_LOOPBACK_GMII_FAR = 11,
914 EFX_LOOPBACK_SGMII_FAR = 12,
915 EFX_LOOPBACK_XFI_FAR = 13,
916 EFX_LOOPBACK_GPHY = 14,
917 EFX_LOOPBACK_PHY_XS = 15,
918 EFX_LOOPBACK_PCS = 16,
919 EFX_LOOPBACK_PMA_PMD = 17,
920 EFX_LOOPBACK_XPORT = 18,
921 EFX_LOOPBACK_XGMII_WS = 19,
922 EFX_LOOPBACK_XAUI_WS = 20,
923 EFX_LOOPBACK_XAUI_WS_FAR = 21,
924 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
925 EFX_LOOPBACK_GMII_WS = 23,
926 EFX_LOOPBACK_XFI_WS = 24,
927 EFX_LOOPBACK_XFI_WS_FAR = 25,
928 EFX_LOOPBACK_PHYXS_WS = 26,
929 EFX_LOOPBACK_PMA_INT = 27,
930 EFX_LOOPBACK_SD_NEAR = 28,
931 EFX_LOOPBACK_SD_FAR = 29,
932 EFX_LOOPBACK_PMA_INT_WS = 30,
933 EFX_LOOPBACK_SD_FEP2_WS = 31,
934 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
935 EFX_LOOPBACK_SD_FEP_WS = 33,
936 EFX_LOOPBACK_SD_FES_WS = 34,
937 EFX_LOOPBACK_AOE_INT_NEAR = 35,
938 EFX_LOOPBACK_DATA_WS = 36,
939 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
941 } efx_loopback_type_t;
943 typedef enum efx_loopback_kind_e {
944 EFX_LOOPBACK_KIND_OFF = 0,
945 EFX_LOOPBACK_KIND_ALL,
946 EFX_LOOPBACK_KIND_MAC,
947 EFX_LOOPBACK_KIND_PHY,
949 } efx_loopback_kind_t;
953 __in efx_loopback_kind_t loopback_kind,
954 __out efx_qword_t *maskp);
956 extern __checkReturn efx_rc_t
957 efx_port_loopback_set(
959 __in efx_link_mode_t link_mode,
960 __in efx_loopback_type_t type);
964 extern __checkReturn const char *
965 efx_loopback_type_name(
967 __in efx_loopback_type_t type);
969 #endif /* EFSYS_OPT_NAMES */
971 #endif /* EFSYS_OPT_LOOPBACK */
973 extern __checkReturn efx_rc_t
976 __out_opt efx_link_mode_t *link_modep);
980 __in efx_nic_t *enp);
982 typedef enum efx_phy_cap_type_e {
983 EFX_PHY_CAP_INVALID = 0,
990 EFX_PHY_CAP_10000FDX,
994 EFX_PHY_CAP_40000FDX,
996 EFX_PHY_CAP_100000FDX,
997 EFX_PHY_CAP_25000FDX,
998 EFX_PHY_CAP_50000FDX,
999 EFX_PHY_CAP_BASER_FEC,
1000 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1002 EFX_PHY_CAP_RS_FEC_REQUESTED,
1003 EFX_PHY_CAP_25G_BASER_FEC,
1004 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1006 } efx_phy_cap_type_t;
1009 #define EFX_PHY_CAP_CURRENT 0x00000000
1010 #define EFX_PHY_CAP_DEFAULT 0x00000001
1011 #define EFX_PHY_CAP_PERM 0x00000002
1014 efx_phy_adv_cap_get(
1015 __in efx_nic_t *enp,
1017 __out uint32_t *maskp);
1019 extern __checkReturn efx_rc_t
1020 efx_phy_adv_cap_set(
1021 __in efx_nic_t *enp,
1022 __in uint32_t mask);
1026 __in efx_nic_t *enp,
1027 __out uint32_t *maskp);
1029 extern __checkReturn efx_rc_t
1031 __in efx_nic_t *enp,
1032 __out uint32_t *ouip);
1034 typedef enum efx_phy_media_type_e {
1035 EFX_PHY_MEDIA_INVALID = 0,
1040 EFX_PHY_MEDIA_SFP_PLUS,
1041 EFX_PHY_MEDIA_BASE_T,
1042 EFX_PHY_MEDIA_QSFP_PLUS,
1043 EFX_PHY_MEDIA_NTYPES
1044 } efx_phy_media_type_t;
1047 * Get the type of medium currently used. If the board has ports for
1048 * modules, a module is present, and we recognise the media type of
1049 * the module, then this will be the media type of the module.
1050 * Otherwise it will be the media type of the port.
1053 efx_phy_media_type_get(
1054 __in efx_nic_t *enp,
1055 __out efx_phy_media_type_t *typep);
1057 extern __checkReturn efx_rc_t
1058 efx_phy_module_get_info(
1059 __in efx_nic_t *enp,
1060 __in uint8_t dev_addr,
1061 __in uint8_t offset,
1063 __out_bcount(len) uint8_t *data);
1065 #if EFSYS_OPT_PHY_STATS
1067 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1068 typedef enum efx_phy_stat_e {
1070 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1071 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1072 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1073 EFX_PHY_STAT_PMA_PMD_REV_A,
1074 EFX_PHY_STAT_PMA_PMD_REV_B,
1075 EFX_PHY_STAT_PMA_PMD_REV_C,
1076 EFX_PHY_STAT_PMA_PMD_REV_D,
1077 EFX_PHY_STAT_PCS_LINK_UP,
1078 EFX_PHY_STAT_PCS_RX_FAULT,
1079 EFX_PHY_STAT_PCS_TX_FAULT,
1080 EFX_PHY_STAT_PCS_BER,
1081 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1082 EFX_PHY_STAT_PHY_XS_LINK_UP,
1083 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1084 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1085 EFX_PHY_STAT_PHY_XS_ALIGN,
1086 EFX_PHY_STAT_PHY_XS_SYNC_A,
1087 EFX_PHY_STAT_PHY_XS_SYNC_B,
1088 EFX_PHY_STAT_PHY_XS_SYNC_C,
1089 EFX_PHY_STAT_PHY_XS_SYNC_D,
1090 EFX_PHY_STAT_AN_LINK_UP,
1091 EFX_PHY_STAT_AN_MASTER,
1092 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1093 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1094 EFX_PHY_STAT_CL22EXT_LINK_UP,
1099 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1100 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1101 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1102 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1103 EFX_PHY_STAT_AN_COMPLETE,
1104 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1105 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1106 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1107 EFX_PHY_STAT_PCS_FW_VERSION_0,
1108 EFX_PHY_STAT_PCS_FW_VERSION_1,
1109 EFX_PHY_STAT_PCS_FW_VERSION_2,
1110 EFX_PHY_STAT_PCS_FW_VERSION_3,
1111 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1112 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1113 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1114 EFX_PHY_STAT_PCS_OP_MODE,
1118 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1124 __in efx_nic_t *enp,
1125 __in efx_phy_stat_t stat);
1127 #endif /* EFSYS_OPT_NAMES */
1129 #define EFX_PHY_STATS_SIZE 0x100
1131 extern __checkReturn efx_rc_t
1132 efx_phy_stats_update(
1133 __in efx_nic_t *enp,
1134 __in efsys_mem_t *esmp,
1135 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1137 #endif /* EFSYS_OPT_PHY_STATS */
1142 typedef enum efx_bist_type_e {
1143 EFX_BIST_TYPE_UNKNOWN,
1144 EFX_BIST_TYPE_PHY_NORMAL,
1145 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1146 EFX_BIST_TYPE_PHY_CABLE_LONG,
1147 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1148 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1149 EFX_BIST_TYPE_REG, /* Test the register memories */
1150 EFX_BIST_TYPE_NTYPES,
1153 typedef enum efx_bist_result_e {
1154 EFX_BIST_RESULT_UNKNOWN,
1155 EFX_BIST_RESULT_RUNNING,
1156 EFX_BIST_RESULT_PASSED,
1157 EFX_BIST_RESULT_FAILED,
1158 } efx_bist_result_t;
1160 typedef enum efx_phy_cable_status_e {
1161 EFX_PHY_CABLE_STATUS_OK,
1162 EFX_PHY_CABLE_STATUS_INVALID,
1163 EFX_PHY_CABLE_STATUS_OPEN,
1164 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1165 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1166 EFX_PHY_CABLE_STATUS_BUSY,
1167 } efx_phy_cable_status_t;
1169 typedef enum efx_bist_value_e {
1170 EFX_BIST_PHY_CABLE_LENGTH_A,
1171 EFX_BIST_PHY_CABLE_LENGTH_B,
1172 EFX_BIST_PHY_CABLE_LENGTH_C,
1173 EFX_BIST_PHY_CABLE_LENGTH_D,
1174 EFX_BIST_PHY_CABLE_STATUS_A,
1175 EFX_BIST_PHY_CABLE_STATUS_B,
1176 EFX_BIST_PHY_CABLE_STATUS_C,
1177 EFX_BIST_PHY_CABLE_STATUS_D,
1178 EFX_BIST_FAULT_CODE,
1180 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1186 EFX_BIST_MEM_EXPECT,
1187 EFX_BIST_MEM_ACTUAL,
1189 EFX_BIST_MEM_ECC_PARITY,
1190 EFX_BIST_MEM_ECC_FATAL,
1194 extern __checkReturn efx_rc_t
1195 efx_bist_enable_offline(
1196 __in efx_nic_t *enp);
1198 extern __checkReturn efx_rc_t
1200 __in efx_nic_t *enp,
1201 __in efx_bist_type_t type);
1203 extern __checkReturn efx_rc_t
1205 __in efx_nic_t *enp,
1206 __in efx_bist_type_t type,
1207 __out efx_bist_result_t *resultp,
1208 __out_opt uint32_t *value_maskp,
1209 __out_ecount_opt(count) unsigned long *valuesp,
1214 __in efx_nic_t *enp,
1215 __in efx_bist_type_t type);
1217 #endif /* EFSYS_OPT_BIST */
1219 #define EFX_FEATURE_IPV6 0x00000001
1220 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1221 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1222 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1223 #define EFX_FEATURE_MCDI 0x00000020
1224 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1225 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1226 #define EFX_FEATURE_TURBO 0x00000100
1227 #define EFX_FEATURE_MCDI_DMA 0x00000200
1228 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1229 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1230 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1231 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1232 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1234 typedef enum efx_tunnel_protocol_e {
1235 EFX_TUNNEL_PROTOCOL_NONE = 0,
1236 EFX_TUNNEL_PROTOCOL_VXLAN,
1237 EFX_TUNNEL_PROTOCOL_GENEVE,
1238 EFX_TUNNEL_PROTOCOL_NVGRE,
1240 } efx_tunnel_protocol_t;
1242 typedef enum efx_vi_window_shift_e {
1243 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1244 EFX_VI_WINDOW_SHIFT_8K = 13,
1245 EFX_VI_WINDOW_SHIFT_16K = 14,
1246 EFX_VI_WINDOW_SHIFT_64K = 16,
1247 } efx_vi_window_shift_t;
1249 typedef struct efx_nic_cfg_s {
1250 uint32_t enc_board_type;
1251 uint32_t enc_phy_type;
1253 char enc_phy_name[21];
1255 char enc_phy_revision[21];
1256 efx_mon_type_t enc_mon_type;
1257 #if EFSYS_OPT_MON_STATS
1258 uint32_t enc_mon_stat_dma_buf_size;
1259 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1261 unsigned int enc_features;
1262 efx_vi_window_shift_t enc_vi_window_shift;
1263 uint8_t enc_mac_addr[6];
1264 uint8_t enc_port; /* PHY port number */
1265 uint32_t enc_intr_vec_base;
1266 uint32_t enc_intr_limit;
1267 uint32_t enc_evq_limit;
1268 uint32_t enc_txq_limit;
1269 uint32_t enc_rxq_limit;
1270 uint32_t enc_txq_max_ndescs;
1271 uint32_t enc_buftbl_limit;
1272 uint32_t enc_piobuf_limit;
1273 uint32_t enc_piobuf_size;
1274 uint32_t enc_piobuf_min_alloc_size;
1275 uint32_t enc_evq_timer_quantum_ns;
1276 uint32_t enc_evq_timer_max_us;
1277 uint32_t enc_clk_mult;
1278 uint32_t enc_rx_prefix_size;
1279 uint32_t enc_rx_buf_align_start;
1280 uint32_t enc_rx_buf_align_end;
1281 uint32_t enc_rx_scale_max_exclusive_contexts;
1283 * Mask of supported hash algorithms.
1284 * Hash algorithm types are used as the bit indices.
1286 uint32_t enc_rx_scale_hash_alg_mask;
1288 * Indicates whether port numbers can be included to the
1289 * input data for hash computation.
1291 boolean_t enc_rx_scale_l4_hash_supported;
1292 boolean_t enc_rx_scale_additional_modes_supported;
1293 #if EFSYS_OPT_LOOPBACK
1294 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1295 #endif /* EFSYS_OPT_LOOPBACK */
1296 #if EFSYS_OPT_PHY_FLAGS
1297 uint32_t enc_phy_flags_mask;
1298 #endif /* EFSYS_OPT_PHY_FLAGS */
1299 #if EFSYS_OPT_PHY_LED_CONTROL
1300 uint32_t enc_led_mask;
1301 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1302 #if EFSYS_OPT_PHY_STATS
1303 uint64_t enc_phy_stat_mask;
1304 #endif /* EFSYS_OPT_PHY_STATS */
1306 uint8_t enc_mcdi_mdio_channel;
1307 #if EFSYS_OPT_PHY_STATS
1308 uint32_t enc_mcdi_phy_stat_mask;
1309 #endif /* EFSYS_OPT_PHY_STATS */
1310 #if EFSYS_OPT_MON_STATS
1311 uint32_t *enc_mcdi_sensor_maskp;
1312 uint32_t enc_mcdi_sensor_mask_size;
1313 #endif /* EFSYS_OPT_MON_STATS */
1314 #endif /* EFSYS_OPT_MCDI */
1316 uint32_t enc_bist_mask;
1317 #endif /* EFSYS_OPT_BIST */
1318 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1321 uint32_t enc_privilege_mask;
1322 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1323 boolean_t enc_bug26807_workaround;
1324 boolean_t enc_bug35388_workaround;
1325 boolean_t enc_bug41750_workaround;
1326 boolean_t enc_bug61265_workaround;
1327 boolean_t enc_bug61297_workaround;
1328 boolean_t enc_rx_batching_enabled;
1329 /* Maximum number of descriptors completed in an rx event. */
1330 uint32_t enc_rx_batch_max;
1331 /* Number of rx descriptors the hardware requires for a push. */
1332 uint32_t enc_rx_push_align;
1333 /* Maximum amount of data in DMA descriptor */
1334 uint32_t enc_tx_dma_desc_size_max;
1336 * Boundary which DMA descriptor data must not cross or 0 if no
1339 uint32_t enc_tx_dma_desc_boundary;
1341 * Maximum number of bytes into the packet the TCP header can start for
1342 * the hardware to apply TSO packet edits.
1344 uint32_t enc_tx_tso_tcp_header_offset_limit;
1345 boolean_t enc_fw_assisted_tso_enabled;
1346 boolean_t enc_fw_assisted_tso_v2_enabled;
1347 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1348 /* Number of TSO contexts on the NIC (FATSOv2) */
1349 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1350 boolean_t enc_hw_tx_insert_vlan_enabled;
1351 /* Number of PFs on the NIC */
1352 uint32_t enc_hw_pf_count;
1353 /* Datapath firmware vadapter/vport/vswitch support */
1354 boolean_t enc_datapath_cap_evb;
1355 boolean_t enc_rx_disable_scatter_supported;
1356 boolean_t enc_allow_set_mac_with_installed_filters;
1357 boolean_t enc_enhanced_set_mac_supported;
1358 boolean_t enc_init_evq_v2_supported;
1359 boolean_t enc_rx_packed_stream_supported;
1360 boolean_t enc_rx_var_packed_stream_supported;
1361 boolean_t enc_rx_es_super_buffer_supported;
1362 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1363 boolean_t enc_pm_and_rxdp_counters;
1364 boolean_t enc_mac_stats_40g_tx_size_bins;
1365 uint32_t enc_tunnel_encapsulations_supported;
1367 * NIC global maximum for unique UDP tunnel ports shared by all
1370 uint32_t enc_tunnel_config_udp_entries_max;
1371 /* External port identifier */
1372 uint8_t enc_external_port;
1373 uint32_t enc_mcdi_max_payload_length;
1374 /* VPD may be per-PF or global */
1375 boolean_t enc_vpd_is_global;
1376 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1377 uint32_t enc_required_pcie_bandwidth_mbps;
1378 uint32_t enc_max_pcie_link_gen;
1379 /* Firmware verifies integrity of NVRAM updates */
1380 uint32_t enc_nvram_update_verify_result_supported;
1381 /* Firmware support for extended MAC_STATS buffer */
1382 uint32_t enc_mac_stats_nstats;
1383 boolean_t enc_fec_counters;
1384 boolean_t enc_hlb_counters;
1385 /* Firmware support for "FLAG" and "MARK" filter actions */
1386 boolean_t enc_filter_action_flag_supported;
1387 boolean_t enc_filter_action_mark_supported;
1388 uint32_t enc_filter_action_mark_max;
1391 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1392 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1394 #define EFX_PCI_FUNCTION(_encp) \
1395 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1397 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1399 extern const efx_nic_cfg_t *
1401 __in efx_nic_t *enp);
1403 /* RxDPCPU firmware id values by which FW variant can be identified */
1404 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1405 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1406 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1407 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1408 #define EFX_RXDP_DPDK_FW_ID 0x6
1410 typedef struct efx_nic_fw_info_s {
1411 /* Basic FW version information */
1412 uint16_t enfi_mc_fw_version[4];
1414 * If datapath capabilities can be detected,
1415 * additional FW information is to be shown
1417 boolean_t enfi_dpcpu_fw_ids_valid;
1418 /* Rx and Tx datapath CPU FW IDs */
1419 uint16_t enfi_rx_dpcpu_fw_id;
1420 uint16_t enfi_tx_dpcpu_fw_id;
1421 } efx_nic_fw_info_t;
1423 extern __checkReturn efx_rc_t
1424 efx_nic_get_fw_version(
1425 __in efx_nic_t *enp,
1426 __out efx_nic_fw_info_t *enfip);
1428 /* Driver resource limits (minimum required/maximum usable). */
1429 typedef struct efx_drv_limits_s {
1430 uint32_t edl_min_evq_count;
1431 uint32_t edl_max_evq_count;
1433 uint32_t edl_min_rxq_count;
1434 uint32_t edl_max_rxq_count;
1436 uint32_t edl_min_txq_count;
1437 uint32_t edl_max_txq_count;
1439 /* PIO blocks (sub-allocated from piobuf) */
1440 uint32_t edl_min_pio_alloc_size;
1441 uint32_t edl_max_pio_alloc_count;
1444 extern __checkReturn efx_rc_t
1445 efx_nic_set_drv_limits(
1446 __inout efx_nic_t *enp,
1447 __in efx_drv_limits_t *edlp);
1449 typedef enum efx_nic_region_e {
1450 EFX_REGION_VI, /* Memory BAR UC mapping */
1451 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1454 extern __checkReturn efx_rc_t
1455 efx_nic_get_bar_region(
1456 __in efx_nic_t *enp,
1457 __in efx_nic_region_t region,
1458 __out uint32_t *offsetp,
1459 __out size_t *sizep);
1461 extern __checkReturn efx_rc_t
1462 efx_nic_get_vi_pool(
1463 __in efx_nic_t *enp,
1464 __out uint32_t *evq_countp,
1465 __out uint32_t *rxq_countp,
1466 __out uint32_t *txq_countp);
1471 typedef enum efx_vpd_tag_e {
1478 typedef uint16_t efx_vpd_keyword_t;
1480 typedef struct efx_vpd_value_s {
1481 efx_vpd_tag_t evv_tag;
1482 efx_vpd_keyword_t evv_keyword;
1484 uint8_t evv_value[0x100];
1488 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1490 extern __checkReturn efx_rc_t
1492 __in efx_nic_t *enp);
1494 extern __checkReturn efx_rc_t
1496 __in efx_nic_t *enp,
1497 __out size_t *sizep);
1499 extern __checkReturn efx_rc_t
1501 __in efx_nic_t *enp,
1502 __out_bcount(size) caddr_t data,
1505 extern __checkReturn efx_rc_t
1507 __in efx_nic_t *enp,
1508 __in_bcount(size) caddr_t data,
1511 extern __checkReturn efx_rc_t
1513 __in efx_nic_t *enp,
1514 __in_bcount(size) caddr_t data,
1517 extern __checkReturn efx_rc_t
1519 __in efx_nic_t *enp,
1520 __in_bcount(size) caddr_t data,
1522 __inout efx_vpd_value_t *evvp);
1524 extern __checkReturn efx_rc_t
1526 __in efx_nic_t *enp,
1527 __inout_bcount(size) caddr_t data,
1529 __in efx_vpd_value_t *evvp);
1531 extern __checkReturn efx_rc_t
1533 __in efx_nic_t *enp,
1534 __inout_bcount(size) caddr_t data,
1536 __out efx_vpd_value_t *evvp,
1537 __inout unsigned int *contp);
1539 extern __checkReturn efx_rc_t
1541 __in efx_nic_t *enp,
1542 __in_bcount(size) caddr_t data,
1547 __in efx_nic_t *enp);
1549 #endif /* EFSYS_OPT_VPD */
1555 typedef enum efx_nvram_type_e {
1556 EFX_NVRAM_INVALID = 0,
1558 EFX_NVRAM_BOOTROM_CFG,
1559 EFX_NVRAM_MC_FIRMWARE,
1560 EFX_NVRAM_MC_GOLDEN,
1566 EFX_NVRAM_FPGA_BACKUP,
1567 EFX_NVRAM_DYNAMIC_CFG,
1570 EFX_NVRAM_MUM_FIRMWARE,
1571 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1572 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1576 extern __checkReturn efx_rc_t
1578 __in efx_nic_t *enp);
1582 extern __checkReturn efx_rc_t
1584 __in efx_nic_t *enp);
1586 #endif /* EFSYS_OPT_DIAG */
1588 extern __checkReturn efx_rc_t
1590 __in efx_nic_t *enp,
1591 __in efx_nvram_type_t type,
1592 __out size_t *sizep);
1594 extern __checkReturn efx_rc_t
1596 __in efx_nic_t *enp,
1597 __in efx_nvram_type_t type,
1598 __out_opt size_t *pref_chunkp);
1600 extern __checkReturn efx_rc_t
1601 efx_nvram_rw_finish(
1602 __in efx_nic_t *enp,
1603 __in efx_nvram_type_t type,
1604 __out_opt uint32_t *verify_resultp);
1606 extern __checkReturn efx_rc_t
1607 efx_nvram_get_version(
1608 __in efx_nic_t *enp,
1609 __in efx_nvram_type_t type,
1610 __out uint32_t *subtypep,
1611 __out_ecount(4) uint16_t version[4]);
1613 extern __checkReturn efx_rc_t
1614 efx_nvram_read_chunk(
1615 __in efx_nic_t *enp,
1616 __in efx_nvram_type_t type,
1617 __in unsigned int offset,
1618 __out_bcount(size) caddr_t data,
1621 extern __checkReturn efx_rc_t
1622 efx_nvram_read_backup(
1623 __in efx_nic_t *enp,
1624 __in efx_nvram_type_t type,
1625 __in unsigned int offset,
1626 __out_bcount(size) caddr_t data,
1629 extern __checkReturn efx_rc_t
1630 efx_nvram_set_version(
1631 __in efx_nic_t *enp,
1632 __in efx_nvram_type_t type,
1633 __in_ecount(4) uint16_t version[4]);
1635 extern __checkReturn efx_rc_t
1637 __in efx_nic_t *enp,
1638 __in efx_nvram_type_t type,
1639 __in_bcount(partn_size) caddr_t partn_data,
1640 __in size_t partn_size);
1642 extern __checkReturn efx_rc_t
1644 __in efx_nic_t *enp,
1645 __in efx_nvram_type_t type);
1647 extern __checkReturn efx_rc_t
1648 efx_nvram_write_chunk(
1649 __in efx_nic_t *enp,
1650 __in efx_nvram_type_t type,
1651 __in unsigned int offset,
1652 __in_bcount(size) caddr_t data,
1657 __in efx_nic_t *enp);
1659 #endif /* EFSYS_OPT_NVRAM */
1661 #if EFSYS_OPT_BOOTCFG
1663 /* Report size and offset of bootcfg sector in NVRAM partition. */
1664 extern __checkReturn efx_rc_t
1665 efx_bootcfg_sector_info(
1666 __in efx_nic_t *enp,
1668 __out_opt uint32_t *sector_countp,
1669 __out size_t *offsetp,
1670 __out size_t *max_sizep);
1673 * Copy bootcfg sector data to a target buffer which may differ in size.
1674 * Optionally corrects format errors in source buffer.
1677 efx_bootcfg_copy_sector(
1678 __in efx_nic_t *enp,
1679 __inout_bcount(sector_length)
1681 __in size_t sector_length,
1682 __out_bcount(data_size) uint8_t *data,
1683 __in size_t data_size,
1684 __in boolean_t handle_format_errors);
1688 __in efx_nic_t *enp,
1689 __out_bcount(size) uint8_t *data,
1694 __in efx_nic_t *enp,
1695 __in_bcount(size) uint8_t *data,
1700 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1701 * (see https://tools.ietf.org/html/rfc1533)
1703 * Summarising the format: the buffer is a sequence of options. All options
1704 * begin with a tag octet, which uniquely identifies the option. Fixed-
1705 * length options without data consist of only a tag octet. Only options PAD
1706 * (0) and END (255) are fixed length. All other options are variable-length
1707 * with a length octet following the tag octet. The value of the length
1708 * octet does not include the two octets specifying the tag and length. The
1709 * length octet is followed by "length" octets of data.
1711 * Option data may be a sequence of sub-options in the same format. The data
1712 * content of the encapsulating option is one or more encapsulated sub-options,
1713 * with no terminating END tag is required.
1715 * To be valid, the top-level sequence of options should be terminated by an
1716 * END tag. The buffer should be padded with the PAD byte.
1718 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1719 * checksum octet. The full buffer (including after the END tag) contributes
1720 * to the checksum, hence the need to fill the buffer to the end with PAD.
1723 #define EFX_DHCP_END ((uint8_t)0xff)
1724 #define EFX_DHCP_PAD ((uint8_t)0)
1726 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1727 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1729 extern __checkReturn uint8_t
1731 __in_bcount(size) uint8_t const *data,
1734 extern __checkReturn efx_rc_t
1736 __in_bcount(size) uint8_t const *data,
1738 __out_opt size_t *usedp);
1740 extern __checkReturn efx_rc_t
1742 __in_bcount(buffer_length) uint8_t *bufferp,
1743 __in size_t buffer_length,
1745 __deref_out uint8_t **valuepp,
1746 __out size_t *value_lengthp);
1748 extern __checkReturn efx_rc_t
1750 __in_bcount(buffer_length) uint8_t *bufferp,
1751 __in size_t buffer_length,
1752 __deref_out uint8_t **endpp);
1755 extern __checkReturn efx_rc_t
1756 efx_dhcp_delete_tag(
1757 __inout_bcount(buffer_length) uint8_t *bufferp,
1758 __in size_t buffer_length,
1761 extern __checkReturn efx_rc_t
1763 __inout_bcount(buffer_length) uint8_t *bufferp,
1764 __in size_t buffer_length,
1766 __in_bcount_opt(value_length) uint8_t *valuep,
1767 __in size_t value_length);
1769 extern __checkReturn efx_rc_t
1770 efx_dhcp_update_tag(
1771 __inout_bcount(buffer_length) uint8_t *bufferp,
1772 __in size_t buffer_length,
1774 __in uint8_t *value_locationp,
1775 __in_bcount_opt(value_length) uint8_t *valuep,
1776 __in size_t value_length);
1779 #endif /* EFSYS_OPT_BOOTCFG */
1781 #if EFSYS_OPT_IMAGE_LAYOUT
1783 #include "ef10_signed_image_layout.h"
1786 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1789 * The image header format is extensible. However, older drivers require an
1790 * exact match of image header version and header length when validating and
1791 * writing firmware images.
1793 * To avoid breaking backward compatibility, we use the upper bits of the
1794 * controller version fields to contain an extra version number used for
1795 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1796 * version). See bug39254 and SF-102785-PS for details.
1798 typedef struct efx_image_header_s {
1800 uint32_t eih_version;
1802 uint32_t eih_subtype;
1803 uint32_t eih_code_size;
1806 uint32_t eih_controller_version_min;
1808 uint16_t eih_controller_version_min_short;
1809 uint8_t eih_extra_version_a;
1810 uint8_t eih_extra_version_b;
1814 uint32_t eih_controller_version_max;
1816 uint16_t eih_controller_version_max_short;
1817 uint8_t eih_extra_version_c;
1818 uint8_t eih_extra_version_d;
1821 uint16_t eih_code_version_a;
1822 uint16_t eih_code_version_b;
1823 uint16_t eih_code_version_c;
1824 uint16_t eih_code_version_d;
1825 } efx_image_header_t;
1827 #define EFX_IMAGE_HEADER_SIZE (40)
1828 #define EFX_IMAGE_HEADER_VERSION (4)
1829 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1832 typedef struct efx_image_trailer_s {
1834 } efx_image_trailer_t;
1836 #define EFX_IMAGE_TRAILER_SIZE (4)
1838 typedef enum efx_image_format_e {
1839 EFX_IMAGE_FORMAT_NO_IMAGE,
1840 EFX_IMAGE_FORMAT_INVALID,
1841 EFX_IMAGE_FORMAT_UNSIGNED,
1842 EFX_IMAGE_FORMAT_SIGNED,
1843 } efx_image_format_t;
1845 typedef struct efx_image_info_s {
1846 efx_image_format_t eii_format;
1847 uint8_t * eii_imagep;
1848 size_t eii_image_size;
1849 efx_image_header_t * eii_headerp;
1852 extern __checkReturn efx_rc_t
1853 efx_check_reflash_image(
1855 __in uint32_t buffer_size,
1856 __out efx_image_info_t *infop);
1858 extern __checkReturn efx_rc_t
1859 efx_build_signed_image_write_buffer(
1860 __out_bcount(buffer_size)
1862 __in uint32_t buffer_size,
1863 __in efx_image_info_t *infop,
1864 __out efx_image_header_t **headerpp);
1866 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1870 typedef enum efx_pattern_type_t {
1871 EFX_PATTERN_BYTE_INCREMENT = 0,
1872 EFX_PATTERN_ALL_THE_SAME,
1873 EFX_PATTERN_BIT_ALTERNATE,
1874 EFX_PATTERN_BYTE_ALTERNATE,
1875 EFX_PATTERN_BYTE_CHANGING,
1876 EFX_PATTERN_BIT_SWEEP,
1878 } efx_pattern_type_t;
1881 (*efx_sram_pattern_fn_t)(
1883 __in boolean_t negate,
1884 __out efx_qword_t *eqp);
1886 extern __checkReturn efx_rc_t
1888 __in efx_nic_t *enp,
1889 __in efx_pattern_type_t type);
1891 #endif /* EFSYS_OPT_DIAG */
1893 extern __checkReturn efx_rc_t
1894 efx_sram_buf_tbl_set(
1895 __in efx_nic_t *enp,
1897 __in efsys_mem_t *esmp,
1901 efx_sram_buf_tbl_clear(
1902 __in efx_nic_t *enp,
1906 #define EFX_BUF_TBL_SIZE 0x20000
1908 #define EFX_BUF_SIZE 4096
1912 typedef struct efx_evq_s efx_evq_t;
1914 #if EFSYS_OPT_QSTATS
1916 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1917 typedef enum efx_ev_qstat_e {
1923 EV_RX_PAUSE_FRM_ERR,
1924 EV_RX_BUF_OWNER_ID_ERR,
1925 EV_RX_IPV4_HDR_CHKSUM_ERR,
1926 EV_RX_TCP_UDP_CHKSUM_ERR,
1930 EV_RX_MCAST_HASH_MATCH,
1947 EV_DRIVER_SRM_UPD_DONE,
1948 EV_DRIVER_TX_DESCQ_FLS_DONE,
1949 EV_DRIVER_RX_DESCQ_FLS_DONE,
1950 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1951 EV_DRIVER_RX_DSC_ERROR,
1952 EV_DRIVER_TX_DSC_ERROR,
1958 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1960 #endif /* EFSYS_OPT_QSTATS */
1962 extern __checkReturn efx_rc_t
1964 __in efx_nic_t *enp);
1968 __in efx_nic_t *enp);
1970 #define EFX_EVQ_MAXNEVS 32768
1971 #define EFX_EVQ_MINNEVS 512
1973 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1974 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1976 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1977 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1978 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1979 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1981 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1982 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1983 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1985 extern __checkReturn efx_rc_t
1987 __in efx_nic_t *enp,
1988 __in unsigned int index,
1989 __in efsys_mem_t *esmp,
1993 __in uint32_t flags,
1994 __deref_out efx_evq_t **eepp);
1998 __in efx_evq_t *eep,
1999 __in uint16_t data);
2001 typedef __checkReturn boolean_t
2002 (*efx_initialized_ev_t)(
2003 __in_opt void *arg);
2005 #define EFX_PKT_UNICAST 0x0004
2006 #define EFX_PKT_START 0x0008
2008 #define EFX_PKT_VLAN_TAGGED 0x0010
2009 #define EFX_CKSUM_TCPUDP 0x0020
2010 #define EFX_CKSUM_IPV4 0x0040
2011 #define EFX_PKT_CONT 0x0080
2013 #define EFX_CHECK_VLAN 0x0100
2014 #define EFX_PKT_TCP 0x0200
2015 #define EFX_PKT_UDP 0x0400
2016 #define EFX_PKT_IPV4 0x0800
2018 #define EFX_PKT_IPV6 0x1000
2019 #define EFX_PKT_PREFIX_LEN 0x2000
2020 #define EFX_ADDR_MISMATCH 0x4000
2021 #define EFX_DISCARD 0x8000
2024 * The following flags are used only for packed stream
2025 * mode. The values for the flags are reused to fit into 16 bit,
2026 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2027 * packed stream mode
2029 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2030 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2033 #define EFX_EV_RX_NLABELS 32
2034 #define EFX_EV_TX_NLABELS 32
2036 typedef __checkReturn boolean_t
2039 __in uint32_t label,
2042 __in uint16_t flags);
2044 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2047 * Packed stream mode is documented in SF-112241-TC.
2048 * The general idea is that, instead of putting each incoming
2049 * packet into a separate buffer which is specified in a RX
2050 * descriptor, a large buffer is provided to the hardware and
2051 * packets are put there in a continuous stream.
2052 * The main advantage of such an approach is that RX queue refilling
2053 * happens much less frequently.
2055 * Equal stride packed stream mode is documented in SF-119419-TC.
2056 * The general idea is to utilize advantages of the packed stream,
2057 * but avoid indirection in packets representation.
2058 * The main advantage of such an approach is that RX queue refilling
2059 * happens much less frequently and packets buffers are independent
2060 * from upper layers point of view.
2063 typedef __checkReturn boolean_t
2066 __in uint32_t label,
2068 __in uint32_t pkt_count,
2069 __in uint16_t flags);
2073 typedef __checkReturn boolean_t
2076 __in uint32_t label,
2079 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2080 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2081 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2082 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2083 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2084 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2085 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2086 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2087 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2089 typedef __checkReturn boolean_t
2090 (*efx_exception_ev_t)(
2092 __in uint32_t label,
2093 __in uint32_t data);
2095 typedef __checkReturn boolean_t
2096 (*efx_rxq_flush_done_ev_t)(
2098 __in uint32_t rxq_index);
2100 typedef __checkReturn boolean_t
2101 (*efx_rxq_flush_failed_ev_t)(
2103 __in uint32_t rxq_index);
2105 typedef __checkReturn boolean_t
2106 (*efx_txq_flush_done_ev_t)(
2108 __in uint32_t txq_index);
2110 typedef __checkReturn boolean_t
2111 (*efx_software_ev_t)(
2113 __in uint16_t magic);
2115 typedef __checkReturn boolean_t
2118 __in uint32_t code);
2120 #define EFX_SRAM_CLEAR 0
2121 #define EFX_SRAM_UPDATE 1
2122 #define EFX_SRAM_ILLEGAL_CLEAR 2
2124 typedef __checkReturn boolean_t
2125 (*efx_wake_up_ev_t)(
2127 __in uint32_t label);
2129 typedef __checkReturn boolean_t
2132 __in uint32_t label);
2134 typedef __checkReturn boolean_t
2135 (*efx_link_change_ev_t)(
2137 __in efx_link_mode_t link_mode);
2139 #if EFSYS_OPT_MON_STATS
2141 typedef __checkReturn boolean_t
2142 (*efx_monitor_ev_t)(
2144 __in efx_mon_stat_t id,
2145 __in efx_mon_stat_value_t value);
2147 #endif /* EFSYS_OPT_MON_STATS */
2149 #if EFSYS_OPT_MAC_STATS
2151 typedef __checkReturn boolean_t
2152 (*efx_mac_stats_ev_t)(
2154 __in uint32_t generation);
2156 #endif /* EFSYS_OPT_MAC_STATS */
2158 typedef struct efx_ev_callbacks_s {
2159 efx_initialized_ev_t eec_initialized;
2161 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2162 efx_rx_ps_ev_t eec_rx_ps;
2165 efx_exception_ev_t eec_exception;
2166 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2167 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2168 efx_txq_flush_done_ev_t eec_txq_flush_done;
2169 efx_software_ev_t eec_software;
2170 efx_sram_ev_t eec_sram;
2171 efx_wake_up_ev_t eec_wake_up;
2172 efx_timer_ev_t eec_timer;
2173 efx_link_change_ev_t eec_link_change;
2174 #if EFSYS_OPT_MON_STATS
2175 efx_monitor_ev_t eec_monitor;
2176 #endif /* EFSYS_OPT_MON_STATS */
2177 #if EFSYS_OPT_MAC_STATS
2178 efx_mac_stats_ev_t eec_mac_stats;
2179 #endif /* EFSYS_OPT_MAC_STATS */
2180 } efx_ev_callbacks_t;
2182 extern __checkReturn boolean_t
2184 __in efx_evq_t *eep,
2185 __in unsigned int count);
2187 #if EFSYS_OPT_EV_PREFETCH
2191 __in efx_evq_t *eep,
2192 __in unsigned int count);
2194 #endif /* EFSYS_OPT_EV_PREFETCH */
2198 __in efx_evq_t *eep,
2199 __inout unsigned int *countp,
2200 __in const efx_ev_callbacks_t *eecp,
2201 __in_opt void *arg);
2203 extern __checkReturn efx_rc_t
2204 efx_ev_usecs_to_ticks(
2205 __in efx_nic_t *enp,
2206 __in unsigned int usecs,
2207 __out unsigned int *ticksp);
2209 extern __checkReturn efx_rc_t
2211 __in efx_evq_t *eep,
2212 __in unsigned int us);
2214 extern __checkReturn efx_rc_t
2216 __in efx_evq_t *eep,
2217 __in unsigned int count);
2219 #if EFSYS_OPT_QSTATS
2225 __in efx_nic_t *enp,
2226 __in unsigned int id);
2228 #endif /* EFSYS_OPT_NAMES */
2231 efx_ev_qstats_update(
2232 __in efx_evq_t *eep,
2233 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2235 #endif /* EFSYS_OPT_QSTATS */
2239 __in efx_evq_t *eep);
2243 extern __checkReturn efx_rc_t
2245 __inout efx_nic_t *enp);
2249 __in efx_nic_t *enp);
2251 #if EFSYS_OPT_RX_SCATTER
2252 __checkReturn efx_rc_t
2253 efx_rx_scatter_enable(
2254 __in efx_nic_t *enp,
2255 __in unsigned int buf_size);
2256 #endif /* EFSYS_OPT_RX_SCATTER */
2258 /* Handle to represent use of the default RSS context. */
2259 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2261 #if EFSYS_OPT_RX_SCALE
2263 typedef enum efx_rx_hash_alg_e {
2264 EFX_RX_HASHALG_LFSR = 0,
2265 EFX_RX_HASHALG_TOEPLITZ,
2266 EFX_RX_HASHALG_PACKED_STREAM,
2268 } efx_rx_hash_alg_t;
2271 * Legacy hash type flags.
2273 * They represent standard tuples for distinct traffic classes.
2275 #define EFX_RX_HASH_IPV4 (1U << 0)
2276 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2277 #define EFX_RX_HASH_IPV6 (1U << 2)
2278 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2280 #define EFX_RX_HASH_LEGACY_MASK \
2281 (EFX_RX_HASH_IPV4 | \
2282 EFX_RX_HASH_TCPIPV4 | \
2283 EFX_RX_HASH_IPV6 | \
2284 EFX_RX_HASH_TCPIPV6)
2287 * The type of the argument used by efx_rx_scale_mode_set() to
2288 * provide a means for the client drivers to configure hashing.
2290 * A properly constructed value can either be:
2291 * - a combination of legacy flags
2292 * - a combination of EFX_RX_HASH() flags
2294 typedef unsigned int efx_rx_hash_type_t;
2296 typedef enum efx_rx_hash_support_e {
2297 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2298 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2299 } efx_rx_hash_support_t;
2301 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2302 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2303 #define EFX_MAXRSS 64 /* RX indirection entry range */
2304 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2306 typedef enum efx_rx_scale_context_type_e {
2307 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2308 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2309 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2310 } efx_rx_scale_context_type_t;
2313 * Traffic classes eligible for hash computation.
2315 * Select packet headers used in computing the receive hash.
2316 * This uses the same encoding as the RSS_MODES field of
2317 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2319 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2320 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2321 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2322 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2323 #define EFX_RX_CLASS_IPV4_LBN 16
2324 #define EFX_RX_CLASS_IPV4_WIDTH 4
2325 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2326 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2327 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2328 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2329 #define EFX_RX_CLASS_IPV6_LBN 28
2330 #define EFX_RX_CLASS_IPV6_WIDTH 4
2332 #define EFX_RX_NCLASSES 6
2335 * Ancillary flags used to construct generic hash tuples.
2336 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2338 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2339 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2340 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2341 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2344 * Generic hash tuples.
2346 * They express combinations of packet fields
2347 * which can contribute to the hash value for
2348 * a particular traffic class.
2350 #define EFX_RX_CLASS_HASH_DISABLE 0
2352 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2353 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2355 #define EFX_RX_CLASS_HASH_2TUPLE \
2356 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2357 EFX_RX_CLASS_HASH_DST_ADDR)
2359 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2360 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2361 EFX_RX_CLASS_HASH_SRC_PORT)
2363 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2364 (EFX_RX_CLASS_HASH_DST_ADDR | \
2365 EFX_RX_CLASS_HASH_DST_PORT)
2367 #define EFX_RX_CLASS_HASH_4TUPLE \
2368 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2369 EFX_RX_CLASS_HASH_DST_ADDR | \
2370 EFX_RX_CLASS_HASH_SRC_PORT | \
2371 EFX_RX_CLASS_HASH_DST_PORT)
2373 #define EFX_RX_CLASS_HASH_NTUPLES 7
2376 * Hash flag constructor.
2378 * Resulting flags encode hash tuples for specific traffic classes.
2379 * The client drivers are encouraged to use these flags to form
2380 * a hash type value.
2382 #define EFX_RX_HASH(_class, _tuple) \
2383 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2384 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2387 * The maximum number of EFX_RX_HASH() flags.
2389 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2391 extern __checkReturn efx_rc_t
2392 efx_rx_scale_hash_flags_get(
2393 __in efx_nic_t *enp,
2394 __in efx_rx_hash_alg_t hash_alg,
2395 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flagsp,
2396 __out unsigned int *nflagsp);
2398 extern __checkReturn efx_rc_t
2399 efx_rx_hash_default_support_get(
2400 __in efx_nic_t *enp,
2401 __out efx_rx_hash_support_t *supportp);
2404 extern __checkReturn efx_rc_t
2405 efx_rx_scale_default_support_get(
2406 __in efx_nic_t *enp,
2407 __out efx_rx_scale_context_type_t *typep);
2409 extern __checkReturn efx_rc_t
2410 efx_rx_scale_context_alloc(
2411 __in efx_nic_t *enp,
2412 __in efx_rx_scale_context_type_t type,
2413 __in uint32_t num_queues,
2414 __out uint32_t *rss_contextp);
2416 extern __checkReturn efx_rc_t
2417 efx_rx_scale_context_free(
2418 __in efx_nic_t *enp,
2419 __in uint32_t rss_context);
2421 extern __checkReturn efx_rc_t
2422 efx_rx_scale_mode_set(
2423 __in efx_nic_t *enp,
2424 __in uint32_t rss_context,
2425 __in efx_rx_hash_alg_t alg,
2426 __in efx_rx_hash_type_t type,
2427 __in boolean_t insert);
2429 extern __checkReturn efx_rc_t
2430 efx_rx_scale_tbl_set(
2431 __in efx_nic_t *enp,
2432 __in uint32_t rss_context,
2433 __in_ecount(n) unsigned int *table,
2436 extern __checkReturn efx_rc_t
2437 efx_rx_scale_key_set(
2438 __in efx_nic_t *enp,
2439 __in uint32_t rss_context,
2440 __in_ecount(n) uint8_t *key,
2443 extern __checkReturn uint32_t
2444 efx_pseudo_hdr_hash_get(
2445 __in efx_rxq_t *erp,
2446 __in efx_rx_hash_alg_t func,
2447 __in uint8_t *buffer);
2449 #endif /* EFSYS_OPT_RX_SCALE */
2451 extern __checkReturn efx_rc_t
2452 efx_pseudo_hdr_pkt_length_get(
2453 __in efx_rxq_t *erp,
2454 __in uint8_t *buffer,
2455 __out uint16_t *pkt_lengthp);
2457 #define EFX_RXQ_MAXNDESCS 4096
2458 #define EFX_RXQ_MINNDESCS 512
2460 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2461 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2462 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2463 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2465 typedef enum efx_rxq_type_e {
2466 EFX_RXQ_TYPE_DEFAULT,
2467 EFX_RXQ_TYPE_PACKED_STREAM,
2468 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2473 * Dummy flag to be used instead of 0 to make it clear that the argument
2474 * is receive queue flags.
2476 #define EFX_RXQ_FLAG_NONE 0x0
2477 #define EFX_RXQ_FLAG_SCATTER 0x1
2479 * If tunnels are supported and Rx event can provide information about
2480 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2481 * full-feature firmware variant running), outer classes are requested by
2482 * default. However, if the driver supports tunnels, the flag allows to
2483 * request inner classes which are required to be able to interpret inner
2484 * Rx checksum offload results.
2486 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2488 extern __checkReturn efx_rc_t
2490 __in efx_nic_t *enp,
2491 __in unsigned int index,
2492 __in unsigned int label,
2493 __in efx_rxq_type_t type,
2494 __in efsys_mem_t *esmp,
2497 __in unsigned int flags,
2498 __in efx_evq_t *eep,
2499 __deref_out efx_rxq_t **erpp);
2501 #if EFSYS_OPT_RX_PACKED_STREAM
2503 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2504 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2505 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2506 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2507 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2509 extern __checkReturn efx_rc_t
2510 efx_rx_qcreate_packed_stream(
2511 __in efx_nic_t *enp,
2512 __in unsigned int index,
2513 __in unsigned int label,
2514 __in uint32_t ps_buf_size,
2515 __in efsys_mem_t *esmp,
2517 __in efx_evq_t *eep,
2518 __deref_out efx_rxq_t **erpp);
2522 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2524 /* Maximum head-of-line block timeout in nanoseconds */
2525 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2527 extern __checkReturn efx_rc_t
2528 efx_rx_qcreate_es_super_buffer(
2529 __in efx_nic_t *enp,
2530 __in unsigned int index,
2531 __in unsigned int label,
2532 __in uint32_t n_bufs_per_desc,
2533 __in uint32_t max_dma_len,
2534 __in uint32_t buf_stride,
2535 __in uint32_t hol_block_timeout,
2536 __in efsys_mem_t *esmp,
2538 __in unsigned int flags,
2539 __in efx_evq_t *eep,
2540 __deref_out efx_rxq_t **erpp);
2544 typedef struct efx_buffer_s {
2545 efsys_dma_addr_t eb_addr;
2550 typedef struct efx_desc_s {
2556 __in efx_rxq_t *erp,
2557 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2559 __in unsigned int ndescs,
2560 __in unsigned int completed,
2561 __in unsigned int added);
2565 __in efx_rxq_t *erp,
2566 __in unsigned int added,
2567 __inout unsigned int *pushedp);
2569 #if EFSYS_OPT_RX_PACKED_STREAM
2572 efx_rx_qpush_ps_credits(
2573 __in efx_rxq_t *erp);
2575 extern __checkReturn uint8_t *
2576 efx_rx_qps_packet_info(
2577 __in efx_rxq_t *erp,
2578 __in uint8_t *buffer,
2579 __in uint32_t buffer_length,
2580 __in uint32_t current_offset,
2581 __out uint16_t *lengthp,
2582 __out uint32_t *next_offsetp,
2583 __out uint32_t *timestamp);
2586 extern __checkReturn efx_rc_t
2588 __in efx_rxq_t *erp);
2592 __in efx_rxq_t *erp);
2596 __in efx_rxq_t *erp);
2600 typedef struct efx_txq_s efx_txq_t;
2602 #if EFSYS_OPT_QSTATS
2604 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2605 typedef enum efx_tx_qstat_e {
2611 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2613 #endif /* EFSYS_OPT_QSTATS */
2615 extern __checkReturn efx_rc_t
2617 __in efx_nic_t *enp);
2621 __in efx_nic_t *enp);
2623 #define EFX_TXQ_MINNDESCS 512
2625 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2626 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2627 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2629 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2631 #define EFX_TXQ_CKSUM_IPV4 0x0001
2632 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2633 #define EFX_TXQ_FATSOV2 0x0004
2634 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2635 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2637 extern __checkReturn efx_rc_t
2639 __in efx_nic_t *enp,
2640 __in unsigned int index,
2641 __in unsigned int label,
2642 __in efsys_mem_t *esmp,
2645 __in uint16_t flags,
2646 __in efx_evq_t *eep,
2647 __deref_out efx_txq_t **etpp,
2648 __out unsigned int *addedp);
2650 extern __checkReturn efx_rc_t
2652 __in efx_txq_t *etp,
2653 __in_ecount(ndescs) efx_buffer_t *eb,
2654 __in unsigned int ndescs,
2655 __in unsigned int completed,
2656 __inout unsigned int *addedp);
2658 extern __checkReturn efx_rc_t
2660 __in efx_txq_t *etp,
2661 __in unsigned int ns);
2665 __in efx_txq_t *etp,
2666 __in unsigned int added,
2667 __in unsigned int pushed);
2669 extern __checkReturn efx_rc_t
2671 __in efx_txq_t *etp);
2675 __in efx_txq_t *etp);
2677 extern __checkReturn efx_rc_t
2679 __in efx_txq_t *etp);
2682 efx_tx_qpio_disable(
2683 __in efx_txq_t *etp);
2685 extern __checkReturn efx_rc_t
2687 __in efx_txq_t *etp,
2688 __in_ecount(buf_length) uint8_t *buffer,
2689 __in size_t buf_length,
2690 __in size_t pio_buf_offset);
2692 extern __checkReturn efx_rc_t
2694 __in efx_txq_t *etp,
2695 __in size_t pkt_length,
2696 __in unsigned int completed,
2697 __inout unsigned int *addedp);
2699 extern __checkReturn efx_rc_t
2701 __in efx_txq_t *etp,
2702 __in_ecount(n) efx_desc_t *ed,
2703 __in unsigned int n,
2704 __in unsigned int completed,
2705 __inout unsigned int *addedp);
2708 efx_tx_qdesc_dma_create(
2709 __in efx_txq_t *etp,
2710 __in efsys_dma_addr_t addr,
2713 __out efx_desc_t *edp);
2716 efx_tx_qdesc_tso_create(
2717 __in efx_txq_t *etp,
2718 __in uint16_t ipv4_id,
2719 __in uint32_t tcp_seq,
2720 __in uint8_t tcp_flags,
2721 __out efx_desc_t *edp);
2723 /* Number of FATSOv2 option descriptors */
2724 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2726 /* Maximum number of DMA segments per TSO packet (not superframe) */
2727 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2730 efx_tx_qdesc_tso2_create(
2731 __in efx_txq_t *etp,
2732 __in uint16_t ipv4_id,
2733 __in uint16_t outer_ipv4_id,
2734 __in uint32_t tcp_seq,
2735 __in uint16_t tcp_mss,
2736 __out_ecount(count) efx_desc_t *edp,
2740 efx_tx_qdesc_vlantci_create(
2741 __in efx_txq_t *etp,
2743 __out efx_desc_t *edp);
2746 efx_tx_qdesc_checksum_create(
2747 __in efx_txq_t *etp,
2748 __in uint16_t flags,
2749 __out efx_desc_t *edp);
2751 #if EFSYS_OPT_QSTATS
2757 __in efx_nic_t *etp,
2758 __in unsigned int id);
2760 #endif /* EFSYS_OPT_NAMES */
2763 efx_tx_qstats_update(
2764 __in efx_txq_t *etp,
2765 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2767 #endif /* EFSYS_OPT_QSTATS */
2771 __in efx_txq_t *etp);
2776 #if EFSYS_OPT_FILTER
2778 #define EFX_ETHER_TYPE_IPV4 0x0800
2779 #define EFX_ETHER_TYPE_IPV6 0x86DD
2781 #define EFX_IPPROTO_TCP 6
2782 #define EFX_IPPROTO_UDP 17
2783 #define EFX_IPPROTO_GRE 47
2785 /* Use RSS to spread across multiple queues */
2786 #define EFX_FILTER_FLAG_RX_RSS 0x01
2787 /* Enable RX scatter */
2788 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2790 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2791 * May only be set by the filter implementation for each type.
2792 * A removal request will restore the automatic filter in its place.
2794 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2795 /* Filter is for RX */
2796 #define EFX_FILTER_FLAG_RX 0x08
2797 /* Filter is for TX */
2798 #define EFX_FILTER_FLAG_TX 0x10
2799 /* Set match flag on the received packet */
2800 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2801 /* Set match mark on the received packet */
2802 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2804 typedef uint8_t efx_filter_flags_t;
2807 * Flags which specify the fields to match on. The values are the same as in the
2808 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2811 /* Match by remote IP host address */
2812 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2813 /* Match by local IP host address */
2814 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2815 /* Match by remote MAC address */
2816 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2817 /* Match by remote TCP/UDP port */
2818 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2819 /* Match by remote TCP/UDP port */
2820 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2821 /* Match by local TCP/UDP port */
2822 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2823 /* Match by Ether-type */
2824 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2825 /* Match by inner VLAN ID */
2826 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2827 /* Match by outer VLAN ID */
2828 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2829 /* Match by IP transport protocol */
2830 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2831 /* Match by VNI or VSID */
2832 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2833 /* For encapsulated packets, match by inner frame local MAC address */
2834 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2835 /* For encapsulated packets, match all multicast inner frames */
2836 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2837 /* For encapsulated packets, match all unicast inner frames */
2838 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2840 * Match by encap type, this flag does not correspond to
2841 * the MCDI match flags and any unoccupied value may be used
2843 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2844 /* Match otherwise-unmatched multicast and broadcast packets */
2845 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2846 /* Match otherwise-unmatched unicast packets */
2847 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2849 typedef uint32_t efx_filter_match_flags_t;
2851 typedef enum efx_filter_priority_s {
2852 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2853 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2854 * address list or hardware
2855 * requirements. This may only be used
2856 * by the filter implementation for
2858 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2859 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2860 * client (e.g. SR-IOV, HyperV VMQ etc.)
2862 } efx_filter_priority_t;
2865 * FIXME: All these fields are assumed to be in little-endian byte order.
2866 * It may be better for some to be big-endian. See bug42804.
2869 typedef struct efx_filter_spec_s {
2870 efx_filter_match_flags_t efs_match_flags;
2871 uint8_t efs_priority;
2872 efx_filter_flags_t efs_flags;
2873 uint16_t efs_dmaq_id;
2874 uint32_t efs_rss_context;
2876 /* Fields below here are hashed for software filter lookup */
2877 uint16_t efs_outer_vid;
2878 uint16_t efs_inner_vid;
2879 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2880 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2881 uint16_t efs_ether_type;
2882 uint8_t efs_ip_proto;
2883 efx_tunnel_protocol_t efs_encap_type;
2884 uint16_t efs_loc_port;
2885 uint16_t efs_rem_port;
2886 efx_oword_t efs_rem_host;
2887 efx_oword_t efs_loc_host;
2888 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2889 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2890 } efx_filter_spec_t;
2893 /* Default values for use in filter specifications */
2894 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2895 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2897 extern __checkReturn efx_rc_t
2899 __in efx_nic_t *enp);
2903 __in efx_nic_t *enp);
2905 extern __checkReturn efx_rc_t
2907 __in efx_nic_t *enp,
2908 __inout efx_filter_spec_t *spec);
2910 extern __checkReturn efx_rc_t
2912 __in efx_nic_t *enp,
2913 __inout efx_filter_spec_t *spec);
2915 extern __checkReturn efx_rc_t
2917 __in efx_nic_t *enp);
2919 extern __checkReturn efx_rc_t
2920 efx_filter_supported_filters(
2921 __in efx_nic_t *enp,
2922 __out_ecount(buffer_length) uint32_t *buffer,
2923 __in size_t buffer_length,
2924 __out size_t *list_lengthp);
2927 efx_filter_spec_init_rx(
2928 __out efx_filter_spec_t *spec,
2929 __in efx_filter_priority_t priority,
2930 __in efx_filter_flags_t flags,
2931 __in efx_rxq_t *erp);
2934 efx_filter_spec_init_tx(
2935 __out efx_filter_spec_t *spec,
2936 __in efx_txq_t *etp);
2938 extern __checkReturn efx_rc_t
2939 efx_filter_spec_set_ipv4_local(
2940 __inout efx_filter_spec_t *spec,
2943 __in uint16_t port);
2945 extern __checkReturn efx_rc_t
2946 efx_filter_spec_set_ipv4_full(
2947 __inout efx_filter_spec_t *spec,
2949 __in uint32_t lhost,
2950 __in uint16_t lport,
2951 __in uint32_t rhost,
2952 __in uint16_t rport);
2954 extern __checkReturn efx_rc_t
2955 efx_filter_spec_set_eth_local(
2956 __inout efx_filter_spec_t *spec,
2958 __in const uint8_t *addr);
2961 efx_filter_spec_set_ether_type(
2962 __inout efx_filter_spec_t *spec,
2963 __in uint16_t ether_type);
2965 extern __checkReturn efx_rc_t
2966 efx_filter_spec_set_uc_def(
2967 __inout efx_filter_spec_t *spec);
2969 extern __checkReturn efx_rc_t
2970 efx_filter_spec_set_mc_def(
2971 __inout efx_filter_spec_t *spec);
2973 typedef enum efx_filter_inner_frame_match_e {
2974 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2975 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2976 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2977 } efx_filter_inner_frame_match_t;
2979 extern __checkReturn efx_rc_t
2980 efx_filter_spec_set_encap_type(
2981 __inout efx_filter_spec_t *spec,
2982 __in efx_tunnel_protocol_t encap_type,
2983 __in efx_filter_inner_frame_match_t inner_frame_match);
2985 extern __checkReturn efx_rc_t
2986 efx_filter_spec_set_vxlan_full(
2987 __inout efx_filter_spec_t *spec,
2988 __in const uint8_t *vxlan_id,
2989 __in const uint8_t *inner_addr,
2990 __in const uint8_t *outer_addr);
2992 #if EFSYS_OPT_RX_SCALE
2993 extern __checkReturn efx_rc_t
2994 efx_filter_spec_set_rss_context(
2995 __inout efx_filter_spec_t *spec,
2996 __in uint32_t rss_context);
2998 #endif /* EFSYS_OPT_FILTER */
3002 extern __checkReturn uint32_t
3004 __in_ecount(count) uint32_t const *input,
3006 __in uint32_t init);
3008 extern __checkReturn uint32_t
3010 __in_ecount(length) uint8_t const *input,
3012 __in uint32_t init);
3014 #if EFSYS_OPT_LICENSING
3018 typedef struct efx_key_stats_s {
3020 uint32_t eks_invalid;
3021 uint32_t eks_blacklisted;
3022 uint32_t eks_unverifiable;
3023 uint32_t eks_wrong_node;
3024 uint32_t eks_licensed_apps_lo;
3025 uint32_t eks_licensed_apps_hi;
3026 uint32_t eks_licensed_features_lo;
3027 uint32_t eks_licensed_features_hi;
3030 extern __checkReturn efx_rc_t
3032 __in efx_nic_t *enp);
3036 __in efx_nic_t *enp);
3038 extern __checkReturn boolean_t
3039 efx_lic_check_support(
3040 __in efx_nic_t *enp);
3042 extern __checkReturn efx_rc_t
3043 efx_lic_update_licenses(
3044 __in efx_nic_t *enp);
3046 extern __checkReturn efx_rc_t
3047 efx_lic_get_key_stats(
3048 __in efx_nic_t *enp,
3049 __out efx_key_stats_t *ksp);
3051 extern __checkReturn efx_rc_t
3053 __in efx_nic_t *enp,
3054 __in uint64_t app_id,
3055 __out boolean_t *licensedp);
3057 extern __checkReturn efx_rc_t
3059 __in efx_nic_t *enp,
3060 __in size_t buffer_size,
3061 __out uint32_t *typep,
3062 __out size_t *lengthp,
3063 __out_opt uint8_t *bufferp);
3066 extern __checkReturn efx_rc_t
3068 __in efx_nic_t *enp,
3069 __in_bcount(buffer_size)
3071 __in size_t buffer_size,
3072 __out uint32_t *startp);
3074 extern __checkReturn efx_rc_t
3076 __in efx_nic_t *enp,
3077 __in_bcount(buffer_size)
3079 __in size_t buffer_size,
3080 __in uint32_t offset,
3081 __out uint32_t *endp);
3083 extern __checkReturn __success(return != B_FALSE) boolean_t
3085 __in efx_nic_t *enp,
3086 __in_bcount(buffer_size)
3088 __in size_t buffer_size,
3089 __in uint32_t offset,
3090 __out uint32_t *startp,
3091 __out uint32_t *lengthp);
3093 extern __checkReturn __success(return != B_FALSE) boolean_t
3094 efx_lic_validate_key(
3095 __in efx_nic_t *enp,
3096 __in_bcount(length) caddr_t keyp,
3097 __in uint32_t length);
3099 extern __checkReturn efx_rc_t
3101 __in efx_nic_t *enp,
3102 __in_bcount(buffer_size)
3104 __in size_t buffer_size,
3105 __in uint32_t offset,
3106 __in uint32_t length,
3107 __out_bcount_part(key_max_size, *lengthp)
3109 __in size_t key_max_size,
3110 __out uint32_t *lengthp);
3112 extern __checkReturn efx_rc_t
3114 __in efx_nic_t *enp,
3115 __in_bcount(buffer_size)
3117 __in size_t buffer_size,
3118 __in uint32_t offset,
3119 __in_bcount(length) caddr_t keyp,
3120 __in uint32_t length,
3121 __out uint32_t *lengthp);
3123 __checkReturn efx_rc_t
3125 __in efx_nic_t *enp,
3126 __in_bcount(buffer_size)
3128 __in size_t buffer_size,
3129 __in uint32_t offset,
3130 __in uint32_t length,
3132 __out uint32_t *deltap);
3134 extern __checkReturn efx_rc_t
3135 efx_lic_create_partition(
3136 __in efx_nic_t *enp,
3137 __in_bcount(buffer_size)
3139 __in size_t buffer_size);
3141 extern __checkReturn efx_rc_t
3142 efx_lic_finish_partition(
3143 __in efx_nic_t *enp,
3144 __in_bcount(buffer_size)
3146 __in size_t buffer_size);
3148 #endif /* EFSYS_OPT_LICENSING */
3152 #if EFSYS_OPT_TUNNEL
3154 extern __checkReturn efx_rc_t
3156 __in efx_nic_t *enp);
3160 __in efx_nic_t *enp);
3163 * For overlay network encapsulation using UDP, the firmware needs to know
3164 * the configured UDP port for the overlay so it can decode encapsulated
3166 * The UDP port/protocol list is global.
3169 extern __checkReturn efx_rc_t
3170 efx_tunnel_config_udp_add(
3171 __in efx_nic_t *enp,
3172 __in uint16_t port /* host/cpu-endian */,
3173 __in efx_tunnel_protocol_t protocol);
3175 extern __checkReturn efx_rc_t
3176 efx_tunnel_config_udp_remove(
3177 __in efx_nic_t *enp,
3178 __in uint16_t port /* host/cpu-endian */,
3179 __in efx_tunnel_protocol_t protocol);
3182 efx_tunnel_config_clear(
3183 __in efx_nic_t *enp);
3186 * Apply tunnel UDP ports configuration to hardware.
3188 * EAGAIN is returned if hardware will be reset (datapath and management CPU
3191 extern __checkReturn efx_rc_t
3192 efx_tunnel_reconfigure(
3193 __in efx_nic_t *enp);
3195 #endif /* EFSYS_OPT_TUNNEL */
3197 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3200 * Firmware subvariant choice options.
3202 * It may be switched to no Tx checksum if attached drivers are either
3203 * preboot or firmware subvariant aware and no VIS are allocated.
3204 * If may be always switched to default explicitly using set request or
3205 * implicitly if unaware driver is attaching. If switching is done when
3206 * a driver is attached, it gets MC_REBOOT event and should recreate its
3209 * See SF-119419-TC DPDK Firmware Driver Interface and
3210 * SF-109306-TC EF10 for Driver Writers for details.
3212 typedef enum efx_nic_fw_subvariant_e {
3213 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3214 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3215 EFX_NIC_FW_SUBVARIANT_NTYPES
3216 } efx_nic_fw_subvariant_t;
3218 extern __checkReturn efx_rc_t
3219 efx_nic_get_fw_subvariant(
3220 __in efx_nic_t *enp,
3221 __out efx_nic_fw_subvariant_t *subvariantp);
3223 extern __checkReturn efx_rc_t
3224 efx_nic_set_fw_subvariant(
3225 __in efx_nic_t *enp,
3226 __in efx_nic_fw_subvariant_t subvariant);
3228 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3234 #endif /* _SYS_EFX_H */