sys/dev/sfxge/common/efx_ev.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright notice,
  13  *    this list of conditions and the following disclaimer in the documentation
  14  *    and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * The views and conclusions contained in the software and documentation are
  29  * those of the authors and should not be interpreted as representing official
  30  * policies, either expressed or implied, of the FreeBSD Project.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "efx.h"
  37 #include "efx_impl.h"
  38 #if EFSYS_OPT_MON_MCDI
  39 #include "mcdi_mon.h"
  40 #endif
  41
  42 #if EFSYS_OPT_QSTATS
  43 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  44         do {                                                            \
  45                 (_eep)->ee_stat[_stat]++;                               \
  46         _NOTE(CONSTANTCONDITION)                                        \
  47         } while (B_FALSE)
  48 #else
  49 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  50 #endif
  51
  52 #define EFX_EV_PRESENT(_qword)                                          \
  53         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  54         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  55
  56
  57
  58 #if EFSYS_OPT_SIENA
  59
  60 static  __checkReturn   efx_rc_t
  61 siena_ev_init(
  62         __in            efx_nic_t *enp);
  63
  64 static                  void
  65 siena_ev_fini(
  66         __in            efx_nic_t *enp);
  67
  68 static  __checkReturn   efx_rc_t
  69 siena_ev_qcreate(
  70         __in            efx_nic_t *enp,
  71         __in            unsigned int index,
  72         __in            efsys_mem_t *esmp,
  73         __in            size_t ndescs,
  74         __in            uint32_t id,
  75         __in            uint32_t us,
  76         __in            uint32_t flags,
  77         __in            efx_evq_t *eep);
  78
  79 static                  void
  80 siena_ev_qdestroy(
  81         __in            efx_evq_t *eep);
  82
  83 static  __checkReturn   efx_rc_t
  84 siena_ev_qprime(
  85         __in            efx_evq_t *eep,
  86         __in            unsigned int count);
  87
  88 static                  void
  89 siena_ev_qpost(
  90         __in    efx_evq_t *eep,
  91         __in    uint16_t data);
  92
  93 static  __checkReturn   efx_rc_t
  94 siena_ev_qmoderate(
  95         __in            efx_evq_t *eep,
  96         __in            unsigned int us);
  97
  98 #if EFSYS_OPT_QSTATS
  99 static                  void
 100 siena_ev_qstats_update(
 101         __in                            efx_evq_t *eep,
 102         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
 103
 104 #endif
 105
 106 #endif /* EFSYS_OPT_SIENA */
 107
 108 #if EFSYS_OPT_SIENA
 109 static const efx_ev_ops_t       __efx_ev_siena_ops = {
 110         siena_ev_init,                          /* eevo_init */
 111         siena_ev_fini,                          /* eevo_fini */
 112         siena_ev_qcreate,                       /* eevo_qcreate */
 113         siena_ev_qdestroy,                      /* eevo_qdestroy */
 114         siena_ev_qprime,                        /* eevo_qprime */
 115         siena_ev_qpost,                         /* eevo_qpost */
 116         siena_ev_qmoderate,                     /* eevo_qmoderate */
 117 #if EFSYS_OPT_QSTATS
 118         siena_ev_qstats_update,                 /* eevo_qstats_update */
 119 #endif
 120 };
 121 #endif /* EFSYS_OPT_SIENA */
 122
 123 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 124 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
 125         ef10_ev_init,                           /* eevo_init */
 126         ef10_ev_fini,                           /* eevo_fini */
 127         ef10_ev_qcreate,                        /* eevo_qcreate */
 128         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 129         ef10_ev_qprime,                         /* eevo_qprime */
 130         ef10_ev_qpost,                          /* eevo_qpost */
 131         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 132 #if EFSYS_OPT_QSTATS
 133         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 134 #endif
 135 };
 136 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 137
 138
 139         __checkReturn   efx_rc_t
 140 efx_ev_init(
 141         __in            efx_nic_t *enp)
 142 {
 143         const efx_ev_ops_t *eevop;
 144         efx_rc_t rc;
 145
 146         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 147         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 148
 149         if (enp->en_mod_flags & EFX_MOD_EV) {
 150                 rc = EINVAL;
 151                 goto fail1;
 152         }
 153
 154         switch (enp->en_family) {
 155 #if EFSYS_OPT_SIENA
 156         case EFX_FAMILY_SIENA:
 157                 eevop = &__efx_ev_siena_ops;
 158                 break;
 159 #endif /* EFSYS_OPT_SIENA */
 160
 161 #if EFSYS_OPT_HUNTINGTON
 162         case EFX_FAMILY_HUNTINGTON:
 163                 eevop = &__efx_ev_ef10_ops;
 164                 break;
 165 #endif /* EFSYS_OPT_HUNTINGTON */
 166
 167 #if EFSYS_OPT_MEDFORD
 168         case EFX_FAMILY_MEDFORD:
 169                 eevop = &__efx_ev_ef10_ops;
 170                 break;
 171 #endif /* EFSYS_OPT_MEDFORD */
 172
 173 #if EFSYS_OPT_MEDFORD2
 174         case EFX_FAMILY_MEDFORD2:
 175                 eevop = &__efx_ev_ef10_ops;
 176                 break;
 177 #endif /* EFSYS_OPT_MEDFORD2 */
 178
 179         default:
 180                 EFSYS_ASSERT(0);
 181                 rc = ENOTSUP;
 182                 goto fail1;
 183         }
 184
 185         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 186
 187         if ((rc = eevop->eevo_init(enp)) != 0)
 188                 goto fail2;
 189
 190         enp->en_eevop = eevop;
 191         enp->en_mod_flags |= EFX_MOD_EV;
 192         return (0);
 193
 194 fail2:
 195         EFSYS_PROBE(fail2);
 196
 197 fail1:
 198         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 199
 200         enp->en_eevop = NULL;
 201         enp->en_mod_flags &= ~EFX_MOD_EV;
 202         return (rc);
 203 }
 204
 205                 void
 206 efx_ev_fini(
 207         __in    efx_nic_t *enp)
 208 {
 209         const efx_ev_ops_t *eevop = enp->en_eevop;
 210
 211         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 212         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 213         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 214         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 215         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 216         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 217
 218         eevop->eevo_fini(enp);
 219
 220         enp->en_eevop = NULL;
 221         enp->en_mod_flags &= ~EFX_MOD_EV;
 222 }
 223
 224
 225         __checkReturn   efx_rc_t
 226 efx_ev_qcreate(
 227         __in            efx_nic_t *enp,
 228         __in            unsigned int index,
 229         __in            efsys_mem_t *esmp,
 230         __in            size_t ndescs,
 231         __in            uint32_t id,
 232         __in            uint32_t us,
 233         __in            uint32_t flags,
 234         __deref_out     efx_evq_t **eepp)
 235 {
 236         const efx_ev_ops_t *eevop = enp->en_eevop;
 237         efx_evq_t *eep;
 238         efx_rc_t rc;
 239
 240         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 241         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 242
 243         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
 244             enp->en_nic_cfg.enc_evq_limit);
 245
 246         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
 247         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
 248                 break;
 249         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
 250                 if (us != 0) {
 251                         rc = EINVAL;
 252                         goto fail1;
 253                 }
 254                 break;
 255         default:
 256                 rc = EINVAL;
 257                 goto fail2;
 258         }
 259
 260         /* Allocate an EVQ object */
 261         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 262         if (eep == NULL) {
 263                 rc = ENOMEM;
 264                 goto fail3;
 265         }
 266
 267         eep->ee_magic = EFX_EVQ_MAGIC;
 268         eep->ee_enp = enp;
 269         eep->ee_index = index;
 270         eep->ee_mask = ndescs - 1;
 271         eep->ee_flags = flags;
 272         eep->ee_esmp = esmp;
 273
 274         /*
 275          * Set outputs before the queue is created because interrupts may be
 276          * raised for events immediately after the queue is created, before the
 277          * function call below returns. See bug58606.
 278          *
 279          * The eepp pointer passed in by the client must therefore point to data
 280          * shared with the client's event processing context.
 281          */
 282         enp->en_ev_qcount++;
 283         *eepp = eep;
 284
 285         if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
 286             eep)) != 0)
 287                 goto fail4;
 288
 289         return (0);
 290
 291 fail4:
 292         EFSYS_PROBE(fail4);
 293
 294         *eepp = NULL;
 295         enp->en_ev_qcount--;
 296         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 297 fail3:
 298         EFSYS_PROBE(fail3);
 299 fail2:
 300         EFSYS_PROBE(fail2);
 301 fail1:
 302         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 303         return (rc);
 304 }
 305
 306                 void
 307 efx_ev_qdestroy(
 308         __in    efx_evq_t *eep)
 309 {
 310         efx_nic_t *enp = eep->ee_enp;
 311         const efx_ev_ops_t *eevop = enp->en_eevop;
 312
 313         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 314
 315         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 316         --enp->en_ev_qcount;
 317
 318         eevop->eevo_qdestroy(eep);
 319
 320         /* Free the EVQ object */
 321         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 322 }
 323
 324         __checkReturn   efx_rc_t
 325 efx_ev_qprime(
 326         __in            efx_evq_t *eep,
 327         __in            unsigned int count)
 328 {
 329         efx_nic_t *enp = eep->ee_enp;
 330         const efx_ev_ops_t *eevop = enp->en_eevop;
 331         efx_rc_t rc;
 332
 333         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 334
 335         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 336                 rc = EINVAL;
 337                 goto fail1;
 338         }
 339
 340         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 341                 goto fail2;
 342
 343         return (0);
 344
 345 fail2:
 346         EFSYS_PROBE(fail2);
 347 fail1:
 348         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 349         return (rc);
 350 }
 351
 352         __checkReturn   boolean_t
 353 efx_ev_qpending(
 354         __in            efx_evq_t *eep,
 355         __in            unsigned int count)
 356 {
 357         size_t offset;
 358         efx_qword_t qword;
 359
 360         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 361
 362         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 363         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 364
 365         return (EFX_EV_PRESENT(qword));
 366 }
 367
 368 #if EFSYS_OPT_EV_PREFETCH
 369
 370                         void
 371 efx_ev_qprefetch(
 372         __in            efx_evq_t *eep,
 373         __in            unsigned int count)
 374 {
 375         unsigned int offset;
 376
 377         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 378
 379         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 380         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 381 }
 382
 383 #endif  /* EFSYS_OPT_EV_PREFETCH */
 384
 385 #define EFX_EV_BATCH    8
 386
 387                         void
 388 efx_ev_qpoll(
 389         __in            efx_evq_t *eep,
 390         __inout         unsigned int *countp,
 391         __in            const efx_ev_callbacks_t *eecp,
 392         __in_opt        void *arg)
 393 {
 394         efx_qword_t ev[EFX_EV_BATCH];
 395         unsigned int batch;
 396         unsigned int total;
 397         unsigned int count;
 398         unsigned int index;
 399         size_t offset;
 400
 401         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
 402         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 403         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 404
 405         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 406         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 407         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 408         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 409             FSE_AZ_EV_CODE_DRV_GEN_EV);
 410 #if EFSYS_OPT_MCDI
 411         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 412             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 413 #endif
 414
 415         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 416         EFSYS_ASSERT(countp != NULL);
 417         EFSYS_ASSERT(eecp != NULL);
 418
 419         count = *countp;
 420         do {
 421                 /* Read up until the end of the batch period */
 422                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
 423                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 424                 for (total = 0; total < batch; ++total) {
 425                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
 426
 427                         if (!EFX_EV_PRESENT(ev[total]))
 428                                 break;
 429
 430                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
 431                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
 432                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
 433
 434                         offset += sizeof (efx_qword_t);
 435                 }
 436
 437 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
 438                 /*
 439                  * Prefetch the next batch when we get within PREFETCH_PERIOD
 440                  * of a completed batch. If the batch is smaller, then prefetch
 441                  * immediately.
 442                  */
 443                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
 444                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 445 #endif  /* EFSYS_OPT_EV_PREFETCH */
 446
 447                 /* Process the batch of events */
 448                 for (index = 0; index < total; ++index) {
 449                         boolean_t should_abort;
 450                         uint32_t code;
 451
 452 #if EFSYS_OPT_EV_PREFETCH
 453                         /* Prefetch if we've now reached the batch period */
 454                         if (total == batch &&
 455                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
 456                                 offset = (count + batch) & eep->ee_mask;
 457                                 offset *= sizeof (efx_qword_t);
 458
 459                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 460                         }
 461 #endif  /* EFSYS_OPT_EV_PREFETCH */
 462
 463                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
 464
 465                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
 466                         switch (code) {
 467                         case FSE_AZ_EV_CODE_RX_EV:
 468                                 should_abort = eep->ee_rx(eep,
 469                                     &(ev[index]), eecp, arg);
 470                                 break;
 471                         case FSE_AZ_EV_CODE_TX_EV:
 472                                 should_abort = eep->ee_tx(eep,
 473                                     &(ev[index]), eecp, arg);
 474                                 break;
 475                         case FSE_AZ_EV_CODE_DRIVER_EV:
 476                                 should_abort = eep->ee_driver(eep,
 477                                     &(ev[index]), eecp, arg);
 478                                 break;
 479                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
 480                                 should_abort = eep->ee_drv_gen(eep,
 481                                     &(ev[index]), eecp, arg);
 482                                 break;
 483 #if EFSYS_OPT_MCDI
 484                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
 485                                 should_abort = eep->ee_mcdi(eep,
 486                                     &(ev[index]), eecp, arg);
 487                                 break;
 488 #endif
 489                         case FSE_AZ_EV_CODE_GLOBAL_EV:
 490                                 if (eep->ee_global) {
 491                                         should_abort = eep->ee_global(eep,
 492                                             &(ev[index]), eecp, arg);
 493                                         break;
 494                                 }
 495                                 /* else fallthrough */
 496                         default:
 497                                 EFSYS_PROBE3(bad_event,
 498                                     unsigned int, eep->ee_index,
 499                                     uint32_t,
 500                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
 501                                     uint32_t,
 502                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
 503
 504                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 505                                 (void) eecp->eec_exception(arg,
 506                                         EFX_EXCEPTION_EV_ERROR, code);
 507                                 should_abort = B_TRUE;
 508                         }
 509                         if (should_abort) {
 510                                 /* Ignore subsequent events */
 511                                 total = index + 1;
 512
 513                                 /*
 514                                  * Poison batch to ensure the outer
 515                                  * loop is broken out of.
 516                                  */
 517                                 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
 518                                 batch += (EFX_EV_BATCH << 1);
 519                                 EFSYS_ASSERT(total != batch);
 520                                 break;
 521                         }
 522                 }
 523
 524                 /*
 525                  * Now that the hardware has most likely moved onto dma'ing
 526                  * into the next cache line, clear the processed events. Take
 527                  * care to only clear out events that we've processed
 528                  */
 529                 EFX_SET_QWORD(ev[0]);
 530                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 531                 for (index = 0; index < total; ++index) {
 532                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
 533                         offset += sizeof (efx_qword_t);
 534                 }
 535
 536                 count += total;
 537
 538         } while (total == batch);
 539
 540         *countp = count;
 541 }
 542
 543                         void
 544 efx_ev_qpost(
 545         __in    efx_evq_t *eep,
 546         __in    uint16_t data)
 547 {
 548         efx_nic_t *enp = eep->ee_enp;
 549         const efx_ev_ops_t *eevop = enp->en_eevop;
 550
 551         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 552
 553         EFSYS_ASSERT(eevop != NULL &&
 554             eevop->eevo_qpost != NULL);
 555
 556         eevop->eevo_qpost(eep, data);
 557 }
 558
 559         __checkReturn   efx_rc_t
 560 efx_ev_usecs_to_ticks(
 561         __in            efx_nic_t *enp,
 562         __in            unsigned int us,
 563         __out           unsigned int *ticksp)
 564 {
 565         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 566         unsigned int ticks;
 567
 568         /* Convert microseconds to a timer tick count */
 569         if (us == 0)
 570                 ticks = 0;
 571         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 572                 ticks = 1;      /* Never round down to zero */
 573         else
 574                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 575
 576         *ticksp = ticks;
 577         return (0);
 578 }
 579
 580         __checkReturn   efx_rc_t
 581 efx_ev_qmoderate(
 582         __in            efx_evq_t *eep,
 583         __in            unsigned int us)
 584 {
 585         efx_nic_t *enp = eep->ee_enp;
 586         const efx_ev_ops_t *eevop = enp->en_eevop;
 587         efx_rc_t rc;
 588
 589         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 590
 591         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
 592             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
 593                 rc = EINVAL;
 594                 goto fail1;
 595         }
 596
 597         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 598                 goto fail2;
 599
 600         return (0);
 601
 602 fail2:
 603         EFSYS_PROBE(fail2);
 604 fail1:
 605         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 606         return (rc);
 607 }
 608
 609 #if EFSYS_OPT_QSTATS
 610                                         void
 611 efx_ev_qstats_update(
 612         __in                            efx_evq_t *eep,
 613         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 614
 615 {       efx_nic_t *enp = eep->ee_enp;
 616         const efx_ev_ops_t *eevop = enp->en_eevop;
 617
 618         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 619
 620         eevop->eevo_qstats_update(eep, stat);
 621 }
 622
 623 #endif  /* EFSYS_OPT_QSTATS */
 624
 625 #if EFSYS_OPT_SIENA
 626
 627 static  __checkReturn   efx_rc_t
 628 siena_ev_init(
 629         __in            efx_nic_t *enp)
 630 {
 631         efx_oword_t oword;
 632
 633         /*
 634          * Program the event queue for receive and transmit queue
 635          * flush events.
 636          */
 637         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 638         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 639         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 640
 641         return (0);
 642
 643 }
 644
 645 static  __checkReturn   boolean_t
 646 siena_ev_rx_not_ok(
 647         __in            efx_evq_t *eep,
 648         __in            efx_qword_t *eqp,
 649         __in            uint32_t label,
 650         __in            uint32_t id,
 651         __inout         uint16_t *flagsp)
 652 {
 653         boolean_t ignore = B_FALSE;
 654
 655         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 656                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 657                 EFSYS_PROBE(tobe_disc);
 658                 /*
 659                  * Assume this is a unicast address mismatch, unless below
 660                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 661                  * EV_RX_PAUSE_FRM_ERR is set.
 662                  */
 663                 (*flagsp) |= EFX_ADDR_MISMATCH;
 664         }
 665
 666         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 667                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 668                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 669                 (*flagsp) |= EFX_DISCARD;
 670
 671 #if EFSYS_OPT_RX_SCATTER
 672                 /*
 673                  * Lookout for payload queue ran dry errors and ignore them.
 674                  *
 675                  * Sadly for the header/data split cases, the descriptor
 676                  * pointer in this event refers to the header queue and
 677                  * therefore cannot be easily detected as duplicate.
 678                  * So we drop these and rely on the receive processing seeing
 679                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 680                  * the partially received packet.
 681                  */
 682                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 683                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 684                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 685                         ignore = B_TRUE;
 686 #endif  /* EFSYS_OPT_RX_SCATTER */
 687         }
 688
 689         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 690                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 691                 EFSYS_PROBE(crc_err);
 692                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 693                 (*flagsp) |= EFX_DISCARD;
 694         }
 695
 696         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 697                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 698                 EFSYS_PROBE(pause_frm_err);
 699                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 700                 (*flagsp) |= EFX_DISCARD;
 701         }
 702
 703         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 704                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 705                 EFSYS_PROBE(owner_id_err);
 706                 (*flagsp) |= EFX_DISCARD;
 707         }
 708
 709         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 710                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 711                 EFSYS_PROBE(ipv4_err);
 712                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 713         }
 714
 715         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 716                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 717                 EFSYS_PROBE(udp_chk_err);
 718                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 719         }
 720
 721         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 722                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 723
 724                 /*
 725                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 726                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 727                  * condition.
 728                  */
 729                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 730         }
 731
 732         return (ignore);
 733 }
 734
 735 static  __checkReturn   boolean_t
 736 siena_ev_rx(
 737         __in            efx_evq_t *eep,
 738         __in            efx_qword_t *eqp,
 739         __in            const efx_ev_callbacks_t *eecp,
 740         __in_opt        void *arg)
 741 {
 742         uint32_t id;
 743         uint32_t size;
 744         uint32_t label;
 745         boolean_t ok;
 746 #if EFSYS_OPT_RX_SCATTER
 747         boolean_t sop;
 748         boolean_t jumbo_cont;
 749 #endif  /* EFSYS_OPT_RX_SCATTER */
 750         uint32_t hdr_type;
 751         boolean_t is_v6;
 752         uint16_t flags;
 753         boolean_t ignore;
 754         boolean_t should_abort;
 755
 756         EFX_EV_QSTAT_INCR(eep, EV_RX);
 757
 758         /* Basic packet information */
 759         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 760         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 761         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 762         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 763
 764 #if EFSYS_OPT_RX_SCATTER
 765         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 766         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 767 #endif  /* EFSYS_OPT_RX_SCATTER */
 768
 769         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 770
 771         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 772
 773         /*
 774          * If packet is marked as OK and packet type is TCP/IP or
 775          * UDP/IP or other IP, then we can rely on the hardware checksums.
 776          */
 777         switch (hdr_type) {
 778         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 779                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 780                 if (is_v6) {
 781                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 782                         flags |= EFX_PKT_IPV6;
 783                 } else {
 784                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 785                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 786                 }
 787                 break;
 788
 789         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 790                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 791                 if (is_v6) {
 792                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 793                         flags |= EFX_PKT_IPV6;
 794                 } else {
 795                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 796                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 797                 }
 798                 break;
 799
 800         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 801                 if (is_v6) {
 802                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 803                         flags = EFX_PKT_IPV6;
 804                 } else {
 805                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 806                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 807                 }
 808                 break;
 809
 810         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 811                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 812                 flags = 0;
 813                 break;
 814
 815         default:
 816                 EFSYS_ASSERT(B_FALSE);
 817                 flags = 0;
 818                 break;
 819         }
 820
 821 #if EFSYS_OPT_RX_SCATTER
 822         /* Report scatter and header/lookahead split buffer flags */
 823         if (sop)
 824                 flags |= EFX_PKT_START;
 825         if (jumbo_cont)
 826                 flags |= EFX_PKT_CONT;
 827 #endif  /* EFSYS_OPT_RX_SCATTER */
 828
 829         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 830         if (!ok) {
 831                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 832                 if (ignore) {
 833                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 834                             uint32_t, size, uint16_t, flags);
 835
 836                         return (B_FALSE);
 837                 }
 838         }
 839
 840         /* If we're not discarding the packet then it is ok */
 841         if (~flags & EFX_DISCARD)
 842                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 843
 844         /* Detect multicast packets that didn't match the filter */
 845         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 846                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 847
 848                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 849                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 850                 } else {
 851                         EFSYS_PROBE(mcast_mismatch);
 852                         flags |= EFX_ADDR_MISMATCH;
 853                 }
 854         } else {
 855                 flags |= EFX_PKT_UNICAST;
 856         }
 857
 858         /*
 859          * The packet parser in Siena can abort parsing packets under
 860          * certain error conditions, setting the PKT_NOT_PARSED bit
 861          * (which clears PKT_OK). If this is set, then don't trust
 862          * the PKT_TYPE field.
 863          */
 864         if (!ok) {
 865                 uint32_t parse_err;
 866
 867                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 868                 if (parse_err != 0)
 869                         flags |= EFX_CHECK_VLAN;
 870         }
 871
 872         if (~flags & EFX_CHECK_VLAN) {
 873                 uint32_t pkt_type;
 874
 875                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 876                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 877                         flags |= EFX_PKT_VLAN_TAGGED;
 878         }
 879
 880         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 881             uint32_t, size, uint16_t, flags);
 882
 883         EFSYS_ASSERT(eecp->eec_rx != NULL);
 884         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 885
 886         return (should_abort);
 887 }
 888
 889 static  __checkReturn   boolean_t
 890 siena_ev_tx(
 891         __in            efx_evq_t *eep,
 892         __in            efx_qword_t *eqp,
 893         __in            const efx_ev_callbacks_t *eecp,
 894         __in_opt        void *arg)
 895 {
 896         uint32_t id;
 897         uint32_t label;
 898         boolean_t should_abort;
 899
 900         EFX_EV_QSTAT_INCR(eep, EV_TX);
 901
 902         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 903             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 904             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 905             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 906
 907                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 908                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 909
 910                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 911
 912                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 913                 should_abort = eecp->eec_tx(arg, label, id);
 914
 915                 return (should_abort);
 916         }
 917
 918         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 919                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 920                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 921                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 922
 923         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 924                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 925
 926         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 927                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 928
 929         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 930                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 931
 932         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 933         return (B_FALSE);
 934 }
 935
 936 static  __checkReturn   boolean_t
 937 siena_ev_global(
 938         __in            efx_evq_t *eep,
 939         __in            efx_qword_t *eqp,
 940         __in            const efx_ev_callbacks_t *eecp,
 941         __in_opt        void *arg)
 942 {
 943         _NOTE(ARGUNUSED(eqp, eecp, arg))
 944
 945         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 946
 947         return (B_FALSE);
 948 }
 949
 950 static  __checkReturn   boolean_t
 951 siena_ev_driver(
 952         __in            efx_evq_t *eep,
 953         __in            efx_qword_t *eqp,
 954         __in            const efx_ev_callbacks_t *eecp,
 955         __in_opt        void *arg)
 956 {
 957         boolean_t should_abort;
 958
 959         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 960         should_abort = B_FALSE;
 961
 962         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 963         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 964                 uint32_t txq_index;
 965
 966                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 967
 968                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 969
 970                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 971
 972                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 973                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 974
 975                 break;
 976         }
 977         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 978                 uint32_t rxq_index;
 979                 uint32_t failed;
 980
 981                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 982                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 983
 984                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 985                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 986
 987                 if (failed) {
 988                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 989
 990                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 991
 992                         should_abort = eecp->eec_rxq_flush_failed(arg,
 993                                                                     rxq_index);
 994                 } else {
 995                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 996
 997                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 998
 999                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1000                 }
1001
1002                 break;
1003         }
1004         case FSE_AZ_EVQ_INIT_DONE_EV:
1005                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1006                 should_abort = eecp->eec_initialized(arg);
1007
1008                 break;
1009
1010         case FSE_AZ_EVQ_NOT_EN_EV:
1011                 EFSYS_PROBE(evq_not_en);
1012                 break;
1013
1014         case FSE_AZ_SRM_UPD_DONE_EV: {
1015                 uint32_t code;
1016
1017                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
1018
1019                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1020
1021                 EFSYS_ASSERT(eecp->eec_sram != NULL);
1022                 should_abort = eecp->eec_sram(arg, code);
1023
1024                 break;
1025         }
1026         case FSE_AZ_WAKE_UP_EV: {
1027                 uint32_t id;
1028
1029                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1030
1031                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1032                 should_abort = eecp->eec_wake_up(arg, id);
1033
1034                 break;
1035         }
1036         case FSE_AZ_TX_PKT_NON_TCP_UDP:
1037                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1038                 break;
1039
1040         case FSE_AZ_TIMER_EV: {
1041                 uint32_t id;
1042
1043                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1044
1045                 EFSYS_ASSERT(eecp->eec_timer != NULL);
1046                 should_abort = eecp->eec_timer(arg, id);
1047
1048                 break;
1049         }
1050         case FSE_AZ_RX_DSC_ERROR_EV:
1051                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1052
1053                 EFSYS_PROBE(rx_dsc_error);
1054
1055                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1056                 should_abort = eecp->eec_exception(arg,
1057                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
1058
1059                 break;
1060
1061         case FSE_AZ_TX_DSC_ERROR_EV:
1062                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1063
1064                 EFSYS_PROBE(tx_dsc_error);
1065
1066                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1067                 should_abort = eecp->eec_exception(arg,
1068                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1069
1070                 break;
1071
1072         default:
1073                 break;
1074         }
1075
1076         return (should_abort);
1077 }
1078
1079 static  __checkReturn   boolean_t
1080 siena_ev_drv_gen(
1081         __in            efx_evq_t *eep,
1082         __in            efx_qword_t *eqp,
1083         __in            const efx_ev_callbacks_t *eecp,
1084         __in_opt        void *arg)
1085 {
1086         uint32_t data;
1087         boolean_t should_abort;
1088
1089         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1090
1091         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1092         if (data >= ((uint32_t)1 << 16)) {
1093                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1094                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1095                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1096                 return (B_TRUE);
1097         }
1098
1099         EFSYS_ASSERT(eecp->eec_software != NULL);
1100         should_abort = eecp->eec_software(arg, (uint16_t)data);
1101
1102         return (should_abort);
1103 }
1104
1105 #if EFSYS_OPT_MCDI
1106
1107 static  __checkReturn   boolean_t
1108 siena_ev_mcdi(
1109         __in            efx_evq_t *eep,
1110         __in            efx_qword_t *eqp,
1111         __in            const efx_ev_callbacks_t *eecp,
1112         __in_opt        void *arg)
1113 {
1114         efx_nic_t *enp = eep->ee_enp;
1115         unsigned int code;
1116         boolean_t should_abort = B_FALSE;
1117
1118         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1119
1120         if (enp->en_family != EFX_FAMILY_SIENA)
1121                 goto out;
1122
1123         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1124         EFSYS_ASSERT(eecp->eec_exception != NULL);
1125 #if EFSYS_OPT_MON_STATS
1126         EFSYS_ASSERT(eecp->eec_monitor != NULL);
1127 #endif
1128
1129         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1130
1131         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1132         switch (code) {
1133         case MCDI_EVENT_CODE_BADSSERT:
1134                 efx_mcdi_ev_death(enp, EINTR);
1135                 break;
1136
1137         case MCDI_EVENT_CODE_CMDDONE:
1138                 efx_mcdi_ev_cpl(enp,
1139                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1140                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1141                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1142                 break;
1143
1144         case MCDI_EVENT_CODE_LINKCHANGE: {
1145                 efx_link_mode_t link_mode;
1146
1147                 siena_phy_link_ev(enp, eqp, &link_mode);
1148                 should_abort = eecp->eec_link_change(arg, link_mode);
1149                 break;
1150         }
1151         case MCDI_EVENT_CODE_SENSOREVT: {
1152 #if EFSYS_OPT_MON_STATS
1153                 efx_mon_stat_t id;
1154                 efx_mon_stat_value_t value;
1155                 efx_rc_t rc;
1156
1157                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1158                         should_abort = eecp->eec_monitor(arg, id, value);
1159                 else if (rc == ENOTSUP) {
1160                         should_abort = eecp->eec_exception(arg,
1161                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1162                                 MCDI_EV_FIELD(eqp, DATA));
1163                 } else
1164                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1165 #else
1166                 should_abort = B_FALSE;
1167 #endif
1168                 break;
1169         }
1170         case MCDI_EVENT_CODE_SCHEDERR:
1171                 /* Informational only */
1172                 break;
1173
1174         case MCDI_EVENT_CODE_REBOOT:
1175                 efx_mcdi_ev_death(enp, EIO);
1176                 break;
1177
1178         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1179 #if EFSYS_OPT_MAC_STATS
1180                 if (eecp->eec_mac_stats != NULL) {
1181                         eecp->eec_mac_stats(arg,
1182                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1183                 }
1184 #endif
1185                 break;
1186
1187         case MCDI_EVENT_CODE_FWALERT: {
1188                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1189
1190                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1191                         should_abort = eecp->eec_exception(arg,
1192                                 EFX_EXCEPTION_FWALERT_SRAM,
1193                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1194                 else
1195                         should_abort = eecp->eec_exception(arg,
1196                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1197                                 MCDI_EV_FIELD(eqp, DATA));
1198                 break;
1199         }
1200
1201         default:
1202                 EFSYS_PROBE1(mc_pcol_error, int, code);
1203                 break;
1204         }
1205
1206 out:
1207         return (should_abort);
1208 }
1209
1210 #endif  /* EFSYS_OPT_MCDI */
1211
1212 static  __checkReturn   efx_rc_t
1213 siena_ev_qprime(
1214         __in            efx_evq_t *eep,
1215         __in            unsigned int count)
1216 {
1217         efx_nic_t *enp = eep->ee_enp;
1218         uint32_t rptr;
1219         efx_dword_t dword;
1220
1221         rptr = count & eep->ee_mask;
1222
1223         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1224
1225         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1226                             &dword, B_FALSE);
1227
1228         return (0);
1229 }
1230
1231 static          void
1232 siena_ev_qpost(
1233         __in    efx_evq_t *eep,
1234         __in    uint16_t data)
1235 {
1236         efx_nic_t *enp = eep->ee_enp;
1237         efx_qword_t ev;
1238         efx_oword_t oword;
1239
1240         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1241             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1242
1243         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1244             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1245             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1246
1247         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1248 }
1249
1250 static  __checkReturn   efx_rc_t
1251 siena_ev_qmoderate(
1252         __in            efx_evq_t *eep,
1253         __in            unsigned int us)
1254 {
1255         efx_nic_t *enp = eep->ee_enp;
1256         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1257         unsigned int locked;
1258         efx_dword_t dword;
1259         efx_rc_t rc;
1260
1261         if (us > encp->enc_evq_timer_max_us) {
1262                 rc = EINVAL;
1263                 goto fail1;
1264         }
1265
1266         /* If the value is zero then disable the timer */
1267         if (us == 0) {
1268                 EFX_POPULATE_DWORD_2(dword,
1269                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1270                     FRF_CZ_TC_TIMER_VAL, 0);
1271         } else {
1272                 unsigned int ticks;
1273
1274                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1275                         goto fail2;
1276
1277                 EFSYS_ASSERT(ticks > 0);
1278                 EFX_POPULATE_DWORD_2(dword,
1279                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1280                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1281         }
1282
1283         locked = (eep->ee_index == 0) ? 1 : 0;
1284
1285         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1286             eep->ee_index, &dword, locked);
1287
1288         return (0);
1289
1290 fail2:
1291         EFSYS_PROBE(fail2);
1292 fail1:
1293         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1294
1295         return (rc);
1296 }
1297
1298 static  __checkReturn   efx_rc_t
1299 siena_ev_qcreate(
1300         __in            efx_nic_t *enp,
1301         __in            unsigned int index,
1302         __in            efsys_mem_t *esmp,
1303         __in            size_t ndescs,
1304         __in            uint32_t id,
1305         __in            uint32_t us,
1306         __in            uint32_t flags,
1307         __in            efx_evq_t *eep)
1308 {
1309         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1310         uint32_t size;
1311         efx_oword_t oword;
1312         efx_rc_t rc;
1313         boolean_t notify_mode;
1314
1315         _NOTE(ARGUNUSED(esmp))
1316
1317         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1318         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1319
1320         if (!ISP2(ndescs) ||
1321             (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
1322                 rc = EINVAL;
1323                 goto fail1;
1324         }
1325         if (index >= encp->enc_evq_limit) {
1326                 rc = EINVAL;
1327                 goto fail2;
1328         }
1329 #if EFSYS_OPT_RX_SCALE
1330         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1331             index >= EFX_MAXRSS_LEGACY) {
1332                 rc = EINVAL;
1333                 goto fail3;
1334         }
1335 #endif
1336         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1337             size++)
1338                 if ((1 << size) == (int)(ndescs / EFX_EVQ_MINNEVS))
1339                         break;
1340         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1341                 rc = EINVAL;
1342                 goto fail4;
1343         }
1344
1345         /* Set up the handler table */
1346         eep->ee_rx      = siena_ev_rx;
1347         eep->ee_tx      = siena_ev_tx;
1348         eep->ee_driver  = siena_ev_driver;
1349         eep->ee_global  = siena_ev_global;
1350         eep->ee_drv_gen = siena_ev_drv_gen;
1351 #if EFSYS_OPT_MCDI
1352         eep->ee_mcdi    = siena_ev_mcdi;
1353 #endif  /* EFSYS_OPT_MCDI */
1354
1355         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1356             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1357
1358         /* Set up the new event queue */
1359         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1360             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1361             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1362         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1363
1364         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1365             FRF_AZ_EVQ_BUF_BASE_ID, id);
1366
1367         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1368
1369         /* Set initial interrupt moderation */
1370         siena_ev_qmoderate(eep, us);
1371
1372         return (0);
1373
1374 fail4:
1375         EFSYS_PROBE(fail4);
1376 #if EFSYS_OPT_RX_SCALE
1377 fail3:
1378         EFSYS_PROBE(fail3);
1379 #endif
1380 fail2:
1381         EFSYS_PROBE(fail2);
1382 fail1:
1383         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1384
1385         return (rc);
1386 }
1387
1388 #endif /* EFSYS_OPT_SIENA */
1389
1390 #if EFSYS_OPT_QSTATS
1391 #if EFSYS_OPT_NAMES
1392 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1393 static const char * const __efx_ev_qstat_name[] = {
1394         "all",
1395         "rx",
1396         "rx_ok",
1397         "rx_frm_trunc",
1398         "rx_tobe_disc",
1399         "rx_pause_frm_err",
1400         "rx_buf_owner_id_err",
1401         "rx_ipv4_hdr_chksum_err",
1402         "rx_tcp_udp_chksum_err",
1403         "rx_eth_crc_err",
1404         "rx_ip_frag_err",
1405         "rx_mcast_pkt",
1406         "rx_mcast_hash_match",
1407         "rx_tcp_ipv4",
1408         "rx_tcp_ipv6",
1409         "rx_udp_ipv4",
1410         "rx_udp_ipv6",
1411         "rx_other_ipv4",
1412         "rx_other_ipv6",
1413         "rx_non_ip",
1414         "rx_batch",
1415         "tx",
1416         "tx_wq_ff_full",
1417         "tx_pkt_err",
1418         "tx_pkt_too_big",
1419         "tx_unexpected",
1420         "global",
1421         "global_mnt",
1422         "driver",
1423         "driver_srm_upd_done",
1424         "driver_tx_descq_fls_done",
1425         "driver_rx_descq_fls_done",
1426         "driver_rx_descq_fls_failed",
1427         "driver_rx_dsc_error",
1428         "driver_tx_dsc_error",
1429         "drv_gen",
1430         "mcdi_response",
1431 };
1432 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1433
1434                 const char *
1435 efx_ev_qstat_name(
1436         __in    efx_nic_t *enp,
1437         __in    unsigned int id)
1438 {
1439         _NOTE(ARGUNUSED(enp))
1440
1441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1442         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1443
1444         return (__efx_ev_qstat_name[id]);
1445 }
1446 #endif  /* EFSYS_OPT_NAMES */
1447 #endif  /* EFSYS_OPT_QSTATS */
1448
1449 #if EFSYS_OPT_SIENA
1450
1451 #if EFSYS_OPT_QSTATS
1452 static                                  void
1453 siena_ev_qstats_update(
1454         __in                            efx_evq_t *eep,
1455         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1456 {
1457         unsigned int id;
1458
1459         for (id = 0; id < EV_NQSTATS; id++) {
1460                 efsys_stat_t *essp = &stat[id];
1461
1462                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1463                 eep->ee_stat[id] = 0;
1464         }
1465 }
1466 #endif  /* EFSYS_OPT_QSTATS */
1467
1468 static          void
1469 siena_ev_qdestroy(
1470         __in    efx_evq_t *eep)
1471 {
1472         efx_nic_t *enp = eep->ee_enp;
1473         efx_oword_t oword;
1474
1475         /* Purge event queue */
1476         EFX_ZERO_OWORD(oword);
1477
1478         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1479             eep->ee_index, &oword, B_TRUE);
1480
1481         EFX_ZERO_OWORD(oword);
1482         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1483 }
1484
1485 static          void
1486 siena_ev_fini(
1487         __in    efx_nic_t *enp)
1488 {
1489         _NOTE(ARGUNUSED(enp))
1490 }
1491
1492 #endif /* EFSYS_OPT_SIENA */