sys/dev/sfxge/common/efx_ev.c

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "efsys.h"
  35 #include "efx.h"
  36 #include "efx_types.h"
  37 #include "efx_regs.h"
  38 #include "efx_impl.h"
  39 #include "mcdi_mon.h"
  40
  41 #if EFSYS_OPT_QSTATS
  42 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  43         do {                                                            \
  44                 (_eep)->ee_stat[_stat]++;                               \
  45         _NOTE(CONSTANTCONDITION)                                        \
  46         } while (B_FALSE)
  47 #else
  48 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  49 #endif
  50
  51 #define EFX_EV_PRESENT(_qword)                                          \
  52         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  53         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  54
  55
  56
  57 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
  58
  59 static  __checkReturn   efx_rc_t
  60 falconsiena_ev_init(
  61         __in            efx_nic_t *enp);
  62
  63 static                  void
  64 falconsiena_ev_fini(
  65         __in            efx_nic_t *enp);
  66
  67 static  __checkReturn   efx_rc_t
  68 falconsiena_ev_qcreate(
  69         __in            efx_nic_t *enp,
  70         __in            unsigned int index,
  71         __in            efsys_mem_t *esmp,
  72         __in            size_t n,
  73         __in            uint32_t id,
  74         __in            efx_evq_t *eep);
  75
  76 static                  void
  77 falconsiena_ev_qdestroy(
  78         __in            efx_evq_t *eep);
  79
  80 static  __checkReturn   efx_rc_t
  81 falconsiena_ev_qprime(
  82         __in            efx_evq_t *eep,
  83         __in            unsigned int count);
  84
  85 static                  void
  86 falconsiena_ev_qpoll(
  87         __in            efx_evq_t *eep,
  88         __inout         unsigned int *countp,
  89         __in            const efx_ev_callbacks_t *eecp,
  90         __in_opt        void *arg);
  91
  92 static                  void
  93 falconsiena_ev_qpost(
  94         __in    efx_evq_t *eep,
  95         __in    uint16_t data);
  96
  97 static  __checkReturn   efx_rc_t
  98 falconsiena_ev_qmoderate(
  99         __in            efx_evq_t *eep,
 100         __in            unsigned int us);
 101
 102 #if EFSYS_OPT_QSTATS
 103 static                  void
 104 falconsiena_ev_qstats_update(
 105         __in                            efx_evq_t *eep,
 106         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
 107
 108 #endif
 109
 110 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
 111
 112 #if EFSYS_OPT_FALCON
 113 static efx_ev_ops_t     __efx_ev_falcon_ops = {
 114         falconsiena_ev_init,                    /* eevo_init */
 115         falconsiena_ev_fini,                    /* eevo_fini */
 116         falconsiena_ev_qcreate,                 /* eevo_qcreate */
 117         falconsiena_ev_qdestroy,                /* eevo_qdestroy */
 118         falconsiena_ev_qprime,                  /* eevo_qprime */
 119         falconsiena_ev_qpost,                   /* eevo_qpost */
 120         falconsiena_ev_qmoderate,               /* eevo_qmoderate */
 121 #if EFSYS_OPT_QSTATS
 122         falconsiena_ev_qstats_update,           /* eevo_qstats_update */
 123 #endif
 124 };
 125 #endif /* EFSYS_OPT_FALCON */
 126
 127 #if EFSYS_OPT_SIENA
 128 static efx_ev_ops_t     __efx_ev_siena_ops = {
 129         falconsiena_ev_init,                    /* eevo_init */
 130         falconsiena_ev_fini,                    /* eevo_fini */
 131         falconsiena_ev_qcreate,                 /* eevo_qcreate */
 132         falconsiena_ev_qdestroy,                /* eevo_qdestroy */
 133         falconsiena_ev_qprime,                  /* eevo_qprime */
 134         falconsiena_ev_qpost,                   /* eevo_qpost */
 135         falconsiena_ev_qmoderate,               /* eevo_qmoderate */
 136 #if EFSYS_OPT_QSTATS
 137         falconsiena_ev_qstats_update,           /* eevo_qstats_update */
 138 #endif
 139 };
 140 #endif /* EFSYS_OPT_SIENA */
 141
 142 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 143 static efx_ev_ops_t     __efx_ev_ef10_ops = {
 144         ef10_ev_init,                           /* eevo_init */
 145         ef10_ev_fini,                           /* eevo_fini */
 146         ef10_ev_qcreate,                        /* eevo_qcreate */
 147         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 148         ef10_ev_qprime,                         /* eevo_qprime */
 149         ef10_ev_qpost,                          /* eevo_qpost */
 150         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 151 #if EFSYS_OPT_QSTATS
 152         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 153 #endif
 154 };
 155 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 156
 157
 158         __checkReturn   efx_rc_t
 159 efx_ev_init(
 160         __in            efx_nic_t *enp)
 161 {
 162         efx_ev_ops_t *eevop;
 163         efx_rc_t rc;
 164
 165         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 166         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 167
 168         if (enp->en_mod_flags & EFX_MOD_EV) {
 169                 rc = EINVAL;
 170                 goto fail1;
 171         }
 172
 173         switch (enp->en_family) {
 174 #if EFSYS_OPT_FALCON
 175         case EFX_FAMILY_FALCON:
 176                 eevop = (efx_ev_ops_t *)&__efx_ev_falcon_ops;
 177                 break;
 178 #endif /* EFSYS_OPT_FALCON */
 179
 180 #if EFSYS_OPT_SIENA
 181         case EFX_FAMILY_SIENA:
 182                 eevop = (efx_ev_ops_t *)&__efx_ev_siena_ops;
 183                 break;
 184 #endif /* EFSYS_OPT_SIENA */
 185
 186 #if EFSYS_OPT_HUNTINGTON
 187         case EFX_FAMILY_HUNTINGTON:
 188                 eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops;
 189                 break;
 190 #endif /* EFSYS_OPT_HUNTINGTON */
 191
 192 #if EFSYS_OPT_MEDFORD
 193         case EFX_FAMILY_MEDFORD:
 194                 eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops;
 195                 break;
 196 #endif /* EFSYS_OPT_MEDFORD */
 197
 198         default:
 199                 EFSYS_ASSERT(0);
 200                 rc = ENOTSUP;
 201                 goto fail1;
 202         }
 203
 204         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 205
 206         if ((rc = eevop->eevo_init(enp)) != 0)
 207                 goto fail2;
 208
 209         enp->en_eevop = eevop;
 210         enp->en_mod_flags |= EFX_MOD_EV;
 211         return (0);
 212
 213 fail2:
 214         EFSYS_PROBE(fail2);
 215
 216 fail1:
 217         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 218
 219         enp->en_eevop = NULL;
 220         enp->en_mod_flags &= ~EFX_MOD_EV;
 221         return (rc);
 222 }
 223
 224                 void
 225 efx_ev_fini(
 226         __in    efx_nic_t *enp)
 227 {
 228         efx_ev_ops_t *eevop = enp->en_eevop;
 229
 230         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 231         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 232         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 233         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 234         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 235         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 236
 237         eevop->eevo_fini(enp);
 238
 239         enp->en_eevop = NULL;
 240         enp->en_mod_flags &= ~EFX_MOD_EV;
 241 }
 242
 243
 244         __checkReturn   efx_rc_t
 245 efx_ev_qcreate(
 246         __in            efx_nic_t *enp,
 247         __in            unsigned int index,
 248         __in            efsys_mem_t *esmp,
 249         __in            size_t n,
 250         __in            uint32_t id,
 251         __deref_out     efx_evq_t **eepp)
 252 {
 253         efx_ev_ops_t *eevop = enp->en_eevop;
 254         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 255         efx_evq_t *eep;
 256         efx_rc_t rc;
 257
 258         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 259         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 260
 261         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
 262
 263         /* Allocate an EVQ object */
 264         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 265         if (eep == NULL) {
 266                 rc = ENOMEM;
 267                 goto fail1;
 268         }
 269
 270         eep->ee_magic = EFX_EVQ_MAGIC;
 271         eep->ee_enp = enp;
 272         eep->ee_index = index;
 273         eep->ee_mask = n - 1;
 274         eep->ee_esmp = esmp;
 275
 276         if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0)
 277                 goto fail2;
 278
 279         enp->en_ev_qcount++;
 280         *eepp = eep;
 281
 282         return (0);
 283
 284 fail2:
 285         EFSYS_PROBE(fail2);
 286         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 287 fail1:
 288         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 289         return (rc);
 290 }
 291
 292                 void
 293 efx_ev_qdestroy(
 294         __in    efx_evq_t *eep)
 295 {
 296         efx_nic_t *enp = eep->ee_enp;
 297         efx_ev_ops_t *eevop = enp->en_eevop;
 298
 299         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 300
 301         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 302         --enp->en_ev_qcount;
 303
 304         eevop->eevo_qdestroy(eep);
 305
 306         /* Free the EVQ object */
 307         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 308 }
 309
 310         __checkReturn   efx_rc_t
 311 efx_ev_qprime(
 312         __in            efx_evq_t *eep,
 313         __in            unsigned int count)
 314 {
 315         efx_nic_t *enp = eep->ee_enp;
 316         efx_ev_ops_t *eevop = enp->en_eevop;
 317         efx_rc_t rc;
 318
 319         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 320
 321         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 322                 rc = EINVAL;
 323                 goto fail1;
 324         }
 325
 326         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 327                 goto fail2;
 328
 329         return (0);
 330
 331 fail2:
 332         EFSYS_PROBE(fail2);
 333 fail1:
 334         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 335         return (rc);
 336 }
 337
 338         __checkReturn   boolean_t
 339 efx_ev_qpending(
 340         __in            efx_evq_t *eep,
 341         __in            unsigned int count)
 342 {
 343         size_t offset;
 344         efx_qword_t qword;
 345
 346         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 347
 348         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 349         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 350
 351         return (EFX_EV_PRESENT(qword));
 352 }
 353
 354 #if EFSYS_OPT_EV_PREFETCH
 355
 356                         void
 357 efx_ev_qprefetch(
 358         __in            efx_evq_t *eep,
 359         __in            unsigned int count)
 360 {
 361         efx_nic_t *enp = eep->ee_enp;
 362         unsigned int offset;
 363
 364         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 365
 366         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 367         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 368 }
 369
 370 #endif  /* EFSYS_OPT_EV_PREFETCH */
 371
 372                         void
 373 efx_ev_qpoll(
 374         __in            efx_evq_t *eep,
 375         __inout         unsigned int *countp,
 376         __in            const efx_ev_callbacks_t *eecp,
 377         __in_opt        void *arg)
 378 {
 379         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 380
 381         /*
 382          * FIXME: Huntington will require support for hardware event batching
 383          * and merging, which will need a different ev_qpoll implementation.
 384          *
 385          * Without those features the Falcon/Siena code can be used unchanged.
 386          */
 387         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 388         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 389
 390         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 391         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 392         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 393         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 394             FSE_AZ_EV_CODE_DRV_GEN_EV);
 395 #if EFSYS_OPT_MCDI
 396         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 397             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 398 #endif
 399         falconsiena_ev_qpoll(eep, countp, eecp, arg);
 400 }
 401
 402                         void
 403 efx_ev_qpost(
 404         __in    efx_evq_t *eep,
 405         __in    uint16_t data)
 406 {
 407         efx_nic_t *enp = eep->ee_enp;
 408         efx_ev_ops_t *eevop = enp->en_eevop;
 409
 410         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 411
 412         EFSYS_ASSERT(eevop != NULL &&
 413             eevop->eevo_qpost != NULL);
 414
 415         eevop->eevo_qpost(eep, data);
 416 }
 417
 418         __checkReturn   efx_rc_t
 419 efx_ev_qmoderate(
 420         __in            efx_evq_t *eep,
 421         __in            unsigned int us)
 422 {
 423         efx_nic_t *enp = eep->ee_enp;
 424         efx_ev_ops_t *eevop = enp->en_eevop;
 425         efx_rc_t rc;
 426
 427         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 428
 429         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 430                 goto fail1;
 431
 432         return (0);
 433
 434 fail1:
 435         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 436         return (rc);
 437 }
 438
 439 #if EFSYS_OPT_QSTATS
 440                                         void
 441 efx_ev_qstats_update(
 442         __in                            efx_evq_t *eep,
 443         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 444
 445 {       efx_nic_t *enp = eep->ee_enp;
 446         efx_ev_ops_t *eevop = enp->en_eevop;
 447
 448         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 449
 450         eevop->eevo_qstats_update(eep, stat);
 451 }
 452
 453 #endif  /* EFSYS_OPT_QSTATS */
 454
 455 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
 456
 457 static  __checkReturn   efx_rc_t
 458 falconsiena_ev_init(
 459         __in            efx_nic_t *enp)
 460 {
 461         efx_oword_t oword;
 462
 463         /*
 464          * Program the event queue for receive and transmit queue
 465          * flush events.
 466          */
 467         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 468         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 469         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 470
 471         return (0);
 472
 473 }
 474
 475 static  __checkReturn   boolean_t
 476 falconsiena_ev_rx_not_ok(
 477         __in            efx_evq_t *eep,
 478         __in            efx_qword_t *eqp,
 479         __in            uint32_t label,
 480         __in            uint32_t id,
 481         __inout         uint16_t *flagsp)
 482 {
 483         boolean_t ignore = B_FALSE;
 484
 485         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 486                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 487                 EFSYS_PROBE(tobe_disc);
 488                 /*
 489                  * Assume this is a unicast address mismatch, unless below
 490                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 491                  * EV_RX_PAUSE_FRM_ERR is set.
 492                  */
 493                 (*flagsp) |= EFX_ADDR_MISMATCH;
 494         }
 495
 496         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 497                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 498                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 499                 (*flagsp) |= EFX_DISCARD;
 500
 501 #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
 502                 /*
 503                  * Lookout for payload queue ran dry errors and ignore them.
 504                  *
 505                  * Sadly for the header/data split cases, the descriptor
 506                  * pointer in this event refers to the header queue and
 507                  * therefore cannot be easily detected as duplicate.
 508                  * So we drop these and rely on the receive processing seeing
 509                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 510                  * the partially received packet.
 511                  */
 512                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 513                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 514                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 515                         ignore = B_TRUE;
 516 #endif  /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
 517         }
 518
 519         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 520                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 521                 EFSYS_PROBE(crc_err);
 522                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 523                 (*flagsp) |= EFX_DISCARD;
 524         }
 525
 526         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 527                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 528                 EFSYS_PROBE(pause_frm_err);
 529                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 530                 (*flagsp) |= EFX_DISCARD;
 531         }
 532
 533         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 534                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 535                 EFSYS_PROBE(owner_id_err);
 536                 (*flagsp) |= EFX_DISCARD;
 537         }
 538
 539         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 540                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 541                 EFSYS_PROBE(ipv4_err);
 542                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 543         }
 544
 545         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 546                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 547                 EFSYS_PROBE(udp_chk_err);
 548                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 549         }
 550
 551         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 552                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 553
 554                 /*
 555                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 556                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 557                  * condition.
 558                  */
 559                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 560         }
 561
 562         return (ignore);
 563 }
 564
 565 static  __checkReturn   boolean_t
 566 falconsiena_ev_rx(
 567         __in            efx_evq_t *eep,
 568         __in            efx_qword_t *eqp,
 569         __in            const efx_ev_callbacks_t *eecp,
 570         __in_opt        void *arg)
 571 {
 572         efx_nic_t *enp = eep->ee_enp;
 573         uint32_t id;
 574         uint32_t size;
 575         uint32_t label;
 576         boolean_t ok;
 577 #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
 578         boolean_t sop;
 579         boolean_t jumbo_cont;
 580 #endif  /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
 581         uint32_t hdr_type;
 582         boolean_t is_v6;
 583         uint16_t flags;
 584         boolean_t ignore;
 585         boolean_t should_abort;
 586
 587         EFX_EV_QSTAT_INCR(eep, EV_RX);
 588
 589         /* Basic packet information */
 590         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 591         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 592         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 593         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 594
 595 #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
 596         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 597         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 598 #endif  /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
 599
 600         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 601
 602         is_v6 = (enp->en_family != EFX_FAMILY_FALCON &&
 603                     EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 604
 605         /*
 606          * If packet is marked as OK and packet type is TCP/IP or
 607          * UDP/IP or other IP, then we can rely on the hardware checksums.
 608          */
 609         switch (hdr_type) {
 610         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 611                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 612                 if (is_v6) {
 613                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 614                         flags |= EFX_PKT_IPV6;
 615                 } else {
 616                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 617                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 618                 }
 619                 break;
 620
 621         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 622                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 623                 if (is_v6) {
 624                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 625                         flags |= EFX_PKT_IPV6;
 626                 } else {
 627                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 628                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 629                 }
 630                 break;
 631
 632         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 633                 if (is_v6) {
 634                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 635                         flags = EFX_PKT_IPV6;
 636                 } else {
 637                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 638                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 639                 }
 640                 break;
 641
 642         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 643                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 644                 flags = 0;
 645                 break;
 646
 647         default:
 648                 EFSYS_ASSERT(B_FALSE);
 649                 flags = 0;
 650                 break;
 651         }
 652
 653 #if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT
 654         /* Report scatter and header/lookahead split buffer flags */
 655         if (sop)
 656                 flags |= EFX_PKT_START;
 657         if (jumbo_cont)
 658                 flags |= EFX_PKT_CONT;
 659 #endif  /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */
 660
 661         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 662         if (!ok) {
 663                 ignore = falconsiena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 664                 if (ignore) {
 665                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 666                             uint32_t, size, uint16_t, flags);
 667
 668                         return (B_FALSE);
 669                 }
 670         }
 671
 672         /* If we're not discarding the packet then it is ok */
 673         if (~flags & EFX_DISCARD)
 674                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 675
 676         /* Detect multicast packets that didn't match the filter */
 677         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 678                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 679
 680                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 681                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 682                 } else {
 683                         EFSYS_PROBE(mcast_mismatch);
 684                         flags |= EFX_ADDR_MISMATCH;
 685                 }
 686         } else {
 687                 flags |= EFX_PKT_UNICAST;
 688         }
 689
 690         /*
 691          * The packet parser in Siena can abort parsing packets under
 692          * certain error conditions, setting the PKT_NOT_PARSED bit
 693          * (which clears PKT_OK). If this is set, then don't trust
 694          * the PKT_TYPE field.
 695          */
 696         if (enp->en_family != EFX_FAMILY_FALCON && !ok) {
 697                 uint32_t parse_err;
 698
 699                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 700                 if (parse_err != 0)
 701                         flags |= EFX_CHECK_VLAN;
 702         }
 703
 704         if (~flags & EFX_CHECK_VLAN) {
 705                 uint32_t pkt_type;
 706
 707                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 708                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 709                         flags |= EFX_PKT_VLAN_TAGGED;
 710         }
 711
 712         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 713             uint32_t, size, uint16_t, flags);
 714
 715         EFSYS_ASSERT(eecp->eec_rx != NULL);
 716         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 717
 718         return (should_abort);
 719 }
 720
 721 static  __checkReturn   boolean_t
 722 falconsiena_ev_tx(
 723         __in            efx_evq_t *eep,
 724         __in            efx_qword_t *eqp,
 725         __in            const efx_ev_callbacks_t *eecp,
 726         __in_opt        void *arg)
 727 {
 728         uint32_t id;
 729         uint32_t label;
 730         boolean_t should_abort;
 731
 732         EFX_EV_QSTAT_INCR(eep, EV_TX);
 733
 734         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 735             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 736             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 737             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 738
 739                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 740                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 741
 742                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 743
 744                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 745                 should_abort = eecp->eec_tx(arg, label, id);
 746
 747                 return (should_abort);
 748         }
 749
 750         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 751                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 752                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 753                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 754
 755         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 756                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 757
 758         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 759                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 760
 761         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 762                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 763
 764         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 765         return (B_FALSE);
 766 }
 767
 768 static  __checkReturn   boolean_t
 769 falconsiena_ev_global(
 770         __in            efx_evq_t *eep,
 771         __in            efx_qword_t *eqp,
 772         __in            const efx_ev_callbacks_t *eecp,
 773         __in_opt        void *arg)
 774 {
 775         efx_nic_t *enp = eep->ee_enp;
 776         efx_port_t *epp = &(enp->en_port);
 777         boolean_t should_abort;
 778
 779         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 780         should_abort = B_FALSE;
 781
 782         /* Check for a link management event */
 783         if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) {
 784                 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT);
 785
 786                 EFSYS_PROBE(xg_mgt);
 787
 788                 epp->ep_mac_poll_needed = B_TRUE;
 789         }
 790
 791         return (should_abort);
 792 }
 793
 794 static  __checkReturn   boolean_t
 795 falconsiena_ev_driver(
 796         __in            efx_evq_t *eep,
 797         __in            efx_qword_t *eqp,
 798         __in            const efx_ev_callbacks_t *eecp,
 799         __in_opt        void *arg)
 800 {
 801         boolean_t should_abort;
 802
 803         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 804         should_abort = B_FALSE;
 805
 806         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 807         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 808                 uint32_t txq_index;
 809
 810                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 811
 812                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 813
 814                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 815
 816                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 817                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 818
 819                 break;
 820         }
 821         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 822                 uint32_t rxq_index;
 823                 uint32_t failed;
 824
 825                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 826                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 827
 828                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 829                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 830
 831                 if (failed) {
 832                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 833
 834                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 835
 836                         should_abort = eecp->eec_rxq_flush_failed(arg,
 837                                                                     rxq_index);
 838                 } else {
 839                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 840
 841                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 842
 843                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 844                 }
 845
 846                 break;
 847         }
 848         case FSE_AZ_EVQ_INIT_DONE_EV:
 849                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 850                 should_abort = eecp->eec_initialized(arg);
 851
 852                 break;
 853
 854         case FSE_AZ_EVQ_NOT_EN_EV:
 855                 EFSYS_PROBE(evq_not_en);
 856                 break;
 857
 858         case FSE_AZ_SRM_UPD_DONE_EV: {
 859                 uint32_t code;
 860
 861                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 862
 863                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 864
 865                 EFSYS_ASSERT(eecp->eec_sram != NULL);
 866                 should_abort = eecp->eec_sram(arg, code);
 867
 868                 break;
 869         }
 870         case FSE_AZ_WAKE_UP_EV: {
 871                 uint32_t id;
 872
 873                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 874
 875                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
 876                 should_abort = eecp->eec_wake_up(arg, id);
 877
 878                 break;
 879         }
 880         case FSE_AZ_TX_PKT_NON_TCP_UDP:
 881                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
 882                 break;
 883
 884         case FSE_AZ_TIMER_EV: {
 885                 uint32_t id;
 886
 887                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 888
 889                 EFSYS_ASSERT(eecp->eec_timer != NULL);
 890                 should_abort = eecp->eec_timer(arg, id);
 891
 892                 break;
 893         }
 894         case FSE_AZ_RX_DSC_ERROR_EV:
 895                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
 896
 897                 EFSYS_PROBE(rx_dsc_error);
 898
 899                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 900                 should_abort = eecp->eec_exception(arg,
 901                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
 902
 903                 break;
 904
 905         case FSE_AZ_TX_DSC_ERROR_EV:
 906                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
 907
 908                 EFSYS_PROBE(tx_dsc_error);
 909
 910                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 911                 should_abort = eecp->eec_exception(arg,
 912                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
 913
 914                 break;
 915
 916         default:
 917                 break;
 918         }
 919
 920         return (should_abort);
 921 }
 922
 923 static  __checkReturn   boolean_t
 924 falconsiena_ev_drv_gen(
 925         __in            efx_evq_t *eep,
 926         __in            efx_qword_t *eqp,
 927         __in            const efx_ev_callbacks_t *eecp,
 928         __in_opt        void *arg)
 929 {
 930         uint32_t data;
 931         boolean_t should_abort;
 932
 933         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
 934
 935         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
 936         if (data >= ((uint32_t)1 << 16)) {
 937                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 938                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 939                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 940                 return (B_TRUE);
 941         }
 942
 943         EFSYS_ASSERT(eecp->eec_software != NULL);
 944         should_abort = eecp->eec_software(arg, (uint16_t)data);
 945
 946         return (should_abort);
 947 }
 948
 949 #if EFSYS_OPT_MCDI
 950
 951 static  __checkReturn   boolean_t
 952 falconsiena_ev_mcdi(
 953         __in            efx_evq_t *eep,
 954         __in            efx_qword_t *eqp,
 955         __in            const efx_ev_callbacks_t *eecp,
 956         __in_opt        void *arg)
 957 {
 958         efx_nic_t *enp = eep->ee_enp;
 959         unsigned code;
 960         boolean_t should_abort = B_FALSE;
 961
 962         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 963
 964         if (enp->en_family != EFX_FAMILY_SIENA)
 965                 goto out;
 966
 967         EFSYS_ASSERT(eecp->eec_link_change != NULL);
 968         EFSYS_ASSERT(eecp->eec_exception != NULL);
 969 #if EFSYS_OPT_MON_STATS
 970         EFSYS_ASSERT(eecp->eec_monitor != NULL);
 971 #endif
 972
 973         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
 974
 975         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
 976         switch (code) {
 977         case MCDI_EVENT_CODE_BADSSERT:
 978                 efx_mcdi_ev_death(enp, EINTR);
 979                 break;
 980
 981         case MCDI_EVENT_CODE_CMDDONE:
 982                 efx_mcdi_ev_cpl(enp,
 983                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
 984                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
 985                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
 986                 break;
 987
 988         case MCDI_EVENT_CODE_LINKCHANGE: {
 989                 efx_link_mode_t link_mode;
 990
 991                 siena_phy_link_ev(enp, eqp, &link_mode);
 992                 should_abort = eecp->eec_link_change(arg, link_mode);
 993                 break;
 994         }
 995         case MCDI_EVENT_CODE_SENSOREVT: {
 996 #if EFSYS_OPT_MON_STATS
 997                 efx_mon_stat_t id;
 998                 efx_mon_stat_value_t value;
 999                 efx_rc_t rc;
1000
1001                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1002                         should_abort = eecp->eec_monitor(arg, id, value);
1003                 else if (rc == ENOTSUP) {
1004                         should_abort = eecp->eec_exception(arg,
1005                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1006                                 MCDI_EV_FIELD(eqp, DATA));
1007                 } else
1008                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1009 #else
1010                 should_abort = B_FALSE;
1011 #endif
1012                 break;
1013         }
1014         case MCDI_EVENT_CODE_SCHEDERR:
1015                 /* Informational only */
1016                 break;
1017
1018         case MCDI_EVENT_CODE_REBOOT:
1019                 efx_mcdi_ev_death(enp, EIO);
1020                 break;
1021
1022         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1023 #if EFSYS_OPT_MAC_STATS
1024                 if (eecp->eec_mac_stats != NULL) {
1025                         eecp->eec_mac_stats(arg,
1026                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1027                 }
1028 #endif
1029                 break;
1030
1031         case MCDI_EVENT_CODE_FWALERT: {
1032                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1033
1034                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1035                         should_abort = eecp->eec_exception(arg,
1036                                 EFX_EXCEPTION_FWALERT_SRAM,
1037                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1038                 else
1039                         should_abort = eecp->eec_exception(arg,
1040                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1041                                 MCDI_EV_FIELD(eqp, DATA));
1042                 break;
1043         }
1044
1045         default:
1046                 EFSYS_PROBE1(mc_pcol_error, int, code);
1047                 break;
1048         }
1049
1050 out:
1051         return (should_abort);
1052 }
1053
1054 #endif  /* EFSYS_OPT_MCDI */
1055
1056 static  __checkReturn   efx_rc_t
1057 falconsiena_ev_qprime(
1058         __in            efx_evq_t *eep,
1059         __in            unsigned int count)
1060 {
1061         efx_nic_t *enp = eep->ee_enp;
1062         uint32_t rptr;
1063         efx_dword_t dword;
1064
1065         rptr = count & eep->ee_mask;
1066
1067         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1068
1069         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1070                             &dword, B_FALSE);
1071
1072         return (0);
1073 }
1074
1075 #define EFX_EV_BATCH    8
1076
1077 static                  void
1078 falconsiena_ev_qpoll(
1079         __in            efx_evq_t *eep,
1080         __inout         unsigned int *countp,
1081         __in            const efx_ev_callbacks_t *eecp,
1082         __in_opt        void *arg)
1083 {
1084         efx_qword_t ev[EFX_EV_BATCH];
1085         unsigned int batch;
1086         unsigned int total;
1087         unsigned int count;
1088         unsigned int index;
1089         size_t offset;
1090
1091         EFSYS_ASSERT(countp != NULL);
1092         EFSYS_ASSERT(eecp != NULL);
1093
1094         count = *countp;
1095         do {
1096                 /* Read up until the end of the batch period */
1097                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1098                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1099                 for (total = 0; total < batch; ++total) {
1100                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1101
1102                         if (!EFX_EV_PRESENT(ev[total]))
1103                                 break;
1104
1105                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1106                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1107                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1108
1109                         offset += sizeof (efx_qword_t);
1110                 }
1111
1112 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1113                 /*
1114                  * Prefetch the next batch when we get within PREFETCH_PERIOD
1115                  * of a completed batch. If the batch is smaller, then prefetch
1116                  * immediately.
1117                  */
1118                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1119                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1120 #endif  /* EFSYS_OPT_EV_PREFETCH */
1121
1122                 /* Process the batch of events */
1123                 for (index = 0; index < total; ++index) {
1124                         boolean_t should_abort;
1125                         uint32_t code;
1126
1127 #if EFSYS_OPT_EV_PREFETCH
1128                         /* Prefetch if we've now reached the batch period */
1129                         if (total == batch &&
1130                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1131                                 offset = (count + batch) & eep->ee_mask;
1132                                 offset *= sizeof (efx_qword_t);
1133
1134                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1135                         }
1136 #endif  /* EFSYS_OPT_EV_PREFETCH */
1137
1138                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
1139
1140                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1141                         switch (code) {
1142                         case FSE_AZ_EV_CODE_RX_EV:
1143                                 should_abort = eep->ee_rx(eep,
1144                                     &(ev[index]), eecp, arg);
1145                                 break;
1146                         case FSE_AZ_EV_CODE_TX_EV:
1147                                 should_abort = eep->ee_tx(eep,
1148                                     &(ev[index]), eecp, arg);
1149                                 break;
1150                         case FSE_AZ_EV_CODE_DRIVER_EV:
1151                                 should_abort = eep->ee_driver(eep,
1152                                     &(ev[index]), eecp, arg);
1153                                 break;
1154                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
1155                                 should_abort = eep->ee_drv_gen(eep,
1156                                     &(ev[index]), eecp, arg);
1157                                 break;
1158 #if EFSYS_OPT_MCDI
1159                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1160                                 should_abort = eep->ee_mcdi(eep,
1161                                     &(ev[index]), eecp, arg);
1162                                 break;
1163 #endif
1164                         case FSE_AZ_EV_CODE_GLOBAL_EV:
1165                                 if (eep->ee_global) {
1166                                         should_abort = eep->ee_global(eep,
1167                                             &(ev[index]), eecp, arg);
1168                                         break;
1169                                 }
1170                                 /* else fallthrough */
1171                         default:
1172                                 EFSYS_PROBE3(bad_event,
1173                                     unsigned int, eep->ee_index,
1174                                     uint32_t,
1175                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1176                                     uint32_t,
1177                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1178
1179                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1180                                 (void) eecp->eec_exception(arg,
1181                                         EFX_EXCEPTION_EV_ERROR, code);
1182                                 should_abort = B_TRUE;
1183                         }
1184                         if (should_abort) {
1185                                 /* Ignore subsequent events */
1186                                 total = index + 1;
1187                                 break;
1188                         }
1189                 }
1190
1191                 /*
1192                  * Now that the hardware has most likely moved onto dma'ing
1193                  * into the next cache line, clear the processed events. Take
1194                  * care to only clear out events that we've processed
1195                  */
1196                 EFX_SET_QWORD(ev[0]);
1197                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1198                 for (index = 0; index < total; ++index) {
1199                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1200                         offset += sizeof (efx_qword_t);
1201                 }
1202
1203                 count += total;
1204
1205         } while (total == batch);
1206
1207         *countp = count;
1208 }
1209
1210 static          void
1211 falconsiena_ev_qpost(
1212         __in    efx_evq_t *eep,
1213         __in    uint16_t data)
1214 {
1215         efx_nic_t *enp = eep->ee_enp;
1216         efx_qword_t ev;
1217         efx_oword_t oword;
1218
1219         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1220             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1221
1222         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1223             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1224             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1225
1226         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1227 }
1228
1229 static  __checkReturn   efx_rc_t
1230 falconsiena_ev_qmoderate(
1231         __in            efx_evq_t *eep,
1232         __in            unsigned int us)
1233 {
1234         efx_nic_t *enp = eep->ee_enp;
1235         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1236         unsigned int locked;
1237         efx_dword_t dword;
1238         efx_rc_t rc;
1239
1240         if (us > encp->enc_evq_timer_max_us) {
1241                 rc = EINVAL;
1242                 goto fail1;
1243         }
1244
1245         /* If the value is zero then disable the timer */
1246         if (us == 0) {
1247                 if (enp->en_family == EFX_FAMILY_FALCON)
1248                         EFX_POPULATE_DWORD_2(dword,
1249                             FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS,
1250                             FRF_AB_TC_TIMER_VAL, 0);
1251                 else
1252                         EFX_POPULATE_DWORD_2(dword,
1253                             FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1254                             FRF_CZ_TC_TIMER_VAL, 0);
1255         } else {
1256                 uint32_t timer_val;
1257
1258                 /* Calculate the timer value in quanta */
1259                 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
1260
1261                 /* Moderation value is base 0 so we need to deduct 1 */
1262                 if (timer_val > 0)
1263                         timer_val--;
1264
1265                 if (enp->en_family == EFX_FAMILY_FALCON)
1266                         EFX_POPULATE_DWORD_2(dword,
1267                             FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF,
1268                             FRF_AB_TIMER_VAL, timer_val);
1269                 else
1270                         EFX_POPULATE_DWORD_2(dword,
1271                             FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1272                             FRF_CZ_TC_TIMER_VAL, timer_val);
1273         }
1274
1275         locked = (eep->ee_index == 0) ? 1 : 0;
1276
1277         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1278             eep->ee_index, &dword, locked);
1279
1280         return (0);
1281
1282 fail1:
1283         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1284
1285         return (rc);
1286 }
1287
1288 static  __checkReturn   efx_rc_t
1289 falconsiena_ev_qcreate(
1290         __in            efx_nic_t *enp,
1291         __in            unsigned int index,
1292         __in            efsys_mem_t *esmp,
1293         __in            size_t n,
1294         __in            uint32_t id,
1295         __in            efx_evq_t *eep)
1296 {
1297         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1298         uint32_t size;
1299         efx_oword_t oword;
1300         efx_rc_t rc;
1301
1302         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1303         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1304
1305         if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1306                 rc = EINVAL;
1307                 goto fail1;
1308         }
1309         if (index >= encp->enc_evq_limit) {
1310                 rc = EINVAL;
1311                 goto fail2;
1312         }
1313 #if EFSYS_OPT_RX_SCALE
1314         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1315             index >= EFX_MAXRSS_LEGACY) {
1316                 rc = EINVAL;
1317                 goto fail3;
1318         }
1319 #endif
1320         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1321             size++)
1322                 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1323                         break;
1324         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1325                 rc = EINVAL;
1326                 goto fail4;
1327         }
1328
1329         /* Set up the handler table */
1330         eep->ee_rx      = falconsiena_ev_rx;
1331         eep->ee_tx      = falconsiena_ev_tx;
1332         eep->ee_driver  = falconsiena_ev_driver;
1333         eep->ee_global  = falconsiena_ev_global;
1334         eep->ee_drv_gen = falconsiena_ev_drv_gen;
1335 #if EFSYS_OPT_MCDI
1336         eep->ee_mcdi    = falconsiena_ev_mcdi;
1337 #endif  /* EFSYS_OPT_MCDI */
1338
1339         /* Set up the new event queue */
1340         if (enp->en_family != EFX_FAMILY_FALCON) {
1341                 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
1342                 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1343         }
1344
1345         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1346             FRF_AZ_EVQ_BUF_BASE_ID, id);
1347
1348         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1349
1350         return (0);
1351
1352 fail4:
1353         EFSYS_PROBE(fail4);
1354 #if EFSYS_OPT_RX_SCALE
1355 fail3:
1356         EFSYS_PROBE(fail3);
1357 #endif
1358 fail2:
1359         EFSYS_PROBE(fail2);
1360 fail1:
1361         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1362
1363         return (rc);
1364 }
1365
1366 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
1367
1368 #if EFSYS_OPT_QSTATS
1369 #if EFSYS_OPT_NAMES
1370 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */
1371 static const char       *__efx_ev_qstat_name[] = {
1372         "all",
1373         "rx",
1374         "rx_ok",
1375         "rx_frm_trunc",
1376         "rx_tobe_disc",
1377         "rx_pause_frm_err",
1378         "rx_buf_owner_id_err",
1379         "rx_ipv4_hdr_chksum_err",
1380         "rx_tcp_udp_chksum_err",
1381         "rx_eth_crc_err",
1382         "rx_ip_frag_err",
1383         "rx_mcast_pkt",
1384         "rx_mcast_hash_match",
1385         "rx_tcp_ipv4",
1386         "rx_tcp_ipv6",
1387         "rx_udp_ipv4",
1388         "rx_udp_ipv6",
1389         "rx_other_ipv4",
1390         "rx_other_ipv6",
1391         "rx_non_ip",
1392         "rx_batch",
1393         "tx",
1394         "tx_wq_ff_full",
1395         "tx_pkt_err",
1396         "tx_pkt_too_big",
1397         "tx_unexpected",
1398         "global",
1399         "global_mnt",
1400         "driver",
1401         "driver_srm_upd_done",
1402         "driver_tx_descq_fls_done",
1403         "driver_rx_descq_fls_done",
1404         "driver_rx_descq_fls_failed",
1405         "driver_rx_dsc_error",
1406         "driver_tx_dsc_error",
1407         "drv_gen",
1408         "mcdi_response",
1409 };
1410 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1411
1412                 const char *
1413 efx_ev_qstat_name(
1414         __in    efx_nic_t *enp,
1415         __in    unsigned int id)
1416 {
1417         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1418         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1419
1420         return (__efx_ev_qstat_name[id]);
1421 }
1422 #endif  /* EFSYS_OPT_NAMES */
1423 #endif  /* EFSYS_OPT_QSTATS */
1424
1425 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
1426
1427 #if EFSYS_OPT_QSTATS
1428 static                                  void
1429 falconsiena_ev_qstats_update(
1430         __in                            efx_evq_t *eep,
1431         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1432 {
1433         unsigned int id;
1434
1435         for (id = 0; id < EV_NQSTATS; id++) {
1436                 efsys_stat_t *essp = &stat[id];
1437
1438                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1439                 eep->ee_stat[id] = 0;
1440         }
1441 }
1442 #endif  /* EFSYS_OPT_QSTATS */
1443
1444 static          void
1445 falconsiena_ev_qdestroy(
1446         __in    efx_evq_t *eep)
1447 {
1448         efx_nic_t *enp = eep->ee_enp;
1449         efx_oword_t oword;
1450
1451         /* Purge event queue */
1452         EFX_ZERO_OWORD(oword);
1453
1454         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1455             eep->ee_index, &oword, B_TRUE);
1456
1457         if (enp->en_family != EFX_FAMILY_FALCON) {
1458                 EFX_ZERO_OWORD(oword);
1459                 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL,
1460                     eep->ee_index, &oword, B_TRUE);
1461         }
1462 }
1463
1464 static          void
1465 falconsiena_ev_fini(
1466         __in    efx_nic_t *enp)
1467 {
1468         _NOTE(ARGUNUSED(enp))
1469 }
1470
1471 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */