sys/dev/sfxge/common/efx_ev.c

   1 /*-
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "efx.h"
  35 #include "efx_impl.h"
  36 #if EFSYS_OPT_MON_MCDI
  37 #include "mcdi_mon.h"
  38 #endif
  39
  40 #if EFSYS_OPT_QSTATS
  41 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  42         do {                                                            \
  43                 (_eep)->ee_stat[_stat]++;                               \
  44         _NOTE(CONSTANTCONDITION)                                        \
  45         } while (B_FALSE)
  46 #else
  47 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  48 #endif
  49
  50 #define EFX_EV_PRESENT(_qword)                                          \
  51         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  52         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  53
  54
  55
  56 #if EFSYS_OPT_SIENA
  57
  58 static  __checkReturn   efx_rc_t
  59 siena_ev_init(
  60         __in            efx_nic_t *enp);
  61
  62 static                  void
  63 siena_ev_fini(
  64         __in            efx_nic_t *enp);
  65
  66 static  __checkReturn   efx_rc_t
  67 siena_ev_qcreate(
  68         __in            efx_nic_t *enp,
  69         __in            unsigned int index,
  70         __in            efsys_mem_t *esmp,
  71         __in            size_t n,
  72         __in            uint32_t id,
  73         __in            uint32_t us,
  74         __in            uint32_t flags,
  75         __in            efx_evq_t *eep);
  76
  77 static                  void
  78 siena_ev_qdestroy(
  79         __in            efx_evq_t *eep);
  80
  81 static  __checkReturn   efx_rc_t
  82 siena_ev_qprime(
  83         __in            efx_evq_t *eep,
  84         __in            unsigned int count);
  85
  86 static                  void
  87 siena_ev_qpost(
  88         __in    efx_evq_t *eep,
  89         __in    uint16_t data);
  90
  91 static  __checkReturn   efx_rc_t
  92 siena_ev_qmoderate(
  93         __in            efx_evq_t *eep,
  94         __in            unsigned int us);
  95
  96 #if EFSYS_OPT_QSTATS
  97 static                  void
  98 siena_ev_qstats_update(
  99         __in                            efx_evq_t *eep,
 100         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
 101
 102 #endif
 103
 104 #endif /* EFSYS_OPT_SIENA */
 105
 106 #if EFSYS_OPT_SIENA
 107 static const efx_ev_ops_t       __efx_ev_siena_ops = {
 108         siena_ev_init,                          /* eevo_init */
 109         siena_ev_fini,                          /* eevo_fini */
 110         siena_ev_qcreate,                       /* eevo_qcreate */
 111         siena_ev_qdestroy,                      /* eevo_qdestroy */
 112         siena_ev_qprime,                        /* eevo_qprime */
 113         siena_ev_qpost,                         /* eevo_qpost */
 114         siena_ev_qmoderate,                     /* eevo_qmoderate */
 115 #if EFSYS_OPT_QSTATS
 116         siena_ev_qstats_update,                 /* eevo_qstats_update */
 117 #endif
 118 };
 119 #endif /* EFSYS_OPT_SIENA */
 120
 121 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 122 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
 123         ef10_ev_init,                           /* eevo_init */
 124         ef10_ev_fini,                           /* eevo_fini */
 125         ef10_ev_qcreate,                        /* eevo_qcreate */
 126         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 127         ef10_ev_qprime,                         /* eevo_qprime */
 128         ef10_ev_qpost,                          /* eevo_qpost */
 129         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 130 #if EFSYS_OPT_QSTATS
 131         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 132 #endif
 133 };
 134 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 135
 136
 137         __checkReturn   efx_rc_t
 138 efx_ev_init(
 139         __in            efx_nic_t *enp)
 140 {
 141         const efx_ev_ops_t *eevop;
 142         efx_rc_t rc;
 143
 144         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 145         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 146
 147         if (enp->en_mod_flags & EFX_MOD_EV) {
 148                 rc = EINVAL;
 149                 goto fail1;
 150         }
 151
 152         switch (enp->en_family) {
 153 #if EFSYS_OPT_SIENA
 154         case EFX_FAMILY_SIENA:
 155                 eevop = &__efx_ev_siena_ops;
 156                 break;
 157 #endif /* EFSYS_OPT_SIENA */
 158
 159 #if EFSYS_OPT_HUNTINGTON
 160         case EFX_FAMILY_HUNTINGTON:
 161                 eevop = &__efx_ev_ef10_ops;
 162                 break;
 163 #endif /* EFSYS_OPT_HUNTINGTON */
 164
 165 #if EFSYS_OPT_MEDFORD
 166         case EFX_FAMILY_MEDFORD:
 167                 eevop = &__efx_ev_ef10_ops;
 168                 break;
 169 #endif /* EFSYS_OPT_MEDFORD */
 170
 171         default:
 172                 EFSYS_ASSERT(0);
 173                 rc = ENOTSUP;
 174                 goto fail1;
 175         }
 176
 177         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 178
 179         if ((rc = eevop->eevo_init(enp)) != 0)
 180                 goto fail2;
 181
 182         enp->en_eevop = eevop;
 183         enp->en_mod_flags |= EFX_MOD_EV;
 184         return (0);
 185
 186 fail2:
 187         EFSYS_PROBE(fail2);
 188
 189 fail1:
 190         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 191
 192         enp->en_eevop = NULL;
 193         enp->en_mod_flags &= ~EFX_MOD_EV;
 194         return (rc);
 195 }
 196
 197                 void
 198 efx_ev_fini(
 199         __in    efx_nic_t *enp)
 200 {
 201         const efx_ev_ops_t *eevop = enp->en_eevop;
 202
 203         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 204         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 205         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 206         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 207         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 208         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 209
 210         eevop->eevo_fini(enp);
 211
 212         enp->en_eevop = NULL;
 213         enp->en_mod_flags &= ~EFX_MOD_EV;
 214 }
 215
 216
 217         __checkReturn   efx_rc_t
 218 efx_ev_qcreate(
 219         __in            efx_nic_t *enp,
 220         __in            unsigned int index,
 221         __in            efsys_mem_t *esmp,
 222         __in            size_t n,
 223         __in            uint32_t id,
 224         __in            uint32_t us,
 225         __in            uint32_t flags,
 226         __deref_out     efx_evq_t **eepp)
 227 {
 228         const efx_ev_ops_t *eevop = enp->en_eevop;
 229         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 230         efx_evq_t *eep;
 231         efx_rc_t rc;
 232
 233         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 234         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 235
 236         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
 237
 238         /* Allocate an EVQ object */
 239         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 240         if (eep == NULL) {
 241                 rc = ENOMEM;
 242                 goto fail1;
 243         }
 244
 245         eep->ee_magic = EFX_EVQ_MAGIC;
 246         eep->ee_enp = enp;
 247         eep->ee_index = index;
 248         eep->ee_mask = n - 1;
 249         eep->ee_esmp = esmp;
 250
 251         /*
 252          * Set outputs before the queue is created because interrupts may be
 253          * raised for events immediately after the queue is created, before the
 254          * function call below returns. See bug58606.
 255          *
 256          * The eepp pointer passed in by the client must therefore point to data
 257          * shared with the client's event processing context.
 258          */
 259         enp->en_ev_qcount++;
 260         *eepp = eep;
 261
 262         if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
 263             eep)) != 0)
 264                 goto fail2;
 265
 266         return (0);
 267
 268 fail2:
 269         EFSYS_PROBE(fail2);
 270
 271         *eepp = NULL;
 272         enp->en_ev_qcount--;
 273         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 274 fail1:
 275         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 276         return (rc);
 277 }
 278
 279                 void
 280 efx_ev_qdestroy(
 281         __in    efx_evq_t *eep)
 282 {
 283         efx_nic_t *enp = eep->ee_enp;
 284         const efx_ev_ops_t *eevop = enp->en_eevop;
 285
 286         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 287
 288         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 289         --enp->en_ev_qcount;
 290
 291         eevop->eevo_qdestroy(eep);
 292
 293         /* Free the EVQ object */
 294         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 295 }
 296
 297         __checkReturn   efx_rc_t
 298 efx_ev_qprime(
 299         __in            efx_evq_t *eep,
 300         __in            unsigned int count)
 301 {
 302         efx_nic_t *enp = eep->ee_enp;
 303         const efx_ev_ops_t *eevop = enp->en_eevop;
 304         efx_rc_t rc;
 305
 306         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 307
 308         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 309                 rc = EINVAL;
 310                 goto fail1;
 311         }
 312
 313         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 314                 goto fail2;
 315
 316         return (0);
 317
 318 fail2:
 319         EFSYS_PROBE(fail2);
 320 fail1:
 321         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 322         return (rc);
 323 }
 324
 325         __checkReturn   boolean_t
 326 efx_ev_qpending(
 327         __in            efx_evq_t *eep,
 328         __in            unsigned int count)
 329 {
 330         size_t offset;
 331         efx_qword_t qword;
 332
 333         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 334
 335         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 336         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 337
 338         return (EFX_EV_PRESENT(qword));
 339 }
 340
 341 #if EFSYS_OPT_EV_PREFETCH
 342
 343                         void
 344 efx_ev_qprefetch(
 345         __in            efx_evq_t *eep,
 346         __in            unsigned int count)
 347 {
 348         unsigned int offset;
 349
 350         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 351
 352         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 353         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 354 }
 355
 356 #endif  /* EFSYS_OPT_EV_PREFETCH */
 357
 358 #define EFX_EV_BATCH    8
 359
 360                         void
 361 efx_ev_qpoll(
 362         __in            efx_evq_t *eep,
 363         __inout         unsigned int *countp,
 364         __in            const efx_ev_callbacks_t *eecp,
 365         __in_opt        void *arg)
 366 {
 367         efx_qword_t ev[EFX_EV_BATCH];
 368         unsigned int batch;
 369         unsigned int total;
 370         unsigned int count;
 371         unsigned int index;
 372         size_t offset;
 373
 374         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
 375         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 376         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 377
 378         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 379         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 380         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 381         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 382             FSE_AZ_EV_CODE_DRV_GEN_EV);
 383 #if EFSYS_OPT_MCDI
 384         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 385             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 386 #endif
 387
 388         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 389         EFSYS_ASSERT(countp != NULL);
 390         EFSYS_ASSERT(eecp != NULL);
 391
 392         count = *countp;
 393         do {
 394                 /* Read up until the end of the batch period */
 395                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
 396                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 397                 for (total = 0; total < batch; ++total) {
 398                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
 399
 400                         if (!EFX_EV_PRESENT(ev[total]))
 401                                 break;
 402
 403                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
 404                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
 405                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
 406
 407                         offset += sizeof (efx_qword_t);
 408                 }
 409
 410 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
 411                 /*
 412                  * Prefetch the next batch when we get within PREFETCH_PERIOD
 413                  * of a completed batch. If the batch is smaller, then prefetch
 414                  * immediately.
 415                  */
 416                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
 417                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 418 #endif  /* EFSYS_OPT_EV_PREFETCH */
 419
 420                 /* Process the batch of events */
 421                 for (index = 0; index < total; ++index) {
 422                         boolean_t should_abort;
 423                         uint32_t code;
 424
 425 #if EFSYS_OPT_EV_PREFETCH
 426                         /* Prefetch if we've now reached the batch period */
 427                         if (total == batch &&
 428                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
 429                                 offset = (count + batch) & eep->ee_mask;
 430                                 offset *= sizeof (efx_qword_t);
 431
 432                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 433                         }
 434 #endif  /* EFSYS_OPT_EV_PREFETCH */
 435
 436                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
 437
 438                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
 439                         switch (code) {
 440                         case FSE_AZ_EV_CODE_RX_EV:
 441                                 should_abort = eep->ee_rx(eep,
 442                                     &(ev[index]), eecp, arg);
 443                                 break;
 444                         case FSE_AZ_EV_CODE_TX_EV:
 445                                 should_abort = eep->ee_tx(eep,
 446                                     &(ev[index]), eecp, arg);
 447                                 break;
 448                         case FSE_AZ_EV_CODE_DRIVER_EV:
 449                                 should_abort = eep->ee_driver(eep,
 450                                     &(ev[index]), eecp, arg);
 451                                 break;
 452                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
 453                                 should_abort = eep->ee_drv_gen(eep,
 454                                     &(ev[index]), eecp, arg);
 455                                 break;
 456 #if EFSYS_OPT_MCDI
 457                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
 458                                 should_abort = eep->ee_mcdi(eep,
 459                                     &(ev[index]), eecp, arg);
 460                                 break;
 461 #endif
 462                         case FSE_AZ_EV_CODE_GLOBAL_EV:
 463                                 if (eep->ee_global) {
 464                                         should_abort = eep->ee_global(eep,
 465                                             &(ev[index]), eecp, arg);
 466                                         break;
 467                                 }
 468                                 /* else fallthrough */
 469                         default:
 470                                 EFSYS_PROBE3(bad_event,
 471                                     unsigned int, eep->ee_index,
 472                                     uint32_t,
 473                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
 474                                     uint32_t,
 475                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
 476
 477                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 478                                 (void) eecp->eec_exception(arg,
 479                                         EFX_EXCEPTION_EV_ERROR, code);
 480                                 should_abort = B_TRUE;
 481                         }
 482                         if (should_abort) {
 483                                 /* Ignore subsequent events */
 484                                 total = index + 1;
 485                                 break;
 486                         }
 487                 }
 488
 489                 /*
 490                  * Now that the hardware has most likely moved onto dma'ing
 491                  * into the next cache line, clear the processed events. Take
 492                  * care to only clear out events that we've processed
 493                  */
 494                 EFX_SET_QWORD(ev[0]);
 495                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 496                 for (index = 0; index < total; ++index) {
 497                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
 498                         offset += sizeof (efx_qword_t);
 499                 }
 500
 501                 count += total;
 502
 503         } while (total == batch);
 504
 505         *countp = count;
 506 }
 507
 508                         void
 509 efx_ev_qpost(
 510         __in    efx_evq_t *eep,
 511         __in    uint16_t data)
 512 {
 513         efx_nic_t *enp = eep->ee_enp;
 514         const efx_ev_ops_t *eevop = enp->en_eevop;
 515
 516         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 517
 518         EFSYS_ASSERT(eevop != NULL &&
 519             eevop->eevo_qpost != NULL);
 520
 521         eevop->eevo_qpost(eep, data);
 522 }
 523
 524         __checkReturn   efx_rc_t
 525 efx_ev_usecs_to_ticks(
 526         __in            efx_nic_t *enp,
 527         __in            unsigned int us,
 528         __out           unsigned int *ticksp)
 529 {
 530         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 531         unsigned int ticks;
 532
 533         /* Convert microseconds to a timer tick count */
 534         if (us == 0)
 535                 ticks = 0;
 536         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 537                 ticks = 1;      /* Never round down to zero */
 538         else
 539                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 540
 541         *ticksp = ticks;
 542         return (0);
 543 }
 544
 545         __checkReturn   efx_rc_t
 546 efx_ev_qmoderate(
 547         __in            efx_evq_t *eep,
 548         __in            unsigned int us)
 549 {
 550         efx_nic_t *enp = eep->ee_enp;
 551         const efx_ev_ops_t *eevop = enp->en_eevop;
 552         efx_rc_t rc;
 553
 554         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 555
 556         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 557                 goto fail1;
 558
 559         return (0);
 560
 561 fail1:
 562         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 563         return (rc);
 564 }
 565
 566 #if EFSYS_OPT_QSTATS
 567                                         void
 568 efx_ev_qstats_update(
 569         __in                            efx_evq_t *eep,
 570         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 571
 572 {       efx_nic_t *enp = eep->ee_enp;
 573         const efx_ev_ops_t *eevop = enp->en_eevop;
 574
 575         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 576
 577         eevop->eevo_qstats_update(eep, stat);
 578 }
 579
 580 #endif  /* EFSYS_OPT_QSTATS */
 581
 582 #if EFSYS_OPT_SIENA
 583
 584 static  __checkReturn   efx_rc_t
 585 siena_ev_init(
 586         __in            efx_nic_t *enp)
 587 {
 588         efx_oword_t oword;
 589
 590         /*
 591          * Program the event queue for receive and transmit queue
 592          * flush events.
 593          */
 594         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 595         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 596         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 597
 598         return (0);
 599
 600 }
 601
 602 static  __checkReturn   boolean_t
 603 siena_ev_rx_not_ok(
 604         __in            efx_evq_t *eep,
 605         __in            efx_qword_t *eqp,
 606         __in            uint32_t label,
 607         __in            uint32_t id,
 608         __inout         uint16_t *flagsp)
 609 {
 610         boolean_t ignore = B_FALSE;
 611
 612         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 613                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 614                 EFSYS_PROBE(tobe_disc);
 615                 /*
 616                  * Assume this is a unicast address mismatch, unless below
 617                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 618                  * EV_RX_PAUSE_FRM_ERR is set.
 619                  */
 620                 (*flagsp) |= EFX_ADDR_MISMATCH;
 621         }
 622
 623         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 624                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 625                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 626                 (*flagsp) |= EFX_DISCARD;
 627
 628 #if EFSYS_OPT_RX_SCATTER
 629                 /*
 630                  * Lookout for payload queue ran dry errors and ignore them.
 631                  *
 632                  * Sadly for the header/data split cases, the descriptor
 633                  * pointer in this event refers to the header queue and
 634                  * therefore cannot be easily detected as duplicate.
 635                  * So we drop these and rely on the receive processing seeing
 636                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 637                  * the partially received packet.
 638                  */
 639                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 640                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 641                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 642                         ignore = B_TRUE;
 643 #endif  /* EFSYS_OPT_RX_SCATTER */
 644         }
 645
 646         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 647                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 648                 EFSYS_PROBE(crc_err);
 649                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 650                 (*flagsp) |= EFX_DISCARD;
 651         }
 652
 653         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 654                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 655                 EFSYS_PROBE(pause_frm_err);
 656                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 657                 (*flagsp) |= EFX_DISCARD;
 658         }
 659
 660         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 661                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 662                 EFSYS_PROBE(owner_id_err);
 663                 (*flagsp) |= EFX_DISCARD;
 664         }
 665
 666         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 667                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 668                 EFSYS_PROBE(ipv4_err);
 669                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 670         }
 671
 672         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 673                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 674                 EFSYS_PROBE(udp_chk_err);
 675                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 676         }
 677
 678         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 679                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 680
 681                 /*
 682                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 683                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 684                  * condition.
 685                  */
 686                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 687         }
 688
 689         return (ignore);
 690 }
 691
 692 static  __checkReturn   boolean_t
 693 siena_ev_rx(
 694         __in            efx_evq_t *eep,
 695         __in            efx_qword_t *eqp,
 696         __in            const efx_ev_callbacks_t *eecp,
 697         __in_opt        void *arg)
 698 {
 699         uint32_t id;
 700         uint32_t size;
 701         uint32_t label;
 702         boolean_t ok;
 703 #if EFSYS_OPT_RX_SCATTER
 704         boolean_t sop;
 705         boolean_t jumbo_cont;
 706 #endif  /* EFSYS_OPT_RX_SCATTER */
 707         uint32_t hdr_type;
 708         boolean_t is_v6;
 709         uint16_t flags;
 710         boolean_t ignore;
 711         boolean_t should_abort;
 712
 713         EFX_EV_QSTAT_INCR(eep, EV_RX);
 714
 715         /* Basic packet information */
 716         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 717         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 718         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 719         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 720
 721 #if EFSYS_OPT_RX_SCATTER
 722         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 723         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 724 #endif  /* EFSYS_OPT_RX_SCATTER */
 725
 726         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 727
 728         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 729
 730         /*
 731          * If packet is marked as OK and packet type is TCP/IP or
 732          * UDP/IP or other IP, then we can rely on the hardware checksums.
 733          */
 734         switch (hdr_type) {
 735         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 736                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 737                 if (is_v6) {
 738                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 739                         flags |= EFX_PKT_IPV6;
 740                 } else {
 741                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 742                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 743                 }
 744                 break;
 745
 746         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 747                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 748                 if (is_v6) {
 749                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 750                         flags |= EFX_PKT_IPV6;
 751                 } else {
 752                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 753                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 754                 }
 755                 break;
 756
 757         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 758                 if (is_v6) {
 759                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 760                         flags = EFX_PKT_IPV6;
 761                 } else {
 762                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 763                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 764                 }
 765                 break;
 766
 767         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 768                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 769                 flags = 0;
 770                 break;
 771
 772         default:
 773                 EFSYS_ASSERT(B_FALSE);
 774                 flags = 0;
 775                 break;
 776         }
 777
 778 #if EFSYS_OPT_RX_SCATTER
 779         /* Report scatter and header/lookahead split buffer flags */
 780         if (sop)
 781                 flags |= EFX_PKT_START;
 782         if (jumbo_cont)
 783                 flags |= EFX_PKT_CONT;
 784 #endif  /* EFSYS_OPT_RX_SCATTER */
 785
 786         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 787         if (!ok) {
 788                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 789                 if (ignore) {
 790                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 791                             uint32_t, size, uint16_t, flags);
 792
 793                         return (B_FALSE);
 794                 }
 795         }
 796
 797         /* If we're not discarding the packet then it is ok */
 798         if (~flags & EFX_DISCARD)
 799                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 800
 801         /* Detect multicast packets that didn't match the filter */
 802         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 803                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 804
 805                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 806                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 807                 } else {
 808                         EFSYS_PROBE(mcast_mismatch);
 809                         flags |= EFX_ADDR_MISMATCH;
 810                 }
 811         } else {
 812                 flags |= EFX_PKT_UNICAST;
 813         }
 814
 815         /*
 816          * The packet parser in Siena can abort parsing packets under
 817          * certain error conditions, setting the PKT_NOT_PARSED bit
 818          * (which clears PKT_OK). If this is set, then don't trust
 819          * the PKT_TYPE field.
 820          */
 821         if (!ok) {
 822                 uint32_t parse_err;
 823
 824                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 825                 if (parse_err != 0)
 826                         flags |= EFX_CHECK_VLAN;
 827         }
 828
 829         if (~flags & EFX_CHECK_VLAN) {
 830                 uint32_t pkt_type;
 831
 832                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 833                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 834                         flags |= EFX_PKT_VLAN_TAGGED;
 835         }
 836
 837         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 838             uint32_t, size, uint16_t, flags);
 839
 840         EFSYS_ASSERT(eecp->eec_rx != NULL);
 841         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 842
 843         return (should_abort);
 844 }
 845
 846 static  __checkReturn   boolean_t
 847 siena_ev_tx(
 848         __in            efx_evq_t *eep,
 849         __in            efx_qword_t *eqp,
 850         __in            const efx_ev_callbacks_t *eecp,
 851         __in_opt        void *arg)
 852 {
 853         uint32_t id;
 854         uint32_t label;
 855         boolean_t should_abort;
 856
 857         EFX_EV_QSTAT_INCR(eep, EV_TX);
 858
 859         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 860             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 861             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 862             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 863
 864                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 865                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 866
 867                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 868
 869                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 870                 should_abort = eecp->eec_tx(arg, label, id);
 871
 872                 return (should_abort);
 873         }
 874
 875         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 876                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 877                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 878                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 879
 880         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 881                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 882
 883         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 884                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 885
 886         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 887                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 888
 889         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 890         return (B_FALSE);
 891 }
 892
 893 static  __checkReturn   boolean_t
 894 siena_ev_global(
 895         __in            efx_evq_t *eep,
 896         __in            efx_qword_t *eqp,
 897         __in            const efx_ev_callbacks_t *eecp,
 898         __in_opt        void *arg)
 899 {
 900         _NOTE(ARGUNUSED(eqp, eecp, arg))
 901
 902         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 903
 904         return (B_FALSE);
 905 }
 906
 907 static  __checkReturn   boolean_t
 908 siena_ev_driver(
 909         __in            efx_evq_t *eep,
 910         __in            efx_qword_t *eqp,
 911         __in            const efx_ev_callbacks_t *eecp,
 912         __in_opt        void *arg)
 913 {
 914         boolean_t should_abort;
 915
 916         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 917         should_abort = B_FALSE;
 918
 919         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 920         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 921                 uint32_t txq_index;
 922
 923                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 924
 925                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 926
 927                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 928
 929                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 930                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 931
 932                 break;
 933         }
 934         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 935                 uint32_t rxq_index;
 936                 uint32_t failed;
 937
 938                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 939                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 940
 941                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 942                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 943
 944                 if (failed) {
 945                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 946
 947                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 948
 949                         should_abort = eecp->eec_rxq_flush_failed(arg,
 950                                                                     rxq_index);
 951                 } else {
 952                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 953
 954                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 955
 956                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 957                 }
 958
 959                 break;
 960         }
 961         case FSE_AZ_EVQ_INIT_DONE_EV:
 962                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 963                 should_abort = eecp->eec_initialized(arg);
 964
 965                 break;
 966
 967         case FSE_AZ_EVQ_NOT_EN_EV:
 968                 EFSYS_PROBE(evq_not_en);
 969                 break;
 970
 971         case FSE_AZ_SRM_UPD_DONE_EV: {
 972                 uint32_t code;
 973
 974                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 975
 976                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 977
 978                 EFSYS_ASSERT(eecp->eec_sram != NULL);
 979                 should_abort = eecp->eec_sram(arg, code);
 980
 981                 break;
 982         }
 983         case FSE_AZ_WAKE_UP_EV: {
 984                 uint32_t id;
 985
 986                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 987
 988                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
 989                 should_abort = eecp->eec_wake_up(arg, id);
 990
 991                 break;
 992         }
 993         case FSE_AZ_TX_PKT_NON_TCP_UDP:
 994                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
 995                 break;
 996
 997         case FSE_AZ_TIMER_EV: {
 998                 uint32_t id;
 999
1000                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1001
1002                 EFSYS_ASSERT(eecp->eec_timer != NULL);
1003                 should_abort = eecp->eec_timer(arg, id);
1004
1005                 break;
1006         }
1007         case FSE_AZ_RX_DSC_ERROR_EV:
1008                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1009
1010                 EFSYS_PROBE(rx_dsc_error);
1011
1012                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1013                 should_abort = eecp->eec_exception(arg,
1014                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
1015
1016                 break;
1017
1018         case FSE_AZ_TX_DSC_ERROR_EV:
1019                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1020
1021                 EFSYS_PROBE(tx_dsc_error);
1022
1023                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1024                 should_abort = eecp->eec_exception(arg,
1025                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1026
1027                 break;
1028
1029         default:
1030                 break;
1031         }
1032
1033         return (should_abort);
1034 }
1035
1036 static  __checkReturn   boolean_t
1037 siena_ev_drv_gen(
1038         __in            efx_evq_t *eep,
1039         __in            efx_qword_t *eqp,
1040         __in            const efx_ev_callbacks_t *eecp,
1041         __in_opt        void *arg)
1042 {
1043         uint32_t data;
1044         boolean_t should_abort;
1045
1046         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1047
1048         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1049         if (data >= ((uint32_t)1 << 16)) {
1050                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1051                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1052                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1053                 return (B_TRUE);
1054         }
1055
1056         EFSYS_ASSERT(eecp->eec_software != NULL);
1057         should_abort = eecp->eec_software(arg, (uint16_t)data);
1058
1059         return (should_abort);
1060 }
1061
1062 #if EFSYS_OPT_MCDI
1063
1064 static  __checkReturn   boolean_t
1065 siena_ev_mcdi(
1066         __in            efx_evq_t *eep,
1067         __in            efx_qword_t *eqp,
1068         __in            const efx_ev_callbacks_t *eecp,
1069         __in_opt        void *arg)
1070 {
1071         efx_nic_t *enp = eep->ee_enp;
1072         unsigned int code;
1073         boolean_t should_abort = B_FALSE;
1074
1075         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1076
1077         if (enp->en_family != EFX_FAMILY_SIENA)
1078                 goto out;
1079
1080         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1081         EFSYS_ASSERT(eecp->eec_exception != NULL);
1082 #if EFSYS_OPT_MON_STATS
1083         EFSYS_ASSERT(eecp->eec_monitor != NULL);
1084 #endif
1085
1086         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1087
1088         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1089         switch (code) {
1090         case MCDI_EVENT_CODE_BADSSERT:
1091                 efx_mcdi_ev_death(enp, EINTR);
1092                 break;
1093
1094         case MCDI_EVENT_CODE_CMDDONE:
1095                 efx_mcdi_ev_cpl(enp,
1096                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1097                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1098                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1099                 break;
1100
1101         case MCDI_EVENT_CODE_LINKCHANGE: {
1102                 efx_link_mode_t link_mode;
1103
1104                 siena_phy_link_ev(enp, eqp, &link_mode);
1105                 should_abort = eecp->eec_link_change(arg, link_mode);
1106                 break;
1107         }
1108         case MCDI_EVENT_CODE_SENSOREVT: {
1109 #if EFSYS_OPT_MON_STATS
1110                 efx_mon_stat_t id;
1111                 efx_mon_stat_value_t value;
1112                 efx_rc_t rc;
1113
1114                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1115                         should_abort = eecp->eec_monitor(arg, id, value);
1116                 else if (rc == ENOTSUP) {
1117                         should_abort = eecp->eec_exception(arg,
1118                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1119                                 MCDI_EV_FIELD(eqp, DATA));
1120                 } else
1121                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1122 #else
1123                 should_abort = B_FALSE;
1124 #endif
1125                 break;
1126         }
1127         case MCDI_EVENT_CODE_SCHEDERR:
1128                 /* Informational only */
1129                 break;
1130
1131         case MCDI_EVENT_CODE_REBOOT:
1132                 efx_mcdi_ev_death(enp, EIO);
1133                 break;
1134
1135         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1136 #if EFSYS_OPT_MAC_STATS
1137                 if (eecp->eec_mac_stats != NULL) {
1138                         eecp->eec_mac_stats(arg,
1139                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1140                 }
1141 #endif
1142                 break;
1143
1144         case MCDI_EVENT_CODE_FWALERT: {
1145                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1146
1147                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1148                         should_abort = eecp->eec_exception(arg,
1149                                 EFX_EXCEPTION_FWALERT_SRAM,
1150                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1151                 else
1152                         should_abort = eecp->eec_exception(arg,
1153                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1154                                 MCDI_EV_FIELD(eqp, DATA));
1155                 break;
1156         }
1157
1158         default:
1159                 EFSYS_PROBE1(mc_pcol_error, int, code);
1160                 break;
1161         }
1162
1163 out:
1164         return (should_abort);
1165 }
1166
1167 #endif  /* EFSYS_OPT_MCDI */
1168
1169 static  __checkReturn   efx_rc_t
1170 siena_ev_qprime(
1171         __in            efx_evq_t *eep,
1172         __in            unsigned int count)
1173 {
1174         efx_nic_t *enp = eep->ee_enp;
1175         uint32_t rptr;
1176         efx_dword_t dword;
1177
1178         rptr = count & eep->ee_mask;
1179
1180         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1181
1182         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1183                             &dword, B_FALSE);
1184
1185         return (0);
1186 }
1187
1188 static          void
1189 siena_ev_qpost(
1190         __in    efx_evq_t *eep,
1191         __in    uint16_t data)
1192 {
1193         efx_nic_t *enp = eep->ee_enp;
1194         efx_qword_t ev;
1195         efx_oword_t oword;
1196
1197         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1198             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1199
1200         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1201             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1202             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1203
1204         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1205 }
1206
1207 static  __checkReturn   efx_rc_t
1208 siena_ev_qmoderate(
1209         __in            efx_evq_t *eep,
1210         __in            unsigned int us)
1211 {
1212         efx_nic_t *enp = eep->ee_enp;
1213         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1214         unsigned int locked;
1215         efx_dword_t dword;
1216         efx_rc_t rc;
1217
1218         if (us > encp->enc_evq_timer_max_us) {
1219                 rc = EINVAL;
1220                 goto fail1;
1221         }
1222
1223         /* If the value is zero then disable the timer */
1224         if (us == 0) {
1225                 EFX_POPULATE_DWORD_2(dword,
1226                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1227                     FRF_CZ_TC_TIMER_VAL, 0);
1228         } else {
1229                 unsigned int ticks;
1230
1231                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1232                         goto fail2;
1233
1234                 EFSYS_ASSERT(ticks > 0);
1235                 EFX_POPULATE_DWORD_2(dword,
1236                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1237                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1238         }
1239
1240         locked = (eep->ee_index == 0) ? 1 : 0;
1241
1242         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1243             eep->ee_index, &dword, locked);
1244
1245         return (0);
1246
1247 fail2:
1248         EFSYS_PROBE(fail2);
1249 fail1:
1250         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1251
1252         return (rc);
1253 }
1254
1255 static  __checkReturn   efx_rc_t
1256 siena_ev_qcreate(
1257         __in            efx_nic_t *enp,
1258         __in            unsigned int index,
1259         __in            efsys_mem_t *esmp,
1260         __in            size_t n,
1261         __in            uint32_t id,
1262         __in            uint32_t us,
1263         __in            uint32_t flags,
1264         __in            efx_evq_t *eep)
1265 {
1266         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1267         uint32_t size;
1268         efx_oword_t oword;
1269         efx_rc_t rc;
1270
1271         _NOTE(ARGUNUSED(esmp))
1272
1273         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1274         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1275
1276         if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1277                 rc = EINVAL;
1278                 goto fail1;
1279         }
1280         if (index >= encp->enc_evq_limit) {
1281                 rc = EINVAL;
1282                 goto fail2;
1283         }
1284 #if EFSYS_OPT_RX_SCALE
1285         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1286             index >= EFX_MAXRSS_LEGACY) {
1287                 rc = EINVAL;
1288                 goto fail3;
1289         }
1290 #endif
1291         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1292             size++)
1293                 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1294                         break;
1295         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1296                 rc = EINVAL;
1297                 goto fail4;
1298         }
1299
1300         /* Set up the handler table */
1301         eep->ee_rx      = siena_ev_rx;
1302         eep->ee_tx      = siena_ev_tx;
1303         eep->ee_driver  = siena_ev_driver;
1304         eep->ee_global  = siena_ev_global;
1305         eep->ee_drv_gen = siena_ev_drv_gen;
1306 #if EFSYS_OPT_MCDI
1307         eep->ee_mcdi    = siena_ev_mcdi;
1308 #endif  /* EFSYS_OPT_MCDI */
1309
1310         /* Set up the new event queue */
1311         EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
1312         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1313
1314         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1315             FRF_AZ_EVQ_BUF_BASE_ID, id);
1316
1317         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1318
1319         /* Set initial interrupt moderation */
1320         siena_ev_qmoderate(eep, us);
1321
1322         return (0);
1323
1324 fail4:
1325         EFSYS_PROBE(fail4);
1326 #if EFSYS_OPT_RX_SCALE
1327 fail3:
1328         EFSYS_PROBE(fail3);
1329 #endif
1330 fail2:
1331         EFSYS_PROBE(fail2);
1332 fail1:
1333         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1334
1335         return (rc);
1336 }
1337
1338 #endif /* EFSYS_OPT_SIENA */
1339
1340 #if EFSYS_OPT_QSTATS
1341 #if EFSYS_OPT_NAMES
1342 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1343 static const char * const __efx_ev_qstat_name[] = {
1344         "all",
1345         "rx",
1346         "rx_ok",
1347         "rx_frm_trunc",
1348         "rx_tobe_disc",
1349         "rx_pause_frm_err",
1350         "rx_buf_owner_id_err",
1351         "rx_ipv4_hdr_chksum_err",
1352         "rx_tcp_udp_chksum_err",
1353         "rx_eth_crc_err",
1354         "rx_ip_frag_err",
1355         "rx_mcast_pkt",
1356         "rx_mcast_hash_match",
1357         "rx_tcp_ipv4",
1358         "rx_tcp_ipv6",
1359         "rx_udp_ipv4",
1360         "rx_udp_ipv6",
1361         "rx_other_ipv4",
1362         "rx_other_ipv6",
1363         "rx_non_ip",
1364         "rx_batch",
1365         "tx",
1366         "tx_wq_ff_full",
1367         "tx_pkt_err",
1368         "tx_pkt_too_big",
1369         "tx_unexpected",
1370         "global",
1371         "global_mnt",
1372         "driver",
1373         "driver_srm_upd_done",
1374         "driver_tx_descq_fls_done",
1375         "driver_rx_descq_fls_done",
1376         "driver_rx_descq_fls_failed",
1377         "driver_rx_dsc_error",
1378         "driver_tx_dsc_error",
1379         "drv_gen",
1380         "mcdi_response",
1381 };
1382 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1383
1384                 const char *
1385 efx_ev_qstat_name(
1386         __in    efx_nic_t *enp,
1387         __in    unsigned int id)
1388 {
1389         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1390         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1391
1392         return (__efx_ev_qstat_name[id]);
1393 }
1394 #endif  /* EFSYS_OPT_NAMES */
1395 #endif  /* EFSYS_OPT_QSTATS */
1396
1397 #if EFSYS_OPT_SIENA
1398
1399 #if EFSYS_OPT_QSTATS
1400 static                                  void
1401 siena_ev_qstats_update(
1402         __in                            efx_evq_t *eep,
1403         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1404 {
1405         unsigned int id;
1406
1407         for (id = 0; id < EV_NQSTATS; id++) {
1408                 efsys_stat_t *essp = &stat[id];
1409
1410                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1411                 eep->ee_stat[id] = 0;
1412         }
1413 }
1414 #endif  /* EFSYS_OPT_QSTATS */
1415
1416 static          void
1417 siena_ev_qdestroy(
1418         __in    efx_evq_t *eep)
1419 {
1420         efx_nic_t *enp = eep->ee_enp;
1421         efx_oword_t oword;
1422
1423         /* Purge event queue */
1424         EFX_ZERO_OWORD(oword);
1425
1426         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1427             eep->ee_index, &oword, B_TRUE);
1428
1429         EFX_ZERO_OWORD(oword);
1430         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1431 }
1432
1433 static          void
1434 siena_ev_fini(
1435         __in    efx_nic_t *enp)
1436 {
1437         _NOTE(ARGUNUSED(enp))
1438 }
1439
1440 #endif /* EFSYS_OPT_SIENA */