sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright notice,
  13  *    this list of conditions and the following disclaimer in the documentation
  14  *    and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * The views and conclusions contained in the software and documentation are
  29  * those of the authors and should not be interpreted as representing official
  30  * policies, either expressed or implied, of the FreeBSD Project.
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 #ifndef _SYS_EFX_IMPL_H
  36 #define _SYS_EFX_IMPL_H
  37
  38 #include "efx.h"
  39 #include "efx_regs.h"
  40 #include "efx_regs_ef10.h"
  41
  42 /* FIXME: Add definition for driver generated software events */
  43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  45 #endif
  46
  47
  48 #if EFSYS_OPT_SIENA
  49 #include "siena_impl.h"
  50 #endif  /* EFSYS_OPT_SIENA */
  51
  52 #if EFSYS_OPT_HUNTINGTON
  53 #include "hunt_impl.h"
  54 #endif  /* EFSYS_OPT_HUNTINGTON */
  55
  56 #if EFSYS_OPT_MEDFORD
  57 #include "medford_impl.h"
  58 #endif  /* EFSYS_OPT_MEDFORD */
  59
  60 #if EFSYS_OPT_MEDFORD2
  61 #include "medford2_impl.h"
  62 #endif  /* EFSYS_OPT_MEDFORD2 */
  63
  64 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  65 #include "ef10_impl.h"
  66 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  67
  68 #ifdef  __cplusplus
  69 extern "C" {
  70 #endif
  71
  72 #define EFX_MOD_MCDI            0x00000001
  73 #define EFX_MOD_PROBE           0x00000002
  74 #define EFX_MOD_NVRAM           0x00000004
  75 #define EFX_MOD_VPD             0x00000008
  76 #define EFX_MOD_NIC             0x00000010
  77 #define EFX_MOD_INTR            0x00000020
  78 #define EFX_MOD_EV              0x00000040
  79 #define EFX_MOD_RX              0x00000080
  80 #define EFX_MOD_TX              0x00000100
  81 #define EFX_MOD_PORT            0x00000200
  82 #define EFX_MOD_MON             0x00000400
  83 #define EFX_MOD_FILTER          0x00001000
  84 #define EFX_MOD_LIC             0x00002000
  85 #define EFX_MOD_TUNNEL          0x00004000
  86
  87 #define EFX_RESET_PHY           0x00000001
  88 #define EFX_RESET_RXQ_ERR       0x00000002
  89 #define EFX_RESET_TXQ_ERR       0x00000004
  90 #define EFX_RESET_HW_UNAVAIL    0x00000008
  91
  92 typedef enum efx_mac_type_e {
  93         EFX_MAC_INVALID = 0,
  94         EFX_MAC_SIENA,
  95         EFX_MAC_HUNTINGTON,
  96         EFX_MAC_MEDFORD,
  97         EFX_MAC_MEDFORD2,
  98         EFX_MAC_NTYPES
  99 } efx_mac_type_t;
 100
 101 typedef struct efx_ev_ops_s {
 102         efx_rc_t        (*eevo_init)(efx_nic_t *);
 103         void            (*eevo_fini)(efx_nic_t *);
 104         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
 105                                           efsys_mem_t *, size_t, uint32_t,
 106                                           uint32_t, uint32_t, efx_evq_t *);
 107         void            (*eevo_qdestroy)(efx_evq_t *);
 108         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 109         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 110         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 111 #if EFSYS_OPT_QSTATS
 112         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 113 #endif
 114 } efx_ev_ops_t;
 115
 116 typedef struct efx_tx_ops_s {
 117         efx_rc_t        (*etxo_init)(efx_nic_t *);
 118         void            (*etxo_fini)(efx_nic_t *);
 119         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 120                                         unsigned int, unsigned int,
 121                                         efsys_mem_t *, size_t,
 122                                         uint32_t, uint16_t,
 123                                         efx_evq_t *, efx_txq_t *,
 124                                         unsigned int *);
 125         void            (*etxo_qdestroy)(efx_txq_t *);
 126         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 127                                       unsigned int, unsigned int,
 128                                       unsigned int *);
 129         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 130         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 131         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 132         void            (*etxo_qenable)(efx_txq_t *);
 133         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 134         void            (*etxo_qpio_disable)(efx_txq_t *);
 135         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 136                                            size_t);
 137         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 138                                            unsigned int *);
 139         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 140                                       unsigned int, unsigned int,
 141                                       unsigned int *);
 142         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 143                                                 size_t, boolean_t,
 144                                                 efx_desc_t *);
 145         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 146                                                 uint32_t, uint8_t,
 147                                                 efx_desc_t *);
 148         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 149                                                 uint16_t, uint32_t, uint16_t,
 150                                                 efx_desc_t *, int);
 151         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 152                                                 efx_desc_t *);
 153         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 154                                                 efx_desc_t *);
 155 #if EFSYS_OPT_QSTATS
 156         void            (*etxo_qstats_update)(efx_txq_t *,
 157                                               efsys_stat_t *);
 158 #endif
 159 } efx_tx_ops_t;
 160
 161 typedef union efx_rxq_type_data_u {
 162         /* Dummy member to have non-empty union if no options are enabled */
 163         uint32_t        ertd_dummy;
 164 #if EFSYS_OPT_RX_PACKED_STREAM
 165         struct {
 166                 uint32_t        eps_buf_size;
 167         } ertd_packed_stream;
 168 #endif
 169 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 170         struct {
 171                 uint32_t        eessb_bufs_per_desc;
 172                 uint32_t        eessb_max_dma_len;
 173                 uint32_t        eessb_buf_stride;
 174                 uint32_t        eessb_hol_block_timeout;
 175         } ertd_es_super_buffer;
 176 #endif
 177 } efx_rxq_type_data_t;
 178
 179 typedef struct efx_rx_ops_s {
 180         efx_rc_t        (*erxo_init)(efx_nic_t *);
 181         void            (*erxo_fini)(efx_nic_t *);
 182 #if EFSYS_OPT_RX_SCATTER
 183         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 184 #endif
 185 #if EFSYS_OPT_RX_SCALE
 186         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 187                                                     efx_rx_scale_context_type_t,
 188                                                     uint32_t, uint32_t *);
 189         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 190         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 191                                                efx_rx_hash_alg_t,
 192                                                efx_rx_hash_type_t, boolean_t);
 193         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 194                                               uint8_t *, size_t);
 195         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 196                                               unsigned int *, size_t);
 197         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 198                                             uint8_t *);
 199 #endif /* EFSYS_OPT_RX_SCALE */
 200         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 201                                               uint16_t *);
 202         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 203                                       unsigned int, unsigned int,
 204                                       unsigned int);
 205         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 206 #if EFSYS_OPT_RX_PACKED_STREAM
 207         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 208         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 209                                                 uint32_t, uint32_t,
 210                                                 uint16_t *, uint32_t *, uint32_t *);
 211 #endif
 212         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 213         void            (*erxo_qenable)(efx_rxq_t *);
 214         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 215                                         unsigned int, efx_rxq_type_t,
 216                                         const efx_rxq_type_data_t *,
 217                                         efsys_mem_t *, size_t, uint32_t,
 218                                         unsigned int,
 219                                         efx_evq_t *, efx_rxq_t *);
 220         void            (*erxo_qdestroy)(efx_rxq_t *);
 221 } efx_rx_ops_t;
 222
 223 typedef struct efx_mac_ops_s {
 224         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 225         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 226         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 227         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 228         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 229         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 230         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 231         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 232                                                       efx_rxq_t *, boolean_t);
 233         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 234 #if EFSYS_OPT_LOOPBACK
 235         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 236                                             efx_loopback_type_t);
 237 #endif  /* EFSYS_OPT_LOOPBACK */
 238 #if EFSYS_OPT_MAC_STATS
 239         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 240         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 241         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 242         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 243                                               uint16_t, boolean_t);
 244         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 245                                             efsys_stat_t *, uint32_t *);
 246 #endif  /* EFSYS_OPT_MAC_STATS */
 247 } efx_mac_ops_t;
 248
 249 typedef struct efx_phy_ops_s {
 250         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 251         efx_rc_t        (*epo_reset)(efx_nic_t *);
 252         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 253         efx_rc_t        (*epo_verify)(efx_nic_t *);
 254         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 255         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 256 #if EFSYS_OPT_PHY_STATS
 257         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 258                                             uint32_t *);
 259 #endif  /* EFSYS_OPT_PHY_STATS */
 260 #if EFSYS_OPT_BIST
 261         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 262         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 263         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 264                                          efx_bist_result_t *, uint32_t *,
 265                                          unsigned long *, size_t);
 266         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 267 #endif  /* EFSYS_OPT_BIST */
 268 } efx_phy_ops_t;
 269
 270 #if EFSYS_OPT_FILTER
 271 typedef struct efx_filter_ops_s {
 272         efx_rc_t        (*efo_init)(efx_nic_t *);
 273         void            (*efo_fini)(efx_nic_t *);
 274         efx_rc_t        (*efo_restore)(efx_nic_t *);
 275         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 276                                    boolean_t may_replace);
 277         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 278         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 279                                    size_t, size_t *);
 280         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 281                                    boolean_t, boolean_t, boolean_t,
 282                                    uint8_t const *, uint32_t);
 283 } efx_filter_ops_t;
 284
 285 extern  __checkReturn   efx_rc_t
 286 efx_filter_reconfigure(
 287         __in                            efx_nic_t *enp,
 288         __in_ecount(6)                  uint8_t const *mac_addr,
 289         __in                            boolean_t all_unicst,
 290         __in                            boolean_t mulcst,
 291         __in                            boolean_t all_mulcst,
 292         __in                            boolean_t brdcst,
 293         __in_ecount(6*count)            uint8_t const *addrs,
 294         __in                            uint32_t count);
 295
 296 #endif /* EFSYS_OPT_FILTER */
 297
 298 #if EFSYS_OPT_TUNNEL
 299 typedef struct efx_tunnel_ops_s {
 300         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 301         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 302 } efx_tunnel_ops_t;
 303 #endif /* EFSYS_OPT_TUNNEL */
 304
 305 typedef struct efx_port_s {
 306         efx_mac_type_t          ep_mac_type;
 307         uint32_t                ep_phy_type;
 308         uint8_t                 ep_port;
 309         uint32_t                ep_mac_pdu;
 310         uint8_t                 ep_mac_addr[6];
 311         efx_link_mode_t         ep_link_mode;
 312         boolean_t               ep_all_unicst;
 313         boolean_t               ep_mulcst;
 314         boolean_t               ep_all_mulcst;
 315         boolean_t               ep_brdcst;
 316         unsigned int            ep_fcntl;
 317         boolean_t               ep_fcntl_autoneg;
 318         efx_oword_t             ep_multicst_hash[2];
 319         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 320                                                     EFX_MAC_MULTICAST_LIST_MAX];
 321         uint32_t                ep_mulcst_addr_count;
 322 #if EFSYS_OPT_LOOPBACK
 323         efx_loopback_type_t     ep_loopback_type;
 324         efx_link_mode_t         ep_loopback_link_mode;
 325 #endif  /* EFSYS_OPT_LOOPBACK */
 326 #if EFSYS_OPT_PHY_FLAGS
 327         uint32_t                ep_phy_flags;
 328 #endif  /* EFSYS_OPT_PHY_FLAGS */
 329 #if EFSYS_OPT_PHY_LED_CONTROL
 330         efx_phy_led_mode_t      ep_phy_led_mode;
 331 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 332         efx_phy_media_type_t    ep_fixed_port_type;
 333         efx_phy_media_type_t    ep_module_type;
 334         uint32_t                ep_adv_cap_mask;
 335         uint32_t                ep_lp_cap_mask;
 336         uint32_t                ep_default_adv_cap_mask;
 337         uint32_t                ep_phy_cap_mask;
 338         boolean_t               ep_mac_drain;
 339 #if EFSYS_OPT_BIST
 340         efx_bist_type_t         ep_current_bist;
 341 #endif
 342         const efx_mac_ops_t     *ep_emop;
 343         const efx_phy_ops_t     *ep_epop;
 344 } efx_port_t;
 345
 346 typedef struct efx_mon_ops_s {
 347 #if EFSYS_OPT_MON_STATS
 348         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 349                                             efx_mon_stat_value_t *);
 350         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 351                                              efx_mon_stat_limits_t *);
 352 #endif  /* EFSYS_OPT_MON_STATS */
 353 } efx_mon_ops_t;
 354
 355 typedef struct efx_mon_s {
 356         efx_mon_type_t          em_type;
 357         const efx_mon_ops_t     *em_emop;
 358 } efx_mon_t;
 359
 360 typedef struct efx_intr_ops_s {
 361         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 362         void            (*eio_enable)(efx_nic_t *);
 363         void            (*eio_disable)(efx_nic_t *);
 364         void            (*eio_disable_unlocked)(efx_nic_t *);
 365         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 366         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 367         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 368                                  boolean_t *);
 369         void            (*eio_fatal)(efx_nic_t *);
 370         void            (*eio_fini)(efx_nic_t *);
 371 } efx_intr_ops_t;
 372
 373 typedef struct efx_intr_s {
 374         const efx_intr_ops_t    *ei_eiop;
 375         efsys_mem_t             *ei_esmp;
 376         efx_intr_type_t         ei_type;
 377         unsigned int            ei_level;
 378 } efx_intr_t;
 379
 380 typedef struct efx_nic_ops_s {
 381         efx_rc_t        (*eno_probe)(efx_nic_t *);
 382         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 383         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 384         efx_rc_t        (*eno_reset)(efx_nic_t *);
 385         efx_rc_t        (*eno_init)(efx_nic_t *);
 386         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 387         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 388                                         uint32_t *, size_t *);
 389         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 390         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 391 #if EFSYS_OPT_DIAG
 392         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 393 #endif  /* EFSYS_OPT_DIAG */
 394         void            (*eno_fini)(efx_nic_t *);
 395         void            (*eno_unprobe)(efx_nic_t *);
 396 } efx_nic_ops_t;
 397
 398 #ifndef EFX_TXQ_LIMIT_TARGET
 399 #define EFX_TXQ_LIMIT_TARGET 259
 400 #endif
 401 #ifndef EFX_RXQ_LIMIT_TARGET
 402 #define EFX_RXQ_LIMIT_TARGET 512
 403 #endif
 404
 405
 406 #if EFSYS_OPT_FILTER
 407
 408 #if EFSYS_OPT_SIENA
 409
 410 typedef struct siena_filter_spec_s {
 411         uint8_t         sfs_type;
 412         uint32_t        sfs_flags;
 413         uint32_t        sfs_dmaq_id;
 414         uint32_t        sfs_dword[3];
 415 } siena_filter_spec_t;
 416
 417 typedef enum siena_filter_type_e {
 418         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 419         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 420         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 421         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 422         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 423         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 424
 425         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 426         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 427         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 428         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 429         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 430         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 431
 432         EFX_SIENA_FILTER_NTYPES
 433 } siena_filter_type_t;
 434
 435 typedef enum siena_filter_tbl_id_e {
 436         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 437         EFX_SIENA_FILTER_TBL_RX_MAC,
 438         EFX_SIENA_FILTER_TBL_TX_IP,
 439         EFX_SIENA_FILTER_TBL_TX_MAC,
 440         EFX_SIENA_FILTER_NTBLS
 441 } siena_filter_tbl_id_t;
 442
 443 typedef struct siena_filter_tbl_s {
 444         int                     sft_size;       /* number of entries */
 445         int                     sft_used;       /* active count */
 446         uint32_t                *sft_bitmap;    /* active bitmap */
 447         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 448 } siena_filter_tbl_t;
 449
 450 typedef struct siena_filter_s {
 451         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 452         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 453 } siena_filter_t;
 454
 455 #endif  /* EFSYS_OPT_SIENA */
 456
 457 typedef struct efx_filter_s {
 458 #if EFSYS_OPT_SIENA
 459         siena_filter_t          *ef_siena_filter;
 460 #endif /* EFSYS_OPT_SIENA */
 461 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 462         ef10_filter_table_t     *ef_ef10_filter_table;
 463 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 464 } efx_filter_t;
 465
 466 #if EFSYS_OPT_SIENA
 467
 468 extern                  void
 469 siena_filter_tbl_clear(
 470         __in            efx_nic_t *enp,
 471         __in            siena_filter_tbl_id_t tbl);
 472
 473 #endif  /* EFSYS_OPT_SIENA */
 474
 475 #endif  /* EFSYS_OPT_FILTER */
 476
 477 #if EFSYS_OPT_MCDI
 478
 479 #define EFX_TUNNEL_MAXNENTRIES  (16)
 480
 481 #if EFSYS_OPT_TUNNEL
 482
 483 typedef struct efx_tunnel_udp_entry_s {
 484         uint16_t                        etue_port; /* host/cpu-endian */
 485         uint16_t                        etue_protocol;
 486 } efx_tunnel_udp_entry_t;
 487
 488 typedef struct efx_tunnel_cfg_s {
 489         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 490         unsigned int            etc_udp_entries_num;
 491 } efx_tunnel_cfg_t;
 492
 493 #endif /* EFSYS_OPT_TUNNEL */
 494
 495 typedef struct efx_mcdi_ops_s {
 496         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 497         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 498                                         void *, size_t);
 499         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 500         boolean_t       (*emco_poll_response)(efx_nic_t *);
 501         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 502         void            (*emco_fini)(efx_nic_t *);
 503         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 504                                             efx_mcdi_feature_id_t, boolean_t *);
 505         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 506                                             uint32_t *);
 507 } efx_mcdi_ops_t;
 508
 509 typedef struct efx_mcdi_s {
 510         const efx_mcdi_ops_t            *em_emcop;
 511         const efx_mcdi_transport_t      *em_emtp;
 512         efx_mcdi_iface_t                em_emip;
 513 } efx_mcdi_t;
 514
 515 #endif /* EFSYS_OPT_MCDI */
 516
 517 #if EFSYS_OPT_NVRAM
 518
 519 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 520 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 521
 522 typedef struct efx_nvram_ops_s {
 523 #if EFSYS_OPT_DIAG
 524         efx_rc_t        (*envo_test)(efx_nic_t *);
 525 #endif  /* EFSYS_OPT_DIAG */
 526         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 527                                             uint32_t *);
 528         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 529         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 530         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 531                                             unsigned int, caddr_t, size_t);
 532         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 533                                             unsigned int, caddr_t, size_t);
 534         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 535                                             unsigned int, size_t);
 536         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 537                                             unsigned int, caddr_t, size_t);
 538         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 539                                             uint32_t *);
 540         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 541                                             uint32_t *, uint16_t *);
 542         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 543                                             uint16_t *);
 544         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 545                                             caddr_t, size_t);
 546 } efx_nvram_ops_t;
 547 #endif /* EFSYS_OPT_NVRAM */
 548
 549 #if EFSYS_OPT_VPD
 550 typedef struct efx_vpd_ops_s {
 551         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 552         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 553         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 554         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 555         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 556         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 557                                         efx_vpd_value_t *);
 558         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 559                                         efx_vpd_value_t *);
 560         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 561                                         efx_vpd_value_t *, unsigned int *);
 562         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 563         void            (*evpdo_fini)(efx_nic_t *);
 564 } efx_vpd_ops_t;
 565 #endif  /* EFSYS_OPT_VPD */
 566
 567 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 568
 569         __checkReturn           efx_rc_t
 570 efx_mcdi_nvram_partitions(
 571         __in                    efx_nic_t *enp,
 572         __out_bcount(size)      caddr_t data,
 573         __in                    size_t size,
 574         __out                   unsigned int *npartnp);
 575
 576         __checkReturn           efx_rc_t
 577 efx_mcdi_nvram_metadata(
 578         __in                    efx_nic_t *enp,
 579         __in                    uint32_t partn,
 580         __out                   uint32_t *subtypep,
 581         __out_ecount(4)         uint16_t version[4],
 582         __out_bcount_opt(size)  char *descp,
 583         __in                    size_t size);
 584
 585         __checkReturn           efx_rc_t
 586 efx_mcdi_nvram_info(
 587         __in                    efx_nic_t *enp,
 588         __in                    uint32_t partn,
 589         __out_opt               size_t *sizep,
 590         __out_opt               uint32_t *addressp,
 591         __out_opt               uint32_t *erase_sizep,
 592         __out_opt               uint32_t *write_sizep);
 593
 594         __checkReturn           efx_rc_t
 595 efx_mcdi_nvram_update_start(
 596         __in                    efx_nic_t *enp,
 597         __in                    uint32_t partn);
 598
 599         __checkReturn           efx_rc_t
 600 efx_mcdi_nvram_read(
 601         __in                    efx_nic_t *enp,
 602         __in                    uint32_t partn,
 603         __in                    uint32_t offset,
 604         __out_bcount(size)      caddr_t data,
 605         __in                    size_t size,
 606         __in                    uint32_t mode);
 607
 608         __checkReturn           efx_rc_t
 609 efx_mcdi_nvram_erase(
 610         __in                    efx_nic_t *enp,
 611         __in                    uint32_t partn,
 612         __in                    uint32_t offset,
 613         __in                    size_t size);
 614
 615         __checkReturn           efx_rc_t
 616 efx_mcdi_nvram_write(
 617         __in                    efx_nic_t *enp,
 618         __in                    uint32_t partn,
 619         __in                    uint32_t offset,
 620         __in_bcount(size)       caddr_t data,
 621         __in                    size_t size);
 622
 623         __checkReturn           efx_rc_t
 624 efx_mcdi_nvram_update_finish(
 625         __in                    efx_nic_t *enp,
 626         __in                    uint32_t partn,
 627         __in                    boolean_t reboot,
 628         __out_opt               uint32_t *verify_resultp);
 629
 630 #if EFSYS_OPT_DIAG
 631
 632         __checkReturn           efx_rc_t
 633 efx_mcdi_nvram_test(
 634         __in                    efx_nic_t *enp,
 635         __in                    uint32_t partn);
 636
 637 #endif  /* EFSYS_OPT_DIAG */
 638
 639 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 640
 641 #if EFSYS_OPT_LICENSING
 642
 643 typedef struct efx_lic_ops_s {
 644         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 645         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 646         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 647         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 648                                       size_t *, uint8_t *);
 649         efx_rc_t        (*elo_find_start)
 650                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 651         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 652                                 uint32_t, uint32_t *);
 653         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 654                                 uint32_t, uint32_t *, uint32_t *);
 655         boolean_t       (*elo_validate_key)(efx_nic_t *,
 656                                 caddr_t, uint32_t);
 657         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 658                                 caddr_t, size_t, uint32_t, uint32_t,
 659                                 caddr_t, size_t, uint32_t *);
 660         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 661                                 caddr_t, size_t, uint32_t,
 662                                 caddr_t, uint32_t, uint32_t *);
 663         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 664                                 caddr_t, size_t, uint32_t,
 665                                 uint32_t, uint32_t, uint32_t *);
 666         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 667                                 caddr_t, size_t);
 668         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 669                                 caddr_t, size_t);
 670 } efx_lic_ops_t;
 671
 672 #endif
 673
 674 typedef struct efx_drv_cfg_s {
 675         uint32_t                edc_min_vi_count;
 676         uint32_t                edc_max_vi_count;
 677
 678         uint32_t                edc_max_piobuf_count;
 679         uint32_t                edc_pio_alloc_size;
 680 } efx_drv_cfg_t;
 681
 682 struct efx_nic_s {
 683         uint32_t                en_magic;
 684         efx_family_t            en_family;
 685         uint32_t                en_features;
 686         efsys_identifier_t      *en_esip;
 687         efsys_lock_t            *en_eslp;
 688         efsys_bar_t             *en_esbp;
 689         unsigned int            en_mod_flags;
 690         unsigned int            en_reset_flags;
 691         efx_nic_cfg_t           en_nic_cfg;
 692         efx_drv_cfg_t           en_drv_cfg;
 693         efx_port_t              en_port;
 694         efx_mon_t               en_mon;
 695         efx_intr_t              en_intr;
 696         uint32_t                en_ev_qcount;
 697         uint32_t                en_rx_qcount;
 698         uint32_t                en_tx_qcount;
 699         const efx_nic_ops_t     *en_enop;
 700         const efx_ev_ops_t      *en_eevop;
 701         const efx_tx_ops_t      *en_etxop;
 702         const efx_rx_ops_t      *en_erxop;
 703         efx_fw_variant_t        efv;
 704 #if EFSYS_OPT_FILTER
 705         efx_filter_t            en_filter;
 706         const efx_filter_ops_t  *en_efop;
 707 #endif  /* EFSYS_OPT_FILTER */
 708 #if EFSYS_OPT_TUNNEL
 709         efx_tunnel_cfg_t        en_tunnel_cfg;
 710         const efx_tunnel_ops_t  *en_etop;
 711 #endif /* EFSYS_OPT_TUNNEL */
 712 #if EFSYS_OPT_MCDI
 713         efx_mcdi_t              en_mcdi;
 714 #endif  /* EFSYS_OPT_MCDI */
 715 #if EFSYS_OPT_NVRAM
 716         uint32_t                en_nvram_partn_locked;
 717         const efx_nvram_ops_t   *en_envop;
 718 #endif  /* EFSYS_OPT_NVRAM */
 719 #if EFSYS_OPT_VPD
 720         const efx_vpd_ops_t     *en_evpdop;
 721 #endif  /* EFSYS_OPT_VPD */
 722 #if EFSYS_OPT_RX_SCALE
 723         efx_rx_hash_support_t           en_hash_support;
 724         efx_rx_scale_context_type_t     en_rss_context_type;
 725         uint32_t                        en_rss_context;
 726 #endif  /* EFSYS_OPT_RX_SCALE */
 727         uint32_t                en_vport_id;
 728 #if EFSYS_OPT_LICENSING
 729         const efx_lic_ops_t     *en_elop;
 730         boolean_t               en_licensing_supported;
 731 #endif
 732         union {
 733 #if EFSYS_OPT_SIENA
 734                 struct {
 735 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 736                         unsigned int            enu_partn_mask;
 737 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 738 #if EFSYS_OPT_VPD
 739                         caddr_t                 enu_svpd;
 740                         size_t                  enu_svpd_length;
 741 #endif  /* EFSYS_OPT_VPD */
 742                         int                     enu_unused;
 743                 } siena;
 744 #endif  /* EFSYS_OPT_SIENA */
 745                 int     enu_unused;
 746         } en_u;
 747 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 748         union en_arch {
 749                 struct {
 750                         int                     ena_vi_base;
 751                         int                     ena_vi_count;
 752                         int                     ena_vi_shift;
 753 #if EFSYS_OPT_VPD
 754                         caddr_t                 ena_svpd;
 755                         size_t                  ena_svpd_length;
 756 #endif  /* EFSYS_OPT_VPD */
 757                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 758                         uint32_t                ena_piobuf_count;
 759                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 760                         uint32_t                ena_pio_write_vi_base;
 761                         /* Memory BAR mapping regions */
 762                         uint32_t                ena_uc_mem_map_offset;
 763                         size_t                  ena_uc_mem_map_size;
 764                         uint32_t                ena_wc_mem_map_offset;
 765                         size_t                  ena_wc_mem_map_size;
 766                 } ef10;
 767         } en_arch;
 768 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 769 };
 770
 771
 772 #define EFX_NIC_MAGIC   0x02121996
 773
 774 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 775     const efx_ev_callbacks_t *, void *);
 776
 777 typedef struct efx_evq_rxq_state_s {
 778         unsigned int                    eers_rx_read_ptr;
 779         unsigned int                    eers_rx_mask;
 780 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 781         unsigned int                    eers_rx_stream_npackets;
 782         boolean_t                       eers_rx_packed_stream;
 783 #endif
 784 #if EFSYS_OPT_RX_PACKED_STREAM
 785         unsigned int                    eers_rx_packed_stream_credits;
 786 #endif
 787 } efx_evq_rxq_state_t;
 788
 789 struct efx_evq_s {
 790         uint32_t                        ee_magic;
 791         efx_nic_t                       *ee_enp;
 792         unsigned int                    ee_index;
 793         unsigned int                    ee_mask;
 794         efsys_mem_t                     *ee_esmp;
 795 #if EFSYS_OPT_QSTATS
 796         uint32_t                        ee_stat[EV_NQSTATS];
 797 #endif  /* EFSYS_OPT_QSTATS */
 798
 799         efx_ev_handler_t                ee_rx;
 800         efx_ev_handler_t                ee_tx;
 801         efx_ev_handler_t                ee_driver;
 802         efx_ev_handler_t                ee_global;
 803         efx_ev_handler_t                ee_drv_gen;
 804 #if EFSYS_OPT_MCDI
 805         efx_ev_handler_t                ee_mcdi;
 806 #endif  /* EFSYS_OPT_MCDI */
 807
 808         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 809
 810         uint32_t                        ee_flags;
 811 };
 812
 813 #define EFX_EVQ_MAGIC   0x08081997
 814
 815 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 816
 817 struct efx_rxq_s {
 818         uint32_t                        er_magic;
 819         efx_nic_t                       *er_enp;
 820         efx_evq_t                       *er_eep;
 821         unsigned int                    er_index;
 822         unsigned int                    er_label;
 823         unsigned int                    er_mask;
 824         efsys_mem_t                     *er_esmp;
 825         efx_evq_rxq_state_t             *er_ev_qstate;
 826 };
 827
 828 #define EFX_RXQ_MAGIC   0x15022005
 829
 830 struct efx_txq_s {
 831         uint32_t                        et_magic;
 832         efx_nic_t                       *et_enp;
 833         unsigned int                    et_index;
 834         unsigned int                    et_mask;
 835         efsys_mem_t                     *et_esmp;
 836 #if EFSYS_OPT_HUNTINGTON
 837         uint32_t                        et_pio_bufnum;
 838         uint32_t                        et_pio_blknum;
 839         uint32_t                        et_pio_write_offset;
 840         uint32_t                        et_pio_offset;
 841         size_t                          et_pio_size;
 842 #endif
 843 #if EFSYS_OPT_QSTATS
 844         uint32_t                        et_stat[TX_NQSTATS];
 845 #endif  /* EFSYS_OPT_QSTATS */
 846 };
 847
 848 #define EFX_TXQ_MAGIC   0x05092005
 849
 850 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 851         do {                                                            \
 852                 (_dst)[0] = (_src)[0];                                  \
 853                 (_dst)[1] = (_src)[1];                                  \
 854                 (_dst)[2] = (_src)[2];                                  \
 855                 (_dst)[3] = (_src)[3];                                  \
 856                 (_dst)[4] = (_src)[4];                                  \
 857                 (_dst)[5] = (_src)[5];                                  \
 858         _NOTE(CONSTANTCONDITION)                                        \
 859         } while (B_FALSE)
 860
 861 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 862         do {                                                            \
 863                 uint16_t *_d = (uint16_t *)(_dst);                      \
 864                 _d[0] = 0xffff;                                         \
 865                 _d[1] = 0xffff;                                         \
 866                 _d[2] = 0xffff;                                         \
 867         _NOTE(CONSTANTCONDITION)                                        \
 868         } while (B_FALSE)
 869
 870 #if EFSYS_OPT_CHECK_REG
 871 #define EFX_CHECK_REG(_enp, _reg)                                       \
 872         do {                                                            \
 873                 const char *name = #_reg;                               \
 874                 char min = name[4];                                     \
 875                 char max = name[5];                                     \
 876                 char rev;                                               \
 877                                                                         \
 878                 switch ((_enp)->en_family) {                            \
 879                 case EFX_FAMILY_SIENA:                                  \
 880                         rev = 'C';                                      \
 881                         break;                                          \
 882                                                                         \
 883                 case EFX_FAMILY_HUNTINGTON:                             \
 884                         rev = 'D';                                      \
 885                         break;                                          \
 886                                                                         \
 887                 case EFX_FAMILY_MEDFORD:                                \
 888                         rev = 'E';                                      \
 889                         break;                                          \
 890                                                                         \
 891                 case EFX_FAMILY_MEDFORD2:                               \
 892                         rev = 'F';                                      \
 893                         break;                                          \
 894                                                                         \
 895                 default:                                                \
 896                         rev = '?';                                      \
 897                         break;                                          \
 898                 }                                                       \
 899                                                                         \
 900                 EFSYS_ASSERT3S(rev, >=, min);                           \
 901                 EFSYS_ASSERT3S(rev, <=, max);                           \
 902                                                                         \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905 #else
 906 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 907         _NOTE(CONSTANTCONDITION)                                        \
 908         } while (B_FALSE)
 909 #endif
 910
 911 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 912         do {                                                            \
 913                 EFX_CHECK_REG((_enp), (_reg));                          \
 914                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 915                     (_edp), (_lock));                                   \
 916                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 917                     uint32_t, _reg ## _OFST,                            \
 918                     uint32_t, (_edp)->ed_u32[0]);                       \
 919         _NOTE(CONSTANTCONDITION)                                        \
 920         } while (B_FALSE)
 921
 922 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 923         do {                                                            \
 924                 EFX_CHECK_REG((_enp), (_reg));                          \
 925                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 926                     uint32_t, _reg ## _OFST,                            \
 927                     uint32_t, (_edp)->ed_u32[0]);                       \
 928                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 929                     (_edp), (_lock));                                   \
 930         _NOTE(CONSTANTCONDITION)                                        \
 931         } while (B_FALSE)
 932
 933 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 934         do {                                                            \
 935                 EFX_CHECK_REG((_enp), (_reg));                          \
 936                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 937                     (_eqp));                                            \
 938                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 939                     uint32_t, _reg ## _OFST,                            \
 940                     uint32_t, (_eqp)->eq_u32[1],                        \
 941                     uint32_t, (_eqp)->eq_u32[0]);                       \
 942         _NOTE(CONSTANTCONDITION)                                        \
 943         } while (B_FALSE)
 944
 945 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 946         do {                                                            \
 947                 EFX_CHECK_REG((_enp), (_reg));                          \
 948                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 949                     uint32_t, _reg ## _OFST,                            \
 950                     uint32_t, (_eqp)->eq_u32[1],                        \
 951                     uint32_t, (_eqp)->eq_u32[0]);                       \
 952                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 953                     (_eqp));                                            \
 954         _NOTE(CONSTANTCONDITION)                                        \
 955         } while (B_FALSE)
 956
 957 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 958         do {                                                            \
 959                 EFX_CHECK_REG((_enp), (_reg));                          \
 960                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 961                     (_eop), B_TRUE);                                    \
 962                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 963                     uint32_t, _reg ## _OFST,                            \
 964                     uint32_t, (_eop)->eo_u32[3],                        \
 965                     uint32_t, (_eop)->eo_u32[2],                        \
 966                     uint32_t, (_eop)->eo_u32[1],                        \
 967                     uint32_t, (_eop)->eo_u32[0]);                       \
 968         _NOTE(CONSTANTCONDITION)                                        \
 969         } while (B_FALSE)
 970
 971 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 972         do {                                                            \
 973                 EFX_CHECK_REG((_enp), (_reg));                          \
 974                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 975                     uint32_t, _reg ## _OFST,                            \
 976                     uint32_t, (_eop)->eo_u32[3],                        \
 977                     uint32_t, (_eop)->eo_u32[2],                        \
 978                     uint32_t, (_eop)->eo_u32[1],                        \
 979                     uint32_t, (_eop)->eo_u32[0]);                       \
 980                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 981                     (_eop), B_TRUE);                                    \
 982         _NOTE(CONSTANTCONDITION)                                        \
 983         } while (B_FALSE)
 984
 985 /*
 986  * Accessors for memory BAR non-VI tables.
 987  *
 988  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 989  * to ensure the correct runtime VI window size is used on Medford2.
 990  *
 991  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 992  */
 993
 994 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 995         do {                                                            \
 996                 EFX_CHECK_REG((_enp), (_reg));                          \
 997                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 998                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 999                     (_edp), (_lock));                                   \
1000                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1001                     uint32_t, (_index),                                 \
1002                     uint32_t, _reg ## _OFST,                            \
1003                     uint32_t, (_edp)->ed_u32[0]);                       \
1004         _NOTE(CONSTANTCONDITION)                                        \
1005         } while (B_FALSE)
1006
1007 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1008         do {                                                            \
1009                 EFX_CHECK_REG((_enp), (_reg));                          \
1010                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1011                     uint32_t, (_index),                                 \
1012                     uint32_t, _reg ## _OFST,                            \
1013                     uint32_t, (_edp)->ed_u32[0]);                       \
1014                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1015                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1016                     (_edp), (_lock));                                   \
1017         _NOTE(CONSTANTCONDITION)                                        \
1018         } while (B_FALSE)
1019
1020 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1021         do {                                                            \
1022                 EFX_CHECK_REG((_enp), (_reg));                          \
1023                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1024                     uint32_t, (_index),                                 \
1025                     uint32_t, _reg ## _OFST,                            \
1026                     uint32_t, (_edp)->ed_u32[0]);                       \
1027                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1028                     (_reg ## _OFST +                                    \
1029                     (3 * sizeof (efx_dword_t)) +                        \
1030                     ((_index) * _reg ## _STEP)),                        \
1031                     (_edp), (_lock));                                   \
1032         _NOTE(CONSTANTCONDITION)                                        \
1033         } while (B_FALSE)
1034
1035 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1036         do {                                                            \
1037                 EFX_CHECK_REG((_enp), (_reg));                          \
1038                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1039                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1040                     (_eqp));                                            \
1041                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1042                     uint32_t, (_index),                                 \
1043                     uint32_t, _reg ## _OFST,                            \
1044                     uint32_t, (_eqp)->eq_u32[1],                        \
1045                     uint32_t, (_eqp)->eq_u32[0]);                       \
1046         _NOTE(CONSTANTCONDITION)                                        \
1047         } while (B_FALSE)
1048
1049 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1050         do {                                                            \
1051                 EFX_CHECK_REG((_enp), (_reg));                          \
1052                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1053                     uint32_t, (_index),                                 \
1054                     uint32_t, _reg ## _OFST,                            \
1055                     uint32_t, (_eqp)->eq_u32[1],                        \
1056                     uint32_t, (_eqp)->eq_u32[0]);                       \
1057                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1058                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1059                     (_eqp));                                            \
1060         _NOTE(CONSTANTCONDITION)                                        \
1061         } while (B_FALSE)
1062
1063 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1064         do {                                                            \
1065                 EFX_CHECK_REG((_enp), (_reg));                          \
1066                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1067                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1068                     (_eop), (_lock));                                   \
1069                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1070                     uint32_t, (_index),                                 \
1071                     uint32_t, _reg ## _OFST,                            \
1072                     uint32_t, (_eop)->eo_u32[3],                        \
1073                     uint32_t, (_eop)->eo_u32[2],                        \
1074                     uint32_t, (_eop)->eo_u32[1],                        \
1075                     uint32_t, (_eop)->eo_u32[0]);                       \
1076         _NOTE(CONSTANTCONDITION)                                        \
1077         } while (B_FALSE)
1078
1079 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1080         do {                                                            \
1081                 EFX_CHECK_REG((_enp), (_reg));                          \
1082                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1083                     uint32_t, (_index),                                 \
1084                     uint32_t, _reg ## _OFST,                            \
1085                     uint32_t, (_eop)->eo_u32[3],                        \
1086                     uint32_t, (_eop)->eo_u32[2],                        \
1087                     uint32_t, (_eop)->eo_u32[1],                        \
1088                     uint32_t, (_eop)->eo_u32[0]);                       \
1089                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1090                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1091                     (_eop), (_lock));                                   \
1092         _NOTE(CONSTANTCONDITION)                                        \
1093         } while (B_FALSE)
1094
1095 /*
1096  * Accessors for memory BAR per-VI registers.
1097  *
1098  * The VI window size is 8KB for Medford and all earlier controllers.
1099  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1100  */
1101
1102 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1103         do {                                                            \
1104                 EFX_CHECK_REG((_enp), (_reg));                          \
1105                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1106                     ((_reg ## _OFST) +                                  \
1107                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1108                     (_edp), (_lock));                                   \
1109                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1110                     uint32_t, (_index),                                 \
1111                     uint32_t, _reg ## _OFST,                            \
1112                     uint32_t, (_edp)->ed_u32[0]);                       \
1113         _NOTE(CONSTANTCONDITION)                                        \
1114         } while (B_FALSE)
1115
1116 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1117         do {                                                            \
1118                 EFX_CHECK_REG((_enp), (_reg));                          \
1119                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1120                     uint32_t, (_index),                                 \
1121                     uint32_t, _reg ## _OFST,                            \
1122                     uint32_t, (_edp)->ed_u32[0]);                       \
1123                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1124                     ((_reg ## _OFST) +                                  \
1125                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1126                     (_edp), (_lock));                                   \
1127         _NOTE(CONSTANTCONDITION)                                        \
1128         } while (B_FALSE)
1129
1130 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1131         do {                                                            \
1132                 EFX_CHECK_REG((_enp), (_reg));                          \
1133                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1134                     uint32_t, (_index),                                 \
1135                     uint32_t, _reg ## _OFST,                            \
1136                     uint32_t, (_edp)->ed_u32[0]);                       \
1137                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1138                     ((_reg ## _OFST) +                                  \
1139                     (2 * sizeof (efx_dword_t)) +                        \
1140                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1141                     (_edp), (_lock));                                   \
1142         _NOTE(CONSTANTCONDITION)                                        \
1143         } while (B_FALSE)
1144
1145 /*
1146  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1147  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1148  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1149  * the need for locking in the host, and are the only ones known to be safe to
1150  * use 128-bites write with.
1151  */
1152 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1153         do {                                                            \
1154                 EFX_CHECK_REG((_enp), (_reg));                          \
1155                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1156                     const char *, #_reg,                                \
1157                     uint32_t, (_index),                                 \
1158                     uint32_t, _reg ## _OFST,                            \
1159                     uint32_t, (_eop)->eo_u32[3],                        \
1160                     uint32_t, (_eop)->eo_u32[2],                        \
1161                     uint32_t, (_eop)->eo_u32[1],                        \
1162                     uint32_t, (_eop)->eo_u32[0]);                       \
1163                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1164                     (_reg ## _OFST +                                    \
1165                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1166                     (_eop));                                            \
1167         _NOTE(CONSTANTCONDITION)                                        \
1168         } while (B_FALSE)
1169
1170 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1171         do {                                                            \
1172                 unsigned int _new = (_wptr);                            \
1173                 unsigned int _old = (_owptr);                           \
1174                                                                         \
1175                 if ((_new) >= (_old))                                   \
1176                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1177                             (_old) * sizeof (efx_desc_t),               \
1178                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1179                 else                                                    \
1180                         /*                                              \
1181                          * It is cheaper to sync entire map than sync   \
1182                          * two parts especially when offset/size are    \
1183                          * ignored and entire map is synced in any case.\
1184                          */                                             \
1185                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1186                             0,                                          \
1187                             (_entries) * sizeof (efx_desc_t));          \
1188         _NOTE(CONSTANTCONDITION)                                        \
1189         } while (B_FALSE)
1190
1191 extern  __checkReturn   efx_rc_t
1192 efx_mac_select(
1193         __in            efx_nic_t *enp);
1194
1195 extern  void
1196 efx_mac_multicast_hash_compute(
1197         __in_ecount(6*count)            uint8_t const *addrs,
1198         __in                            int count,
1199         __out                           efx_oword_t *hash_low,
1200         __out                           efx_oword_t *hash_high);
1201
1202 extern  __checkReturn   efx_rc_t
1203 efx_phy_probe(
1204         __in            efx_nic_t *enp);
1205
1206 extern                  void
1207 efx_phy_unprobe(
1208         __in            efx_nic_t *enp);
1209
1210 #if EFSYS_OPT_VPD
1211
1212 /* VPD utility functions */
1213
1214 extern  __checkReturn           efx_rc_t
1215 efx_vpd_hunk_length(
1216         __in_bcount(size)       caddr_t data,
1217         __in                    size_t size,
1218         __out                   size_t *lengthp);
1219
1220 extern  __checkReturn           efx_rc_t
1221 efx_vpd_hunk_verify(
1222         __in_bcount(size)       caddr_t data,
1223         __in                    size_t size,
1224         __out_opt               boolean_t *cksummedp);
1225
1226 extern  __checkReturn           efx_rc_t
1227 efx_vpd_hunk_reinit(
1228         __in_bcount(size)       caddr_t data,
1229         __in                    size_t size,
1230         __in                    boolean_t wantpid);
1231
1232 extern  __checkReturn           efx_rc_t
1233 efx_vpd_hunk_get(
1234         __in_bcount(size)       caddr_t data,
1235         __in                    size_t size,
1236         __in                    efx_vpd_tag_t tag,
1237         __in                    efx_vpd_keyword_t keyword,
1238         __out                   unsigned int *payloadp,
1239         __out                   uint8_t *paylenp);
1240
1241 extern  __checkReturn                   efx_rc_t
1242 efx_vpd_hunk_next(
1243         __in_bcount(size)               caddr_t data,
1244         __in                            size_t size,
1245         __out                           efx_vpd_tag_t *tagp,
1246         __out                           efx_vpd_keyword_t *keyword,
1247         __out_opt                       unsigned int *payloadp,
1248         __out_opt                       uint8_t *paylenp,
1249         __inout                         unsigned int *contp);
1250
1251 extern  __checkReturn           efx_rc_t
1252 efx_vpd_hunk_set(
1253         __in_bcount(size)       caddr_t data,
1254         __in                    size_t size,
1255         __in                    efx_vpd_value_t *evvp);
1256
1257 #endif  /* EFSYS_OPT_VPD */
1258
1259 #if EFSYS_OPT_MCDI
1260
1261 extern  __checkReturn           efx_rc_t
1262 efx_mcdi_set_workaround(
1263         __in                    efx_nic_t *enp,
1264         __in                    uint32_t type,
1265         __in                    boolean_t enabled,
1266         __out_opt               uint32_t *flagsp);
1267
1268 extern  __checkReturn           efx_rc_t
1269 efx_mcdi_get_workarounds(
1270         __in                    efx_nic_t *enp,
1271         __out_opt               uint32_t *implementedp,
1272         __out_opt               uint32_t *enabledp);
1273
1274 #endif /* EFSYS_OPT_MCDI */
1275
1276 #if EFSYS_OPT_MAC_STATS
1277
1278 /*
1279  * Closed range of stats (i.e. the first and the last are included).
1280  * The last must be greater or equal (if the range is one item only) to
1281  * the first.
1282  */
1283 struct efx_mac_stats_range {
1284         efx_mac_stat_t          first;
1285         efx_mac_stat_t          last;
1286 };
1287
1288 extern                                  efx_rc_t
1289 efx_mac_stats_mask_add_ranges(
1290         __inout_bcount(mask_size)       uint32_t *maskp,
1291         __in                            size_t mask_size,
1292         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1293         __in                            unsigned int rng_count);
1294
1295 #endif  /* EFSYS_OPT_MAC_STATS */
1296
1297 #ifdef  __cplusplus
1298 }
1299 #endif
1300
1301 #endif  /* _SYS_EFX_IMPL_H */