sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright notice,
  13  *    this list of conditions and the following disclaimer in the documentation
  14  *    and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * The views and conclusions contained in the software and documentation are
  29  * those of the authors and should not be interpreted as representing official
  30  * policies, either expressed or implied, of the FreeBSD Project.
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 #ifndef _SYS_EFX_IMPL_H
  36 #define _SYS_EFX_IMPL_H
  37
  38 #include "efx.h"
  39 #include "efx_regs.h"
  40 #include "efx_regs_ef10.h"
  41
  42 /* FIXME: Add definition for driver generated software events */
  43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  45 #endif
  46
  47
  48 #if EFSYS_OPT_SIENA
  49 #include "siena_impl.h"
  50 #endif  /* EFSYS_OPT_SIENA */
  51
  52 #if EFSYS_OPT_HUNTINGTON
  53 #include "hunt_impl.h"
  54 #endif  /* EFSYS_OPT_HUNTINGTON */
  55
  56 #if EFSYS_OPT_MEDFORD
  57 #include "medford_impl.h"
  58 #endif  /* EFSYS_OPT_MEDFORD */
  59
  60 #if EFSYS_OPT_MEDFORD2
  61 #include "medford2_impl.h"
  62 #endif  /* EFSYS_OPT_MEDFORD2 */
  63
  64 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  65 #include "ef10_impl.h"
  66 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  67
  68 #ifdef  __cplusplus
  69 extern "C" {
  70 #endif
  71
  72 #define EFX_MOD_MCDI            0x00000001
  73 #define EFX_MOD_PROBE           0x00000002
  74 #define EFX_MOD_NVRAM           0x00000004
  75 #define EFX_MOD_VPD             0x00000008
  76 #define EFX_MOD_NIC             0x00000010
  77 #define EFX_MOD_INTR            0x00000020
  78 #define EFX_MOD_EV              0x00000040
  79 #define EFX_MOD_RX              0x00000080
  80 #define EFX_MOD_TX              0x00000100
  81 #define EFX_MOD_PORT            0x00000200
  82 #define EFX_MOD_MON             0x00000400
  83 #define EFX_MOD_FILTER          0x00001000
  84 #define EFX_MOD_LIC             0x00002000
  85 #define EFX_MOD_TUNNEL          0x00004000
  86
  87 #define EFX_RESET_PHY           0x00000001
  88 #define EFX_RESET_RXQ_ERR       0x00000002
  89 #define EFX_RESET_TXQ_ERR       0x00000004
  90
  91 typedef enum efx_mac_type_e {
  92         EFX_MAC_INVALID = 0,
  93         EFX_MAC_SIENA,
  94         EFX_MAC_HUNTINGTON,
  95         EFX_MAC_MEDFORD,
  96         EFX_MAC_MEDFORD2,
  97         EFX_MAC_NTYPES
  98 } efx_mac_type_t;
  99
 100 typedef struct efx_ev_ops_s {
 101         efx_rc_t        (*eevo_init)(efx_nic_t *);
 102         void            (*eevo_fini)(efx_nic_t *);
 103         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
 104                                           efsys_mem_t *, size_t, uint32_t,
 105                                           uint32_t, uint32_t, efx_evq_t *);
 106         void            (*eevo_qdestroy)(efx_evq_t *);
 107         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 108         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 109         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 110 #if EFSYS_OPT_QSTATS
 111         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 112 #endif
 113 } efx_ev_ops_t;
 114
 115 typedef struct efx_tx_ops_s {
 116         efx_rc_t        (*etxo_init)(efx_nic_t *);
 117         void            (*etxo_fini)(efx_nic_t *);
 118         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 119                                         unsigned int, unsigned int,
 120                                         efsys_mem_t *, size_t,
 121                                         uint32_t, uint16_t,
 122                                         efx_evq_t *, efx_txq_t *,
 123                                         unsigned int *);
 124         void            (*etxo_qdestroy)(efx_txq_t *);
 125         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 129         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 130         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 131         void            (*etxo_qenable)(efx_txq_t *);
 132         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 133         void            (*etxo_qpio_disable)(efx_txq_t *);
 134         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 135                                            size_t);
 136         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 137                                            unsigned int *);
 138         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 139                                       unsigned int, unsigned int,
 140                                       unsigned int *);
 141         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 142                                                 size_t, boolean_t,
 143                                                 efx_desc_t *);
 144         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 145                                                 uint32_t, uint8_t,
 146                                                 efx_desc_t *);
 147         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 148                                                 uint16_t, uint32_t, uint16_t,
 149                                                 efx_desc_t *, int);
 150         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 151                                                 efx_desc_t *);
 152         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 153                                                 efx_desc_t *);
 154 #if EFSYS_OPT_QSTATS
 155         void            (*etxo_qstats_update)(efx_txq_t *,
 156                                               efsys_stat_t *);
 157 #endif
 158 } efx_tx_ops_t;
 159
 160 typedef union efx_rxq_type_data_u {
 161         /* Dummy member to have non-empty union if no options are enabled */
 162         uint32_t        ertd_dummy;
 163 #if EFSYS_OPT_RX_PACKED_STREAM
 164         struct {
 165                 uint32_t        eps_buf_size;
 166         } ertd_packed_stream;
 167 #endif
 168 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 169         struct {
 170                 uint32_t        eessb_bufs_per_desc;
 171                 uint32_t        eessb_max_dma_len;
 172                 uint32_t        eessb_buf_stride;
 173                 uint32_t        eessb_hol_block_timeout;
 174         } ertd_es_super_buffer;
 175 #endif
 176 } efx_rxq_type_data_t;
 177
 178 typedef struct efx_rx_ops_s {
 179         efx_rc_t        (*erxo_init)(efx_nic_t *);
 180         void            (*erxo_fini)(efx_nic_t *);
 181 #if EFSYS_OPT_RX_SCATTER
 182         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 183 #endif
 184 #if EFSYS_OPT_RX_SCALE
 185         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 186                                                     efx_rx_scale_context_type_t,
 187                                                     uint32_t, uint32_t *);
 188         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 189         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 190                                                efx_rx_hash_alg_t,
 191                                                efx_rx_hash_type_t, boolean_t);
 192         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 193                                               uint8_t *, size_t);
 194         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 195                                               unsigned int *, size_t);
 196         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 197                                             uint8_t *);
 198 #endif /* EFSYS_OPT_RX_SCALE */
 199         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 200                                               uint16_t *);
 201         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 202                                       unsigned int, unsigned int,
 203                                       unsigned int);
 204         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 205 #if EFSYS_OPT_RX_PACKED_STREAM
 206         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 207         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 208                                                 uint32_t, uint32_t,
 209                                                 uint16_t *, uint32_t *, uint32_t *);
 210 #endif
 211         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 212         void            (*erxo_qenable)(efx_rxq_t *);
 213         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 214                                         unsigned int, efx_rxq_type_t,
 215                                         const efx_rxq_type_data_t *,
 216                                         efsys_mem_t *, size_t, uint32_t,
 217                                         unsigned int,
 218                                         efx_evq_t *, efx_rxq_t *);
 219         void            (*erxo_qdestroy)(efx_rxq_t *);
 220 } efx_rx_ops_t;
 221
 222 typedef struct efx_mac_ops_s {
 223         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 224         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 225         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 226         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 227         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 228         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 229         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 230         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 231                                                       efx_rxq_t *, boolean_t);
 232         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 233 #if EFSYS_OPT_LOOPBACK
 234         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 235                                             efx_loopback_type_t);
 236 #endif  /* EFSYS_OPT_LOOPBACK */
 237 #if EFSYS_OPT_MAC_STATS
 238         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 239         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 240         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 241         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 242                                               uint16_t, boolean_t);
 243         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 244                                             efsys_stat_t *, uint32_t *);
 245 #endif  /* EFSYS_OPT_MAC_STATS */
 246 } efx_mac_ops_t;
 247
 248 typedef struct efx_phy_ops_s {
 249         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 250         efx_rc_t        (*epo_reset)(efx_nic_t *);
 251         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 252         efx_rc_t        (*epo_verify)(efx_nic_t *);
 253         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 254 #if EFSYS_OPT_PHY_STATS
 255         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 256                                             uint32_t *);
 257 #endif  /* EFSYS_OPT_PHY_STATS */
 258 #if EFSYS_OPT_BIST
 259         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 260         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 261         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 262                                          efx_bist_result_t *, uint32_t *,
 263                                          unsigned long *, size_t);
 264         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 265 #endif  /* EFSYS_OPT_BIST */
 266 } efx_phy_ops_t;
 267
 268 #if EFSYS_OPT_FILTER
 269 typedef struct efx_filter_ops_s {
 270         efx_rc_t        (*efo_init)(efx_nic_t *);
 271         void            (*efo_fini)(efx_nic_t *);
 272         efx_rc_t        (*efo_restore)(efx_nic_t *);
 273         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 274                                    boolean_t may_replace);
 275         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 276         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 277                                    size_t, size_t *);
 278         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 279                                    boolean_t, boolean_t, boolean_t,
 280                                    uint8_t const *, uint32_t);
 281 } efx_filter_ops_t;
 282
 283 extern  __checkReturn   efx_rc_t
 284 efx_filter_reconfigure(
 285         __in                            efx_nic_t *enp,
 286         __in_ecount(6)                  uint8_t const *mac_addr,
 287         __in                            boolean_t all_unicst,
 288         __in                            boolean_t mulcst,
 289         __in                            boolean_t all_mulcst,
 290         __in                            boolean_t brdcst,
 291         __in_ecount(6*count)            uint8_t const *addrs,
 292         __in                            uint32_t count);
 293
 294 #endif /* EFSYS_OPT_FILTER */
 295
 296 #if EFSYS_OPT_TUNNEL
 297 typedef struct efx_tunnel_ops_s {
 298         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 299         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 300 } efx_tunnel_ops_t;
 301 #endif /* EFSYS_OPT_TUNNEL */
 302
 303 typedef struct efx_port_s {
 304         efx_mac_type_t          ep_mac_type;
 305         uint32_t                ep_phy_type;
 306         uint8_t                 ep_port;
 307         uint32_t                ep_mac_pdu;
 308         uint8_t                 ep_mac_addr[6];
 309         efx_link_mode_t         ep_link_mode;
 310         boolean_t               ep_all_unicst;
 311         boolean_t               ep_mulcst;
 312         boolean_t               ep_all_mulcst;
 313         boolean_t               ep_brdcst;
 314         unsigned int            ep_fcntl;
 315         boolean_t               ep_fcntl_autoneg;
 316         efx_oword_t             ep_multicst_hash[2];
 317         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 318                                                     EFX_MAC_MULTICAST_LIST_MAX];
 319         uint32_t                ep_mulcst_addr_count;
 320 #if EFSYS_OPT_LOOPBACK
 321         efx_loopback_type_t     ep_loopback_type;
 322         efx_link_mode_t         ep_loopback_link_mode;
 323 #endif  /* EFSYS_OPT_LOOPBACK */
 324 #if EFSYS_OPT_PHY_FLAGS
 325         uint32_t                ep_phy_flags;
 326 #endif  /* EFSYS_OPT_PHY_FLAGS */
 327 #if EFSYS_OPT_PHY_LED_CONTROL
 328         efx_phy_led_mode_t      ep_phy_led_mode;
 329 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 330         efx_phy_media_type_t    ep_fixed_port_type;
 331         efx_phy_media_type_t    ep_module_type;
 332         uint32_t                ep_adv_cap_mask;
 333         uint32_t                ep_lp_cap_mask;
 334         uint32_t                ep_default_adv_cap_mask;
 335         uint32_t                ep_phy_cap_mask;
 336         boolean_t               ep_mac_drain;
 337 #if EFSYS_OPT_BIST
 338         efx_bist_type_t         ep_current_bist;
 339 #endif
 340         const efx_mac_ops_t     *ep_emop;
 341         const efx_phy_ops_t     *ep_epop;
 342 } efx_port_t;
 343
 344 typedef struct efx_mon_ops_s {
 345 #if EFSYS_OPT_MON_STATS
 346         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 347                                             efx_mon_stat_value_t *);
 348         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 349                                              efx_mon_stat_limits_t *);
 350 #endif  /* EFSYS_OPT_MON_STATS */
 351 } efx_mon_ops_t;
 352
 353 typedef struct efx_mon_s {
 354         efx_mon_type_t          em_type;
 355         const efx_mon_ops_t     *em_emop;
 356 } efx_mon_t;
 357
 358 typedef struct efx_intr_ops_s {
 359         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 360         void            (*eio_enable)(efx_nic_t *);
 361         void            (*eio_disable)(efx_nic_t *);
 362         void            (*eio_disable_unlocked)(efx_nic_t *);
 363         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 364         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 365         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 366                                  boolean_t *);
 367         void            (*eio_fatal)(efx_nic_t *);
 368         void            (*eio_fini)(efx_nic_t *);
 369 } efx_intr_ops_t;
 370
 371 typedef struct efx_intr_s {
 372         const efx_intr_ops_t    *ei_eiop;
 373         efsys_mem_t             *ei_esmp;
 374         efx_intr_type_t         ei_type;
 375         unsigned int            ei_level;
 376 } efx_intr_t;
 377
 378 typedef struct efx_nic_ops_s {
 379         efx_rc_t        (*eno_probe)(efx_nic_t *);
 380         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 381         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 382         efx_rc_t        (*eno_reset)(efx_nic_t *);
 383         efx_rc_t        (*eno_init)(efx_nic_t *);
 384         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 385         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 386                                         uint32_t *, size_t *);
 387 #if EFSYS_OPT_DIAG
 388         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 389 #endif  /* EFSYS_OPT_DIAG */
 390         void            (*eno_fini)(efx_nic_t *);
 391         void            (*eno_unprobe)(efx_nic_t *);
 392 } efx_nic_ops_t;
 393
 394 #ifndef EFX_TXQ_LIMIT_TARGET
 395 #define EFX_TXQ_LIMIT_TARGET 259
 396 #endif
 397 #ifndef EFX_RXQ_LIMIT_TARGET
 398 #define EFX_RXQ_LIMIT_TARGET 512
 399 #endif
 400
 401
 402 #if EFSYS_OPT_FILTER
 403
 404 #if EFSYS_OPT_SIENA
 405
 406 typedef struct siena_filter_spec_s {
 407         uint8_t         sfs_type;
 408         uint32_t        sfs_flags;
 409         uint32_t        sfs_dmaq_id;
 410         uint32_t        sfs_dword[3];
 411 } siena_filter_spec_t;
 412
 413 typedef enum siena_filter_type_e {
 414         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 415         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 416         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 417         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 418         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 419         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 420
 421         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 422         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 423         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 424         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 425         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 426         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 427
 428         EFX_SIENA_FILTER_NTYPES
 429 } siena_filter_type_t;
 430
 431 typedef enum siena_filter_tbl_id_e {
 432         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 433         EFX_SIENA_FILTER_TBL_RX_MAC,
 434         EFX_SIENA_FILTER_TBL_TX_IP,
 435         EFX_SIENA_FILTER_TBL_TX_MAC,
 436         EFX_SIENA_FILTER_NTBLS
 437 } siena_filter_tbl_id_t;
 438
 439 typedef struct siena_filter_tbl_s {
 440         int                     sft_size;       /* number of entries */
 441         int                     sft_used;       /* active count */
 442         uint32_t                *sft_bitmap;    /* active bitmap */
 443         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 444 } siena_filter_tbl_t;
 445
 446 typedef struct siena_filter_s {
 447         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 448         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 449 } siena_filter_t;
 450
 451 #endif  /* EFSYS_OPT_SIENA */
 452
 453 typedef struct efx_filter_s {
 454 #if EFSYS_OPT_SIENA
 455         siena_filter_t          *ef_siena_filter;
 456 #endif /* EFSYS_OPT_SIENA */
 457 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 458         ef10_filter_table_t     *ef_ef10_filter_table;
 459 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 460 } efx_filter_t;
 461
 462 #if EFSYS_OPT_SIENA
 463
 464 extern                  void
 465 siena_filter_tbl_clear(
 466         __in            efx_nic_t *enp,
 467         __in            siena_filter_tbl_id_t tbl);
 468
 469 #endif  /* EFSYS_OPT_SIENA */
 470
 471 #endif  /* EFSYS_OPT_FILTER */
 472
 473 #if EFSYS_OPT_MCDI
 474
 475 #define EFX_TUNNEL_MAXNENTRIES  (16)
 476
 477 #if EFSYS_OPT_TUNNEL
 478
 479 typedef struct efx_tunnel_udp_entry_s {
 480         uint16_t                        etue_port; /* host/cpu-endian */
 481         uint16_t                        etue_protocol;
 482 } efx_tunnel_udp_entry_t;
 483
 484 typedef struct efx_tunnel_cfg_s {
 485         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 486         unsigned int            etc_udp_entries_num;
 487 } efx_tunnel_cfg_t;
 488
 489 #endif /* EFSYS_OPT_TUNNEL */
 490
 491 typedef struct efx_mcdi_ops_s {
 492         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 493         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 494                                         void *, size_t);
 495         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 496         boolean_t       (*emco_poll_response)(efx_nic_t *);
 497         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 498         void            (*emco_fini)(efx_nic_t *);
 499         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 500                                             efx_mcdi_feature_id_t, boolean_t *);
 501         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 502                                             uint32_t *);
 503 } efx_mcdi_ops_t;
 504
 505 typedef struct efx_mcdi_s {
 506         const efx_mcdi_ops_t            *em_emcop;
 507         const efx_mcdi_transport_t      *em_emtp;
 508         efx_mcdi_iface_t                em_emip;
 509 } efx_mcdi_t;
 510
 511 #endif /* EFSYS_OPT_MCDI */
 512
 513 #if EFSYS_OPT_NVRAM
 514
 515 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 516 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 517
 518 typedef struct efx_nvram_ops_s {
 519 #if EFSYS_OPT_DIAG
 520         efx_rc_t        (*envo_test)(efx_nic_t *);
 521 #endif  /* EFSYS_OPT_DIAG */
 522         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 523                                             uint32_t *);
 524         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 525         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 526         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 527                                             unsigned int, caddr_t, size_t);
 528         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 529                                             unsigned int, caddr_t, size_t);
 530         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 531                                             unsigned int, size_t);
 532         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 533                                             unsigned int, caddr_t, size_t);
 534         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 535                                             uint32_t *);
 536         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 537                                             uint32_t *, uint16_t *);
 538         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 539                                             uint16_t *);
 540         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 541                                             caddr_t, size_t);
 542 } efx_nvram_ops_t;
 543 #endif /* EFSYS_OPT_NVRAM */
 544
 545 #if EFSYS_OPT_VPD
 546 typedef struct efx_vpd_ops_s {
 547         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 548         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 549         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 550         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 551         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 552         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 553                                         efx_vpd_value_t *);
 554         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 555                                         efx_vpd_value_t *);
 556         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 557                                         efx_vpd_value_t *, unsigned int *);
 558         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 559         void            (*evpdo_fini)(efx_nic_t *);
 560 } efx_vpd_ops_t;
 561 #endif  /* EFSYS_OPT_VPD */
 562
 563 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 564
 565         __checkReturn           efx_rc_t
 566 efx_mcdi_nvram_partitions(
 567         __in                    efx_nic_t *enp,
 568         __out_bcount(size)      caddr_t data,
 569         __in                    size_t size,
 570         __out                   unsigned int *npartnp);
 571
 572         __checkReturn           efx_rc_t
 573 efx_mcdi_nvram_metadata(
 574         __in                    efx_nic_t *enp,
 575         __in                    uint32_t partn,
 576         __out                   uint32_t *subtypep,
 577         __out_ecount(4)         uint16_t version[4],
 578         __out_bcount_opt(size)  char *descp,
 579         __in                    size_t size);
 580
 581         __checkReturn           efx_rc_t
 582 efx_mcdi_nvram_info(
 583         __in                    efx_nic_t *enp,
 584         __in                    uint32_t partn,
 585         __out_opt               size_t *sizep,
 586         __out_opt               uint32_t *addressp,
 587         __out_opt               uint32_t *erase_sizep,
 588         __out_opt               uint32_t *write_sizep);
 589
 590         __checkReturn           efx_rc_t
 591 efx_mcdi_nvram_update_start(
 592         __in                    efx_nic_t *enp,
 593         __in                    uint32_t partn);
 594
 595         __checkReturn           efx_rc_t
 596 efx_mcdi_nvram_read(
 597         __in                    efx_nic_t *enp,
 598         __in                    uint32_t partn,
 599         __in                    uint32_t offset,
 600         __out_bcount(size)      caddr_t data,
 601         __in                    size_t size,
 602         __in                    uint32_t mode);
 603
 604         __checkReturn           efx_rc_t
 605 efx_mcdi_nvram_erase(
 606         __in                    efx_nic_t *enp,
 607         __in                    uint32_t partn,
 608         __in                    uint32_t offset,
 609         __in                    size_t size);
 610
 611         __checkReturn           efx_rc_t
 612 efx_mcdi_nvram_write(
 613         __in                    efx_nic_t *enp,
 614         __in                    uint32_t partn,
 615         __in                    uint32_t offset,
 616         __in_bcount(size)       caddr_t data,
 617         __in                    size_t size);
 618
 619         __checkReturn           efx_rc_t
 620 efx_mcdi_nvram_update_finish(
 621         __in                    efx_nic_t *enp,
 622         __in                    uint32_t partn,
 623         __in                    boolean_t reboot,
 624         __out_opt               uint32_t *verify_resultp);
 625
 626 #if EFSYS_OPT_DIAG
 627
 628         __checkReturn           efx_rc_t
 629 efx_mcdi_nvram_test(
 630         __in                    efx_nic_t *enp,
 631         __in                    uint32_t partn);
 632
 633 #endif  /* EFSYS_OPT_DIAG */
 634
 635 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 636
 637 #if EFSYS_OPT_LICENSING
 638
 639 typedef struct efx_lic_ops_s {
 640         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 641         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 642         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 643         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 644                                       size_t *, uint8_t *);
 645         efx_rc_t        (*elo_find_start)
 646                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 647         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 648                                 uint32_t, uint32_t *);
 649         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 650                                 uint32_t, uint32_t *, uint32_t *);
 651         boolean_t       (*elo_validate_key)(efx_nic_t *,
 652                                 caddr_t, uint32_t);
 653         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 654                                 caddr_t, size_t, uint32_t, uint32_t,
 655                                 caddr_t, size_t, uint32_t *);
 656         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 657                                 caddr_t, size_t, uint32_t,
 658                                 caddr_t, uint32_t, uint32_t *);
 659         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 660                                 caddr_t, size_t, uint32_t,
 661                                 uint32_t, uint32_t, uint32_t *);
 662         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 663                                 caddr_t, size_t);
 664         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 665                                 caddr_t, size_t);
 666 } efx_lic_ops_t;
 667
 668 #endif
 669
 670 typedef struct efx_drv_cfg_s {
 671         uint32_t                edc_min_vi_count;
 672         uint32_t                edc_max_vi_count;
 673
 674         uint32_t                edc_max_piobuf_count;
 675         uint32_t                edc_pio_alloc_size;
 676 } efx_drv_cfg_t;
 677
 678 struct efx_nic_s {
 679         uint32_t                en_magic;
 680         efx_family_t            en_family;
 681         uint32_t                en_features;
 682         efsys_identifier_t      *en_esip;
 683         efsys_lock_t            *en_eslp;
 684         efsys_bar_t             *en_esbp;
 685         unsigned int            en_mod_flags;
 686         unsigned int            en_reset_flags;
 687         efx_nic_cfg_t           en_nic_cfg;
 688         efx_drv_cfg_t           en_drv_cfg;
 689         efx_port_t              en_port;
 690         efx_mon_t               en_mon;
 691         efx_intr_t              en_intr;
 692         uint32_t                en_ev_qcount;
 693         uint32_t                en_rx_qcount;
 694         uint32_t                en_tx_qcount;
 695         const efx_nic_ops_t     *en_enop;
 696         const efx_ev_ops_t      *en_eevop;
 697         const efx_tx_ops_t      *en_etxop;
 698         const efx_rx_ops_t      *en_erxop;
 699         efx_fw_variant_t        efv;
 700 #if EFSYS_OPT_FILTER
 701         efx_filter_t            en_filter;
 702         const efx_filter_ops_t  *en_efop;
 703 #endif  /* EFSYS_OPT_FILTER */
 704 #if EFSYS_OPT_TUNNEL
 705         efx_tunnel_cfg_t        en_tunnel_cfg;
 706         const efx_tunnel_ops_t  *en_etop;
 707 #endif /* EFSYS_OPT_TUNNEL */
 708 #if EFSYS_OPT_MCDI
 709         efx_mcdi_t              en_mcdi;
 710 #endif  /* EFSYS_OPT_MCDI */
 711 #if EFSYS_OPT_NVRAM
 712         uint32_t                en_nvram_partn_locked;
 713         const efx_nvram_ops_t   *en_envop;
 714 #endif  /* EFSYS_OPT_NVRAM */
 715 #if EFSYS_OPT_VPD
 716         const efx_vpd_ops_t     *en_evpdop;
 717 #endif  /* EFSYS_OPT_VPD */
 718 #if EFSYS_OPT_RX_SCALE
 719         efx_rx_hash_support_t           en_hash_support;
 720         efx_rx_scale_context_type_t     en_rss_context_type;
 721         uint32_t                        en_rss_context;
 722 #endif  /* EFSYS_OPT_RX_SCALE */
 723         uint32_t                en_vport_id;
 724 #if EFSYS_OPT_LICENSING
 725         const efx_lic_ops_t     *en_elop;
 726         boolean_t               en_licensing_supported;
 727 #endif
 728         union {
 729 #if EFSYS_OPT_SIENA
 730                 struct {
 731 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 732                         unsigned int            enu_partn_mask;
 733 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 734 #if EFSYS_OPT_VPD
 735                         caddr_t                 enu_svpd;
 736                         size_t                  enu_svpd_length;
 737 #endif  /* EFSYS_OPT_VPD */
 738                         int                     enu_unused;
 739                 } siena;
 740 #endif  /* EFSYS_OPT_SIENA */
 741                 int     enu_unused;
 742         } en_u;
 743 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 744         union en_arch {
 745                 struct {
 746                         int                     ena_vi_base;
 747                         int                     ena_vi_count;
 748                         int                     ena_vi_shift;
 749 #if EFSYS_OPT_VPD
 750                         caddr_t                 ena_svpd;
 751                         size_t                  ena_svpd_length;
 752 #endif  /* EFSYS_OPT_VPD */
 753                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 754                         uint32_t                ena_piobuf_count;
 755                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 756                         uint32_t                ena_pio_write_vi_base;
 757                         /* Memory BAR mapping regions */
 758                         uint32_t                ena_uc_mem_map_offset;
 759                         size_t                  ena_uc_mem_map_size;
 760                         uint32_t                ena_wc_mem_map_offset;
 761                         size_t                  ena_wc_mem_map_size;
 762                 } ef10;
 763         } en_arch;
 764 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 765 };
 766
 767
 768 #define EFX_NIC_MAGIC   0x02121996
 769
 770 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 771     const efx_ev_callbacks_t *, void *);
 772
 773 typedef struct efx_evq_rxq_state_s {
 774         unsigned int                    eers_rx_read_ptr;
 775         unsigned int                    eers_rx_mask;
 776 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 777         unsigned int                    eers_rx_stream_npackets;
 778         boolean_t                       eers_rx_packed_stream;
 779 #endif
 780 #if EFSYS_OPT_RX_PACKED_STREAM
 781         unsigned int                    eers_rx_packed_stream_credits;
 782 #endif
 783 } efx_evq_rxq_state_t;
 784
 785 struct efx_evq_s {
 786         uint32_t                        ee_magic;
 787         efx_nic_t                       *ee_enp;
 788         unsigned int                    ee_index;
 789         unsigned int                    ee_mask;
 790         efsys_mem_t                     *ee_esmp;
 791 #if EFSYS_OPT_QSTATS
 792         uint32_t                        ee_stat[EV_NQSTATS];
 793 #endif  /* EFSYS_OPT_QSTATS */
 794
 795         efx_ev_handler_t                ee_rx;
 796         efx_ev_handler_t                ee_tx;
 797         efx_ev_handler_t                ee_driver;
 798         efx_ev_handler_t                ee_global;
 799         efx_ev_handler_t                ee_drv_gen;
 800 #if EFSYS_OPT_MCDI
 801         efx_ev_handler_t                ee_mcdi;
 802 #endif  /* EFSYS_OPT_MCDI */
 803
 804         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 805
 806         uint32_t                        ee_flags;
 807 };
 808
 809 #define EFX_EVQ_MAGIC   0x08081997
 810
 811 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 812
 813 struct efx_rxq_s {
 814         uint32_t                        er_magic;
 815         efx_nic_t                       *er_enp;
 816         efx_evq_t                       *er_eep;
 817         unsigned int                    er_index;
 818         unsigned int                    er_label;
 819         unsigned int                    er_mask;
 820         efsys_mem_t                     *er_esmp;
 821         efx_evq_rxq_state_t             *er_ev_qstate;
 822 };
 823
 824 #define EFX_RXQ_MAGIC   0x15022005
 825
 826 struct efx_txq_s {
 827         uint32_t                        et_magic;
 828         efx_nic_t                       *et_enp;
 829         unsigned int                    et_index;
 830         unsigned int                    et_mask;
 831         efsys_mem_t                     *et_esmp;
 832 #if EFSYS_OPT_HUNTINGTON
 833         uint32_t                        et_pio_bufnum;
 834         uint32_t                        et_pio_blknum;
 835         uint32_t                        et_pio_write_offset;
 836         uint32_t                        et_pio_offset;
 837         size_t                          et_pio_size;
 838 #endif
 839 #if EFSYS_OPT_QSTATS
 840         uint32_t                        et_stat[TX_NQSTATS];
 841 #endif  /* EFSYS_OPT_QSTATS */
 842 };
 843
 844 #define EFX_TXQ_MAGIC   0x05092005
 845
 846 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 847         do {                                                            \
 848                 (_dst)[0] = (_src)[0];                                  \
 849                 (_dst)[1] = (_src)[1];                                  \
 850                 (_dst)[2] = (_src)[2];                                  \
 851                 (_dst)[3] = (_src)[3];                                  \
 852                 (_dst)[4] = (_src)[4];                                  \
 853                 (_dst)[5] = (_src)[5];                                  \
 854         _NOTE(CONSTANTCONDITION)                                        \
 855         } while (B_FALSE)
 856
 857 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 858         do {                                                            \
 859                 uint16_t *_d = (uint16_t *)(_dst);                      \
 860                 _d[0] = 0xffff;                                         \
 861                 _d[1] = 0xffff;                                         \
 862                 _d[2] = 0xffff;                                         \
 863         _NOTE(CONSTANTCONDITION)                                        \
 864         } while (B_FALSE)
 865
 866 #if EFSYS_OPT_CHECK_REG
 867 #define EFX_CHECK_REG(_enp, _reg)                                       \
 868         do {                                                            \
 869                 const char *name = #_reg;                               \
 870                 char min = name[4];                                     \
 871                 char max = name[5];                                     \
 872                 char rev;                                               \
 873                                                                         \
 874                 switch ((_enp)->en_family) {                            \
 875                 case EFX_FAMILY_SIENA:                                  \
 876                         rev = 'C';                                      \
 877                         break;                                          \
 878                                                                         \
 879                 case EFX_FAMILY_HUNTINGTON:                             \
 880                         rev = 'D';                                      \
 881                         break;                                          \
 882                                                                         \
 883                 case EFX_FAMILY_MEDFORD:                                \
 884                         rev = 'E';                                      \
 885                         break;                                          \
 886                                                                         \
 887                 case EFX_FAMILY_MEDFORD2:                               \
 888                         rev = 'F';                                      \
 889                         break;                                          \
 890                                                                         \
 891                 default:                                                \
 892                         rev = '?';                                      \
 893                         break;                                          \
 894                 }                                                       \
 895                                                                         \
 896                 EFSYS_ASSERT3S(rev, >=, min);                           \
 897                 EFSYS_ASSERT3S(rev, <=, max);                           \
 898                                                                         \
 899         _NOTE(CONSTANTCONDITION)                                        \
 900         } while (B_FALSE)
 901 #else
 902 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905 #endif
 906
 907 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 908         do {                                                            \
 909                 EFX_CHECK_REG((_enp), (_reg));                          \
 910                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 911                     (_edp), (_lock));                                   \
 912                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 913                     uint32_t, _reg ## _OFST,                            \
 914                     uint32_t, (_edp)->ed_u32[0]);                       \
 915         _NOTE(CONSTANTCONDITION)                                        \
 916         } while (B_FALSE)
 917
 918 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 919         do {                                                            \
 920                 EFX_CHECK_REG((_enp), (_reg));                          \
 921                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 922                     uint32_t, _reg ## _OFST,                            \
 923                     uint32_t, (_edp)->ed_u32[0]);                       \
 924                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 925                     (_edp), (_lock));                                   \
 926         _NOTE(CONSTANTCONDITION)                                        \
 927         } while (B_FALSE)
 928
 929 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 930         do {                                                            \
 931                 EFX_CHECK_REG((_enp), (_reg));                          \
 932                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 933                     (_eqp));                                            \
 934                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 935                     uint32_t, _reg ## _OFST,                            \
 936                     uint32_t, (_eqp)->eq_u32[1],                        \
 937                     uint32_t, (_eqp)->eq_u32[0]);                       \
 938         _NOTE(CONSTANTCONDITION)                                        \
 939         } while (B_FALSE)
 940
 941 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 942         do {                                                            \
 943                 EFX_CHECK_REG((_enp), (_reg));                          \
 944                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 945                     uint32_t, _reg ## _OFST,                            \
 946                     uint32_t, (_eqp)->eq_u32[1],                        \
 947                     uint32_t, (_eqp)->eq_u32[0]);                       \
 948                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 949                     (_eqp));                                            \
 950         _NOTE(CONSTANTCONDITION)                                        \
 951         } while (B_FALSE)
 952
 953 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 954         do {                                                            \
 955                 EFX_CHECK_REG((_enp), (_reg));                          \
 956                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 957                     (_eop), B_TRUE);                                    \
 958                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 959                     uint32_t, _reg ## _OFST,                            \
 960                     uint32_t, (_eop)->eo_u32[3],                        \
 961                     uint32_t, (_eop)->eo_u32[2],                        \
 962                     uint32_t, (_eop)->eo_u32[1],                        \
 963                     uint32_t, (_eop)->eo_u32[0]);                       \
 964         _NOTE(CONSTANTCONDITION)                                        \
 965         } while (B_FALSE)
 966
 967 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 971                     uint32_t, _reg ## _OFST,                            \
 972                     uint32_t, (_eop)->eo_u32[3],                        \
 973                     uint32_t, (_eop)->eo_u32[2],                        \
 974                     uint32_t, (_eop)->eo_u32[1],                        \
 975                     uint32_t, (_eop)->eo_u32[0]);                       \
 976                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 977                     (_eop), B_TRUE);                                    \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980
 981 /*
 982  * Accessors for memory BAR non-VI tables.
 983  *
 984  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 985  * to ensure the correct runtime VI window size is used on Medford2.
 986  *
 987  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 988  */
 989
 990 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 994                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 995                     (_edp), (_lock));                                   \
 996                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 997                     uint32_t, (_index),                                 \
 998                     uint32_t, _reg ## _OFST,                            \
 999                     uint32_t, (_edp)->ed_u32[0]);                       \
1000         _NOTE(CONSTANTCONDITION)                                        \
1001         } while (B_FALSE)
1002
1003 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1004         do {                                                            \
1005                 EFX_CHECK_REG((_enp), (_reg));                          \
1006                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1007                     uint32_t, (_index),                                 \
1008                     uint32_t, _reg ## _OFST,                            \
1009                     uint32_t, (_edp)->ed_u32[0]);                       \
1010                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1011                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1012                     (_edp), (_lock));                                   \
1013         _NOTE(CONSTANTCONDITION)                                        \
1014         } while (B_FALSE)
1015
1016 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1017         do {                                                            \
1018                 EFX_CHECK_REG((_enp), (_reg));                          \
1019                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1020                     uint32_t, (_index),                                 \
1021                     uint32_t, _reg ## _OFST,                            \
1022                     uint32_t, (_edp)->ed_u32[0]);                       \
1023                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1024                     (_reg ## _OFST +                                    \
1025                     (3 * sizeof (efx_dword_t)) +                        \
1026                     ((_index) * _reg ## _STEP)),                        \
1027                     (_edp), (_lock));                                   \
1028         _NOTE(CONSTANTCONDITION)                                        \
1029         } while (B_FALSE)
1030
1031 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1032         do {                                                            \
1033                 EFX_CHECK_REG((_enp), (_reg));                          \
1034                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1035                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1036                     (_eqp));                                            \
1037                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1038                     uint32_t, (_index),                                 \
1039                     uint32_t, _reg ## _OFST,                            \
1040                     uint32_t, (_eqp)->eq_u32[1],                        \
1041                     uint32_t, (_eqp)->eq_u32[0]);                       \
1042         _NOTE(CONSTANTCONDITION)                                        \
1043         } while (B_FALSE)
1044
1045 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1046         do {                                                            \
1047                 EFX_CHECK_REG((_enp), (_reg));                          \
1048                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1049                     uint32_t, (_index),                                 \
1050                     uint32_t, _reg ## _OFST,                            \
1051                     uint32_t, (_eqp)->eq_u32[1],                        \
1052                     uint32_t, (_eqp)->eq_u32[0]);                       \
1053                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1054                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1055                     (_eqp));                                            \
1056         _NOTE(CONSTANTCONDITION)                                        \
1057         } while (B_FALSE)
1058
1059 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1060         do {                                                            \
1061                 EFX_CHECK_REG((_enp), (_reg));                          \
1062                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1063                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1064                     (_eop), (_lock));                                   \
1065                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1066                     uint32_t, (_index),                                 \
1067                     uint32_t, _reg ## _OFST,                            \
1068                     uint32_t, (_eop)->eo_u32[3],                        \
1069                     uint32_t, (_eop)->eo_u32[2],                        \
1070                     uint32_t, (_eop)->eo_u32[1],                        \
1071                     uint32_t, (_eop)->eo_u32[0]);                       \
1072         _NOTE(CONSTANTCONDITION)                                        \
1073         } while (B_FALSE)
1074
1075 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1076         do {                                                            \
1077                 EFX_CHECK_REG((_enp), (_reg));                          \
1078                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1079                     uint32_t, (_index),                                 \
1080                     uint32_t, _reg ## _OFST,                            \
1081                     uint32_t, (_eop)->eo_u32[3],                        \
1082                     uint32_t, (_eop)->eo_u32[2],                        \
1083                     uint32_t, (_eop)->eo_u32[1],                        \
1084                     uint32_t, (_eop)->eo_u32[0]);                       \
1085                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1086                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1087                     (_eop), (_lock));                                   \
1088         _NOTE(CONSTANTCONDITION)                                        \
1089         } while (B_FALSE)
1090
1091 /*
1092  * Accessors for memory BAR per-VI registers.
1093  *
1094  * The VI window size is 8KB for Medford and all earlier controllers.
1095  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1096  */
1097
1098 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1099         do {                                                            \
1100                 EFX_CHECK_REG((_enp), (_reg));                          \
1101                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1102                     ((_reg ## _OFST) +                                  \
1103                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1104                     (_edp), (_lock));                                   \
1105                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1106                     uint32_t, (_index),                                 \
1107                     uint32_t, _reg ## _OFST,                            \
1108                     uint32_t, (_edp)->ed_u32[0]);                       \
1109         _NOTE(CONSTANTCONDITION)                                        \
1110         } while (B_FALSE)
1111
1112 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1113         do {                                                            \
1114                 EFX_CHECK_REG((_enp), (_reg));                          \
1115                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1116                     uint32_t, (_index),                                 \
1117                     uint32_t, _reg ## _OFST,                            \
1118                     uint32_t, (_edp)->ed_u32[0]);                       \
1119                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1120                     ((_reg ## _OFST) +                                  \
1121                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1122                     (_edp), (_lock));                                   \
1123         _NOTE(CONSTANTCONDITION)                                        \
1124         } while (B_FALSE)
1125
1126 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1127         do {                                                            \
1128                 EFX_CHECK_REG((_enp), (_reg));                          \
1129                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1130                     uint32_t, (_index),                                 \
1131                     uint32_t, _reg ## _OFST,                            \
1132                     uint32_t, (_edp)->ed_u32[0]);                       \
1133                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1134                     ((_reg ## _OFST) +                                  \
1135                     (2 * sizeof (efx_dword_t)) +                        \
1136                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1137                     (_edp), (_lock));                                   \
1138         _NOTE(CONSTANTCONDITION)                                        \
1139         } while (B_FALSE)
1140
1141 /*
1142  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1143  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1144  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1145  * the need for locking in the host, and are the only ones known to be safe to
1146  * use 128-bites write with.
1147  */
1148 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1149         do {                                                            \
1150                 EFX_CHECK_REG((_enp), (_reg));                          \
1151                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1152                     const char *, #_reg,                                \
1153                     uint32_t, (_index),                                 \
1154                     uint32_t, _reg ## _OFST,                            \
1155                     uint32_t, (_eop)->eo_u32[3],                        \
1156                     uint32_t, (_eop)->eo_u32[2],                        \
1157                     uint32_t, (_eop)->eo_u32[1],                        \
1158                     uint32_t, (_eop)->eo_u32[0]);                       \
1159                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1160                     (_reg ## _OFST +                                    \
1161                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1162                     (_eop));                                            \
1163         _NOTE(CONSTANTCONDITION)                                        \
1164         } while (B_FALSE)
1165
1166 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1167         do {                                                            \
1168                 unsigned int _new = (_wptr);                            \
1169                 unsigned int _old = (_owptr);                           \
1170                                                                         \
1171                 if ((_new) >= (_old))                                   \
1172                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1173                             (_old) * sizeof (efx_desc_t),               \
1174                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1175                 else                                                    \
1176                         /*                                              \
1177                          * It is cheaper to sync entire map than sync   \
1178                          * two parts especially when offset/size are    \
1179                          * ignored and entire map is synced in any case.\
1180                          */                                             \
1181                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1182                             0,                                          \
1183                             (_entries) * sizeof (efx_desc_t));          \
1184         _NOTE(CONSTANTCONDITION)                                        \
1185         } while (B_FALSE)
1186
1187 extern  __checkReturn   efx_rc_t
1188 efx_mac_select(
1189         __in            efx_nic_t *enp);
1190
1191 extern  void
1192 efx_mac_multicast_hash_compute(
1193         __in_ecount(6*count)            uint8_t const *addrs,
1194         __in                            int count,
1195         __out                           efx_oword_t *hash_low,
1196         __out                           efx_oword_t *hash_high);
1197
1198 extern  __checkReturn   efx_rc_t
1199 efx_phy_probe(
1200         __in            efx_nic_t *enp);
1201
1202 extern                  void
1203 efx_phy_unprobe(
1204         __in            efx_nic_t *enp);
1205
1206 #if EFSYS_OPT_VPD
1207
1208 /* VPD utility functions */
1209
1210 extern  __checkReturn           efx_rc_t
1211 efx_vpd_hunk_length(
1212         __in_bcount(size)       caddr_t data,
1213         __in                    size_t size,
1214         __out                   size_t *lengthp);
1215
1216 extern  __checkReturn           efx_rc_t
1217 efx_vpd_hunk_verify(
1218         __in_bcount(size)       caddr_t data,
1219         __in                    size_t size,
1220         __out_opt               boolean_t *cksummedp);
1221
1222 extern  __checkReturn           efx_rc_t
1223 efx_vpd_hunk_reinit(
1224         __in_bcount(size)       caddr_t data,
1225         __in                    size_t size,
1226         __in                    boolean_t wantpid);
1227
1228 extern  __checkReturn           efx_rc_t
1229 efx_vpd_hunk_get(
1230         __in_bcount(size)       caddr_t data,
1231         __in                    size_t size,
1232         __in                    efx_vpd_tag_t tag,
1233         __in                    efx_vpd_keyword_t keyword,
1234         __out                   unsigned int *payloadp,
1235         __out                   uint8_t *paylenp);
1236
1237 extern  __checkReturn                   efx_rc_t
1238 efx_vpd_hunk_next(
1239         __in_bcount(size)               caddr_t data,
1240         __in                            size_t size,
1241         __out                           efx_vpd_tag_t *tagp,
1242         __out                           efx_vpd_keyword_t *keyword,
1243         __out_opt                       unsigned int *payloadp,
1244         __out_opt                       uint8_t *paylenp,
1245         __inout                         unsigned int *contp);
1246
1247 extern  __checkReturn           efx_rc_t
1248 efx_vpd_hunk_set(
1249         __in_bcount(size)       caddr_t data,
1250         __in                    size_t size,
1251         __in                    efx_vpd_value_t *evvp);
1252
1253 #endif  /* EFSYS_OPT_VPD */
1254
1255 #if EFSYS_OPT_MCDI
1256
1257 extern  __checkReturn           efx_rc_t
1258 efx_mcdi_set_workaround(
1259         __in                    efx_nic_t *enp,
1260         __in                    uint32_t type,
1261         __in                    boolean_t enabled,
1262         __out_opt               uint32_t *flagsp);
1263
1264 extern  __checkReturn           efx_rc_t
1265 efx_mcdi_get_workarounds(
1266         __in                    efx_nic_t *enp,
1267         __out_opt               uint32_t *implementedp,
1268         __out_opt               uint32_t *enabledp);
1269
1270 #endif /* EFSYS_OPT_MCDI */
1271
1272 #if EFSYS_OPT_MAC_STATS
1273
1274 /*
1275  * Closed range of stats (i.e. the first and the last are included).
1276  * The last must be greater or equal (if the range is one item only) to
1277  * the first.
1278  */
1279 struct efx_mac_stats_range {
1280         efx_mac_stat_t          first;
1281         efx_mac_stat_t          last;
1282 };
1283
1284 extern                                  efx_rc_t
1285 efx_mac_stats_mask_add_ranges(
1286         __inout_bcount(mask_size)       uint32_t *maskp,
1287         __in                            size_t mask_size,
1288         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1289         __in                            unsigned int rng_count);
1290
1291 #endif  /* EFSYS_OPT_MAC_STATS */
1292
1293 #ifdef  __cplusplus
1294 }
1295 #endif
1296
1297 #endif  /* _SYS_EFX_IMPL_H */