2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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33 #ifndef _SYS_EFX_IMPL_H
34 #define _SYS_EFX_IMPL_H
38 #include "efx_regs_ef10.h"
40 /* FIXME: Add definition for driver generated software events */
41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
47 #include "siena_impl.h"
48 #endif /* EFSYS_OPT_SIENA */
50 #if EFSYS_OPT_HUNTINGTON
51 #include "hunt_impl.h"
52 #endif /* EFSYS_OPT_HUNTINGTON */
55 #include "medford_impl.h"
56 #endif /* EFSYS_OPT_MEDFORD */
58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
59 #include "ef10_impl.h"
60 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
66 #define EFX_MOD_MCDI 0x00000001
67 #define EFX_MOD_PROBE 0x00000002
68 #define EFX_MOD_NVRAM 0x00000004
69 #define EFX_MOD_VPD 0x00000008
70 #define EFX_MOD_NIC 0x00000010
71 #define EFX_MOD_INTR 0x00000020
72 #define EFX_MOD_EV 0x00000040
73 #define EFX_MOD_RX 0x00000080
74 #define EFX_MOD_TX 0x00000100
75 #define EFX_MOD_PORT 0x00000200
76 #define EFX_MOD_MON 0x00000400
77 #define EFX_MOD_WOL 0x00000800
78 #define EFX_MOD_FILTER 0x00001000
79 #define EFX_MOD_LIC 0x00002000
81 #define EFX_RESET_PHY 0x00000001
82 #define EFX_RESET_RXQ_ERR 0x00000002
83 #define EFX_RESET_TXQ_ERR 0x00000004
85 typedef enum efx_mac_type_e {
93 typedef struct efx_ev_ops_s {
94 efx_rc_t (*eevo_init)(efx_nic_t *);
95 void (*eevo_fini)(efx_nic_t *);
96 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
97 efsys_mem_t *, size_t, uint32_t,
98 uint32_t, uint32_t, efx_evq_t *);
99 void (*eevo_qdestroy)(efx_evq_t *);
100 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
101 void (*eevo_qpost)(efx_evq_t *, uint16_t);
102 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
104 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
108 typedef struct efx_tx_ops_s {
109 efx_rc_t (*etxo_init)(efx_nic_t *);
110 void (*etxo_fini)(efx_nic_t *);
111 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
112 unsigned int, unsigned int,
113 efsys_mem_t *, size_t,
115 efx_evq_t *, efx_txq_t *,
117 void (*etxo_qdestroy)(efx_txq_t *);
118 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
119 unsigned int, unsigned int,
121 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
122 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
123 efx_rc_t (*etxo_qflush)(efx_txq_t *);
124 void (*etxo_qenable)(efx_txq_t *);
125 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
126 void (*etxo_qpio_disable)(efx_txq_t *);
127 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
129 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
131 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
132 unsigned int, unsigned int,
134 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
137 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
146 void (*etxo_qstats_update)(efx_txq_t *,
151 typedef struct efx_rx_ops_s {
152 efx_rc_t (*erxo_init)(efx_nic_t *);
153 void (*erxo_fini)(efx_nic_t *);
154 #if EFSYS_OPT_RX_SCATTER
155 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
157 #if EFSYS_OPT_RX_SCALE
158 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
159 efx_rx_hash_type_t, boolean_t);
160 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
161 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
163 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
165 #endif /* EFSYS_OPT_RX_SCALE */
166 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
168 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
169 unsigned int, unsigned int,
171 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
172 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
173 void (*erxo_qenable)(efx_rxq_t *);
174 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
175 unsigned int, efx_rxq_type_t,
176 efsys_mem_t *, size_t, uint32_t,
177 efx_evq_t *, efx_rxq_t *);
178 void (*erxo_qdestroy)(efx_rxq_t *);
181 typedef struct efx_mac_ops_s {
182 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
183 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
184 efx_rc_t (*emo_addr_set)(efx_nic_t *);
185 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
186 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
187 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
188 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
189 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
190 efx_rxq_t *, boolean_t);
191 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
192 #if EFSYS_OPT_LOOPBACK
193 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
194 efx_loopback_type_t);
195 #endif /* EFSYS_OPT_LOOPBACK */
196 #if EFSYS_OPT_MAC_STATS
197 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
198 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
199 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
200 uint16_t, boolean_t);
201 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
202 efsys_stat_t *, uint32_t *);
203 #endif /* EFSYS_OPT_MAC_STATS */
206 typedef struct efx_phy_ops_s {
207 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
208 efx_rc_t (*epo_reset)(efx_nic_t *);
209 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
210 efx_rc_t (*epo_verify)(efx_nic_t *);
211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
212 #if EFSYS_OPT_PHY_STATS
213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
215 #endif /* EFSYS_OPT_PHY_STATS */
217 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
218 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
219 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
220 efx_bist_result_t *, uint32_t *,
221 unsigned long *, size_t);
222 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
223 #endif /* EFSYS_OPT_BIST */
227 typedef struct efx_filter_ops_s {
228 efx_rc_t (*efo_init)(efx_nic_t *);
229 void (*efo_fini)(efx_nic_t *);
230 efx_rc_t (*efo_restore)(efx_nic_t *);
231 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
232 boolean_t may_replace);
233 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
234 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
235 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
236 boolean_t, boolean_t, boolean_t,
237 uint8_t const *, uint32_t);
240 extern __checkReturn efx_rc_t
241 efx_filter_reconfigure(
243 __in_ecount(6) uint8_t const *mac_addr,
244 __in boolean_t all_unicst,
245 __in boolean_t mulcst,
246 __in boolean_t all_mulcst,
247 __in boolean_t brdcst,
248 __in_ecount(6*count) uint8_t const *addrs,
249 __in uint32_t count);
251 #endif /* EFSYS_OPT_FILTER */
254 typedef struct efx_port_s {
255 efx_mac_type_t ep_mac_type;
256 uint32_t ep_phy_type;
259 uint8_t ep_mac_addr[6];
260 efx_link_mode_t ep_link_mode;
261 boolean_t ep_all_unicst;
263 boolean_t ep_all_mulcst;
265 unsigned int ep_fcntl;
266 boolean_t ep_fcntl_autoneg;
267 efx_oword_t ep_multicst_hash[2];
268 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
269 EFX_MAC_MULTICAST_LIST_MAX];
270 uint32_t ep_mulcst_addr_count;
271 #if EFSYS_OPT_LOOPBACK
272 efx_loopback_type_t ep_loopback_type;
273 efx_link_mode_t ep_loopback_link_mode;
274 #endif /* EFSYS_OPT_LOOPBACK */
275 #if EFSYS_OPT_PHY_FLAGS
276 uint32_t ep_phy_flags;
277 #endif /* EFSYS_OPT_PHY_FLAGS */
278 #if EFSYS_OPT_PHY_LED_CONTROL
279 efx_phy_led_mode_t ep_phy_led_mode;
280 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
281 efx_phy_media_type_t ep_fixed_port_type;
282 efx_phy_media_type_t ep_module_type;
283 uint32_t ep_adv_cap_mask;
284 uint32_t ep_lp_cap_mask;
285 uint32_t ep_default_adv_cap_mask;
286 uint32_t ep_phy_cap_mask;
287 boolean_t ep_mac_drain;
288 boolean_t ep_mac_stats_pending;
290 efx_bist_type_t ep_current_bist;
292 const efx_mac_ops_t *ep_emop;
293 const efx_phy_ops_t *ep_epop;
296 typedef struct efx_mon_ops_s {
297 #if EFSYS_OPT_MON_STATS
298 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
299 efx_mon_stat_value_t *);
300 #endif /* EFSYS_OPT_MON_STATS */
303 typedef struct efx_mon_s {
304 efx_mon_type_t em_type;
305 const efx_mon_ops_t *em_emop;
308 typedef struct efx_intr_ops_s {
309 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
310 void (*eio_enable)(efx_nic_t *);
311 void (*eio_disable)(efx_nic_t *);
312 void (*eio_disable_unlocked)(efx_nic_t *);
313 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
314 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
315 void (*eio_status_message)(efx_nic_t *, unsigned int,
317 void (*eio_fatal)(efx_nic_t *);
318 void (*eio_fini)(efx_nic_t *);
321 typedef struct efx_intr_s {
322 const efx_intr_ops_t *ei_eiop;
323 efsys_mem_t *ei_esmp;
324 efx_intr_type_t ei_type;
325 unsigned int ei_level;
328 typedef struct efx_nic_ops_s {
329 efx_rc_t (*eno_probe)(efx_nic_t *);
330 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
331 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
332 efx_rc_t (*eno_reset)(efx_nic_t *);
333 efx_rc_t (*eno_init)(efx_nic_t *);
334 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
335 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
336 uint32_t *, size_t *);
338 efx_rc_t (*eno_register_test)(efx_nic_t *);
339 #endif /* EFSYS_OPT_DIAG */
340 void (*eno_fini)(efx_nic_t *);
341 void (*eno_unprobe)(efx_nic_t *);
344 #ifndef EFX_TXQ_LIMIT_TARGET
345 #define EFX_TXQ_LIMIT_TARGET 259
347 #ifndef EFX_RXQ_LIMIT_TARGET
348 #define EFX_RXQ_LIMIT_TARGET 512
350 #ifndef EFX_TXQ_DC_SIZE
351 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
353 #ifndef EFX_RXQ_DC_SIZE
354 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
359 typedef struct siena_filter_spec_s {
362 uint32_t sfs_dmaq_id;
363 uint32_t sfs_dword[3];
364 } siena_filter_spec_t;
366 typedef enum siena_filter_type_e {
367 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
368 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
369 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
370 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
371 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
372 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
374 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
375 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
376 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
377 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
378 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
379 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
381 EFX_SIENA_FILTER_NTYPES
382 } siena_filter_type_t;
384 typedef enum siena_filter_tbl_id_e {
385 EFX_SIENA_FILTER_TBL_RX_IP = 0,
386 EFX_SIENA_FILTER_TBL_RX_MAC,
387 EFX_SIENA_FILTER_TBL_TX_IP,
388 EFX_SIENA_FILTER_TBL_TX_MAC,
389 EFX_SIENA_FILTER_NTBLS
390 } siena_filter_tbl_id_t;
392 typedef struct siena_filter_tbl_s {
393 int sft_size; /* number of entries */
394 int sft_used; /* active count */
395 uint32_t *sft_bitmap; /* active bitmap */
396 siena_filter_spec_t *sft_spec; /* array of saved specs */
397 } siena_filter_tbl_t;
399 typedef struct siena_filter_s {
400 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
401 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
404 typedef struct efx_filter_s {
406 siena_filter_t *ef_siena_filter;
407 #endif /* EFSYS_OPT_SIENA */
408 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
409 ef10_filter_table_t *ef_ef10_filter_table;
410 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
414 siena_filter_tbl_clear(
416 __in siena_filter_tbl_id_t tbl);
418 #endif /* EFSYS_OPT_FILTER */
422 typedef struct efx_mcdi_ops_s {
423 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
424 void (*emco_send_request)(efx_nic_t *, void *, size_t,
426 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
427 boolean_t (*emco_poll_response)(efx_nic_t *);
428 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
429 void (*emco_fini)(efx_nic_t *);
430 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
433 typedef struct efx_mcdi_s {
434 const efx_mcdi_ops_t *em_emcop;
435 const efx_mcdi_transport_t *em_emtp;
436 efx_mcdi_iface_t em_emip;
439 #endif /* EFSYS_OPT_MCDI */
442 typedef struct efx_nvram_ops_s {
444 efx_rc_t (*envo_test)(efx_nic_t *);
445 #endif /* EFSYS_OPT_DIAG */
446 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
448 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
449 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
450 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
451 unsigned int, caddr_t, size_t);
452 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
453 unsigned int, size_t);
454 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
455 unsigned int, caddr_t, size_t);
456 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
457 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
458 uint32_t *, uint16_t *);
459 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
461 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
464 #endif /* EFSYS_OPT_NVRAM */
467 typedef struct efx_vpd_ops_s {
468 efx_rc_t (*evpdo_init)(efx_nic_t *);
469 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
470 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
471 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
472 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
473 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
475 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
477 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
478 efx_vpd_value_t *, unsigned int *);
479 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
480 void (*evpdo_fini)(efx_nic_t *);
482 #endif /* EFSYS_OPT_VPD */
484 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
486 __checkReturn efx_rc_t
487 efx_mcdi_nvram_partitions(
489 __out_bcount(size) caddr_t data,
491 __out unsigned int *npartnp);
493 __checkReturn efx_rc_t
494 efx_mcdi_nvram_metadata(
497 __out uint32_t *subtypep,
498 __out_ecount(4) uint16_t version[4],
499 __out_bcount_opt(size) char *descp,
502 __checkReturn efx_rc_t
506 __out_opt size_t *sizep,
507 __out_opt uint32_t *addressp,
508 __out_opt uint32_t *erase_sizep,
509 __out_opt uint32_t *write_sizep);
511 __checkReturn efx_rc_t
512 efx_mcdi_nvram_update_start(
514 __in uint32_t partn);
516 __checkReturn efx_rc_t
520 __in uint32_t offset,
521 __out_bcount(size) caddr_t data,
525 __checkReturn efx_rc_t
526 efx_mcdi_nvram_erase(
529 __in uint32_t offset,
532 __checkReturn efx_rc_t
533 efx_mcdi_nvram_write(
536 __in uint32_t offset,
537 __out_bcount(size) caddr_t data,
540 __checkReturn efx_rc_t
541 efx_mcdi_nvram_update_finish(
544 __in boolean_t reboot,
545 __out_opt uint32_t *resultp);
549 __checkReturn efx_rc_t
552 __in uint32_t partn);
554 #endif /* EFSYS_OPT_DIAG */
556 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
558 #if EFSYS_OPT_LICENSING
560 typedef struct efx_lic_ops_s {
561 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
562 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
563 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
564 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
565 size_t *, uint8_t *);
566 efx_rc_t (*elo_find_start)
567 (efx_nic_t *, caddr_t, size_t, uint32_t *);
568 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
569 uint32_t, uint32_t *);
570 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
571 uint32_t, uint32_t *, uint32_t *);
572 boolean_t (*elo_validate_key)(efx_nic_t *,
574 efx_rc_t (*elo_read_key)(efx_nic_t *,
575 caddr_t, size_t, uint32_t, uint32_t,
576 caddr_t, size_t, uint32_t *);
577 efx_rc_t (*elo_write_key)(efx_nic_t *,
578 caddr_t, size_t, uint32_t,
579 caddr_t, uint32_t, uint32_t *);
580 efx_rc_t (*elo_delete_key)(efx_nic_t *,
581 caddr_t, size_t, uint32_t,
582 uint32_t, uint32_t, uint32_t *);
583 efx_rc_t (*elo_create_partition)(efx_nic_t *,
585 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
591 typedef struct efx_drv_cfg_s {
592 uint32_t edc_min_vi_count;
593 uint32_t edc_max_vi_count;
595 uint32_t edc_max_piobuf_count;
596 uint32_t edc_pio_alloc_size;
601 efx_family_t en_family;
602 uint32_t en_features;
603 efsys_identifier_t *en_esip;
604 efsys_lock_t *en_eslp;
605 efsys_bar_t *en_esbp;
606 unsigned int en_mod_flags;
607 unsigned int en_reset_flags;
608 efx_nic_cfg_t en_nic_cfg;
609 efx_drv_cfg_t en_drv_cfg;
613 uint32_t en_ev_qcount;
614 uint32_t en_rx_qcount;
615 uint32_t en_tx_qcount;
616 const efx_nic_ops_t *en_enop;
617 const efx_ev_ops_t *en_eevop;
618 const efx_tx_ops_t *en_etxop;
619 const efx_rx_ops_t *en_erxop;
621 efx_filter_t en_filter;
622 const efx_filter_ops_t *en_efop;
623 #endif /* EFSYS_OPT_FILTER */
626 #endif /* EFSYS_OPT_MCDI */
628 efx_nvram_type_t en_nvram_locked;
629 const efx_nvram_ops_t *en_envop;
630 #endif /* EFSYS_OPT_NVRAM */
632 const efx_vpd_ops_t *en_evpdop;
633 #endif /* EFSYS_OPT_VPD */
634 #if EFSYS_OPT_RX_SCALE
635 efx_rx_hash_support_t en_hash_support;
636 efx_rx_scale_support_t en_rss_support;
637 uint32_t en_rss_context;
638 #endif /* EFSYS_OPT_RX_SCALE */
639 uint32_t en_vport_id;
640 #if EFSYS_OPT_LICENSING
641 const efx_lic_ops_t *en_elop;
642 boolean_t en_licensing_supported;
647 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
648 unsigned int enu_partn_mask;
649 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
652 size_t enu_svpd_length;
653 #endif /* EFSYS_OPT_VPD */
656 #endif /* EFSYS_OPT_SIENA */
659 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
667 size_t ena_svpd_length;
668 #endif /* EFSYS_OPT_VPD */
669 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
670 uint32_t ena_piobuf_count;
671 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
672 uint32_t ena_pio_write_vi_base;
673 /* Memory BAR mapping regions */
674 uint32_t ena_uc_mem_map_offset;
675 size_t ena_uc_mem_map_size;
676 uint32_t ena_wc_mem_map_offset;
677 size_t ena_wc_mem_map_size;
680 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
684 #define EFX_NIC_MAGIC 0x02121996
686 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
687 const efx_ev_callbacks_t *, void *);
689 typedef struct efx_evq_rxq_state_s {
690 unsigned int eers_rx_read_ptr;
691 unsigned int eers_rx_mask;
692 } efx_evq_rxq_state_t;
697 unsigned int ee_index;
698 unsigned int ee_mask;
699 efsys_mem_t *ee_esmp;
701 uint32_t ee_stat[EV_NQSTATS];
702 #endif /* EFSYS_OPT_QSTATS */
704 efx_ev_handler_t ee_rx;
705 efx_ev_handler_t ee_tx;
706 efx_ev_handler_t ee_driver;
707 efx_ev_handler_t ee_global;
708 efx_ev_handler_t ee_drv_gen;
710 efx_ev_handler_t ee_mcdi;
711 #endif /* EFSYS_OPT_MCDI */
713 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
716 #define EFX_EVQ_MAGIC 0x08081997
718 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
724 unsigned int er_index;
725 unsigned int er_label;
726 unsigned int er_mask;
727 efsys_mem_t *er_esmp;
730 #define EFX_RXQ_MAGIC 0x15022005
735 unsigned int et_index;
736 unsigned int et_mask;
737 efsys_mem_t *et_esmp;
738 #if EFSYS_OPT_HUNTINGTON
739 uint32_t et_pio_bufnum;
740 uint32_t et_pio_blknum;
741 uint32_t et_pio_write_offset;
742 uint32_t et_pio_offset;
746 uint32_t et_stat[TX_NQSTATS];
747 #endif /* EFSYS_OPT_QSTATS */
750 #define EFX_TXQ_MAGIC 0x05092005
752 #define EFX_MAC_ADDR_COPY(_dst, _src) \
754 (_dst)[0] = (_src)[0]; \
755 (_dst)[1] = (_src)[1]; \
756 (_dst)[2] = (_src)[2]; \
757 (_dst)[3] = (_src)[3]; \
758 (_dst)[4] = (_src)[4]; \
759 (_dst)[5] = (_src)[5]; \
760 _NOTE(CONSTANTCONDITION) \
763 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
765 uint16_t *_d = (uint16_t *)(_dst); \
769 _NOTE(CONSTANTCONDITION) \
772 #if EFSYS_OPT_CHECK_REG
773 #define EFX_CHECK_REG(_enp, _reg) \
775 const char *name = #_reg; \
776 char min = name[4]; \
777 char max = name[5]; \
780 switch ((_enp)->en_family) { \
781 case EFX_FAMILY_SIENA: \
785 case EFX_FAMILY_HUNTINGTON: \
789 case EFX_FAMILY_MEDFORD: \
798 EFSYS_ASSERT3S(rev, >=, min); \
799 EFSYS_ASSERT3S(rev, <=, max); \
801 _NOTE(CONSTANTCONDITION) \
804 #define EFX_CHECK_REG(_enp, _reg) do { \
805 _NOTE(CONSTANTCONDITION) \
809 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
811 EFX_CHECK_REG((_enp), (_reg)); \
812 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
814 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
815 uint32_t, _reg ## _OFST, \
816 uint32_t, (_edp)->ed_u32[0]); \
817 _NOTE(CONSTANTCONDITION) \
820 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
822 EFX_CHECK_REG((_enp), (_reg)); \
823 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
824 uint32_t, _reg ## _OFST, \
825 uint32_t, (_edp)->ed_u32[0]); \
826 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
828 _NOTE(CONSTANTCONDITION) \
831 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
833 EFX_CHECK_REG((_enp), (_reg)); \
834 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
836 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
837 uint32_t, _reg ## _OFST, \
838 uint32_t, (_eqp)->eq_u32[1], \
839 uint32_t, (_eqp)->eq_u32[0]); \
840 _NOTE(CONSTANTCONDITION) \
843 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
845 EFX_CHECK_REG((_enp), (_reg)); \
846 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
847 uint32_t, _reg ## _OFST, \
848 uint32_t, (_eqp)->eq_u32[1], \
849 uint32_t, (_eqp)->eq_u32[0]); \
850 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
852 _NOTE(CONSTANTCONDITION) \
855 #define EFX_BAR_READO(_enp, _reg, _eop) \
857 EFX_CHECK_REG((_enp), (_reg)); \
858 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
860 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
861 uint32_t, _reg ## _OFST, \
862 uint32_t, (_eop)->eo_u32[3], \
863 uint32_t, (_eop)->eo_u32[2], \
864 uint32_t, (_eop)->eo_u32[1], \
865 uint32_t, (_eop)->eo_u32[0]); \
866 _NOTE(CONSTANTCONDITION) \
869 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
871 EFX_CHECK_REG((_enp), (_reg)); \
872 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
873 uint32_t, _reg ## _OFST, \
874 uint32_t, (_eop)->eo_u32[3], \
875 uint32_t, (_eop)->eo_u32[2], \
876 uint32_t, (_eop)->eo_u32[1], \
877 uint32_t, (_eop)->eo_u32[0]); \
878 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
880 _NOTE(CONSTANTCONDITION) \
883 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
885 EFX_CHECK_REG((_enp), (_reg)); \
886 EFSYS_BAR_READD((_enp)->en_esbp, \
887 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
889 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
890 uint32_t, (_index), \
891 uint32_t, _reg ## _OFST, \
892 uint32_t, (_edp)->ed_u32[0]); \
893 _NOTE(CONSTANTCONDITION) \
896 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
898 EFX_CHECK_REG((_enp), (_reg)); \
899 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
900 uint32_t, (_index), \
901 uint32_t, _reg ## _OFST, \
902 uint32_t, (_edp)->ed_u32[0]); \
903 EFSYS_BAR_WRITED((_enp)->en_esbp, \
904 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
906 _NOTE(CONSTANTCONDITION) \
909 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
911 EFX_CHECK_REG((_enp), (_reg)); \
912 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
913 uint32_t, (_index), \
914 uint32_t, _reg ## _OFST, \
915 uint32_t, (_edp)->ed_u32[0]); \
916 EFSYS_BAR_WRITED((_enp)->en_esbp, \
918 (2 * sizeof (efx_dword_t)) + \
919 ((_index) * _reg ## _STEP)), \
921 _NOTE(CONSTANTCONDITION) \
924 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
926 EFX_CHECK_REG((_enp), (_reg)); \
927 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
928 uint32_t, (_index), \
929 uint32_t, _reg ## _OFST, \
930 uint32_t, (_edp)->ed_u32[0]); \
931 EFSYS_BAR_WRITED((_enp)->en_esbp, \
933 (3 * sizeof (efx_dword_t)) + \
934 ((_index) * _reg ## _STEP)), \
936 _NOTE(CONSTANTCONDITION) \
939 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
941 EFX_CHECK_REG((_enp), (_reg)); \
942 EFSYS_BAR_READQ((_enp)->en_esbp, \
943 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
945 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
946 uint32_t, (_index), \
947 uint32_t, _reg ## _OFST, \
948 uint32_t, (_eqp)->eq_u32[1], \
949 uint32_t, (_eqp)->eq_u32[0]); \
950 _NOTE(CONSTANTCONDITION) \
953 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
955 EFX_CHECK_REG((_enp), (_reg)); \
956 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
957 uint32_t, (_index), \
958 uint32_t, _reg ## _OFST, \
959 uint32_t, (_eqp)->eq_u32[1], \
960 uint32_t, (_eqp)->eq_u32[0]); \
961 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
962 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
964 _NOTE(CONSTANTCONDITION) \
967 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
969 EFX_CHECK_REG((_enp), (_reg)); \
970 EFSYS_BAR_READO((_enp)->en_esbp, \
971 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
973 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
974 uint32_t, (_index), \
975 uint32_t, _reg ## _OFST, \
976 uint32_t, (_eop)->eo_u32[3], \
977 uint32_t, (_eop)->eo_u32[2], \
978 uint32_t, (_eop)->eo_u32[1], \
979 uint32_t, (_eop)->eo_u32[0]); \
980 _NOTE(CONSTANTCONDITION) \
983 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
985 EFX_CHECK_REG((_enp), (_reg)); \
986 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
987 uint32_t, (_index), \
988 uint32_t, _reg ## _OFST, \
989 uint32_t, (_eop)->eo_u32[3], \
990 uint32_t, (_eop)->eo_u32[2], \
991 uint32_t, (_eop)->eo_u32[1], \
992 uint32_t, (_eop)->eo_u32[0]); \
993 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
994 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
996 _NOTE(CONSTANTCONDITION) \
1000 * Allow drivers to perform optimised 128-bit doorbell writes.
1001 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1002 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1003 * the need for locking in the host, and are the only ones known to be safe to
1004 * use 128-bites write with.
1006 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1008 EFX_CHECK_REG((_enp), (_reg)); \
1009 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1012 uint32_t, (_index), \
1013 uint32_t, _reg ## _OFST, \
1014 uint32_t, (_eop)->eo_u32[3], \
1015 uint32_t, (_eop)->eo_u32[2], \
1016 uint32_t, (_eop)->eo_u32[1], \
1017 uint32_t, (_eop)->eo_u32[0]); \
1018 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1019 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1021 _NOTE(CONSTANTCONDITION) \
1024 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1026 unsigned int _new = (_wptr); \
1027 unsigned int _old = (_owptr); \
1029 if ((_new) >= (_old)) \
1030 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1031 (_old) * sizeof (efx_desc_t), \
1032 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1035 * It is cheaper to sync entire map than sync \
1036 * two parts especially when offset/size are \
1037 * ignored and entire map is synced in any case.\
1039 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1041 (_entries) * sizeof (efx_desc_t)); \
1042 _NOTE(CONSTANTCONDITION) \
1045 extern __checkReturn efx_rc_t
1047 __in efx_nic_t *enp);
1049 extern __checkReturn efx_rc_t
1051 __in efx_nic_t *enp);
1054 efx_mac_multicast_hash_compute(
1055 __in_ecount(6*count) uint8_t const *addrs,
1057 __out efx_oword_t *hash_low,
1058 __out efx_oword_t *hash_high);
1060 extern __checkReturn efx_rc_t
1062 __in efx_nic_t *enp);
1066 __in efx_nic_t *enp);
1070 /* VPD utility functions */
1072 extern __checkReturn efx_rc_t
1073 efx_vpd_hunk_length(
1074 __in_bcount(size) caddr_t data,
1076 __out size_t *lengthp);
1078 extern __checkReturn efx_rc_t
1079 efx_vpd_hunk_verify(
1080 __in_bcount(size) caddr_t data,
1082 __out_opt boolean_t *cksummedp);
1084 extern __checkReturn efx_rc_t
1085 efx_vpd_hunk_reinit(
1086 __in_bcount(size) caddr_t data,
1088 __in boolean_t wantpid);
1090 extern __checkReturn efx_rc_t
1092 __in_bcount(size) caddr_t data,
1094 __in efx_vpd_tag_t tag,
1095 __in efx_vpd_keyword_t keyword,
1096 __out unsigned int *payloadp,
1097 __out uint8_t *paylenp);
1099 extern __checkReturn efx_rc_t
1101 __in_bcount(size) caddr_t data,
1103 __out efx_vpd_tag_t *tagp,
1104 __out efx_vpd_keyword_t *keyword,
1105 __out_opt unsigned int *payloadp,
1106 __out_opt uint8_t *paylenp,
1107 __inout unsigned int *contp);
1109 extern __checkReturn efx_rc_t
1111 __in_bcount(size) caddr_t data,
1113 __in efx_vpd_value_t *evvp);
1115 #endif /* EFSYS_OPT_VPD */
1119 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1121 typedef struct efx_register_set_s {
1122 unsigned int address;
1126 } efx_register_set_t;
1128 extern __checkReturn efx_rc_t
1129 efx_nic_test_registers(
1130 __in efx_nic_t *enp,
1131 __in efx_register_set_t *rsp,
1134 extern __checkReturn efx_rc_t
1135 efx_nic_test_tables(
1136 __in efx_nic_t *enp,
1137 __in efx_register_set_t *rsp,
1138 __in efx_pattern_type_t pattern,
1141 #endif /* EFSYS_OPT_DIAG */
1145 extern __checkReturn efx_rc_t
1146 efx_mcdi_set_workaround(
1147 __in efx_nic_t *enp,
1149 __in boolean_t enabled,
1150 __out_opt uint32_t *flagsp);
1152 extern __checkReturn efx_rc_t
1153 efx_mcdi_get_workarounds(
1154 __in efx_nic_t *enp,
1155 __out_opt uint32_t *implementedp,
1156 __out_opt uint32_t *enabledp);
1158 #endif /* EFSYS_OPT_MCDI */
1160 #if EFSYS_OPT_MAC_STATS
1163 * Closed range of stats (i.e. the first and the last are included).
1164 * The last must be greater or equal (if the range is one item only) to
1167 struct efx_mac_stats_range {
1168 efx_mac_stat_t first;
1169 efx_mac_stat_t last;
1173 efx_mac_stats_mask_add_ranges(
1174 __inout_bcount(mask_size) uint32_t *maskp,
1175 __in size_t mask_size,
1176 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1177 __in unsigned int rng_count);
1179 #endif /* EFSYS_OPT_MAC_STATS */
1185 #endif /* _SYS_EFX_IMPL_H */