sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efx.h"
  37 #include "efx_regs.h"
  38 #include "efx_regs_ef10.h"
  39
  40 /* FIXME: Add definition for driver generated software events */
  41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  43 #endif
  44
  45
  46 #if EFSYS_OPT_SIENA
  47 #include "siena_impl.h"
  48 #endif  /* EFSYS_OPT_SIENA */
  49
  50 #if EFSYS_OPT_HUNTINGTON
  51 #include "hunt_impl.h"
  52 #endif  /* EFSYS_OPT_HUNTINGTON */
  53
  54 #if EFSYS_OPT_MEDFORD
  55 #include "medford_impl.h"
  56 #endif  /* EFSYS_OPT_MEDFORD */
  57
  58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  59 #include "ef10_impl.h"
  60 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  61
  62 #ifdef  __cplusplus
  63 extern "C" {
  64 #endif
  65
  66 #define EFX_MOD_MCDI            0x00000001
  67 #define EFX_MOD_PROBE           0x00000002
  68 #define EFX_MOD_NVRAM           0x00000004
  69 #define EFX_MOD_VPD             0x00000008
  70 #define EFX_MOD_NIC             0x00000010
  71 #define EFX_MOD_INTR            0x00000020
  72 #define EFX_MOD_EV              0x00000040
  73 #define EFX_MOD_RX              0x00000080
  74 #define EFX_MOD_TX              0x00000100
  75 #define EFX_MOD_PORT            0x00000200
  76 #define EFX_MOD_MON             0x00000400
  77 #define EFX_MOD_WOL             0x00000800
  78 #define EFX_MOD_FILTER          0x00001000
  79 #define EFX_MOD_LIC             0x00002000
  80
  81 #define EFX_RESET_PHY           0x00000001
  82 #define EFX_RESET_RXQ_ERR       0x00000002
  83 #define EFX_RESET_TXQ_ERR       0x00000004
  84
  85 typedef enum efx_mac_type_e {
  86         EFX_MAC_INVALID = 0,
  87         EFX_MAC_SIENA,
  88         EFX_MAC_HUNTINGTON,
  89         EFX_MAC_MEDFORD,
  90         EFX_MAC_NTYPES
  91 } efx_mac_type_t;
  92
  93 typedef struct efx_ev_ops_s {
  94         efx_rc_t        (*eevo_init)(efx_nic_t *);
  95         void            (*eevo_fini)(efx_nic_t *);
  96         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  97                                           efsys_mem_t *, size_t, uint32_t,
  98                                           efx_evq_t *);
  99         void            (*eevo_qdestroy)(efx_evq_t *);
 100         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 101         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 102         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 103 #if EFSYS_OPT_QSTATS
 104         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 105 #endif
 106 } efx_ev_ops_t;
 107
 108 typedef struct efx_tx_ops_s {
 109         efx_rc_t        (*etxo_init)(efx_nic_t *);
 110         void            (*etxo_fini)(efx_nic_t *);
 111         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 112                                         unsigned int, unsigned int,
 113                                         efsys_mem_t *, size_t,
 114                                         uint32_t, uint16_t,
 115                                         efx_evq_t *, efx_txq_t *,
 116                                         unsigned int *);
 117         void            (*etxo_qdestroy)(efx_txq_t *);
 118         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 119                                       unsigned int, unsigned int,
 120                                       unsigned int *);
 121         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 122         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 123         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 124         void            (*etxo_qenable)(efx_txq_t *);
 125         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 126         void            (*etxo_qpio_disable)(efx_txq_t *);
 127         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 128                                            size_t);
 129         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 130                                            unsigned int *);
 131         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 132                                       unsigned int, unsigned int,
 133                                       unsigned int *);
 134         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 135                                                 size_t, boolean_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint8_t,
 139                                                 efx_desc_t *);
 140         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 141                                                 uint32_t, uint16_t,
 142                                                 efx_desc_t *, int);
 143         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 144                                                 efx_desc_t *);
 145 #if EFSYS_OPT_QSTATS
 146         void            (*etxo_qstats_update)(efx_txq_t *,
 147                                               efsys_stat_t *);
 148 #endif
 149 } efx_tx_ops_t;
 150
 151 typedef struct efx_rx_ops_s {
 152         efx_rc_t        (*erxo_init)(efx_nic_t *);
 153         void            (*erxo_fini)(efx_nic_t *);
 154 #if EFSYS_OPT_RX_SCATTER
 155         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 156 #endif
 157 #if EFSYS_OPT_RX_SCALE
 158         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 159                                                efx_rx_hash_type_t, boolean_t);
 160         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 161         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 162                                               size_t);
 163         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 164                                             uint8_t *);
 165 #endif /* EFSYS_OPT_RX_SCALE */
 166         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 167                                               uint16_t *);
 168         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 169                                       unsigned int, unsigned int,
 170                                       unsigned int);
 171         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 172         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 173         void            (*erxo_qenable)(efx_rxq_t *);
 174         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 175                                         unsigned int, efx_rxq_type_t,
 176                                         efsys_mem_t *, size_t, uint32_t,
 177                                         efx_evq_t *, efx_rxq_t *);
 178         void            (*erxo_qdestroy)(efx_rxq_t *);
 179 } efx_rx_ops_t;
 180
 181 typedef struct efx_mac_ops_s {
 182         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 183         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 184         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 185         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 186         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 187         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 189                                                       efx_rxq_t *, boolean_t);
 190         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 191 #if EFSYS_OPT_LOOPBACK
 192         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 193                                             efx_loopback_type_t);
 194 #endif  /* EFSYS_OPT_LOOPBACK */
 195 #if EFSYS_OPT_MAC_STATS
 196         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 197         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 198                                               uint16_t, boolean_t);
 199         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 200                                             efsys_stat_t *, uint32_t *);
 201 #endif  /* EFSYS_OPT_MAC_STATS */
 202 } efx_mac_ops_t;
 203
 204 typedef struct efx_phy_ops_s {
 205         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 206         efx_rc_t        (*epo_reset)(efx_nic_t *);
 207         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 208         efx_rc_t        (*epo_verify)(efx_nic_t *);
 209         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 210 #if EFSYS_OPT_PHY_STATS
 211         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             uint32_t *);
 213 #endif  /* EFSYS_OPT_PHY_STATS */
 214 #if EFSYS_OPT_BIST
 215         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 216         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 217         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 218                                          efx_bist_result_t *, uint32_t *,
 219                                          unsigned long *, size_t);
 220         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 221 #endif  /* EFSYS_OPT_BIST */
 222 } efx_phy_ops_t;
 223
 224 #if EFSYS_OPT_FILTER
 225 typedef struct efx_filter_ops_s {
 226         efx_rc_t        (*efo_init)(efx_nic_t *);
 227         void            (*efo_fini)(efx_nic_t *);
 228         efx_rc_t        (*efo_restore)(efx_nic_t *);
 229         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 230                                    boolean_t may_replace);
 231         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 232         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 233         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 234                                    boolean_t, boolean_t, boolean_t,
 235                                    uint8_t const *, uint32_t);
 236 } efx_filter_ops_t;
 237
 238 extern  __checkReturn   efx_rc_t
 239 efx_filter_reconfigure(
 240         __in                            efx_nic_t *enp,
 241         __in_ecount(6)                  uint8_t const *mac_addr,
 242         __in                            boolean_t all_unicst,
 243         __in                            boolean_t mulcst,
 244         __in                            boolean_t all_mulcst,
 245         __in                            boolean_t brdcst,
 246         __in_ecount(6*count)            uint8_t const *addrs,
 247         __in                            uint32_t count);
 248
 249 #endif /* EFSYS_OPT_FILTER */
 250
 251
 252 typedef struct efx_port_s {
 253         efx_mac_type_t          ep_mac_type;
 254         uint32_t                ep_phy_type;
 255         uint8_t                 ep_port;
 256         uint32_t                ep_mac_pdu;
 257         uint8_t                 ep_mac_addr[6];
 258         efx_link_mode_t         ep_link_mode;
 259         boolean_t               ep_all_unicst;
 260         boolean_t               ep_mulcst;
 261         boolean_t               ep_all_mulcst;
 262         boolean_t               ep_brdcst;
 263         unsigned int            ep_fcntl;
 264         boolean_t               ep_fcntl_autoneg;
 265         efx_oword_t             ep_multicst_hash[2];
 266         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 267                                                     EFX_MAC_MULTICAST_LIST_MAX];
 268         uint32_t                ep_mulcst_addr_count;
 269 #if EFSYS_OPT_LOOPBACK
 270         efx_loopback_type_t     ep_loopback_type;
 271         efx_link_mode_t         ep_loopback_link_mode;
 272 #endif  /* EFSYS_OPT_LOOPBACK */
 273 #if EFSYS_OPT_PHY_FLAGS
 274         uint32_t                ep_phy_flags;
 275 #endif  /* EFSYS_OPT_PHY_FLAGS */
 276 #if EFSYS_OPT_PHY_LED_CONTROL
 277         efx_phy_led_mode_t      ep_phy_led_mode;
 278 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 279         efx_phy_media_type_t    ep_fixed_port_type;
 280         efx_phy_media_type_t    ep_module_type;
 281         uint32_t                ep_adv_cap_mask;
 282         uint32_t                ep_lp_cap_mask;
 283         uint32_t                ep_default_adv_cap_mask;
 284         uint32_t                ep_phy_cap_mask;
 285         boolean_t               ep_mac_drain;
 286         boolean_t               ep_mac_stats_pending;
 287 #if EFSYS_OPT_BIST
 288         efx_bist_type_t         ep_current_bist;
 289 #endif
 290         const efx_mac_ops_t     *ep_emop;
 291         const efx_phy_ops_t     *ep_epop;
 292 } efx_port_t;
 293
 294 typedef struct efx_mon_ops_s {
 295 #if EFSYS_OPT_MON_STATS
 296         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 297                                             efx_mon_stat_value_t *);
 298 #endif  /* EFSYS_OPT_MON_STATS */
 299 } efx_mon_ops_t;
 300
 301 typedef struct efx_mon_s {
 302         efx_mon_type_t          em_type;
 303         const efx_mon_ops_t     *em_emop;
 304 } efx_mon_t;
 305
 306 typedef struct efx_intr_ops_s {
 307         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 308         void            (*eio_enable)(efx_nic_t *);
 309         void            (*eio_disable)(efx_nic_t *);
 310         void            (*eio_disable_unlocked)(efx_nic_t *);
 311         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 312         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 313         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 314                                  boolean_t *);
 315         void            (*eio_fatal)(efx_nic_t *);
 316         void            (*eio_fini)(efx_nic_t *);
 317 } efx_intr_ops_t;
 318
 319 typedef struct efx_intr_s {
 320         const efx_intr_ops_t    *ei_eiop;
 321         efsys_mem_t             *ei_esmp;
 322         efx_intr_type_t         ei_type;
 323         unsigned int            ei_level;
 324 } efx_intr_t;
 325
 326 typedef struct efx_nic_ops_s {
 327         efx_rc_t        (*eno_probe)(efx_nic_t *);
 328         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 329         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 330         efx_rc_t        (*eno_reset)(efx_nic_t *);
 331         efx_rc_t        (*eno_init)(efx_nic_t *);
 332         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 333         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 334                                         uint32_t *, size_t *);
 335 #if EFSYS_OPT_DIAG
 336         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 337 #endif  /* EFSYS_OPT_DIAG */
 338         void            (*eno_fini)(efx_nic_t *);
 339         void            (*eno_unprobe)(efx_nic_t *);
 340 } efx_nic_ops_t;
 341
 342 #ifndef EFX_TXQ_LIMIT_TARGET
 343 #define EFX_TXQ_LIMIT_TARGET 259
 344 #endif
 345 #ifndef EFX_RXQ_LIMIT_TARGET
 346 #define EFX_RXQ_LIMIT_TARGET 512
 347 #endif
 348 #ifndef EFX_TXQ_DC_SIZE
 349 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 350 #endif
 351 #ifndef EFX_RXQ_DC_SIZE
 352 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 353 #endif
 354
 355 #if EFSYS_OPT_FILTER
 356
 357 typedef struct siena_filter_spec_s {
 358         uint8_t         sfs_type;
 359         uint32_t        sfs_flags;
 360         uint32_t        sfs_dmaq_id;
 361         uint32_t        sfs_dword[3];
 362 } siena_filter_spec_t;
 363
 364 typedef enum siena_filter_type_e {
 365         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 366         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 367         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 368         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 369         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 370         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 371
 372         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 373         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 374         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 375         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 376         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 377         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 378
 379         EFX_SIENA_FILTER_NTYPES
 380 } siena_filter_type_t;
 381
 382 typedef enum siena_filter_tbl_id_e {
 383         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 384         EFX_SIENA_FILTER_TBL_RX_MAC,
 385         EFX_SIENA_FILTER_TBL_TX_IP,
 386         EFX_SIENA_FILTER_TBL_TX_MAC,
 387         EFX_SIENA_FILTER_NTBLS
 388 } siena_filter_tbl_id_t;
 389
 390 typedef struct siena_filter_tbl_s {
 391         int                     sft_size;       /* number of entries */
 392         int                     sft_used;       /* active count */
 393         uint32_t                *sft_bitmap;    /* active bitmap */
 394         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 395 } siena_filter_tbl_t;
 396
 397 typedef struct siena_filter_s {
 398         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 399         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 400 } siena_filter_t;
 401
 402 typedef struct efx_filter_s {
 403 #if EFSYS_OPT_SIENA
 404         siena_filter_t          *ef_siena_filter;
 405 #endif /* EFSYS_OPT_SIENA */
 406 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 407         ef10_filter_table_t     *ef_ef10_filter_table;
 408 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 409 } efx_filter_t;
 410
 411 extern                  void
 412 siena_filter_tbl_clear(
 413         __in            efx_nic_t *enp,
 414         __in            siena_filter_tbl_id_t tbl);
 415
 416 #endif  /* EFSYS_OPT_FILTER */
 417
 418 #if EFSYS_OPT_MCDI
 419
 420 typedef struct efx_mcdi_ops_s {
 421         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 422         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 423                                         void *, size_t);
 424         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 425         boolean_t       (*emco_poll_response)(efx_nic_t *);
 426         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 427         void            (*emco_fini)(efx_nic_t *);
 428         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 429 } efx_mcdi_ops_t;
 430
 431 typedef struct efx_mcdi_s {
 432         const efx_mcdi_ops_t            *em_emcop;
 433         const efx_mcdi_transport_t      *em_emtp;
 434         efx_mcdi_iface_t                em_emip;
 435 } efx_mcdi_t;
 436
 437 #endif /* EFSYS_OPT_MCDI */
 438
 439 #if EFSYS_OPT_NVRAM
 440 typedef struct efx_nvram_ops_s {
 441 #if EFSYS_OPT_DIAG
 442         efx_rc_t        (*envo_test)(efx_nic_t *);
 443 #endif  /* EFSYS_OPT_DIAG */
 444         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 445                                             uint32_t *);
 446         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 447         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 448         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 449                                             unsigned int, caddr_t, size_t);
 450         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 451                                             unsigned int, size_t);
 452         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 453                                             unsigned int, caddr_t, size_t);
 454         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 455         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 456                                             uint32_t *, uint16_t *);
 457         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 458                                             uint16_t *);
 459         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 460                                             caddr_t, size_t);
 461 } efx_nvram_ops_t;
 462 #endif /* EFSYS_OPT_NVRAM */
 463
 464 #if EFSYS_OPT_VPD
 465 typedef struct efx_vpd_ops_s {
 466         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 467         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 468         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 469         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 470         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 471         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 472                                         efx_vpd_value_t *);
 473         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 474                                         efx_vpd_value_t *);
 475         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 476                                         efx_vpd_value_t *, unsigned int *);
 477         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 478         void            (*evpdo_fini)(efx_nic_t *);
 479 } efx_vpd_ops_t;
 480 #endif  /* EFSYS_OPT_VPD */
 481
 482 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 483
 484         __checkReturn           efx_rc_t
 485 efx_mcdi_nvram_partitions(
 486         __in                    efx_nic_t *enp,
 487         __out_bcount(size)      caddr_t data,
 488         __in                    size_t size,
 489         __out                   unsigned int *npartnp);
 490
 491         __checkReturn           efx_rc_t
 492 efx_mcdi_nvram_metadata(
 493         __in                    efx_nic_t *enp,
 494         __in                    uint32_t partn,
 495         __out                   uint32_t *subtypep,
 496         __out_ecount(4)         uint16_t version[4],
 497         __out_bcount_opt(size)  char *descp,
 498         __in                    size_t size);
 499
 500         __checkReturn           efx_rc_t
 501 efx_mcdi_nvram_info(
 502         __in                    efx_nic_t *enp,
 503         __in                    uint32_t partn,
 504         __out_opt               size_t *sizep,
 505         __out_opt               uint32_t *addressp,
 506         __out_opt               uint32_t *erase_sizep,
 507         __out_opt               uint32_t *write_sizep);
 508
 509         __checkReturn           efx_rc_t
 510 efx_mcdi_nvram_update_start(
 511         __in                    efx_nic_t *enp,
 512         __in                    uint32_t partn);
 513
 514         __checkReturn           efx_rc_t
 515 efx_mcdi_nvram_read(
 516         __in                    efx_nic_t *enp,
 517         __in                    uint32_t partn,
 518         __in                    uint32_t offset,
 519         __out_bcount(size)      caddr_t data,
 520         __in                    size_t size,
 521         __in                    uint32_t mode);
 522
 523         __checkReturn           efx_rc_t
 524 efx_mcdi_nvram_erase(
 525         __in                    efx_nic_t *enp,
 526         __in                    uint32_t partn,
 527         __in                    uint32_t offset,
 528         __in                    size_t size);
 529
 530         __checkReturn           efx_rc_t
 531 efx_mcdi_nvram_write(
 532         __in                    efx_nic_t *enp,
 533         __in                    uint32_t partn,
 534         __in                    uint32_t offset,
 535         __out_bcount(size)      caddr_t data,
 536         __in                    size_t size);
 537
 538         __checkReturn           efx_rc_t
 539 efx_mcdi_nvram_update_finish(
 540         __in                    efx_nic_t *enp,
 541         __in                    uint32_t partn,
 542         __in                    boolean_t reboot);
 543
 544 #if EFSYS_OPT_DIAG
 545
 546         __checkReturn           efx_rc_t
 547 efx_mcdi_nvram_test(
 548         __in                    efx_nic_t *enp,
 549         __in                    uint32_t partn);
 550
 551 #endif  /* EFSYS_OPT_DIAG */
 552
 553 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 554
 555 #if EFSYS_OPT_LICENSING
 556
 557 typedef struct efx_lic_ops_s {
 558         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 559         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 560         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 561         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 562                                       size_t *, uint8_t *);
 563         efx_rc_t        (*elo_find_start)
 564                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 565         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 566                                 uint32_t , uint32_t *);
 567         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 568                                 uint32_t, uint32_t *, uint32_t *);
 569         boolean_t       (*elo_validate_key)(efx_nic_t *,
 570                                 caddr_t, uint32_t);
 571         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 572                                 caddr_t, size_t, uint32_t, uint32_t,
 573                                 caddr_t, size_t, uint32_t *);
 574         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 575                                 caddr_t, size_t, uint32_t,
 576                                 caddr_t, uint32_t, uint32_t *);
 577         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 578                                 caddr_t, size_t, uint32_t,
 579                                 uint32_t, uint32_t, uint32_t *);
 580         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 581                                 caddr_t, size_t);
 582         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 583                                 caddr_t, size_t);
 584 } efx_lic_ops_t;
 585
 586 #endif
 587
 588 typedef struct efx_drv_cfg_s {
 589         uint32_t                edc_min_vi_count;
 590         uint32_t                edc_max_vi_count;
 591
 592         uint32_t                edc_max_piobuf_count;
 593         uint32_t                edc_pio_alloc_size;
 594 } efx_drv_cfg_t;
 595
 596 struct efx_nic_s {
 597         uint32_t                en_magic;
 598         efx_family_t            en_family;
 599         uint32_t                en_features;
 600         efsys_identifier_t      *en_esip;
 601         efsys_lock_t            *en_eslp;
 602         efsys_bar_t             *en_esbp;
 603         unsigned int            en_mod_flags;
 604         unsigned int            en_reset_flags;
 605         efx_nic_cfg_t           en_nic_cfg;
 606         efx_drv_cfg_t           en_drv_cfg;
 607         efx_port_t              en_port;
 608         efx_mon_t               en_mon;
 609         efx_intr_t              en_intr;
 610         uint32_t                en_ev_qcount;
 611         uint32_t                en_rx_qcount;
 612         uint32_t                en_tx_qcount;
 613         const efx_nic_ops_t     *en_enop;
 614         const efx_ev_ops_t      *en_eevop;
 615         const efx_tx_ops_t      *en_etxop;
 616         const efx_rx_ops_t      *en_erxop;
 617 #if EFSYS_OPT_FILTER
 618         efx_filter_t            en_filter;
 619         const efx_filter_ops_t  *en_efop;
 620 #endif  /* EFSYS_OPT_FILTER */
 621 #if EFSYS_OPT_MCDI
 622         efx_mcdi_t              en_mcdi;
 623 #endif  /* EFSYS_OPT_MCDI */
 624 #if EFSYS_OPT_NVRAM
 625         efx_nvram_type_t        en_nvram_locked;
 626         const efx_nvram_ops_t   *en_envop;
 627 #endif  /* EFSYS_OPT_NVRAM */
 628 #if EFSYS_OPT_VPD
 629         const efx_vpd_ops_t     *en_evpdop;
 630 #endif  /* EFSYS_OPT_VPD */
 631 #if EFSYS_OPT_RX_SCALE
 632         efx_rx_hash_support_t   en_hash_support;
 633         efx_rx_scale_support_t  en_rss_support;
 634         uint32_t                en_rss_context;
 635 #endif  /* EFSYS_OPT_RX_SCALE */
 636         uint32_t                en_vport_id;
 637 #if EFSYS_OPT_LICENSING
 638         const efx_lic_ops_t     *en_elop;
 639         boolean_t               en_licensing_supported;
 640 #endif
 641         union {
 642 #if EFSYS_OPT_SIENA
 643                 struct {
 644 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 645                         unsigned int            enu_partn_mask;
 646 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 647 #if EFSYS_OPT_VPD
 648                         caddr_t                 enu_svpd;
 649                         size_t                  enu_svpd_length;
 650 #endif  /* EFSYS_OPT_VPD */
 651                         int                     enu_unused;
 652                 } siena;
 653 #endif  /* EFSYS_OPT_SIENA */
 654                 int     enu_unused;
 655         } en_u;
 656 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 657         union en_arch {
 658                 struct {
 659                         int                     ena_vi_base;
 660                         int                     ena_vi_count;
 661                         int                     ena_vi_shift;
 662 #if EFSYS_OPT_VPD
 663                         caddr_t                 ena_svpd;
 664                         size_t                  ena_svpd_length;
 665 #endif  /* EFSYS_OPT_VPD */
 666                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 667                         uint32_t                ena_piobuf_count;
 668                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 669                         uint32_t                ena_pio_write_vi_base;
 670                         /* Memory BAR mapping regions */
 671                         uint32_t                ena_uc_mem_map_offset;
 672                         size_t                  ena_uc_mem_map_size;
 673                         uint32_t                ena_wc_mem_map_offset;
 674                         size_t                  ena_wc_mem_map_size;
 675                 } ef10;
 676         } en_arch;
 677 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 678 };
 679
 680
 681 #define EFX_NIC_MAGIC   0x02121996
 682
 683 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 684     const efx_ev_callbacks_t *, void *);
 685
 686 typedef struct efx_evq_rxq_state_s {
 687         unsigned int                    eers_rx_read_ptr;
 688         unsigned int                    eers_rx_mask;
 689 } efx_evq_rxq_state_t;
 690
 691 struct efx_evq_s {
 692         uint32_t                        ee_magic;
 693         efx_nic_t                       *ee_enp;
 694         unsigned int                    ee_index;
 695         unsigned int                    ee_mask;
 696         efsys_mem_t                     *ee_esmp;
 697 #if EFSYS_OPT_QSTATS
 698         uint32_t                        ee_stat[EV_NQSTATS];
 699 #endif  /* EFSYS_OPT_QSTATS */
 700
 701         efx_ev_handler_t                ee_rx;
 702         efx_ev_handler_t                ee_tx;
 703         efx_ev_handler_t                ee_driver;
 704         efx_ev_handler_t                ee_global;
 705         efx_ev_handler_t                ee_drv_gen;
 706 #if EFSYS_OPT_MCDI
 707         efx_ev_handler_t                ee_mcdi;
 708 #endif  /* EFSYS_OPT_MCDI */
 709
 710         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 711 };
 712
 713 #define EFX_EVQ_MAGIC   0x08081997
 714
 715 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 716
 717 struct efx_rxq_s {
 718         uint32_t                        er_magic;
 719         efx_nic_t                       *er_enp;
 720         efx_evq_t                       *er_eep;
 721         unsigned int                    er_index;
 722         unsigned int                    er_label;
 723         unsigned int                    er_mask;
 724         efsys_mem_t                     *er_esmp;
 725 };
 726
 727 #define EFX_RXQ_MAGIC   0x15022005
 728
 729 struct efx_txq_s {
 730         uint32_t                        et_magic;
 731         efx_nic_t                       *et_enp;
 732         unsigned int                    et_index;
 733         unsigned int                    et_mask;
 734         efsys_mem_t                     *et_esmp;
 735 #if EFSYS_OPT_HUNTINGTON
 736         uint32_t                        et_pio_bufnum;
 737         uint32_t                        et_pio_blknum;
 738         uint32_t                        et_pio_write_offset;
 739         uint32_t                        et_pio_offset;
 740         size_t                          et_pio_size;
 741 #endif
 742 #if EFSYS_OPT_QSTATS
 743         uint32_t                        et_stat[TX_NQSTATS];
 744 #endif  /* EFSYS_OPT_QSTATS */
 745 };
 746
 747 #define EFX_TXQ_MAGIC   0x05092005
 748
 749 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 750         do {                                                            \
 751                 (_dst)[0] = (_src)[0];                                  \
 752                 (_dst)[1] = (_src)[1];                                  \
 753                 (_dst)[2] = (_src)[2];                                  \
 754                 (_dst)[3] = (_src)[3];                                  \
 755                 (_dst)[4] = (_src)[4];                                  \
 756                 (_dst)[5] = (_src)[5];                                  \
 757         _NOTE(CONSTANTCONDITION)                                        \
 758         } while (B_FALSE)
 759
 760 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 761         do {                                                            \
 762                 uint16_t *_d = (uint16_t *)(_dst);                      \
 763                 _d[0] = 0xffff;                                         \
 764                 _d[1] = 0xffff;                                         \
 765                 _d[2] = 0xffff;                                         \
 766         _NOTE(CONSTANTCONDITION)                                        \
 767         } while (B_FALSE)
 768
 769 #if EFSYS_OPT_CHECK_REG
 770 #define EFX_CHECK_REG(_enp, _reg)                                       \
 771         do {                                                            \
 772                 const char *name = #_reg;                               \
 773                 char min = name[4];                                     \
 774                 char max = name[5];                                     \
 775                 char rev;                                               \
 776                                                                         \
 777                 switch ((_enp)->en_family) {                            \
 778                 case EFX_FAMILY_SIENA:                                  \
 779                         rev = 'C';                                      \
 780                         break;                                          \
 781                                                                         \
 782                 case EFX_FAMILY_HUNTINGTON:                             \
 783                         rev = 'D';                                      \
 784                         break;                                          \
 785                                                                         \
 786                 case EFX_FAMILY_MEDFORD:                                \
 787                         rev = 'E';                                      \
 788                         break;                                          \
 789                                                                         \
 790                 default:                                                \
 791                         rev = '?';                                      \
 792                         break;                                          \
 793                 }                                                       \
 794                                                                         \
 795                 EFSYS_ASSERT3S(rev, >=, min);                           \
 796                 EFSYS_ASSERT3S(rev, <=, max);                           \
 797                                                                         \
 798         _NOTE(CONSTANTCONDITION)                                        \
 799         } while (B_FALSE)
 800 #else
 801 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 802         _NOTE(CONSTANTCONDITION)                                        \
 803         } while(B_FALSE)
 804 #endif
 805
 806 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 807         do {                                                            \
 808                 EFX_CHECK_REG((_enp), (_reg));                          \
 809                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 810                     (_edp), (_lock));                                   \
 811                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 812                     uint32_t, _reg ## _OFST,                            \
 813                     uint32_t, (_edp)->ed_u32[0]);                       \
 814         _NOTE(CONSTANTCONDITION)                                        \
 815         } while (B_FALSE)
 816
 817 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 818         do {                                                            \
 819                 EFX_CHECK_REG((_enp), (_reg));                          \
 820                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 821                     uint32_t, _reg ## _OFST,                            \
 822                     uint32_t, (_edp)->ed_u32[0]);                       \
 823                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 824                     (_edp), (_lock));                                   \
 825         _NOTE(CONSTANTCONDITION)                                        \
 826         } while (B_FALSE)
 827
 828 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 829         do {                                                            \
 830                 EFX_CHECK_REG((_enp), (_reg));                          \
 831                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 832                     (_eqp));                                            \
 833                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 834                     uint32_t, _reg ## _OFST,                            \
 835                     uint32_t, (_eqp)->eq_u32[1],                        \
 836                     uint32_t, (_eqp)->eq_u32[0]);                       \
 837         _NOTE(CONSTANTCONDITION)                                        \
 838         } while (B_FALSE)
 839
 840 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 841         do {                                                            \
 842                 EFX_CHECK_REG((_enp), (_reg));                          \
 843                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 844                     uint32_t, _reg ## _OFST,                            \
 845                     uint32_t, (_eqp)->eq_u32[1],                        \
 846                     uint32_t, (_eqp)->eq_u32[0]);                       \
 847                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 848                     (_eqp));                                            \
 849         _NOTE(CONSTANTCONDITION)                                        \
 850         } while (B_FALSE)
 851
 852 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 853         do {                                                            \
 854                 EFX_CHECK_REG((_enp), (_reg));                          \
 855                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 856                     (_eop), B_TRUE);                                    \
 857                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 858                     uint32_t, _reg ## _OFST,                            \
 859                     uint32_t, (_eop)->eo_u32[3],                        \
 860                     uint32_t, (_eop)->eo_u32[2],                        \
 861                     uint32_t, (_eop)->eo_u32[1],                        \
 862                     uint32_t, (_eop)->eo_u32[0]);                       \
 863         _NOTE(CONSTANTCONDITION)                                        \
 864         } while (B_FALSE)
 865
 866 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 867         do {                                                            \
 868                 EFX_CHECK_REG((_enp), (_reg));                          \
 869                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 870                     uint32_t, _reg ## _OFST,                            \
 871                     uint32_t, (_eop)->eo_u32[3],                        \
 872                     uint32_t, (_eop)->eo_u32[2],                        \
 873                     uint32_t, (_eop)->eo_u32[1],                        \
 874                     uint32_t, (_eop)->eo_u32[0]);                       \
 875                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 876                     (_eop), B_TRUE);                                    \
 877         _NOTE(CONSTANTCONDITION)                                        \
 878         } while (B_FALSE)
 879
 880 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 881         do {                                                            \
 882                 EFX_CHECK_REG((_enp), (_reg));                          \
 883                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 884                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 885                     (_edp), (_lock));                                   \
 886                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 887                     uint32_t, (_index),                                 \
 888                     uint32_t, _reg ## _OFST,                            \
 889                     uint32_t, (_edp)->ed_u32[0]);                       \
 890         _NOTE(CONSTANTCONDITION)                                        \
 891         } while (B_FALSE)
 892
 893 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 894         do {                                                            \
 895                 EFX_CHECK_REG((_enp), (_reg));                          \
 896                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 897                     uint32_t, (_index),                                 \
 898                     uint32_t, _reg ## _OFST,                            \
 899                     uint32_t, (_edp)->ed_u32[0]);                       \
 900                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 901                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 902                     (_edp), (_lock));                                   \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905
 906 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 907         do {                                                            \
 908                 EFX_CHECK_REG((_enp), (_reg));                          \
 909                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 910                     uint32_t, (_index),                                 \
 911                     uint32_t, _reg ## _OFST,                            \
 912                     uint32_t, (_edp)->ed_u32[0]);                       \
 913                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 914                     (_reg ## _OFST +                                    \
 915                     (2 * sizeof (efx_dword_t)) +                        \
 916                     ((_index) * _reg ## _STEP)),                        \
 917                     (_edp), (_lock));                                   \
 918         _NOTE(CONSTANTCONDITION)                                        \
 919         } while (B_FALSE)
 920
 921 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 922         do {                                                            \
 923                 EFX_CHECK_REG((_enp), (_reg));                          \
 924                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 925                     uint32_t, (_index),                                 \
 926                     uint32_t, _reg ## _OFST,                            \
 927                     uint32_t, (_edp)->ed_u32[0]);                       \
 928                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 929                     (_reg ## _OFST +                                    \
 930                     (3 * sizeof (efx_dword_t)) +                        \
 931                     ((_index) * _reg ## _STEP)),                        \
 932                     (_edp), (_lock));                                   \
 933         _NOTE(CONSTANTCONDITION)                                        \
 934         } while (B_FALSE)
 935
 936 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 937         do {                                                            \
 938                 EFX_CHECK_REG((_enp), (_reg));                          \
 939                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 940                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 941                     (_eqp));                                            \
 942                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 943                     uint32_t, (_index),                                 \
 944                     uint32_t, _reg ## _OFST,                            \
 945                     uint32_t, (_eqp)->eq_u32[1],                        \
 946                     uint32_t, (_eqp)->eq_u32[0]);                       \
 947         _NOTE(CONSTANTCONDITION)                                        \
 948         } while (B_FALSE)
 949
 950 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 951         do {                                                            \
 952                 EFX_CHECK_REG((_enp), (_reg));                          \
 953                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 954                     uint32_t, (_index),                                 \
 955                     uint32_t, _reg ## _OFST,                            \
 956                     uint32_t, (_eqp)->eq_u32[1],                        \
 957                     uint32_t, (_eqp)->eq_u32[0]);                       \
 958                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 959                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 960                     (_eqp));                                            \
 961         _NOTE(CONSTANTCONDITION)                                        \
 962         } while (B_FALSE)
 963
 964 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 965         do {                                                            \
 966                 EFX_CHECK_REG((_enp), (_reg));                          \
 967                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 968                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 969                     (_eop), (_lock));                                   \
 970                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 971                     uint32_t, (_index),                                 \
 972                     uint32_t, _reg ## _OFST,                            \
 973                     uint32_t, (_eop)->eo_u32[3],                        \
 974                     uint32_t, (_eop)->eo_u32[2],                        \
 975                     uint32_t, (_eop)->eo_u32[1],                        \
 976                     uint32_t, (_eop)->eo_u32[0]);                       \
 977         _NOTE(CONSTANTCONDITION)                                        \
 978         } while (B_FALSE)
 979
 980 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 981         do {                                                            \
 982                 EFX_CHECK_REG((_enp), (_reg));                          \
 983                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 984                     uint32_t, (_index),                                 \
 985                     uint32_t, _reg ## _OFST,                            \
 986                     uint32_t, (_eop)->eo_u32[3],                        \
 987                     uint32_t, (_eop)->eo_u32[2],                        \
 988                     uint32_t, (_eop)->eo_u32[1],                        \
 989                     uint32_t, (_eop)->eo_u32[0]);                       \
 990                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 991                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 992                     (_eop), (_lock));                                   \
 993         _NOTE(CONSTANTCONDITION)                                        \
 994         } while (B_FALSE)
 995
 996 /*
 997  * Allow drivers to perform optimised 128-bit doorbell writes.
 998  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 999  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1000  * the need for locking in the host, and are the only ones known to be safe to
1001  * use 128-bites write with.
1002  */
1003 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1004         do {                                                            \
1005                 EFX_CHECK_REG((_enp), (_reg));                          \
1006                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1007                     const char *,                                       \
1008                     #_reg,                                              \
1009                     uint32_t, (_index),                                 \
1010                     uint32_t, _reg ## _OFST,                            \
1011                     uint32_t, (_eop)->eo_u32[3],                        \
1012                     uint32_t, (_eop)->eo_u32[2],                        \
1013                     uint32_t, (_eop)->eo_u32[1],                        \
1014                     uint32_t, (_eop)->eo_u32[0]);                       \
1015                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1016                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1017                     (_eop));                                            \
1018         _NOTE(CONSTANTCONDITION)                                        \
1019         } while (B_FALSE)
1020
1021 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1022         do {                                                            \
1023                 unsigned int _new = (_wptr);                            \
1024                 unsigned int _old = (_owptr);                           \
1025                                                                         \
1026                 if ((_new) >= (_old))                                   \
1027                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1028                             (_old) * sizeof (efx_desc_t),               \
1029                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1030                 else                                                    \
1031                         /*                                              \
1032                          * It is cheaper to sync entire map than sync   \
1033                          * two parts especially when offset/size are    \
1034                          * ignored and entire map is synced in any case.\
1035                          */                                             \
1036                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1037                             0,                                          \
1038                             (_entries) * sizeof (efx_desc_t));          \
1039         _NOTE(CONSTANTCONDITION)                                        \
1040         } while (B_FALSE)
1041
1042 extern  __checkReturn   efx_rc_t
1043 efx_nic_biu_test(
1044         __in            efx_nic_t *enp);
1045
1046 extern  __checkReturn   efx_rc_t
1047 efx_mac_select(
1048         __in            efx_nic_t *enp);
1049
1050 extern  void
1051 efx_mac_multicast_hash_compute(
1052         __in_ecount(6*count)            uint8_t const *addrs,
1053         __in                            int count,
1054         __out                           efx_oword_t *hash_low,
1055         __out                           efx_oword_t *hash_high);
1056
1057 extern  __checkReturn   efx_rc_t
1058 efx_phy_probe(
1059         __in            efx_nic_t *enp);
1060
1061 extern                  void
1062 efx_phy_unprobe(
1063         __in            efx_nic_t *enp);
1064
1065 #if EFSYS_OPT_VPD
1066
1067 /* VPD utility functions */
1068
1069 extern  __checkReturn           efx_rc_t
1070 efx_vpd_hunk_length(
1071         __in_bcount(size)       caddr_t data,
1072         __in                    size_t size,
1073         __out                   size_t *lengthp);
1074
1075 extern  __checkReturn           efx_rc_t
1076 efx_vpd_hunk_verify(
1077         __in_bcount(size)       caddr_t data,
1078         __in                    size_t size,
1079         __out_opt               boolean_t *cksummedp);
1080
1081 extern  __checkReturn           efx_rc_t
1082 efx_vpd_hunk_reinit(
1083         __in_bcount(size)       caddr_t data,
1084         __in                    size_t size,
1085         __in                    boolean_t wantpid);
1086
1087 extern  __checkReturn           efx_rc_t
1088 efx_vpd_hunk_get(
1089         __in_bcount(size)       caddr_t data,
1090         __in                    size_t size,
1091         __in                    efx_vpd_tag_t tag,
1092         __in                    efx_vpd_keyword_t keyword,
1093         __out                   unsigned int *payloadp,
1094         __out                   uint8_t *paylenp);
1095
1096 extern  __checkReturn                   efx_rc_t
1097 efx_vpd_hunk_next(
1098         __in_bcount(size)               caddr_t data,
1099         __in                            size_t size,
1100         __out                           efx_vpd_tag_t *tagp,
1101         __out                           efx_vpd_keyword_t *keyword,
1102         __out_opt                       unsigned int *payloadp,
1103         __out_opt                       uint8_t *paylenp,
1104         __inout                         unsigned int *contp);
1105
1106 extern  __checkReturn           efx_rc_t
1107 efx_vpd_hunk_set(
1108         __in_bcount(size)       caddr_t data,
1109         __in                    size_t size,
1110         __in                    efx_vpd_value_t *evvp);
1111
1112 #endif  /* EFSYS_OPT_VPD */
1113
1114 #if EFSYS_OPT_DIAG
1115
1116 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1117
1118 typedef struct efx_register_set_s {
1119         unsigned int            address;
1120         unsigned int            step;
1121         unsigned int            rows;
1122         efx_oword_t             mask;
1123 } efx_register_set_t;
1124
1125 extern  __checkReturn   efx_rc_t
1126 efx_nic_test_registers(
1127         __in            efx_nic_t *enp,
1128         __in            efx_register_set_t *rsp,
1129         __in            size_t count);
1130
1131 extern  __checkReturn   efx_rc_t
1132 efx_nic_test_tables(
1133         __in            efx_nic_t *enp,
1134         __in            efx_register_set_t *rsp,
1135         __in            efx_pattern_type_t pattern,
1136         __in            size_t count);
1137
1138 #endif  /* EFSYS_OPT_DIAG */
1139
1140 #if EFSYS_OPT_MCDI
1141
1142 extern  __checkReturn           efx_rc_t
1143 efx_mcdi_set_workaround(
1144         __in                    efx_nic_t *enp,
1145         __in                    uint32_t type,
1146         __in                    boolean_t enabled,
1147         __out_opt               uint32_t *flagsp);
1148
1149 extern  __checkReturn           efx_rc_t
1150 efx_mcdi_get_workarounds(
1151         __in                    efx_nic_t *enp,
1152         __out_opt               uint32_t *implementedp,
1153         __out_opt               uint32_t *enabledp);
1154
1155 #endif /* EFSYS_OPT_MCDI */
1156
1157 #ifdef  __cplusplus
1158 }
1159 #endif
1160
1161 #endif  /* _SYS_EFX_IMPL_H */