2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_EFX_IMPL_H
34 #define _SYS_EFX_IMPL_H
39 #include "efx_regs_ef10.h"
41 /* FIXME: Add definition for driver generated software events */
42 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
46 #include "efx_check.h"
50 #include "falcon_impl.h"
51 #endif /* EFSYS_OPT_FALCON */
54 #include "siena_impl.h"
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON
58 #include "hunt_impl.h"
59 #endif /* EFSYS_OPT_HUNTINGTON */
65 #define EFX_MOD_MCDI 0x00000001
66 #define EFX_MOD_PROBE 0x00000002
67 #define EFX_MOD_NVRAM 0x00000004
68 #define EFX_MOD_VPD 0x00000008
69 #define EFX_MOD_NIC 0x00000010
70 #define EFX_MOD_INTR 0x00000020
71 #define EFX_MOD_EV 0x00000040
72 #define EFX_MOD_RX 0x00000080
73 #define EFX_MOD_TX 0x00000100
74 #define EFX_MOD_PORT 0x00000200
75 #define EFX_MOD_MON 0x00000400
76 #define EFX_MOD_WOL 0x00000800
77 #define EFX_MOD_FILTER 0x00001000
78 #define EFX_MOD_PKTFILTER 0x00002000
80 #define EFX_RESET_MAC 0x00000001
81 #define EFX_RESET_PHY 0x00000002
82 #define EFX_RESET_RXQ_ERR 0x00000004
83 #define EFX_RESET_TXQ_ERR 0x00000008
85 typedef enum efx_mac_type_e {
94 typedef struct efx_ev_ops_s {
95 int (*eevo_init)(efx_nic_t *);
96 void (*eevo_fini)(efx_nic_t *);
97 int (*eevo_qcreate)(efx_nic_t *, unsigned int,
98 efsys_mem_t *, size_t, uint32_t,
100 void (*eevo_qdestroy)(efx_evq_t *);
101 int (*eevo_qprime)(efx_evq_t *, unsigned int);
102 void (*eevo_qpost)(efx_evq_t *, uint16_t);
103 int (*eevo_qmoderate)(efx_evq_t *, unsigned int);
105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
109 typedef struct efx_tx_ops_s {
110 int (*etxo_init)(efx_nic_t *);
111 void (*etxo_fini)(efx_nic_t *);
112 int (*etxo_qcreate)(efx_nic_t *,
113 unsigned int, unsigned int,
114 efsys_mem_t *, size_t,
116 efx_evq_t *, efx_txq_t *,
118 void (*etxo_qdestroy)(efx_txq_t *);
119 int (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
120 unsigned int, unsigned int,
122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123 int (*etxo_qpace)(efx_txq_t *, unsigned int);
124 int (*etxo_qflush)(efx_txq_t *);
125 void (*etxo_qenable)(efx_txq_t *);
126 int (*etxo_qpio_enable)(efx_txq_t *);
127 void (*etxo_qpio_disable)(efx_txq_t *);
128 int (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
130 int (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
132 int (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
133 unsigned int, unsigned int,
135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
144 void (*etxo_qstats_update)(efx_txq_t *,
149 typedef struct efx_rx_ops_s {
150 int (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152 #if EFSYS_OPT_RX_HDR_SPLIT
153 int (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
156 #if EFSYS_OPT_RX_SCATTER
157 int (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
159 #if EFSYS_OPT_RX_SCALE
160 int (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
161 efx_rx_hash_type_t, boolean_t);
162 int (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
163 int (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
167 unsigned int, unsigned int,
169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170 int (*erxo_qflush)(efx_rxq_t *);
171 void (*erxo_qenable)(efx_rxq_t *);
172 int (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
173 unsigned int, efx_rxq_type_t,
174 efsys_mem_t *, size_t, uint32_t,
175 efx_evq_t *, efx_rxq_t *);
176 void (*erxo_qdestroy)(efx_rxq_t *);
179 typedef struct efx_mac_ops_s {
180 int (*emo_reset)(efx_nic_t *); /* optional */
181 int (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182 int (*emo_up)(efx_nic_t *, boolean_t *);
183 int (*emo_addr_set)(efx_nic_t *);
184 int (*emo_reconfigure)(efx_nic_t *);
185 int (*emo_multicast_list_set)(efx_nic_t *);
186 int (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189 #if EFSYS_OPT_LOOPBACK
190 int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192 #endif /* EFSYS_OPT_LOOPBACK */
193 #if EFSYS_OPT_MAC_STATS
194 int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195 int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196 uint16_t, boolean_t);
197 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198 efsys_stat_t *, uint32_t *);
199 #endif /* EFSYS_OPT_MAC_STATS */
202 typedef struct efx_phy_ops_s {
203 int (*epo_power)(efx_nic_t *, boolean_t); /* optional */
204 int (*epo_reset)(efx_nic_t *);
205 int (*epo_reconfigure)(efx_nic_t *);
206 int (*epo_verify)(efx_nic_t *);
207 int (*epo_uplink_check)(efx_nic_t *,
208 boolean_t *); /* optional */
209 int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
210 unsigned int *, uint32_t *);
211 int (*epo_oui_get)(efx_nic_t *, uint32_t *);
212 #if EFSYS_OPT_PHY_STATS
213 int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
215 #endif /* EFSYS_OPT_PHY_STATS */
216 #if EFSYS_OPT_PHY_PROPS
218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
219 #endif /* EFSYS_OPT_PHY_PROPS */
220 int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
222 int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
223 #endif /* EFSYS_OPT_PHY_PROPS */
225 int (*epo_bist_enable_offline)(efx_nic_t *);
226 int (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227 int (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
228 efx_bist_result_t *, uint32_t *,
229 unsigned long *, size_t);
230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
231 #endif /* EFSYS_OPT_BIST */
235 typedef struct efx_filter_ops_s {
236 int (*efo_init)(efx_nic_t *);
237 void (*efo_fini)(efx_nic_t *);
238 int (*efo_restore)(efx_nic_t *);
239 int (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
240 boolean_t may_replace);
241 int (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242 int (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
243 int (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
244 boolean_t, boolean_t, boolean_t,
245 uint8_t const *, int);
248 extern __checkReturn int
249 efx_filter_reconfigure(
251 __in_ecount(6) uint8_t const *mac_addr,
252 __in boolean_t all_unicst,
253 __in boolean_t mulcst,
254 __in boolean_t all_mulcst,
255 __in boolean_t brdcst,
256 __in_ecount(6*count) uint8_t const *addrs,
259 #endif /* EFSYS_OPT_FILTER */
261 typedef struct efx_pktfilter_ops_s {
262 int (*epfo_set)(efx_nic_t *,
265 #if EFSYS_OPT_MCAST_FILTER_LIST
266 int (*epfo_mcast_list_set)(efx_nic_t *, uint8_t const *addrs, int count);
267 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
268 int (*epfo_mcast_all)(efx_nic_t *);
269 } efx_pktfilter_ops_t;
271 typedef struct efx_port_s {
272 efx_mac_type_t ep_mac_type;
273 uint32_t ep_phy_type;
276 uint8_t ep_mac_addr[6];
277 efx_link_mode_t ep_link_mode;
278 boolean_t ep_all_unicst;
280 boolean_t ep_all_mulcst;
282 unsigned int ep_fcntl;
283 boolean_t ep_fcntl_autoneg;
284 efx_oword_t ep_multicst_hash[2];
285 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
286 EFX_MAC_MULTICAST_LIST_MAX];
287 uint32_t ep_mulcst_addr_count;
288 #if EFSYS_OPT_LOOPBACK
289 efx_loopback_type_t ep_loopback_type;
290 efx_link_mode_t ep_loopback_link_mode;
291 #endif /* EFSYS_OPT_LOOPBACK */
292 #if EFSYS_OPT_PHY_FLAGS
293 uint32_t ep_phy_flags;
294 #endif /* EFSYS_OPT_PHY_FLAGS */
295 #if EFSYS_OPT_PHY_LED_CONTROL
296 efx_phy_led_mode_t ep_phy_led_mode;
297 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
298 efx_phy_media_type_t ep_fixed_port_type;
299 efx_phy_media_type_t ep_module_type;
300 uint32_t ep_adv_cap_mask;
301 uint32_t ep_lp_cap_mask;
302 uint32_t ep_default_adv_cap_mask;
303 uint32_t ep_phy_cap_mask;
304 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
307 unsigned int bug10934_count;
310 unsigned int bug17190_count;
314 boolean_t ep_mac_poll_needed; /* falcon only */
315 boolean_t ep_mac_up; /* falcon only */
316 uint32_t ep_fwver; /* falcon only */
317 boolean_t ep_mac_drain;
318 boolean_t ep_mac_stats_pending;
320 efx_bist_type_t ep_current_bist;
322 efx_mac_ops_t *ep_emop;
323 efx_phy_ops_t *ep_epop;
326 typedef struct efx_mon_ops_s {
327 int (*emo_reset)(efx_nic_t *);
328 int (*emo_reconfigure)(efx_nic_t *);
329 #if EFSYS_OPT_MON_STATS
330 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
331 efx_mon_stat_value_t *);
332 #endif /* EFSYS_OPT_MON_STATS */
335 typedef struct efx_mon_s {
336 efx_mon_type_t em_type;
337 efx_mon_ops_t *em_emop;
340 typedef struct efx_intr_ops_s {
341 int (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
342 void (*eio_enable)(efx_nic_t *);
343 void (*eio_disable)(efx_nic_t *);
344 void (*eio_disable_unlocked)(efx_nic_t *);
345 int (*eio_trigger)(efx_nic_t *, unsigned int);
346 void (*eio_fini)(efx_nic_t *);
349 typedef struct efx_intr_s {
350 efx_intr_ops_t *ei_eiop;
351 efsys_mem_t *ei_esmp;
352 efx_intr_type_t ei_type;
353 unsigned int ei_level;
356 typedef struct efx_nic_ops_s {
357 int (*eno_probe)(efx_nic_t *);
358 int (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
359 int (*eno_reset)(efx_nic_t *);
360 int (*eno_init)(efx_nic_t *);
361 int (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
362 int (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
363 uint32_t *, size_t *);
365 int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
366 int (*eno_register_test)(efx_nic_t *);
367 #endif /* EFSYS_OPT_DIAG */
368 void (*eno_fini)(efx_nic_t *);
369 void (*eno_unprobe)(efx_nic_t *);
372 #ifndef EFX_TXQ_LIMIT_TARGET
373 #define EFX_TXQ_LIMIT_TARGET 259
375 #ifndef EFX_RXQ_LIMIT_TARGET
376 #define EFX_RXQ_LIMIT_TARGET 512
378 #ifndef EFX_TXQ_DC_SIZE
379 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
381 #ifndef EFX_RXQ_DC_SIZE
382 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
387 typedef struct falconsiena_filter_spec_s {
390 uint32_t fsfs_dmaq_id;
391 uint32_t fsfs_dword[3];
392 } falconsiena_filter_spec_t;
394 typedef enum falconsiena_filter_type_e {
395 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
396 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
397 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
398 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
401 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
402 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
404 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
405 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
406 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
407 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
409 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
410 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
411 #endif /* EFSYS_OPT_SIENA */
414 } falconsiena_filter_type_t;
416 typedef enum falconsiena_filter_tbl_id_e {
417 EFX_FS_FILTER_TBL_RX_IP = 0,
418 EFX_FS_FILTER_TBL_RX_MAC,
419 EFX_FS_FILTER_TBL_TX_IP,
420 EFX_FS_FILTER_TBL_TX_MAC,
422 } falconsiena_filter_tbl_id_t;
424 typedef struct falconsiena_filter_tbl_s {
425 int fsft_size; /* number of entries */
426 int fsft_used; /* active count */
427 uint32_t *fsft_bitmap; /* active bitmap */
428 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
429 } falconsiena_filter_tbl_t;
431 typedef struct falconsiena_filter_s {
432 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
433 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
434 } falconsiena_filter_t;
436 typedef struct efx_filter_s {
437 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
438 falconsiena_filter_t *ef_falconsiena_filter;
439 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
440 #if EFSYS_OPT_HUNTINGTON
441 hunt_filter_table_t *ef_hunt_filter_table;
442 #endif /* EFSYS_OPT_HUNTINGTON */
446 falconsiena_filter_tbl_clear(
448 __in falconsiena_filter_tbl_id_t tbl);
450 #endif /* EFSYS_OPT_FILTER */
454 typedef struct efx_mcdi_ops_s {
455 int (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
456 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
457 unsigned int, boolean_t, boolean_t);
458 boolean_t (*emco_request_poll)(efx_nic_t *);
459 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
460 int (*emco_poll_reboot)(efx_nic_t *);
461 void (*emco_fini)(efx_nic_t *);
462 int (*emco_fw_update_supported)(efx_nic_t *, boolean_t *);
463 int (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
466 typedef struct efx_mcdi_s {
467 efx_mcdi_ops_t *em_emcop;
468 const efx_mcdi_transport_t *em_emtp;
469 efx_mcdi_iface_t em_emip;
472 #endif /* EFSYS_OPT_MCDI */
475 typedef struct efx_nvram_ops_s {
477 int (*envo_test)(efx_nic_t *);
478 #endif /* EFSYS_OPT_DIAG */
479 int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
480 int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
481 uint32_t *, uint16_t *);
482 int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
483 int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
484 unsigned int, caddr_t, size_t);
485 int (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
486 int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
487 unsigned int, caddr_t, size_t);
488 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
489 int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *);
492 #endif /* EFSYS_OPT_NVRAM */
495 typedef struct efx_vpd_ops_s {
496 int (*evpdo_init)(efx_nic_t *);
497 int (*evpdo_size)(efx_nic_t *, size_t *);
498 int (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
499 int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
500 int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
501 int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
502 int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
503 int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *,
505 int (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
506 void (*evpdo_fini)(efx_nic_t *);
508 #endif /* EFSYS_OPT_VPD */
510 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
513 efx_mcdi_nvram_partitions(
515 __out_bcount(size) caddr_t data,
517 __out unsigned int *npartnp);
520 efx_mcdi_nvram_metadata(
523 __out uint32_t *subtypep,
524 __out_ecount(4) uint16_t version[4],
525 __out_bcount_opt(size) char *descp,
532 __out_opt size_t *sizep,
533 __out_opt uint32_t *addressp,
534 __out_opt uint32_t *erase_sizep);
537 efx_mcdi_nvram_update_start(
539 __in uint32_t partn);
545 __in uint32_t offset,
546 __out_bcount(size) caddr_t data,
550 efx_mcdi_nvram_erase(
553 __in uint32_t offset,
557 efx_mcdi_nvram_write(
560 __in uint32_t offset,
561 __out_bcount(size) caddr_t data,
565 efx_mcdi_nvram_update_finish(
568 __in boolean_t reboot);
575 __in uint32_t partn);
577 #endif /* EFSYS_OPT_DIAG */
579 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
581 typedef struct efx_drv_cfg_s {
582 uint32_t edc_min_vi_count;
583 uint32_t edc_max_vi_count;
585 uint32_t edc_max_piobuf_count;
586 uint32_t edc_pio_alloc_size;
591 efx_family_t en_family;
592 uint32_t en_features;
593 efsys_identifier_t *en_esip;
594 efsys_lock_t *en_eslp;
595 efsys_bar_t *en_esbp;
596 unsigned int en_mod_flags;
597 unsigned int en_reset_flags;
598 efx_nic_cfg_t en_nic_cfg;
599 efx_drv_cfg_t en_drv_cfg;
603 uint32_t en_ev_qcount;
604 uint32_t en_rx_qcount;
605 uint32_t en_tx_qcount;
606 efx_nic_ops_t *en_enop;
607 efx_ev_ops_t *en_eevop;
608 efx_tx_ops_t *en_etxop;
609 efx_rx_ops_t *en_erxop;
611 efx_filter_t en_filter;
612 efx_filter_ops_t *en_efop;
613 #endif /* EFSYS_OPT_FILTER */
614 efx_pktfilter_ops_t *en_epfop;
617 #endif /* EFSYS_OPT_MCDI */
619 efx_nvram_type_t en_nvram_locked;
620 efx_nvram_ops_t *en_envop;
621 #endif /* EFSYS_OPT_NVRAM */
623 efx_vpd_ops_t *en_evpdop;
624 #endif /* EFSYS_OPT_VPD */
625 #if EFSYS_OPT_RX_SCALE
626 efx_rx_hash_support_t en_hash_support;
627 efx_rx_scale_support_t en_rss_support;
628 uint32_t en_rss_context;
629 #endif /* EFSYS_OPT_RX_SCALE */
630 uint32_t en_vport_id;
634 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
635 falcon_i2c_t enu_fip;
636 boolean_t enu_i2c_locked;
637 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
638 const uint8_t *enu_forced_cfg;
639 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
640 uint8_t enu_mon_devid;
641 #if EFSYS_OPT_PCIE_TUNE
642 unsigned int enu_nlanes;
643 #endif /* EFSYS_OPT_PCIE_TUNE */
644 uint16_t enu_board_rev;
645 boolean_t enu_internal_sram;
646 uint8_t enu_sram_num_bank;
647 uint8_t enu_sram_bank_size;
649 #endif /* EFSYS_OPT_FALCON */
652 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
653 unsigned int enu_partn_mask;
654 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
657 size_t enu_svpd_length;
658 #endif /* EFSYS_OPT_VPD */
661 #endif /* EFSYS_OPT_SIENA */
662 #if EFSYS_OPT_HUNTINGTON
668 size_t enu_svpd_length;
669 #endif /* EFSYS_OPT_VPD */
670 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
671 uint32_t enu_piobuf_count;
672 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
673 uint32_t enu_pio_write_vi_base;
674 /* Memory BAR mapping regions */
675 uint32_t enu_uc_mem_map_offset;
676 size_t enu_uc_mem_map_size;
677 uint32_t enu_wc_mem_map_offset;
678 size_t enu_wc_mem_map_size;
680 #endif /* EFSYS_OPT_HUNTINGTON */
685 #define EFX_NIC_MAGIC 0x02121996
687 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
688 const efx_ev_callbacks_t *, void *);
690 typedef struct efx_evq_rxq_state_s {
691 unsigned int eers_rx_read_ptr;
692 unsigned int eers_rx_mask;
693 } efx_evq_rxq_state_t;
698 unsigned int ee_index;
699 unsigned int ee_mask;
700 efsys_mem_t *ee_esmp;
702 uint32_t ee_stat[EV_NQSTATS];
703 #endif /* EFSYS_OPT_QSTATS */
705 efx_ev_handler_t ee_rx;
706 efx_ev_handler_t ee_tx;
707 efx_ev_handler_t ee_driver;
708 efx_ev_handler_t ee_global;
709 efx_ev_handler_t ee_drv_gen;
711 efx_ev_handler_t ee_mcdi;
712 #endif /* EFSYS_OPT_MCDI */
714 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
717 #define EFX_EVQ_MAGIC 0x08081997
719 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
720 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
726 unsigned int er_index;
727 unsigned int er_label;
728 unsigned int er_mask;
729 efsys_mem_t *er_esmp;
732 #define EFX_RXQ_MAGIC 0x15022005
737 unsigned int et_index;
738 unsigned int et_mask;
739 efsys_mem_t *et_esmp;
740 #if EFSYS_OPT_HUNTINGTON
741 uint32_t et_pio_bufnum;
742 uint32_t et_pio_blknum;
743 uint32_t et_pio_write_offset;
744 uint32_t et_pio_offset;
748 uint32_t et_stat[TX_NQSTATS];
749 #endif /* EFSYS_OPT_QSTATS */
752 #define EFX_TXQ_MAGIC 0x05092005
754 #define EFX_MAC_ADDR_COPY(_dst, _src) \
756 (_dst)[0] = (_src)[0]; \
757 (_dst)[1] = (_src)[1]; \
758 (_dst)[2] = (_src)[2]; \
759 (_dst)[3] = (_src)[3]; \
760 (_dst)[4] = (_src)[4]; \
761 (_dst)[5] = (_src)[5]; \
762 _NOTE(CONSTANTCONDITION) \
765 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
767 uint16_t *_d = (uint16_t *)(_dst); \
771 _NOTE(CONSTANTCONDITION) \
774 #if EFSYS_OPT_CHECK_REG
775 #define EFX_CHECK_REG(_enp, _reg) \
777 const char *name = #_reg; \
778 char min = name[4]; \
779 char max = name[5]; \
782 switch ((_enp)->en_family) { \
783 case EFX_FAMILY_FALCON: \
787 case EFX_FAMILY_SIENA: \
791 case EFX_FAMILY_HUNTINGTON: \
800 EFSYS_ASSERT3S(rev, >=, min); \
801 EFSYS_ASSERT3S(rev, <=, max); \
803 _NOTE(CONSTANTCONDITION) \
806 #define EFX_CHECK_REG(_enp, _reg) do { \
807 _NOTE(CONSTANTCONDITION) \
811 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
813 EFX_CHECK_REG((_enp), (_reg)); \
814 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
816 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
817 uint32_t, _reg ## _OFST, \
818 uint32_t, (_edp)->ed_u32[0]); \
819 _NOTE(CONSTANTCONDITION) \
822 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
824 EFX_CHECK_REG((_enp), (_reg)); \
825 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
826 uint32_t, _reg ## _OFST, \
827 uint32_t, (_edp)->ed_u32[0]); \
828 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
830 _NOTE(CONSTANTCONDITION) \
833 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
835 EFX_CHECK_REG((_enp), (_reg)); \
836 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
838 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
839 uint32_t, _reg ## _OFST, \
840 uint32_t, (_eqp)->eq_u32[1], \
841 uint32_t, (_eqp)->eq_u32[0]); \
842 _NOTE(CONSTANTCONDITION) \
845 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
847 EFX_CHECK_REG((_enp), (_reg)); \
848 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
849 uint32_t, _reg ## _OFST, \
850 uint32_t, (_eqp)->eq_u32[1], \
851 uint32_t, (_eqp)->eq_u32[0]); \
852 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
854 _NOTE(CONSTANTCONDITION) \
857 #define EFX_BAR_READO(_enp, _reg, _eop) \
859 EFX_CHECK_REG((_enp), (_reg)); \
860 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
862 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
863 uint32_t, _reg ## _OFST, \
864 uint32_t, (_eop)->eo_u32[3], \
865 uint32_t, (_eop)->eo_u32[2], \
866 uint32_t, (_eop)->eo_u32[1], \
867 uint32_t, (_eop)->eo_u32[0]); \
868 _NOTE(CONSTANTCONDITION) \
871 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
873 EFX_CHECK_REG((_enp), (_reg)); \
874 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
875 uint32_t, _reg ## _OFST, \
876 uint32_t, (_eop)->eo_u32[3], \
877 uint32_t, (_eop)->eo_u32[2], \
878 uint32_t, (_eop)->eo_u32[1], \
879 uint32_t, (_eop)->eo_u32[0]); \
880 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
882 _NOTE(CONSTANTCONDITION) \
885 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
887 EFX_CHECK_REG((_enp), (_reg)); \
888 EFSYS_BAR_READD((_enp)->en_esbp, \
889 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
891 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
892 uint32_t, (_index), \
893 uint32_t, _reg ## _OFST, \
894 uint32_t, (_edp)->ed_u32[0]); \
895 _NOTE(CONSTANTCONDITION) \
898 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
900 EFX_CHECK_REG((_enp), (_reg)); \
901 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
902 uint32_t, (_index), \
903 uint32_t, _reg ## _OFST, \
904 uint32_t, (_edp)->ed_u32[0]); \
905 EFSYS_BAR_WRITED((_enp)->en_esbp, \
906 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
908 _NOTE(CONSTANTCONDITION) \
911 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
913 EFX_CHECK_REG((_enp), (_reg)); \
914 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
915 uint32_t, (_index), \
916 uint32_t, _reg ## _OFST, \
917 uint32_t, (_edp)->ed_u32[0]); \
918 EFSYS_BAR_WRITED((_enp)->en_esbp, \
920 (2 * sizeof (efx_dword_t)) + \
921 ((_index) * _reg ## _STEP)), \
923 _NOTE(CONSTANTCONDITION) \
926 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
928 EFX_CHECK_REG((_enp), (_reg)); \
929 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
930 uint32_t, (_index), \
931 uint32_t, _reg ## _OFST, \
932 uint32_t, (_edp)->ed_u32[0]); \
933 EFSYS_BAR_WRITED((_enp)->en_esbp, \
935 (3 * sizeof (efx_dword_t)) + \
936 ((_index) * _reg ## _STEP)), \
938 _NOTE(CONSTANTCONDITION) \
941 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
943 EFX_CHECK_REG((_enp), (_reg)); \
944 EFSYS_BAR_READQ((_enp)->en_esbp, \
945 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
947 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
948 uint32_t, (_index), \
949 uint32_t, _reg ## _OFST, \
950 uint32_t, (_eqp)->eq_u32[1], \
951 uint32_t, (_eqp)->eq_u32[0]); \
952 _NOTE(CONSTANTCONDITION) \
955 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
957 EFX_CHECK_REG((_enp), (_reg)); \
958 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
959 uint32_t, (_index), \
960 uint32_t, _reg ## _OFST, \
961 uint32_t, (_eqp)->eq_u32[1], \
962 uint32_t, (_eqp)->eq_u32[0]); \
963 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
964 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
966 _NOTE(CONSTANTCONDITION) \
969 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
971 EFX_CHECK_REG((_enp), (_reg)); \
972 EFSYS_BAR_READO((_enp)->en_esbp, \
973 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
975 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
976 uint32_t, (_index), \
977 uint32_t, _reg ## _OFST, \
978 uint32_t, (_eop)->eo_u32[3], \
979 uint32_t, (_eop)->eo_u32[2], \
980 uint32_t, (_eop)->eo_u32[1], \
981 uint32_t, (_eop)->eo_u32[0]); \
982 _NOTE(CONSTANTCONDITION) \
985 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
987 EFX_CHECK_REG((_enp), (_reg)); \
988 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
989 uint32_t, (_index), \
990 uint32_t, _reg ## _OFST, \
991 uint32_t, (_eop)->eo_u32[3], \
992 uint32_t, (_eop)->eo_u32[2], \
993 uint32_t, (_eop)->eo_u32[1], \
994 uint32_t, (_eop)->eo_u32[0]); \
995 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
996 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
998 _NOTE(CONSTANTCONDITION) \
1002 * Allow drivers to perform optimised 128-bit doorbell writes.
1003 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1004 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1005 * the need for locking in the host, and are the only ones known to be safe to
1006 * use 128-bites write with.
1008 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1010 EFX_CHECK_REG((_enp), (_reg)); \
1011 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1014 uint32_t, (_index), \
1015 uint32_t, _reg ## _OFST, \
1016 uint32_t, (_eop)->eo_u32[3], \
1017 uint32_t, (_eop)->eo_u32[2], \
1018 uint32_t, (_eop)->eo_u32[1], \
1019 uint32_t, (_eop)->eo_u32[0]); \
1020 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1021 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1023 _NOTE(CONSTANTCONDITION) \
1026 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1028 unsigned int _new = (_wptr); \
1029 unsigned int _old = (_owptr); \
1031 if ((_new) >= (_old)) \
1032 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1033 (_old) * sizeof (efx_desc_t), \
1034 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1037 * It is cheaper to sync entire map than sync \
1038 * two parts especially when offset/size are \
1039 * ignored and entire map is synced in any case.\
1041 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1043 (_entries) * sizeof (efx_desc_t)); \
1044 _NOTE(CONSTANTCONDITION) \
1047 extern __checkReturn int
1049 __in efx_nic_t *enp);
1051 extern __checkReturn int
1053 __in efx_nic_t *enp);
1056 efx_mac_multicast_hash_compute(
1057 __in_ecount(6*count) uint8_t const *addrs,
1059 __out efx_oword_t *hash_low,
1060 __out efx_oword_t *hash_high);
1062 extern __checkReturn int
1064 __in efx_nic_t *enp);
1068 __in efx_nic_t *enp);
1072 /* VPD utility functions */
1074 extern __checkReturn int
1075 efx_vpd_hunk_length(
1076 __in_bcount(size) caddr_t data,
1078 __out size_t *lengthp);
1080 extern __checkReturn int
1081 efx_vpd_hunk_verify(
1082 __in_bcount(size) caddr_t data,
1084 __out_opt boolean_t *cksummedp);
1086 extern __checkReturn int
1087 efx_vpd_hunk_reinit(
1088 __in_bcount(size) caddr_t data,
1090 __in boolean_t wantpid);
1092 extern __checkReturn int
1094 __in_bcount(size) caddr_t data,
1096 __in efx_vpd_tag_t tag,
1097 __in efx_vpd_keyword_t keyword,
1098 __out unsigned int *payloadp,
1099 __out uint8_t *paylenp);
1101 extern __checkReturn int
1103 __in_bcount(size) caddr_t data,
1105 __out efx_vpd_tag_t *tagp,
1106 __out efx_vpd_keyword_t *keyword,
1107 __out_bcount_opt(*paylenp) unsigned int *payloadp,
1108 __out_opt uint8_t *paylenp,
1109 __inout unsigned int *contp);
1111 extern __checkReturn int
1113 __in_bcount(size) caddr_t data,
1115 __in efx_vpd_value_t *evvp);
1117 #endif /* EFSYS_OPT_VPD */
1121 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1123 typedef struct efx_register_set_s {
1124 unsigned int address;
1128 } efx_register_set_t;
1130 extern __checkReturn int
1131 efx_nic_test_registers(
1132 __in efx_nic_t *enp,
1133 __in efx_register_set_t *rsp,
1136 extern __checkReturn int
1137 efx_nic_test_tables(
1138 __in efx_nic_t *enp,
1139 __in efx_register_set_t *rsp,
1140 __in efx_pattern_type_t pattern,
1143 #endif /* EFSYS_OPT_DIAG */
1147 extern __checkReturn int
1148 efx_mcdi_set_workaround(
1149 __in efx_nic_t *enp,
1151 __in boolean_t enabled,
1152 __out_opt uint32_t *flagsp);
1154 extern __checkReturn int
1155 efx_mcdi_get_workarounds(
1156 __in efx_nic_t *enp,
1157 __out_opt uint32_t *implementedp,
1158 __out_opt uint32_t *enabledp);
1160 #endif /* EFSYS_OPT_MCDI */
1166 #endif /* _SYS_EFX_IMPL_H */