2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 #ifndef _SYS_EFX_IMPL_H
36 #define _SYS_EFX_IMPL_H
40 #include "efx_regs_ef10.h"
42 /* FIXME: Add definition for driver generated software events */
43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
49 #include "siena_impl.h"
50 #endif /* EFSYS_OPT_SIENA */
52 #if EFSYS_OPT_HUNTINGTON
53 #include "hunt_impl.h"
54 #endif /* EFSYS_OPT_HUNTINGTON */
57 #include "medford_impl.h"
58 #endif /* EFSYS_OPT_MEDFORD */
60 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
61 #include "ef10_impl.h"
62 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
68 #define EFX_MOD_MCDI 0x00000001
69 #define EFX_MOD_PROBE 0x00000002
70 #define EFX_MOD_NVRAM 0x00000004
71 #define EFX_MOD_VPD 0x00000008
72 #define EFX_MOD_NIC 0x00000010
73 #define EFX_MOD_INTR 0x00000020
74 #define EFX_MOD_EV 0x00000040
75 #define EFX_MOD_RX 0x00000080
76 #define EFX_MOD_TX 0x00000100
77 #define EFX_MOD_PORT 0x00000200
78 #define EFX_MOD_MON 0x00000400
79 #define EFX_MOD_FILTER 0x00001000
80 #define EFX_MOD_LIC 0x00002000
82 #define EFX_RESET_PHY 0x00000001
83 #define EFX_RESET_RXQ_ERR 0x00000002
84 #define EFX_RESET_TXQ_ERR 0x00000004
86 typedef enum efx_mac_type_e {
94 typedef struct efx_ev_ops_s {
95 efx_rc_t (*eevo_init)(efx_nic_t *);
96 void (*eevo_fini)(efx_nic_t *);
97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
98 efsys_mem_t *, size_t, uint32_t,
99 uint32_t, uint32_t, efx_evq_t *);
100 void (*eevo_qdestroy)(efx_evq_t *);
101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
102 void (*eevo_qpost)(efx_evq_t *, uint16_t);
103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
109 typedef struct efx_tx_ops_s {
110 efx_rc_t (*etxo_init)(efx_nic_t *);
111 void (*etxo_fini)(efx_nic_t *);
112 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
113 unsigned int, unsigned int,
114 efsys_mem_t *, size_t,
116 efx_evq_t *, efx_txq_t *,
118 void (*etxo_qdestroy)(efx_txq_t *);
119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
120 unsigned int, unsigned int,
122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
124 efx_rc_t (*etxo_qflush)(efx_txq_t *);
125 void (*etxo_qenable)(efx_txq_t *);
126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
127 void (*etxo_qpio_disable)(efx_txq_t *);
128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
133 unsigned int, unsigned int,
135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
141 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
144 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
147 void (*etxo_qstats_update)(efx_txq_t *,
152 typedef struct efx_rx_ops_s {
153 efx_rc_t (*erxo_init)(efx_nic_t *);
154 void (*erxo_fini)(efx_nic_t *);
155 #if EFSYS_OPT_RX_SCATTER
156 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
158 #if EFSYS_OPT_RX_SCALE
159 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
160 efx_rx_hash_type_t, boolean_t);
161 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
162 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
164 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
166 #endif /* EFSYS_OPT_RX_SCALE */
167 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
169 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
170 unsigned int, unsigned int,
172 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
173 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
174 void (*erxo_qenable)(efx_rxq_t *);
175 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
176 unsigned int, efx_rxq_type_t,
177 efsys_mem_t *, size_t, uint32_t,
178 efx_evq_t *, efx_rxq_t *);
179 void (*erxo_qdestroy)(efx_rxq_t *);
182 typedef struct efx_mac_ops_s {
183 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
184 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
185 efx_rc_t (*emo_addr_set)(efx_nic_t *);
186 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
187 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
188 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
189 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
190 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
191 efx_rxq_t *, boolean_t);
192 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
193 #if EFSYS_OPT_LOOPBACK
194 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
195 efx_loopback_type_t);
196 #endif /* EFSYS_OPT_LOOPBACK */
197 #if EFSYS_OPT_MAC_STATS
198 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
199 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
200 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
201 uint16_t, boolean_t);
202 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
203 efsys_stat_t *, uint32_t *);
204 #endif /* EFSYS_OPT_MAC_STATS */
207 typedef struct efx_phy_ops_s {
208 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
209 efx_rc_t (*epo_reset)(efx_nic_t *);
210 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
211 efx_rc_t (*epo_verify)(efx_nic_t *);
212 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
213 #if EFSYS_OPT_PHY_STATS
214 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
216 #endif /* EFSYS_OPT_PHY_STATS */
218 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
219 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
220 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
221 efx_bist_result_t *, uint32_t *,
222 unsigned long *, size_t);
223 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
224 #endif /* EFSYS_OPT_BIST */
228 typedef struct efx_filter_ops_s {
229 efx_rc_t (*efo_init)(efx_nic_t *);
230 void (*efo_fini)(efx_nic_t *);
231 efx_rc_t (*efo_restore)(efx_nic_t *);
232 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
233 boolean_t may_replace);
234 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
235 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
237 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
238 boolean_t, boolean_t, boolean_t,
239 uint8_t const *, uint32_t);
242 extern __checkReturn efx_rc_t
243 efx_filter_reconfigure(
245 __in_ecount(6) uint8_t const *mac_addr,
246 __in boolean_t all_unicst,
247 __in boolean_t mulcst,
248 __in boolean_t all_mulcst,
249 __in boolean_t brdcst,
250 __in_ecount(6*count) uint8_t const *addrs,
251 __in uint32_t count);
253 #endif /* EFSYS_OPT_FILTER */
256 typedef struct efx_port_s {
257 efx_mac_type_t ep_mac_type;
258 uint32_t ep_phy_type;
261 uint8_t ep_mac_addr[6];
262 efx_link_mode_t ep_link_mode;
263 boolean_t ep_all_unicst;
265 boolean_t ep_all_mulcst;
267 unsigned int ep_fcntl;
268 boolean_t ep_fcntl_autoneg;
269 efx_oword_t ep_multicst_hash[2];
270 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
271 EFX_MAC_MULTICAST_LIST_MAX];
272 uint32_t ep_mulcst_addr_count;
273 #if EFSYS_OPT_LOOPBACK
274 efx_loopback_type_t ep_loopback_type;
275 efx_link_mode_t ep_loopback_link_mode;
276 #endif /* EFSYS_OPT_LOOPBACK */
277 #if EFSYS_OPT_PHY_FLAGS
278 uint32_t ep_phy_flags;
279 #endif /* EFSYS_OPT_PHY_FLAGS */
280 #if EFSYS_OPT_PHY_LED_CONTROL
281 efx_phy_led_mode_t ep_phy_led_mode;
282 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
283 efx_phy_media_type_t ep_fixed_port_type;
284 efx_phy_media_type_t ep_module_type;
285 uint32_t ep_adv_cap_mask;
286 uint32_t ep_lp_cap_mask;
287 uint32_t ep_default_adv_cap_mask;
288 uint32_t ep_phy_cap_mask;
289 boolean_t ep_mac_drain;
290 boolean_t ep_mac_stats_pending;
292 efx_bist_type_t ep_current_bist;
294 const efx_mac_ops_t *ep_emop;
295 const efx_phy_ops_t *ep_epop;
298 typedef struct efx_mon_ops_s {
299 #if EFSYS_OPT_MON_STATS
300 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
301 efx_mon_stat_value_t *);
302 #endif /* EFSYS_OPT_MON_STATS */
305 typedef struct efx_mon_s {
306 efx_mon_type_t em_type;
307 const efx_mon_ops_t *em_emop;
310 typedef struct efx_intr_ops_s {
311 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
312 void (*eio_enable)(efx_nic_t *);
313 void (*eio_disable)(efx_nic_t *);
314 void (*eio_disable_unlocked)(efx_nic_t *);
315 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
316 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
317 void (*eio_status_message)(efx_nic_t *, unsigned int,
319 void (*eio_fatal)(efx_nic_t *);
320 void (*eio_fini)(efx_nic_t *);
323 typedef struct efx_intr_s {
324 const efx_intr_ops_t *ei_eiop;
325 efsys_mem_t *ei_esmp;
326 efx_intr_type_t ei_type;
327 unsigned int ei_level;
330 typedef struct efx_nic_ops_s {
331 efx_rc_t (*eno_probe)(efx_nic_t *);
332 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
333 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
334 efx_rc_t (*eno_reset)(efx_nic_t *);
335 efx_rc_t (*eno_init)(efx_nic_t *);
336 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
337 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
338 uint32_t *, size_t *);
340 efx_rc_t (*eno_register_test)(efx_nic_t *);
341 #endif /* EFSYS_OPT_DIAG */
342 void (*eno_fini)(efx_nic_t *);
343 void (*eno_unprobe)(efx_nic_t *);
346 #ifndef EFX_TXQ_LIMIT_TARGET
347 #define EFX_TXQ_LIMIT_TARGET 259
349 #ifndef EFX_RXQ_LIMIT_TARGET
350 #define EFX_RXQ_LIMIT_TARGET 512
352 #ifndef EFX_TXQ_DC_SIZE
353 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
355 #ifndef EFX_RXQ_DC_SIZE
356 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
361 typedef struct siena_filter_spec_s {
364 uint32_t sfs_dmaq_id;
365 uint32_t sfs_dword[3];
366 } siena_filter_spec_t;
368 typedef enum siena_filter_type_e {
369 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
370 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
371 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
372 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
373 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
374 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
376 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
377 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
378 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
379 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
380 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
381 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
383 EFX_SIENA_FILTER_NTYPES
384 } siena_filter_type_t;
386 typedef enum siena_filter_tbl_id_e {
387 EFX_SIENA_FILTER_TBL_RX_IP = 0,
388 EFX_SIENA_FILTER_TBL_RX_MAC,
389 EFX_SIENA_FILTER_TBL_TX_IP,
390 EFX_SIENA_FILTER_TBL_TX_MAC,
391 EFX_SIENA_FILTER_NTBLS
392 } siena_filter_tbl_id_t;
394 typedef struct siena_filter_tbl_s {
395 int sft_size; /* number of entries */
396 int sft_used; /* active count */
397 uint32_t *sft_bitmap; /* active bitmap */
398 siena_filter_spec_t *sft_spec; /* array of saved specs */
399 } siena_filter_tbl_t;
401 typedef struct siena_filter_s {
402 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
403 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
406 typedef struct efx_filter_s {
408 siena_filter_t *ef_siena_filter;
409 #endif /* EFSYS_OPT_SIENA */
410 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
411 ef10_filter_table_t *ef_ef10_filter_table;
412 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
416 siena_filter_tbl_clear(
418 __in siena_filter_tbl_id_t tbl);
420 #endif /* EFSYS_OPT_FILTER */
424 typedef struct efx_mcdi_ops_s {
425 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
426 void (*emco_send_request)(efx_nic_t *, void *, size_t,
428 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
429 boolean_t (*emco_poll_response)(efx_nic_t *);
430 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
431 void (*emco_fini)(efx_nic_t *);
432 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
433 efx_mcdi_feature_id_t, boolean_t *);
434 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
438 typedef struct efx_mcdi_s {
439 const efx_mcdi_ops_t *em_emcop;
440 const efx_mcdi_transport_t *em_emtp;
441 efx_mcdi_iface_t em_emip;
444 #endif /* EFSYS_OPT_MCDI */
447 typedef struct efx_nvram_ops_s {
449 efx_rc_t (*envo_test)(efx_nic_t *);
450 #endif /* EFSYS_OPT_DIAG */
451 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
453 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
454 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
455 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
456 unsigned int, caddr_t, size_t);
457 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
458 unsigned int, size_t);
459 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
460 unsigned int, caddr_t, size_t);
461 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
462 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
463 uint32_t *, uint16_t *);
464 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
466 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
469 #endif /* EFSYS_OPT_NVRAM */
472 typedef struct efx_vpd_ops_s {
473 efx_rc_t (*evpdo_init)(efx_nic_t *);
474 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
475 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
476 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
477 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
478 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
480 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
482 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
483 efx_vpd_value_t *, unsigned int *);
484 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
485 void (*evpdo_fini)(efx_nic_t *);
487 #endif /* EFSYS_OPT_VPD */
489 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
491 __checkReturn efx_rc_t
492 efx_mcdi_nvram_partitions(
494 __out_bcount(size) caddr_t data,
496 __out unsigned int *npartnp);
498 __checkReturn efx_rc_t
499 efx_mcdi_nvram_metadata(
502 __out uint32_t *subtypep,
503 __out_ecount(4) uint16_t version[4],
504 __out_bcount_opt(size) char *descp,
507 __checkReturn efx_rc_t
511 __out_opt size_t *sizep,
512 __out_opt uint32_t *addressp,
513 __out_opt uint32_t *erase_sizep,
514 __out_opt uint32_t *write_sizep);
516 __checkReturn efx_rc_t
517 efx_mcdi_nvram_update_start(
519 __in uint32_t partn);
521 __checkReturn efx_rc_t
525 __in uint32_t offset,
526 __out_bcount(size) caddr_t data,
530 __checkReturn efx_rc_t
531 efx_mcdi_nvram_erase(
534 __in uint32_t offset,
537 __checkReturn efx_rc_t
538 efx_mcdi_nvram_write(
541 __in uint32_t offset,
542 __out_bcount(size) caddr_t data,
545 __checkReturn efx_rc_t
546 efx_mcdi_nvram_update_finish(
549 __in boolean_t reboot,
550 __out_opt uint32_t *resultp);
554 __checkReturn efx_rc_t
557 __in uint32_t partn);
559 #endif /* EFSYS_OPT_DIAG */
561 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
563 #if EFSYS_OPT_LICENSING
565 typedef struct efx_lic_ops_s {
566 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
567 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
568 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
569 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
570 size_t *, uint8_t *);
571 efx_rc_t (*elo_find_start)
572 (efx_nic_t *, caddr_t, size_t, uint32_t *);
573 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
574 uint32_t, uint32_t *);
575 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
576 uint32_t, uint32_t *, uint32_t *);
577 boolean_t (*elo_validate_key)(efx_nic_t *,
579 efx_rc_t (*elo_read_key)(efx_nic_t *,
580 caddr_t, size_t, uint32_t, uint32_t,
581 caddr_t, size_t, uint32_t *);
582 efx_rc_t (*elo_write_key)(efx_nic_t *,
583 caddr_t, size_t, uint32_t,
584 caddr_t, uint32_t, uint32_t *);
585 efx_rc_t (*elo_delete_key)(efx_nic_t *,
586 caddr_t, size_t, uint32_t,
587 uint32_t, uint32_t, uint32_t *);
588 efx_rc_t (*elo_create_partition)(efx_nic_t *,
590 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
596 typedef struct efx_drv_cfg_s {
597 uint32_t edc_min_vi_count;
598 uint32_t edc_max_vi_count;
600 uint32_t edc_max_piobuf_count;
601 uint32_t edc_pio_alloc_size;
606 efx_family_t en_family;
607 uint32_t en_features;
608 efsys_identifier_t *en_esip;
609 efsys_lock_t *en_eslp;
610 efsys_bar_t *en_esbp;
611 unsigned int en_mod_flags;
612 unsigned int en_reset_flags;
613 efx_nic_cfg_t en_nic_cfg;
614 efx_drv_cfg_t en_drv_cfg;
618 uint32_t en_ev_qcount;
619 uint32_t en_rx_qcount;
620 uint32_t en_tx_qcount;
621 const efx_nic_ops_t *en_enop;
622 const efx_ev_ops_t *en_eevop;
623 const efx_tx_ops_t *en_etxop;
624 const efx_rx_ops_t *en_erxop;
626 efx_filter_t en_filter;
627 const efx_filter_ops_t *en_efop;
628 #endif /* EFSYS_OPT_FILTER */
631 #endif /* EFSYS_OPT_MCDI */
633 efx_nvram_type_t en_nvram_locked;
634 const efx_nvram_ops_t *en_envop;
635 #endif /* EFSYS_OPT_NVRAM */
637 const efx_vpd_ops_t *en_evpdop;
638 #endif /* EFSYS_OPT_VPD */
639 #if EFSYS_OPT_RX_SCALE
640 efx_rx_hash_support_t en_hash_support;
641 efx_rx_scale_support_t en_rss_support;
642 uint32_t en_rss_context;
643 #endif /* EFSYS_OPT_RX_SCALE */
644 uint32_t en_vport_id;
645 #if EFSYS_OPT_LICENSING
646 const efx_lic_ops_t *en_elop;
647 boolean_t en_licensing_supported;
652 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
653 unsigned int enu_partn_mask;
654 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
657 size_t enu_svpd_length;
658 #endif /* EFSYS_OPT_VPD */
661 #endif /* EFSYS_OPT_SIENA */
664 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
672 size_t ena_svpd_length;
673 #endif /* EFSYS_OPT_VPD */
674 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
675 uint32_t ena_piobuf_count;
676 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
677 uint32_t ena_pio_write_vi_base;
678 /* Memory BAR mapping regions */
679 uint32_t ena_uc_mem_map_offset;
680 size_t ena_uc_mem_map_size;
681 uint32_t ena_wc_mem_map_offset;
682 size_t ena_wc_mem_map_size;
685 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
689 #define EFX_NIC_MAGIC 0x02121996
691 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
692 const efx_ev_callbacks_t *, void *);
694 typedef struct efx_evq_rxq_state_s {
695 unsigned int eers_rx_read_ptr;
696 unsigned int eers_rx_mask;
697 } efx_evq_rxq_state_t;
702 unsigned int ee_index;
703 unsigned int ee_mask;
704 efsys_mem_t *ee_esmp;
706 uint32_t ee_stat[EV_NQSTATS];
707 #endif /* EFSYS_OPT_QSTATS */
709 efx_ev_handler_t ee_rx;
710 efx_ev_handler_t ee_tx;
711 efx_ev_handler_t ee_driver;
712 efx_ev_handler_t ee_global;
713 efx_ev_handler_t ee_drv_gen;
715 efx_ev_handler_t ee_mcdi;
716 #endif /* EFSYS_OPT_MCDI */
718 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
723 #define EFX_EVQ_MAGIC 0x08081997
725 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
731 unsigned int er_index;
732 unsigned int er_label;
733 unsigned int er_mask;
734 efsys_mem_t *er_esmp;
737 #define EFX_RXQ_MAGIC 0x15022005
742 unsigned int et_index;
743 unsigned int et_mask;
744 efsys_mem_t *et_esmp;
745 #if EFSYS_OPT_HUNTINGTON
746 uint32_t et_pio_bufnum;
747 uint32_t et_pio_blknum;
748 uint32_t et_pio_write_offset;
749 uint32_t et_pio_offset;
753 uint32_t et_stat[TX_NQSTATS];
754 #endif /* EFSYS_OPT_QSTATS */
757 #define EFX_TXQ_MAGIC 0x05092005
759 #define EFX_MAC_ADDR_COPY(_dst, _src) \
761 (_dst)[0] = (_src)[0]; \
762 (_dst)[1] = (_src)[1]; \
763 (_dst)[2] = (_src)[2]; \
764 (_dst)[3] = (_src)[3]; \
765 (_dst)[4] = (_src)[4]; \
766 (_dst)[5] = (_src)[5]; \
767 _NOTE(CONSTANTCONDITION) \
770 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
772 uint16_t *_d = (uint16_t *)(_dst); \
776 _NOTE(CONSTANTCONDITION) \
779 #if EFSYS_OPT_CHECK_REG
780 #define EFX_CHECK_REG(_enp, _reg) \
782 const char *name = #_reg; \
783 char min = name[4]; \
784 char max = name[5]; \
787 switch ((_enp)->en_family) { \
788 case EFX_FAMILY_SIENA: \
792 case EFX_FAMILY_HUNTINGTON: \
796 case EFX_FAMILY_MEDFORD: \
805 EFSYS_ASSERT3S(rev, >=, min); \
806 EFSYS_ASSERT3S(rev, <=, max); \
808 _NOTE(CONSTANTCONDITION) \
811 #define EFX_CHECK_REG(_enp, _reg) do { \
812 _NOTE(CONSTANTCONDITION) \
816 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
818 EFX_CHECK_REG((_enp), (_reg)); \
819 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
821 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
822 uint32_t, _reg ## _OFST, \
823 uint32_t, (_edp)->ed_u32[0]); \
824 _NOTE(CONSTANTCONDITION) \
827 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
829 EFX_CHECK_REG((_enp), (_reg)); \
830 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
831 uint32_t, _reg ## _OFST, \
832 uint32_t, (_edp)->ed_u32[0]); \
833 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
835 _NOTE(CONSTANTCONDITION) \
838 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
840 EFX_CHECK_REG((_enp), (_reg)); \
841 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
843 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
844 uint32_t, _reg ## _OFST, \
845 uint32_t, (_eqp)->eq_u32[1], \
846 uint32_t, (_eqp)->eq_u32[0]); \
847 _NOTE(CONSTANTCONDITION) \
850 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
852 EFX_CHECK_REG((_enp), (_reg)); \
853 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
854 uint32_t, _reg ## _OFST, \
855 uint32_t, (_eqp)->eq_u32[1], \
856 uint32_t, (_eqp)->eq_u32[0]); \
857 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
859 _NOTE(CONSTANTCONDITION) \
862 #define EFX_BAR_READO(_enp, _reg, _eop) \
864 EFX_CHECK_REG((_enp), (_reg)); \
865 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
867 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
868 uint32_t, _reg ## _OFST, \
869 uint32_t, (_eop)->eo_u32[3], \
870 uint32_t, (_eop)->eo_u32[2], \
871 uint32_t, (_eop)->eo_u32[1], \
872 uint32_t, (_eop)->eo_u32[0]); \
873 _NOTE(CONSTANTCONDITION) \
876 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
878 EFX_CHECK_REG((_enp), (_reg)); \
879 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
880 uint32_t, _reg ## _OFST, \
881 uint32_t, (_eop)->eo_u32[3], \
882 uint32_t, (_eop)->eo_u32[2], \
883 uint32_t, (_eop)->eo_u32[1], \
884 uint32_t, (_eop)->eo_u32[0]); \
885 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
887 _NOTE(CONSTANTCONDITION) \
890 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
892 EFX_CHECK_REG((_enp), (_reg)); \
893 EFSYS_BAR_READD((_enp)->en_esbp, \
894 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
896 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
897 uint32_t, (_index), \
898 uint32_t, _reg ## _OFST, \
899 uint32_t, (_edp)->ed_u32[0]); \
900 _NOTE(CONSTANTCONDITION) \
903 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
905 EFX_CHECK_REG((_enp), (_reg)); \
906 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
907 uint32_t, (_index), \
908 uint32_t, _reg ## _OFST, \
909 uint32_t, (_edp)->ed_u32[0]); \
910 EFSYS_BAR_WRITED((_enp)->en_esbp, \
911 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
913 _NOTE(CONSTANTCONDITION) \
916 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
918 EFX_CHECK_REG((_enp), (_reg)); \
919 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
920 uint32_t, (_index), \
921 uint32_t, _reg ## _OFST, \
922 uint32_t, (_edp)->ed_u32[0]); \
923 EFSYS_BAR_WRITED((_enp)->en_esbp, \
925 (2 * sizeof (efx_dword_t)) + \
926 ((_index) * _reg ## _STEP)), \
928 _NOTE(CONSTANTCONDITION) \
931 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
933 EFX_CHECK_REG((_enp), (_reg)); \
934 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
935 uint32_t, (_index), \
936 uint32_t, _reg ## _OFST, \
937 uint32_t, (_edp)->ed_u32[0]); \
938 EFSYS_BAR_WRITED((_enp)->en_esbp, \
940 (3 * sizeof (efx_dword_t)) + \
941 ((_index) * _reg ## _STEP)), \
943 _NOTE(CONSTANTCONDITION) \
946 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
948 EFX_CHECK_REG((_enp), (_reg)); \
949 EFSYS_BAR_READQ((_enp)->en_esbp, \
950 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
952 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
953 uint32_t, (_index), \
954 uint32_t, _reg ## _OFST, \
955 uint32_t, (_eqp)->eq_u32[1], \
956 uint32_t, (_eqp)->eq_u32[0]); \
957 _NOTE(CONSTANTCONDITION) \
960 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
962 EFX_CHECK_REG((_enp), (_reg)); \
963 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
964 uint32_t, (_index), \
965 uint32_t, _reg ## _OFST, \
966 uint32_t, (_eqp)->eq_u32[1], \
967 uint32_t, (_eqp)->eq_u32[0]); \
968 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
969 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
971 _NOTE(CONSTANTCONDITION) \
974 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
976 EFX_CHECK_REG((_enp), (_reg)); \
977 EFSYS_BAR_READO((_enp)->en_esbp, \
978 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
980 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
981 uint32_t, (_index), \
982 uint32_t, _reg ## _OFST, \
983 uint32_t, (_eop)->eo_u32[3], \
984 uint32_t, (_eop)->eo_u32[2], \
985 uint32_t, (_eop)->eo_u32[1], \
986 uint32_t, (_eop)->eo_u32[0]); \
987 _NOTE(CONSTANTCONDITION) \
990 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
992 EFX_CHECK_REG((_enp), (_reg)); \
993 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
994 uint32_t, (_index), \
995 uint32_t, _reg ## _OFST, \
996 uint32_t, (_eop)->eo_u32[3], \
997 uint32_t, (_eop)->eo_u32[2], \
998 uint32_t, (_eop)->eo_u32[1], \
999 uint32_t, (_eop)->eo_u32[0]); \
1000 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1001 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1003 _NOTE(CONSTANTCONDITION) \
1007 * Allow drivers to perform optimised 128-bit doorbell writes.
1008 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1009 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1010 * the need for locking in the host, and are the only ones known to be safe to
1011 * use 128-bites write with.
1013 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1015 EFX_CHECK_REG((_enp), (_reg)); \
1016 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1019 uint32_t, (_index), \
1020 uint32_t, _reg ## _OFST, \
1021 uint32_t, (_eop)->eo_u32[3], \
1022 uint32_t, (_eop)->eo_u32[2], \
1023 uint32_t, (_eop)->eo_u32[1], \
1024 uint32_t, (_eop)->eo_u32[0]); \
1025 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1026 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1028 _NOTE(CONSTANTCONDITION) \
1031 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1033 unsigned int _new = (_wptr); \
1034 unsigned int _old = (_owptr); \
1036 if ((_new) >= (_old)) \
1037 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1038 (_old) * sizeof (efx_desc_t), \
1039 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1042 * It is cheaper to sync entire map than sync \
1043 * two parts especially when offset/size are \
1044 * ignored and entire map is synced in any case.\
1046 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1048 (_entries) * sizeof (efx_desc_t)); \
1049 _NOTE(CONSTANTCONDITION) \
1052 extern __checkReturn efx_rc_t
1054 __in efx_nic_t *enp);
1056 extern __checkReturn efx_rc_t
1058 __in efx_nic_t *enp);
1061 efx_mac_multicast_hash_compute(
1062 __in_ecount(6*count) uint8_t const *addrs,
1064 __out efx_oword_t *hash_low,
1065 __out efx_oword_t *hash_high);
1067 extern __checkReturn efx_rc_t
1069 __in efx_nic_t *enp);
1073 __in efx_nic_t *enp);
1077 /* VPD utility functions */
1079 extern __checkReturn efx_rc_t
1080 efx_vpd_hunk_length(
1081 __in_bcount(size) caddr_t data,
1083 __out size_t *lengthp);
1085 extern __checkReturn efx_rc_t
1086 efx_vpd_hunk_verify(
1087 __in_bcount(size) caddr_t data,
1089 __out_opt boolean_t *cksummedp);
1091 extern __checkReturn efx_rc_t
1092 efx_vpd_hunk_reinit(
1093 __in_bcount(size) caddr_t data,
1095 __in boolean_t wantpid);
1097 extern __checkReturn efx_rc_t
1099 __in_bcount(size) caddr_t data,
1101 __in efx_vpd_tag_t tag,
1102 __in efx_vpd_keyword_t keyword,
1103 __out unsigned int *payloadp,
1104 __out uint8_t *paylenp);
1106 extern __checkReturn efx_rc_t
1108 __in_bcount(size) caddr_t data,
1110 __out efx_vpd_tag_t *tagp,
1111 __out efx_vpd_keyword_t *keyword,
1112 __out_opt unsigned int *payloadp,
1113 __out_opt uint8_t *paylenp,
1114 __inout unsigned int *contp);
1116 extern __checkReturn efx_rc_t
1118 __in_bcount(size) caddr_t data,
1120 __in efx_vpd_value_t *evvp);
1122 #endif /* EFSYS_OPT_VPD */
1126 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1128 typedef struct efx_register_set_s {
1129 unsigned int address;
1133 } efx_register_set_t;
1135 extern __checkReturn efx_rc_t
1136 efx_nic_test_registers(
1137 __in efx_nic_t *enp,
1138 __in efx_register_set_t *rsp,
1141 extern __checkReturn efx_rc_t
1142 efx_nic_test_tables(
1143 __in efx_nic_t *enp,
1144 __in efx_register_set_t *rsp,
1145 __in efx_pattern_type_t pattern,
1148 #endif /* EFSYS_OPT_DIAG */
1152 extern __checkReturn efx_rc_t
1153 efx_mcdi_set_workaround(
1154 __in efx_nic_t *enp,
1156 __in boolean_t enabled,
1157 __out_opt uint32_t *flagsp);
1159 extern __checkReturn efx_rc_t
1160 efx_mcdi_get_workarounds(
1161 __in efx_nic_t *enp,
1162 __out_opt uint32_t *implementedp,
1163 __out_opt uint32_t *enabledp);
1165 #endif /* EFSYS_OPT_MCDI */
1167 #if EFSYS_OPT_MAC_STATS
1170 * Closed range of stats (i.e. the first and the last are included).
1171 * The last must be greater or equal (if the range is one item only) to
1174 struct efx_mac_stats_range {
1175 efx_mac_stat_t first;
1176 efx_mac_stat_t last;
1180 efx_mac_stats_mask_add_ranges(
1181 __inout_bcount(mask_size) uint32_t *maskp,
1182 __in size_t mask_size,
1183 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1184 __in unsigned int rng_count);
1186 #endif /* EFSYS_OPT_MAC_STATS */
1192 #endif /* _SYS_EFX_IMPL_H */